2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3368-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
51 #include <dt-bindings/display/mipi_dsi.h>
52 #include <dt-bindings/display/drm_mipi_dsi.h>
53 #include <dt-bindings/display/media-bus-format.h>
56 compatible = "rockchip,rk3368";
57 interrupt-parent = <&gic>;
80 #address-cells = <0x2>;
116 entry-method = "psci";
118 cpu_sleep: cpu-sleep-0 {
119 compatible = "arm,idle-state";
120 arm,psci-suspend-param = <0x1010000>;
121 entry-latency-us = <0x3fffffff>;
122 exit-latency-us = <0x40000000>;
123 min-residency-us = <0xffffffff>;
129 compatible = "arm,cortex-a53", "arm,armv8";
131 cpu-idle-states = <&cpu_sleep>;
132 enable-method = "psci";
133 clocks = <&cru ARMCLKL>;
134 operating-points-v2 = <&cluster0_opp>;
136 #cooling-cells = <2>; /* min followed by max */
141 compatible = "arm,cortex-a53", "arm,armv8";
143 cpu-idle-states = <&cpu_sleep>;
144 enable-method = "psci";
145 clocks = <&cru ARMCLKL>;
146 operating-points-v2 = <&cluster0_opp>;
151 compatible = "arm,cortex-a53", "arm,armv8";
153 cpu-idle-states = <&cpu_sleep>;
154 enable-method = "psci";
155 clocks = <&cru ARMCLKL>;
156 operating-points-v2 = <&cluster0_opp>;
161 compatible = "arm,cortex-a53", "arm,armv8";
163 cpu-idle-states = <&cpu_sleep>;
164 enable-method = "psci";
165 clocks = <&cru ARMCLKL>;
166 operating-points-v2 = <&cluster0_opp>;
171 compatible = "arm,cortex-a53", "arm,armv8";
173 cpu-idle-states = <&cpu_sleep>;
174 enable-method = "psci";
175 clocks = <&cru ARMCLKB>;
176 operating-points-v2 = <&cluster1_opp>;
178 #cooling-cells = <2>; /* min followed by max */
183 compatible = "arm,cortex-a53", "arm,armv8";
185 cpu-idle-states = <&cpu_sleep>;
186 enable-method = "psci";
187 clocks = <&cru ARMCLKB>;
188 operating-points-v2 = <&cluster1_opp>;
193 compatible = "arm,cortex-a53", "arm,armv8";
195 cpu-idle-states = <&cpu_sleep>;
196 enable-method = "psci";
197 clocks = <&cru ARMCLKB>;
198 operating-points-v2 = <&cluster1_opp>;
203 compatible = "arm,cortex-a53", "arm,armv8";
205 cpu-idle-states = <&cpu_sleep>;
206 enable-method = "psci";
207 clocks = <&cru ARMCLKB>;
208 operating-points-v2 = <&cluster1_opp>;
212 cluster0_opp: opp_table0 {
213 compatible = "operating-points-v2";
217 opp-hz = /bits/ 64 <216000000>;
218 opp-microvolt = <950000 950000 1350000>;
219 clock-latency-ns = <40000>;
223 opp-hz = /bits/ 64 <408000000>;
224 opp-microvolt = <950000 950000 1350000>;
225 clock-latency-ns = <40000>;
228 opp-hz = /bits/ 64 <600000000>;
229 opp-microvolt = <950000 950000 1350000>;
230 clock-latency-ns = <40000>;
233 opp-hz = /bits/ 64 <816000000>;
234 opp-microvolt = <1025000 1025000 1350000>;
235 clock-latency-ns = <40000>;
238 opp-hz = /bits/ 64 <1008000000>;
239 opp-microvolt = <1125000 1125000 1350000>;
240 clock-latency-ns = <40000>;
243 opp-hz = /bits/ 64 <1200000000>;
244 opp-microvolt = <1225000 1225000 1350000>;
245 clock-latency-ns = <40000>;
249 cluster1_opp: opp_table1 {
250 compatible = "operating-points-v2";
254 opp-hz = /bits/ 64 <216000000>;
255 opp-microvolt = <950000 950000 1350000>;
256 clock-latency-ns = <40000>;
260 opp-hz = /bits/ 64 <408000000>;
261 opp-microvolt = <950000 950000 1350000>;
262 clock-latency-ns = <40000>;
265 opp-hz = /bits/ 64 <600000000>;
266 opp-microvolt = <950000 950000 1350000>;
267 clock-latency-ns = <40000>;
270 opp-hz = /bits/ 64 <816000000>;
271 opp-microvolt = <975000 975000 1350000>;
272 clock-latency-ns = <40000>;
275 opp-hz = /bits/ 64 <1008000000>;
276 opp-microvolt = <1050000 1050000 1350000>;
277 clock-latency-ns = <40000>;
280 opp-hz = /bits/ 64 <1200000000>;
281 opp-microvolt = <1150000 1150000 1350000>;
282 clock-latency-ns = <40000>;
285 opp-hz = /bits/ 64 <1296000000>;
286 opp-microvolt = <1225000 1225000 1350000>;
287 clock-latency-ns = <40000>;
290 opp-hz = /bits/ 64 <1416000000>;
291 opp-microvolt = <1300000 1300000 1350000>;
292 clock-latency-ns = <40000>;
295 opp-hz = /bits/ 64 <1512000000>;
296 opp-microvolt = <1350000 1350000 1350000>;
297 clock-latency-ns = <40000>;
304 min-volt = <950000>; /* uV */
305 min-freq = <216000>; /* KHz */
306 leakage-adjust-volt = <
310 nvmem-cells = <&cpu_leakage>;
311 nvmem-cell-names = "cpu_leakage";
315 min-volt = <950000>; /* uV */
316 min-freq = <216000>; /* KHz */
317 leakage-adjust-volt = <
321 nvmem-cells = <&cpu_leakage>;
322 nvmem-cell-names = "cpu_leakage";
327 compatible = "arm,armv8-pmuv3";
328 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
336 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
337 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
338 <&cpu_b2>, <&cpu_b3>;
342 compatible = "arm,amba-bus";
343 #address-cells = <2>;
347 dmac_peri: dma-controller@ff250000 {
348 compatible = "arm,pl330", "arm,primecell";
349 reg = <0x0 0xff250000 0x0 0x4000>;
350 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&cru ACLK_DMAC_PERI>;
354 clock-names = "apb_pclk";
355 arm,pl330-broken-no-flushp;
356 peripherals-req-type-burst;
359 dmac_bus: dma-controller@ff600000 {
360 compatible = "arm,pl330", "arm,primecell";
361 reg = <0x0 0xff600000 0x0 0x4000>;
362 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&cru ACLK_DMAC_BUS>;
366 clock-names = "apb_pclk";
367 arm,pl330-broken-no-flushp;
368 peripherals-req-type-burst;
373 compatible = "arm,psci-0.2";
378 compatible = "arm,armv8-timer";
379 interrupts = <GIC_PPI 13
380 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
382 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
384 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
386 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
390 compatible = "fixed-clock";
391 clock-frequency = <24000000>;
392 clock-output-names = "xin24m";
396 sdmmc: rksdmmc@ff0c0000 {
397 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
398 reg = <0x0 0xff0c0000 0x0 0x4000>;
399 clock-freq-min-max = <400000 150000000>;
400 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
401 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
402 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
403 fifo-depth = <0x100>;
404 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
408 sdio0: dwmmc@ff0d0000 {
409 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
410 reg = <0x0 0xff0d0000 0x0 0x4000>;
411 clock-freq-min-max = <400000 150000000>;
412 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
413 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
414 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
415 fifo-depth = <0x100>;
416 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
420 emmc: rksdmmc@ff0f0000 {
421 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
422 reg = <0x0 0xff0f0000 0x0 0x4000>;
423 clock-freq-min-max = <400000 150000000>;
424 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
425 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
426 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
427 fifo-depth = <0x100>;
428 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
432 saradc: saradc@ff100000 {
433 compatible = "rockchip,saradc";
434 reg = <0x0 0xff100000 0x0 0x100>;
435 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
436 #io-channel-cells = <1>;
437 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
438 clock-names = "saradc", "apb_pclk";
439 resets = <&cru SRST_SARADC>;
440 reset-names = "saradc-apb";
445 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
446 reg = <0x0 0xff110000 0x0 0x1000>;
447 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
448 clock-names = "spiclk", "apb_pclk";
449 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
450 pinctrl-names = "default";
451 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
452 #address-cells = <1>;
458 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
459 reg = <0x0 0xff120000 0x0 0x1000>;
460 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
461 clock-names = "spiclk", "apb_pclk";
462 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
465 #address-cells = <1>;
471 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
472 reg = <0x0 0xff130000 0x0 0x1000>;
473 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
474 clock-names = "spiclk", "apb_pclk";
475 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
478 #address-cells = <1>;
484 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
485 reg = <0x0 0xff650000 0x0 0x1000>;
486 clocks = <&cru PCLK_I2C0>;
488 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
489 pinctrl-names = "default";
490 pinctrl-0 = <&i2c0_xfer>;
491 #address-cells = <1>;
497 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
498 reg = <0x0 0xff140000 0x0 0x1000>;
499 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
500 #address-cells = <1>;
503 clocks = <&cru PCLK_I2C2>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&i2c2_xfer>;
510 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
511 reg = <0x0 0xff150000 0x0 0x1000>;
512 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
513 #address-cells = <1>;
516 clocks = <&cru PCLK_I2C3>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&i2c3_xfer>;
523 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
524 reg = <0x0 0xff160000 0x0 0x1000>;
525 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
526 #address-cells = <1>;
529 clocks = <&cru PCLK_I2C4>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&i2c4_xfer>;
536 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
537 reg = <0x0 0xff170000 0x0 0x1000>;
538 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
539 #address-cells = <1>;
542 clocks = <&cru PCLK_I2C5>;
543 pinctrl-names = "default";
544 pinctrl-0 = <&i2c5_xfer>;
548 uart0: serial@ff180000 {
549 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
550 reg = <0x0 0xff180000 0x0 0x100>;
551 clock-frequency = <24000000>;
552 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
553 clock-names = "baudclk", "apb_pclk";
554 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
560 uart1: serial@ff190000 {
561 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
562 reg = <0x0 0xff190000 0x0 0x100>;
563 clock-frequency = <24000000>;
564 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
565 clock-names = "baudclk", "apb_pclk";
566 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
572 uart3: serial@ff1b0000 {
573 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
574 reg = <0x0 0xff1b0000 0x0 0x100>;
575 clock-frequency = <24000000>;
576 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
577 clock-names = "baudclk", "apb_pclk";
578 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
584 uart4: serial@ff1c0000 {
585 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
586 reg = <0x0 0xff1c0000 0x0 0x100>;
587 clock-frequency = <24000000>;
588 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
589 clock-names = "baudclk", "apb_pclk";
590 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
598 polling-delay-passive = <100>; /* milliseconds */
599 polling-delay = <5000>; /* milliseconds */
601 thermal-sensors = <&tsadc 0>;
604 cpu_alert0: cpu_alert0 {
605 temperature = <75000>; /* millicelsius */
606 hysteresis = <2000>; /* millicelsius */
609 cpu_alert1: cpu_alert1 {
610 temperature = <80000>; /* millicelsius */
611 hysteresis = <2000>; /* millicelsius */
615 temperature = <95000>; /* millicelsius */
616 hysteresis = <2000>; /* millicelsius */
623 trip = <&cpu_alert0>;
625 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
628 trip = <&cpu_alert1>;
630 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
636 polling-delay-passive = <100>; /* milliseconds */
637 polling-delay = <5000>; /* milliseconds */
639 thermal-sensors = <&tsadc 1>;
642 gpu_alert0: gpu_alert0 {
643 temperature = <80000>; /* millicelsius */
644 hysteresis = <2000>; /* millicelsius */
648 temperature = <115000>; /* millicelsius */
649 hysteresis = <2000>; /* millicelsius */
656 trip = <&gpu_alert0>;
658 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
664 tsadc: tsadc@ff280000 {
665 compatible = "rockchip,rk3368-tsadc-legacy";
666 reg = <0x0 0xff280000 0x0 0x100>;
667 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
669 clock-names = "tsadc", "apb_pclk";
670 clock-frequency = <32768>;
671 resets = <&cru SRST_TSADC>;
672 reset-names = "tsadc-apb";
673 nvmem-cells = <&temp_adjust>;
674 nvmem-cell-names = "temp_adjust";
675 #thermal-sensor-cells = <1>;
676 hw-shut-temp = <95000>;
680 gmac: ethernet@ff290000 {
681 compatible = "rockchip,rk3368-gmac";
682 reg = <0x0 0xff290000 0x0 0x10000>;
683 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
684 interrupt-names = "macirq";
685 rockchip,grf = <&grf>;
686 clocks = <&cru SCLK_MAC>,
687 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
688 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
689 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
690 clock-names = "stmmaceth",
691 "mac_clk_rx", "mac_clk_tx",
692 "clk_mac_ref", "clk_mac_refout",
693 "aclk_mac", "pclk_mac";
697 nandc0: nandc@ff400000 {
698 compatible = "rockchip,rk-nandc";
699 reg = <0x0 0xff400000 0x0 0x4000>;
700 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
703 clock-names = "clk_nandc", "hclk_nandc";
707 usb_host0_ehci: usb@ff500000 {
708 compatible = "generic-ehci";
709 reg = <0x0 0xff500000 0x0 0x20000>;
710 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&cru HCLK_HOST0>, <&u2phy>;
712 clock-names = "usbhost", "utmi";
713 phys = <&u2phy_host>;
718 usb_host0_ohci: usb@ff520000 {
719 compatible = "generic-ohci";
720 reg = <0x0 0xff520000 0x0 0x20000>;
721 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&cru HCLK_HOST0>, <&u2phy>;
723 clock-names = "usbhost", "utmi";
724 phys = <&u2phy_host>;
729 usb_otg: usb@ff580000 {
730 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
732 reg = <0x0 0xff580000 0x0 0x40000>;
733 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&cru HCLK_OTG0>;
737 g-np-tx-fifo-size = <16>;
738 g-rx-fifo-size = <275>;
739 g-tx-fifo-size = <256 128 128 64 64 32>;
744 ddrpctl: syscon@ff610000 {
745 compatible = "rockchip,rk3368-ddrpctl", "syscon";
746 reg = <0x0 0xff610000 0x0 0x400>;
750 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
751 reg = <0x0 0xff660000 0x0 0x1000>;
752 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
753 #address-cells = <1>;
756 clocks = <&cru PCLK_I2C1>;
757 pinctrl-names = "default";
758 pinctrl-0 = <&i2c1_xfer>;
763 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
764 reg = <0x0 0xff680000 0x0 0x10>;
766 pinctrl-names = "default";
767 pinctrl-0 = <&pwm0_pin>;
768 clocks = <&cru PCLK_PWM1>;
774 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
775 reg = <0x0 0xff680010 0x0 0x10>;
777 pinctrl-names = "default";
778 pinctrl-0 = <&pwm1_pin>;
779 clocks = <&cru PCLK_PWM1>;
785 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
786 reg = <0x0 0xff680020 0x0 0x10>;
788 clocks = <&cru PCLK_PWM1>;
794 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
795 reg = <0x0 0xff680030 0x0 0x10>;
797 pinctrl-names = "default";
798 pinctrl-0 = <&pwm3_pin>;
799 clocks = <&cru PCLK_PWM1>;
804 uart2: serial@ff690000 {
805 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
806 reg = <0x0 0xff690000 0x0 0x100>;
807 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
808 clock-names = "baudclk", "apb_pclk";
809 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
810 pinctrl-names = "default";
811 pinctrl-0 = <&uart2_xfer>;
817 mbox: mbox@ff6b0000 {
818 compatible = "rockchip,rk3368-mailbox";
819 reg = <0x0 0xff6b0000 0x0 0x1000>;
820 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&cru PCLK_MAILBOX>;
825 clock-names = "pclk_mailbox";
830 mailbox: mailbox@ff6b0000 {
831 compatible = "rockchip,rk3368-mbox-legacy";
832 reg = <0x0 0xff6b0000 0x0 0x1000>,
833 <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
834 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
836 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
837 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&cru PCLK_MAILBOX>;
839 clock-names = "pclk_mailbox";
844 mailbox_scpi: mailbox-scpi {
845 compatible = "rockchip,rk3368-scpi-legacy";
846 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
851 qos_iep: qos@ffad0000 {
852 compatible = "syscon";
853 reg = <0x0 0xffad0000 0x0 0x20>;
856 qos_isp_r0: qos@ffad0080 {
857 compatible = "syscon";
858 reg = <0x0 0xffad0080 0x0 0x20>;
861 qos_isp_r1: qos@ffad0100 {
862 compatible = "syscon";
863 reg = <0x0 0xffad0100 0x0 0x20>;
866 qos_isp_w0: qos@ffad0180 {
867 compatible = "syscon";
868 reg = <0x0 0xffad0180 0x0 0x20>;
871 qos_isp_w1: qos@ffad0200 {
872 compatible = "syscon";
873 reg = <0x0 0xffad0200 0x0 0x20>;
876 qos_vip: qos@ffad0280 {
877 compatible = "syscon";
878 reg = <0x0 0xffad0280 0x0 0x20>;
881 qos_vop: qos@ffad0300 {
882 compatible = "syscon";
883 reg = <0x0 0xffad0300 0x0 0x20>;
886 qos_rga_r: qos@ffad0380 {
887 compatible = "syscon";
888 reg = <0x0 0xffad0380 0x0 0x20>;
891 qos_rga_w: qos@ffad0400 {
892 compatible = "syscon";
893 reg = <0x0 0xffad0400 0x0 0x20>;
896 qos_hevc_r: qos@ffae0000 {
897 compatible = "syscon";
898 reg = <0x0 0xffae0000 0x0 0x20>;
901 qos_vpu_r: qos@ffae0100 {
902 compatible = "syscon";
903 reg = <0x0 0xffae0100 0x0 0x20>;
906 qos_vpu_w: qos@ffae0180 {
907 compatible = "syscon";
908 reg = <0x0 0xffae0180 0x0 0x20>;
911 qos_gpu: qos@ffaf0000 {
912 compatible = "syscon";
913 reg = <0x0 0xffaf0000 0x0 0x20>;
916 pmu: power-management@ff730000 {
917 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
918 reg = <0x0 0xff730000 0x0 0x1000>;
920 power: power-controller {
921 compatible = "rockchip,rk3368-power-controller";
922 #power-domain-cells = <1>;
923 #address-cells = <1>;
927 * Note: Although SCLK_* are the working clocks
928 * of device without including on the NOC, needed for
931 * The clocks on the which NOC:
932 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
933 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
934 * ACLK_RGA is on ACLK_RGA_NIU.
935 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
937 * Which clock are device clocks:
939 * *_IEP IEP:Image Enhancement Processor
940 * *_ISP ISP:Image Signal Processing
941 * *_VIP VIP:Video Input Processor
942 * *_VOP* VOP:Visual Output Processor
950 reg = <RK3368_PD_VIO>;
951 clocks = <&cru ACLK_IEP>,
963 <&cru HCLK_VIO_HDCPMMU>,
964 <&cru PCLK_EDP_CTRL>,
965 <&cru PCLK_HDMI_CTRL>,
971 <&cru PCLK_MIPI_CSI>,
972 <&cru PCLK_MIPI_DSI0>,
973 <&cru SCLK_VOP0_PWM>,
979 <&cru SCLK_HDMI_CEC>,
980 <&cru SCLK_HDMI_HDCP>;
992 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
993 * (video endecoder & decoder) clocks that on the
994 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
997 reg = <RK3368_PD_VIDEO>;
998 clocks = <&cru ACLK_VIDEO>,
1000 <&cru SCLK_HEVC_CABAC>,
1001 <&cru SCLK_HEVC_CORE>;
1002 pm_qos = <&qos_hevc_r>,
1007 * Note: ACLK_GPU is the GPU clock,
1008 * and on the ACLK_GPU_NIU (NOC).
1011 reg = <RK3368_PD_GPU_1>;
1012 clocks = <&cru ACLK_GPU_CFG>,
1013 <&cru ACLK_GPU_MEM>,
1014 <&cru SCLK_GPU_CORE>;
1015 pm_qos = <&qos_gpu>;
1020 pmugrf: syscon@ff738000 {
1021 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
1022 reg = <0x0 0xff738000 0x0 0x1000>;
1024 pmu_io_domains: io-domains {
1025 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
1026 status = "disabled";
1030 compatible = "syscon-reboot-mode";
1032 mode-normal = <BOOT_NORMAL>;
1033 mode-recovery = <BOOT_RECOVERY>;
1034 mode-bootloader = <BOOT_FASTBOOT>;
1035 mode-loader = <BOOT_BL_DOWNLOAD>;
1039 cru: clock-controller@ff760000 {
1040 compatible = "rockchip,rk3368-cru";
1041 reg = <0x0 0xff760000 0x0 0x1000>;
1042 rockchip,grf = <&grf>;
1046 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1047 <&cru ACLK_BUS>, <&cru ACLK_PERI>,
1048 <&cru HCLK_BUS>, <&cru HCLK_PERI>,
1049 <&cru PCLK_BUS>, <&cru PCLK_PERI>;
1050 assigned-clock-rates =
1051 <576000000>, <400000000>,
1052 <300000000>, <300000000>,
1053 <150000000>, <150000000>,
1054 <75000000>, <75000000>;
1057 grf: syscon@ff770000 {
1058 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
1059 reg = <0x0 0xff770000 0x0 0x1000>;
1060 #address-cells = <1>;
1063 io_domains: io-domains {
1064 compatible = "rockchip,rk3368-io-voltage-domain";
1065 status = "disabled";
1068 u2phy: usb2-phy@700 {
1069 compatible = "rockchip,rk3368-usb2phy";
1071 clocks = <&cru SCLK_OTGPHY0>;
1072 clock-names = "phyclk";
1074 clock-output-names = "usbotg_out";
1075 assigned-clocks = <&cru SCLK_USBPHY480M>;
1076 assigned-clock-parents = <&u2phy>;
1077 status = "disabled";
1079 u2phy_host: host-port {
1081 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1082 interrupt-names = "linestate";
1083 status = "disabled";
1088 wdt: watchdog@ff800000 {
1089 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
1090 reg = <0x0 0xff800000 0x0 0x100>;
1091 clocks = <&cru PCLK_WDT>;
1092 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1093 status = "disabled";
1097 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
1098 reg = <0x0 0xff810000 0x0 0x20>;
1099 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1102 i2s_2ch: i2s-2ch@ff890000 {
1103 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1104 reg = <0x0 0xff890000 0x0 0x1000>;
1105 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1106 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1107 dma-names = "tx", "rx";
1108 clock-names = "i2s_clk", "i2s_hclk";
1109 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1110 status = "disabled";
1113 i2s_8ch: i2s-8ch@ff898000 {
1114 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1115 reg = <0x0 0xff898000 0x0 0x1000>;
1116 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1117 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1118 dma-names = "tx", "rx";
1119 clock-names = "i2s_clk", "i2s_hclk";
1120 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1121 pinctrl-names = "default";
1122 pinctrl-0 = <&i2s_8ch_bus>;
1123 status = "disabled";
1126 isp_mmu: iommu@ff914000 {
1127 compatible = "rockchip,iommu";
1128 reg = <0x0 0xff914000 0x0 0x100>,
1129 <0x0 0xff915000 0x0 0x100>;
1130 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1131 interrupt-names = "isp_mmu";
1133 status = "disabled";
1137 compatible = "rockchip,rk3368-vop";
1138 reg = <0x0 0xff930000 0x0 0x2fc>;
1139 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1140 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1141 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1142 assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1143 assigned-clock-rates = <400000000>, <200000000>;
1144 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1145 reset-names = "axi", "ahb", "dclk";
1146 power-domains = <&power RK3368_PD_VIO>;
1147 iommus = <&vop_mmu>;
1148 status = "disabled";
1151 #address-cells = <1>;
1154 vop_out_mipi: endpoint@0 {
1156 remote-endpoint = <&mipi_in_vop>;
1161 display_subsystem: display-subsystem {
1162 compatible = "rockchip,display-subsystem";
1164 status = "disabled";
1167 vop_mmu: iommu@ff930300 {
1168 compatible = "rockchip,iommu";
1169 reg = <0x0 0xff930300 0x0 0x100>;
1170 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1171 interrupt-names = "vop_mmu";
1172 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1173 clock-names = "aclk", "hclk";
1174 power-domains = <&power RK3368_PD_VIO>;
1176 status = "disabled";
1179 mipi_dsi_host: mipi-dsi-host@ff960000 {
1180 compatible = "rockchip,rk3368-mipi-dsi";
1181 reg = <0x0 0xff960000 0x0 0x4000>;
1182 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1183 clocks = <&cru PCLK_MIPI_DSI0>;
1184 clock-names = "pclk";
1185 phys = <&mipi_dphy>;
1186 phy-names = "mipi_dphy";
1187 rockchip,grf = <&grf>;
1188 power-domains = <&power RK3368_PD_VIO>;
1189 #address-cells = <1>;
1191 status = "disabled";
1194 #address-cells = <1>;
1199 #address-cells = <1>;
1202 mipi_in_vop: endpoint@0 {
1204 remote-endpoint = <&vop_out_mipi>;
1210 mipi_dphy: mipi-dphy@ff968000 {
1211 compatible = "rockchip,rk3368-mipi-dphy";
1212 reg = <0x0 0xff968000 0x0 0x4000>;
1214 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
1215 clock-names = "ref", "pclk";
1216 status = "disabled";
1219 hevc_mmu: iommu@ff9a0440 {
1220 compatible = "rockchip,iommu";
1221 reg = <0x0 0xff9a0440 0x0 0x100>,
1222 <0x0 0xff9a0480 0x0 0x100>;
1223 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1224 interrupt-names = "hevc_mmu";
1225 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1226 clock-names = "aclk", "hclk";
1227 power-domains = <&power RK3368_PD_VIDEO>;
1229 status = "disabled";
1232 vpu_mmu: iommu@ff9a0800 {
1233 compatible = "rockchip,iommu";
1234 reg = <0x0 0xff9a0800 0x0 0x100>;
1235 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1236 interrupt-names = "vpu_mmu";
1237 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1238 clock-names = "aclk", "hclk";
1239 power-domains = <&power RK3368_PD_VIDEO>;
1241 status = "disabled";
1244 gic: interrupt-controller@ffb71000 {
1245 compatible = "arm,gic-400";
1246 interrupt-controller;
1247 #interrupt-cells = <3>;
1248 #address-cells = <0>;
1250 reg = <0x0 0xffb71000 0x0 0x1000>,
1251 <0x0 0xffb72000 0x0 0x2000>,
1252 <0x0 0xffb74000 0x0 0x2000>,
1253 <0x0 0xffb76000 0x0 0x2000>;
1254 interrupts = <GIC_PPI 9
1255 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1258 gpu: rogue-g6110@ffa30000 {
1259 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1260 reg = <0x0 0xffa30000 0x0 0x10000>;
1262 <&cru SCLK_GPU_CORE>,
1263 <&cru ACLK_GPU_MEM>,
1264 <&cru ACLK_GPU_CFG>;
1269 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1270 interrupt-names = "rogue-g6110-irq";
1271 power-domains = <&power RK3368_PD_GPU_1>;
1272 operating-points-v2 = <&gpu_opp_table>;
1275 gpu_opp_table: gpu_opp_table {
1276 compatible = "operating-points-v2";
1280 opp-hz = /bits/ 64 <200000000>;
1281 opp-microvolt = <1100000>;
1284 opp-hz = /bits/ 64 <288000000>;
1285 opp-microvolt = <1100000>;
1288 opp-hz = /bits/ 64 <400000000>;
1289 opp-microvolt = <1100000>;
1292 opp-hz = /bits/ 64 <576000000>;
1293 opp-microvolt = <1200000>;
1297 efuse: efuse@ffb00000 {
1298 compatible = "rockchip,rk3368-efuse";
1299 reg = <0x0 0xffb00000 0x0 0x20>;
1300 #address-cells = <1>;
1302 clocks = <&cru PCLK_EFUSE256>;
1303 clock-names = "pclk_efuse";
1306 cpu_leakage: cpu-leakage@17 {
1309 temp_adjust: temp-adjust@1f {
1315 compatible = "rockchip,rk3368-pinctrl";
1316 rockchip,grf = <&grf>;
1317 rockchip,pmu = <&pmugrf>;
1318 #address-cells = <0x2>;
1319 #size-cells = <0x2>;
1322 gpio0: gpio0@ff750000 {
1323 compatible = "rockchip,gpio-bank";
1324 reg = <0x0 0xff750000 0x0 0x100>;
1325 clocks = <&cru PCLK_GPIO0>;
1326 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1329 #gpio-cells = <0x2>;
1331 interrupt-controller;
1332 #interrupt-cells = <0x2>;
1335 gpio1: gpio1@ff780000 {
1336 compatible = "rockchip,gpio-bank";
1337 reg = <0x0 0xff780000 0x0 0x100>;
1338 clocks = <&cru PCLK_GPIO1>;
1339 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1342 #gpio-cells = <0x2>;
1344 interrupt-controller;
1345 #interrupt-cells = <0x2>;
1348 gpio2: gpio2@ff790000 {
1349 compatible = "rockchip,gpio-bank";
1350 reg = <0x0 0xff790000 0x0 0x100>;
1351 clocks = <&cru PCLK_GPIO2>;
1352 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1355 #gpio-cells = <0x2>;
1357 interrupt-controller;
1358 #interrupt-cells = <0x2>;
1361 gpio3: gpio3@ff7a0000 {
1362 compatible = "rockchip,gpio-bank";
1363 reg = <0x0 0xff7a0000 0x0 0x100>;
1364 clocks = <&cru PCLK_GPIO3>;
1365 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1368 #gpio-cells = <0x2>;
1370 interrupt-controller;
1371 #interrupt-cells = <0x2>;
1374 pcfg_pull_up: pcfg-pull-up {
1378 pcfg_pull_down: pcfg-pull-down {
1382 pcfg_pull_none: pcfg-pull-none {
1386 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1388 drive-strength = <12>;
1392 emmc_clk: emmc-clk {
1393 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1396 emmc_cmd: emmc-cmd {
1397 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1400 emmc_pwr: emmc-pwr {
1401 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1404 emmc_bus1: emmc-bus1 {
1405 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1408 emmc_bus4: emmc-bus4 {
1409 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1410 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1411 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1412 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1415 emmc_bus8: emmc-bus8 {
1416 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1417 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1418 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1419 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1420 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1421 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1422 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1423 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1428 rgmii_pins: rgmii-pins {
1429 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1430 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1431 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1432 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1433 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1434 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1435 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1436 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1437 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1438 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1439 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1440 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1441 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1442 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1443 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1446 rmii_pins: rmii-pins {
1447 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1448 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1449 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1450 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1451 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1452 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1453 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1454 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1455 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1456 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1461 i2c0_xfer: i2c0-xfer {
1462 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1463 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1468 i2c1_xfer: i2c1-xfer {
1469 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1470 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1475 i2c2_xfer: i2c2-xfer {
1476 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1477 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1482 i2c3_xfer: i2c3-xfer {
1483 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1484 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1489 i2c4_xfer: i2c4-xfer {
1490 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1491 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1496 i2c5_xfer: i2c5-xfer {
1497 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1498 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1503 i2s_8ch_bus: i2s-8ch-bus {
1504 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1505 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1506 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1507 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1508 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1509 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1510 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1511 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1512 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1517 pwm0_pin: pwm0-pin {
1518 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1521 vop_pwm_pin: vop-pwm {
1522 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1527 pwm1_pin: pwm1-pin {
1528 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1533 pwm3_pin: pwm3-pin {
1534 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1539 sdio0_bus1: sdio0-bus1 {
1540 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1543 sdio0_bus4: sdio0-bus4 {
1544 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1545 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1546 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1547 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1550 sdio0_cmd: sdio0-cmd {
1551 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1554 sdio0_clk: sdio0-clk {
1555 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1558 sdio0_cd: sdio0-cd {
1559 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1562 sdio0_wp: sdio0-wp {
1563 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1566 sdio0_pwr: sdio0-pwr {
1567 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1570 sdio0_bkpwr: sdio0-bkpwr {
1571 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1574 sdio0_int: sdio0-int {
1575 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1580 sdmmc_clk: sdmmc-clk {
1581 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1584 sdmmc_cmd: sdmmc-cmd {
1585 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1588 sdmmc_cd: sdmmc-cd {
1589 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1592 sdmmc_bus1: sdmmc-bus1 {
1593 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1596 sdmmc_bus4: sdmmc-bus4 {
1597 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1598 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1599 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1600 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1605 spi0_clk: spi0-clk {
1606 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1608 spi0_cs0: spi0-cs0 {
1609 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1611 spi0_cs1: spi0-cs1 {
1612 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1615 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1618 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1623 spi1_clk: spi1-clk {
1624 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1626 spi1_cs0: spi1-cs0 {
1627 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1629 spi1_cs1: spi1-cs1 {
1630 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1633 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1636 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1641 spi2_clk: spi2-clk {
1642 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1644 spi2_cs0: spi2-cs0 {
1645 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1648 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1651 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1656 uart0_xfer: uart0-xfer {
1657 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1658 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1661 uart0_cts: uart0-cts {
1662 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1665 uart0_rts: uart0-rts {
1666 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1671 uart1_xfer: uart1-xfer {
1672 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1673 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1676 uart1_cts: uart1-cts {
1677 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1680 uart1_rts: uart1-rts {
1681 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1686 uart2_xfer: uart2-xfer {
1687 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1688 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1690 /* no rts / cts for uart2 */
1694 uart3_xfer: uart3-xfer {
1695 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1696 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1699 uart3_cts: uart3-cts {
1700 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1703 uart3_rts: uart3-rts {
1704 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1709 uart4_xfer: uart4-xfer {
1710 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1711 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1714 uart4_cts: uart4-cts {
1715 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1718 uart4_rts: uart4-rts {
1719 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;