2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3368-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
51 #include <dt-bindings/display/mipi_dsi.h>
52 #include <dt-bindings/display/drm_mipi_dsi.h>
53 #include <dt-bindings/display/media-bus-format.h>
56 compatible = "rockchip,rk3368";
57 interrupt-parent = <&gic>;
80 #address-cells = <0x2>;
116 entry-method = "psci";
118 cpu_sleep: cpu-sleep-0 {
119 compatible = "arm,idle-state";
120 arm,psci-suspend-param = <0x1010000>;
121 entry-latency-us = <0x3fffffff>;
122 exit-latency-us = <0x40000000>;
123 min-residency-us = <0xffffffff>;
129 compatible = "arm,cortex-a53", "arm,armv8";
131 cpu-idle-states = <&cpu_sleep>;
132 enable-method = "psci";
133 clocks = <&cru ARMCLKL>;
134 operating-points-v2 = <&cluster0_opp>;
135 sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
136 #cooling-cells = <2>; /* min followed by max */
137 dynamic-power-coefficient = <149>;
142 compatible = "arm,cortex-a53", "arm,armv8";
144 cpu-idle-states = <&cpu_sleep>;
145 enable-method = "psci";
146 clocks = <&cru ARMCLKL>;
147 operating-points-v2 = <&cluster0_opp>;
148 sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
153 compatible = "arm,cortex-a53", "arm,armv8";
155 cpu-idle-states = <&cpu_sleep>;
156 enable-method = "psci";
157 clocks = <&cru ARMCLKL>;
158 operating-points-v2 = <&cluster0_opp>;
159 sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
164 compatible = "arm,cortex-a53", "arm,armv8";
166 cpu-idle-states = <&cpu_sleep>;
167 enable-method = "psci";
168 clocks = <&cru ARMCLKL>;
169 operating-points-v2 = <&cluster0_opp>;
170 sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
175 compatible = "arm,cortex-a53", "arm,armv8";
177 cpu-idle-states = <&cpu_sleep>;
178 enable-method = "psci";
179 clocks = <&cru ARMCLKB>;
180 operating-points-v2 = <&cluster1_opp>;
181 sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
182 #cooling-cells = <2>; /* min followed by max */
183 dynamic-power-coefficient = <160>;
188 compatible = "arm,cortex-a53", "arm,armv8";
190 cpu-idle-states = <&cpu_sleep>;
191 enable-method = "psci";
192 clocks = <&cru ARMCLKB>;
193 operating-points-v2 = <&cluster1_opp>;
194 sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
199 compatible = "arm,cortex-a53", "arm,armv8";
201 cpu-idle-states = <&cpu_sleep>;
202 enable-method = "psci";
203 clocks = <&cru ARMCLKB>;
204 operating-points-v2 = <&cluster1_opp>;
205 sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
210 compatible = "arm,cortex-a53", "arm,armv8";
212 cpu-idle-states = <&cpu_sleep>;
213 enable-method = "psci";
214 clocks = <&cru ARMCLKB>;
215 operating-points-v2 = <&cluster1_opp>;
216 sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
220 cluster0_opp: opp_table0 {
221 compatible = "operating-points-v2";
225 opp-hz = /bits/ 64 <216000000>;
226 opp-microvolt = <950000 950000 1350000>;
227 clock-latency-ns = <40000>;
231 opp-hz = /bits/ 64 <408000000>;
232 opp-microvolt = <950000 950000 1350000>;
233 clock-latency-ns = <40000>;
236 opp-hz = /bits/ 64 <600000000>;
237 opp-microvolt = <950000 950000 1350000>;
238 clock-latency-ns = <40000>;
241 opp-hz = /bits/ 64 <816000000>;
242 opp-microvolt = <1025000 1025000 1350000>;
243 clock-latency-ns = <40000>;
246 opp-hz = /bits/ 64 <1008000000>;
247 opp-microvolt = <1125000 1125000 1350000>;
248 clock-latency-ns = <40000>;
251 opp-hz = /bits/ 64 <1200000000>;
252 opp-microvolt = <1225000 1225000 1350000>;
253 clock-latency-ns = <40000>;
257 cluster1_opp: opp_table1 {
258 compatible = "operating-points-v2";
262 opp-hz = /bits/ 64 <216000000>;
263 opp-microvolt = <950000 950000 1350000>;
264 clock-latency-ns = <40000>;
268 opp-hz = /bits/ 64 <408000000>;
269 opp-microvolt = <950000 950000 1350000>;
270 clock-latency-ns = <40000>;
273 opp-hz = /bits/ 64 <600000000>;
274 opp-microvolt = <950000 950000 1350000>;
275 clock-latency-ns = <40000>;
278 opp-hz = /bits/ 64 <816000000>;
279 opp-microvolt = <975000 975000 1350000>;
280 clock-latency-ns = <40000>;
283 opp-hz = /bits/ 64 <1008000000>;
284 opp-microvolt = <1050000 1050000 1350000>;
285 clock-latency-ns = <40000>;
288 opp-hz = /bits/ 64 <1200000000>;
289 opp-microvolt = <1150000 1150000 1350000>;
290 clock-latency-ns = <40000>;
293 opp-hz = /bits/ 64 <1296000000>;
294 opp-microvolt = <1225000 1225000 1350000>;
295 clock-latency-ns = <40000>;
298 opp-hz = /bits/ 64 <1416000000>;
299 opp-microvolt = <1300000 1300000 1350000>;
300 clock-latency-ns = <40000>;
303 opp-hz = /bits/ 64 <1512000000>;
304 opp-microvolt = <1350000 1350000 1350000>;
305 clock-latency-ns = <40000>;
310 RK3368_CPU_COST_0: rk3368-core-cost0 {
326 RK3368_CPU_COST_1: rk3368-core-cost1 {
345 RK3368_CLUSTER_COST_0: rk3368-cluster-cost0 {
361 RK3368_CLUSTER_COST_1: rk3368-cluster-cost1 {
384 min-volt = <950000>; /* uV */
385 min-freq = <216000>; /* KHz */
386 leakage-adjust-volt = <
390 nvmem-cells = <&cpu_leakage>;
391 nvmem-cell-names = "cpu_leakage";
395 min-volt = <950000>; /* uV */
396 min-freq = <216000>; /* KHz */
397 leakage-adjust-volt = <
401 nvmem-cells = <&cpu_leakage>;
402 nvmem-cell-names = "cpu_leakage";
407 compatible = "arm,armv8-pmuv3";
408 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
416 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
417 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
418 <&cpu_b2>, <&cpu_b3>;
422 compatible = "arm,amba-bus";
423 #address-cells = <2>;
427 dmac_peri: dma-controller@ff250000 {
428 compatible = "arm,pl330", "arm,primecell";
429 reg = <0x0 0xff250000 0x0 0x4000>;
430 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&cru ACLK_DMAC_PERI>;
434 clock-names = "apb_pclk";
435 arm,pl330-broken-no-flushp;
436 peripherals-req-type-burst;
439 dmac_bus: dma-controller@ff600000 {
440 compatible = "arm,pl330", "arm,primecell";
441 reg = <0x0 0xff600000 0x0 0x4000>;
442 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&cru ACLK_DMAC_BUS>;
446 clock-names = "apb_pclk";
447 arm,pl330-broken-no-flushp;
448 peripherals-req-type-burst;
453 compatible = "arm,psci-0.2";
458 compatible = "arm,armv8-timer";
459 interrupts = <GIC_PPI 13
460 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
462 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
464 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
466 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
470 compatible = "fixed-clock";
471 clock-frequency = <24000000>;
472 clock-output-names = "xin24m";
477 compatible = "fixed-clock";
478 clock-frequency = <32768>;
479 clock-output-names = "xin32k";
483 sdmmc: dwmmc@ff0c0000 {
484 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
485 reg = <0x0 0xff0c0000 0x0 0x4000>;
486 clock-freq-min-max = <400000 150000000>;
487 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
488 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
489 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
490 fifo-depth = <0x100>;
491 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
495 sdio0: dwmmc@ff0d0000 {
496 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
497 reg = <0x0 0xff0d0000 0x0 0x4000>;
498 clock-freq-min-max = <400000 150000000>;
499 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
500 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
501 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
502 fifo-depth = <0x100>;
503 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
507 emmc: dwmmc@ff0f0000 {
508 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
509 reg = <0x0 0xff0f0000 0x0 0x4000>;
510 clock-freq-min-max = <400000 150000000>;
511 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
512 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
513 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
514 fifo-depth = <0x100>;
515 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
519 saradc: saradc@ff100000 {
520 compatible = "rockchip,saradc";
521 reg = <0x0 0xff100000 0x0 0x100>;
522 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
523 #io-channel-cells = <1>;
524 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
525 clock-names = "saradc", "apb_pclk";
526 resets = <&cru SRST_SARADC>;
527 reset-names = "saradc-apb";
532 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
533 reg = <0x0 0xff110000 0x0 0x1000>;
534 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
535 clock-names = "spiclk", "apb_pclk";
536 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
537 pinctrl-names = "default";
538 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
539 #address-cells = <1>;
545 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
546 reg = <0x0 0xff120000 0x0 0x1000>;
547 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
548 clock-names = "spiclk", "apb_pclk";
549 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
552 #address-cells = <1>;
558 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
559 reg = <0x0 0xff130000 0x0 0x1000>;
560 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
561 clock-names = "spiclk", "apb_pclk";
562 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
563 pinctrl-names = "default";
564 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
565 #address-cells = <1>;
571 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
572 reg = <0x0 0xff650000 0x0 0x1000>;
573 clocks = <&cru PCLK_I2C0>;
575 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
576 pinctrl-names = "default";
577 pinctrl-0 = <&i2c0_xfer>;
578 #address-cells = <1>;
584 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
585 reg = <0x0 0xff140000 0x0 0x1000>;
586 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
587 #address-cells = <1>;
590 clocks = <&cru PCLK_I2C2>;
591 pinctrl-names = "default";
592 pinctrl-0 = <&i2c2_xfer>;
597 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
598 reg = <0x0 0xff150000 0x0 0x1000>;
599 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
600 #address-cells = <1>;
603 clocks = <&cru PCLK_I2C3>;
604 pinctrl-names = "default";
605 pinctrl-0 = <&i2c3_xfer>;
610 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
611 reg = <0x0 0xff160000 0x0 0x1000>;
612 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
613 #address-cells = <1>;
616 clocks = <&cru PCLK_I2C4>;
617 pinctrl-names = "default";
618 pinctrl-0 = <&i2c4_xfer>;
623 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
624 reg = <0x0 0xff170000 0x0 0x1000>;
625 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
626 #address-cells = <1>;
629 clocks = <&cru PCLK_I2C5>;
630 pinctrl-names = "default";
631 pinctrl-0 = <&i2c5_xfer>;
635 uart0: serial@ff180000 {
636 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
637 reg = <0x0 0xff180000 0x0 0x100>;
638 clock-frequency = <24000000>;
639 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
640 clock-names = "baudclk", "apb_pclk";
641 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
647 uart1: serial@ff190000 {
648 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
649 reg = <0x0 0xff190000 0x0 0x100>;
650 clock-frequency = <24000000>;
651 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
652 clock-names = "baudclk", "apb_pclk";
653 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
659 uart3: serial@ff1b0000 {
660 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
661 reg = <0x0 0xff1b0000 0x0 0x100>;
662 clock-frequency = <24000000>;
663 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
664 clock-names = "baudclk", "apb_pclk";
665 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
671 uart4: serial@ff1c0000 {
672 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
673 reg = <0x0 0xff1c0000 0x0 0x100>;
674 clock-frequency = <24000000>;
675 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
676 clock-names = "baudclk", "apb_pclk";
677 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
683 thermal_zones: thermal-zones {
684 soc_thermal: soc-thermal {
685 polling-delay-passive = <200>; /* milliseconds */
686 polling-delay = <200>; /* milliseconds */
687 sustainable-power = <600>; /* milliwatts */
689 thermal-sensors = <&tsadc 0>;
691 threshold: trip-point@0 {
692 temperature = <70000>; /* millicelsius */
693 hysteresis = <2000>; /* millicelsius */
696 target: trip-point@1 {
697 temperature = <80000>; /* millicelsius */
698 hysteresis = <2000>; /* millicelsius */
702 temperature = <95000>; /* millicelsius */
703 hysteresis = <2000>; /* millicelsius */
712 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
713 contribution = <1024>;
718 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
719 contribution = <1024>;
724 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
725 contribution = <1024>;
730 gpu_thermal: gpu-thermal {
731 polling-delay-passive = <200>; /* milliseconds */
732 polling-delay = <200>; /* milliseconds */
733 thermal-sensors = <&tsadc 1>;
737 tsadc: tsadc@ff280000 {
738 compatible = "rockchip,rk3368-tsadc-legacy";
739 reg = <0x0 0xff280000 0x0 0x100>;
740 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
742 clock-names = "tsadc", "apb_pclk";
743 clock-frequency = <32768>;
744 resets = <&cru SRST_TSADC>;
745 reset-names = "tsadc-apb";
746 nvmem-cells = <&temp_adjust>;
747 nvmem-cell-names = "temp_adjust";
748 #thermal-sensor-cells = <1>;
749 hw-shut-temp = <95000>;
753 gmac: ethernet@ff290000 {
754 compatible = "rockchip,rk3368-gmac";
755 reg = <0x0 0xff290000 0x0 0x10000>;
756 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
757 interrupt-names = "macirq";
758 rockchip,grf = <&grf>;
759 clocks = <&cru SCLK_MAC>,
760 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
761 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
762 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
763 clock-names = "stmmaceth",
764 "mac_clk_rx", "mac_clk_tx",
765 "clk_mac_ref", "clk_mac_refout",
766 "aclk_mac", "pclk_mac";
770 nandc0: nandc@ff400000 {
771 compatible = "rockchip,rk-nandc";
772 reg = <0x0 0xff400000 0x0 0x4000>;
773 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
776 clock-names = "clk_nandc", "hclk_nandc";
780 usb_host0_ehci: usb@ff500000 {
781 compatible = "generic-ehci";
782 reg = <0x0 0xff500000 0x0 0x20000>;
783 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&cru HCLK_HOST0>, <&u2phy>;
785 clock-names = "usbhost", "utmi";
786 phys = <&u2phy_host>;
791 usb_host0_ohci: usb@ff520000 {
792 compatible = "generic-ohci";
793 reg = <0x0 0xff520000 0x0 0x20000>;
794 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&cru HCLK_HOST0>, <&u2phy>;
796 clock-names = "usbhost", "utmi";
797 phys = <&u2phy_host>;
802 usb_otg: usb@ff580000 {
803 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
805 reg = <0x0 0xff580000 0x0 0x40000>;
806 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&cru HCLK_OTG0>;
810 g-np-tx-fifo-size = <16>;
811 g-rx-fifo-size = <275>;
812 g-tx-fifo-size = <256 128 128 64 64 32>;
817 ddrpctl: syscon@ff610000 {
818 compatible = "rockchip,rk3368-ddrpctl", "syscon";
819 reg = <0x0 0xff610000 0x0 0x400>;
823 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
824 reg = <0x0 0xff660000 0x0 0x1000>;
825 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
826 #address-cells = <1>;
829 clocks = <&cru PCLK_I2C1>;
830 pinctrl-names = "default";
831 pinctrl-0 = <&i2c1_xfer>;
836 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
837 reg = <0x0 0xff680000 0x0 0x10>;
839 pinctrl-names = "default";
840 pinctrl-0 = <&pwm0_pin>;
841 clocks = <&cru PCLK_PWM1>;
847 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
848 reg = <0x0 0xff680010 0x0 0x10>;
850 pinctrl-names = "default";
851 pinctrl-0 = <&pwm1_pin>;
852 clocks = <&cru PCLK_PWM1>;
858 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
859 reg = <0x0 0xff680020 0x0 0x10>;
861 clocks = <&cru PCLK_PWM1>;
867 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
868 reg = <0x0 0xff680030 0x0 0x10>;
870 pinctrl-names = "default";
871 pinctrl-0 = <&pwm3_pin>;
872 clocks = <&cru PCLK_PWM1>;
877 uart2: serial@ff690000 {
878 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
879 reg = <0x0 0xff690000 0x0 0x100>;
880 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
881 clock-names = "baudclk", "apb_pclk";
882 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
883 pinctrl-names = "default";
884 pinctrl-0 = <&uart2_xfer>;
890 mbox: mbox@ff6b0000 {
891 compatible = "rockchip,rk3368-mailbox";
892 reg = <0x0 0xff6b0000 0x0 0x1000>;
893 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
894 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
895 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
896 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&cru PCLK_MAILBOX>;
898 clock-names = "pclk_mailbox";
903 mailbox: mailbox@ff6b0000 {
904 compatible = "rockchip,rk3368-mbox-legacy";
905 reg = <0x0 0xff6b0000 0x0 0x1000>,
906 <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
907 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
908 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
910 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&cru PCLK_MAILBOX>;
912 clock-names = "pclk_mailbox";
917 mailbox_scpi: mailbox-scpi {
918 compatible = "rockchip,rk3368-scpi-legacy";
919 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
924 qos_iep: qos@ffad0000 {
925 compatible = "syscon";
926 reg = <0x0 0xffad0000 0x0 0x20>;
929 qos_isp_r0: qos@ffad0080 {
930 compatible = "syscon";
931 reg = <0x0 0xffad0080 0x0 0x20>;
934 qos_isp_r1: qos@ffad0100 {
935 compatible = "syscon";
936 reg = <0x0 0xffad0100 0x0 0x20>;
939 qos_isp_w0: qos@ffad0180 {
940 compatible = "syscon";
941 reg = <0x0 0xffad0180 0x0 0x20>;
944 qos_isp_w1: qos@ffad0200 {
945 compatible = "syscon";
946 reg = <0x0 0xffad0200 0x0 0x20>;
949 qos_vip: qos@ffad0280 {
950 compatible = "syscon";
951 reg = <0x0 0xffad0280 0x0 0x20>;
954 qos_vop: qos@ffad0300 {
955 compatible = "syscon";
956 reg = <0x0 0xffad0300 0x0 0x20>;
959 qos_rga_r: qos@ffad0380 {
960 compatible = "syscon";
961 reg = <0x0 0xffad0380 0x0 0x20>;
964 qos_rga_w: qos@ffad0400 {
965 compatible = "syscon";
966 reg = <0x0 0xffad0400 0x0 0x20>;
969 qos_hevc_r: qos@ffae0000 {
970 compatible = "syscon";
971 reg = <0x0 0xffae0000 0x0 0x20>;
974 qos_vpu_r: qos@ffae0100 {
975 compatible = "syscon";
976 reg = <0x0 0xffae0100 0x0 0x20>;
979 qos_vpu_w: qos@ffae0180 {
980 compatible = "syscon";
981 reg = <0x0 0xffae0180 0x0 0x20>;
984 qos_gpu: qos@ffaf0000 {
985 compatible = "syscon";
986 reg = <0x0 0xffaf0000 0x0 0x20>;
989 pmu: power-management@ff730000 {
990 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
991 reg = <0x0 0xff730000 0x0 0x1000>;
993 power: power-controller {
994 compatible = "rockchip,rk3368-power-controller";
995 #power-domain-cells = <1>;
996 #address-cells = <1>;
1000 * Note: Although SCLK_* are the working clocks
1001 * of device without including on the NOC, needed for
1002 * synchronous reset.
1004 * The clocks on the which NOC:
1005 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
1006 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
1007 * ACLK_RGA is on ACLK_RGA_NIU.
1008 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
1010 * Which clock are device clocks:
1012 * *_IEP IEP:Image Enhancement Processor
1013 * *_ISP ISP:Image Signal Processing
1014 * *_VIP VIP:Video Input Processor
1015 * *_VOP* VOP:Visual Output Processor
1023 reg = <RK3368_PD_VIO>;
1024 clocks = <&cru ACLK_IEP>,
1029 <&cru ACLK_VOP_IEP>,
1036 <&cru HCLK_VIO_HDCPMMU>,
1037 <&cru PCLK_EDP_CTRL>,
1038 <&cru PCLK_HDMI_CTRL>,
1043 <&cru PCLK_DPHYTX0>,
1044 <&cru PCLK_MIPI_CSI>,
1045 <&cru PCLK_MIPI_DSI0>,
1046 <&cru SCLK_VOP0_PWM>,
1047 <&cru SCLK_EDP_24M>,
1052 <&cru SCLK_HDMI_CEC>,
1053 <&cru SCLK_HDMI_HDCP>;
1054 pm_qos = <&qos_iep>,
1065 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
1066 * (video endecoder & decoder) clocks that on the
1067 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
1070 reg = <RK3368_PD_VIDEO>;
1071 clocks = <&cru ACLK_VIDEO>,
1073 <&cru SCLK_HEVC_CABAC>,
1074 <&cru SCLK_HEVC_CORE>;
1075 pm_qos = <&qos_hevc_r>,
1080 * Note: ACLK_GPU is the GPU clock,
1081 * and on the ACLK_GPU_NIU (NOC).
1084 reg = <RK3368_PD_GPU_1>;
1085 clocks = <&cru ACLK_GPU_CFG>,
1086 <&cru ACLK_GPU_MEM>,
1087 <&cru SCLK_GPU_CORE>;
1088 pm_qos = <&qos_gpu>;
1093 pmugrf: syscon@ff738000 {
1094 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
1095 reg = <0x0 0xff738000 0x0 0x1000>;
1097 pmu_io_domains: io-domains {
1098 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
1099 status = "disabled";
1103 compatible = "syscon-reboot-mode";
1105 mode-normal = <BOOT_NORMAL>;
1106 mode-recovery = <BOOT_RECOVERY>;
1107 mode-bootloader = <BOOT_FASTBOOT>;
1108 mode-loader = <BOOT_BL_DOWNLOAD>;
1112 cru: clock-controller@ff760000 {
1113 compatible = "rockchip,rk3368-cru";
1114 reg = <0x0 0xff760000 0x0 0x1000>;
1115 rockchip,grf = <&grf>;
1119 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1120 <&cru ACLK_BUS>, <&cru ACLK_PERI>,
1121 <&cru HCLK_BUS>, <&cru HCLK_PERI>,
1122 <&cru PCLK_BUS>, <&cru PCLK_PERI>;
1123 assigned-clock-rates =
1124 <576000000>, <400000000>,
1125 <300000000>, <300000000>,
1126 <150000000>, <150000000>,
1127 <75000000>, <75000000>;
1130 grf: syscon@ff770000 {
1131 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
1132 reg = <0x0 0xff770000 0x0 0x1000>;
1133 #address-cells = <1>;
1137 compatible = "rockchip,rk3368-dp-phy";
1138 clocks = <&cru SCLK_EDP_24M>;
1139 clock-names = "24m";
1140 resets = <&cru SRST_EDP_24M>;
1141 reset-names = "edp_24m";
1143 status = "disabled";
1146 io_domains: io-domains {
1147 compatible = "rockchip,rk3368-io-voltage-domain";
1148 status = "disabled";
1151 u2phy: usb2-phy@700 {
1152 compatible = "rockchip,rk3368-usb2phy";
1154 clocks = <&cru SCLK_OTGPHY0>;
1155 clock-names = "phyclk";
1157 clock-output-names = "usbotg_out";
1158 assigned-clocks = <&cru SCLK_USBPHY480M>;
1159 assigned-clock-parents = <&u2phy>;
1160 status = "disabled";
1162 u2phy_host: host-port {
1164 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1165 interrupt-names = "linestate";
1166 status = "disabled";
1171 wdt: watchdog@ff800000 {
1172 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
1173 reg = <0x0 0xff800000 0x0 0x100>;
1174 clocks = <&cru PCLK_WDT>;
1175 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1176 status = "disabled";
1180 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
1181 reg = <0x0 0xff810000 0x0 0x20>;
1182 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1185 i2s_2ch: i2s-2ch@ff890000 {
1186 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1187 reg = <0x0 0xff890000 0x0 0x1000>;
1188 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1189 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1190 dma-names = "tx", "rx";
1191 clock-names = "i2s_clk", "i2s_hclk";
1192 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1193 status = "disabled";
1196 i2s_8ch: i2s-8ch@ff898000 {
1197 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1198 reg = <0x0 0xff898000 0x0 0x1000>;
1199 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1200 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1201 dma-names = "tx", "rx";
1202 clock-names = "i2s_clk", "i2s_hclk";
1203 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1204 pinctrl-names = "default";
1205 pinctrl-0 = <&i2s_8ch_bus>;
1206 status = "disabled";
1210 compatible = "rockchip,rk3368-isp", "rockchip,isp";
1211 reg = <0x0 0xff910000 0x0 0x4000>;
1212 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1213 power-domains = <&power RK3368_PD_VIO>;
1215 <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1216 <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
1217 <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
1218 <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
1220 "aclk_isp", "hclk_isp", "clk_isp",
1221 "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1222 "clk_cif_pll", "hclk_mipiphy1",
1223 "pclk_dphyrx", "clk_vio0_noc";
1226 "default", "isp_dvp8bit2", "isp_dvp10bit",
1227 "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4",
1228 "isp_mipi_fl", "isp_mipi_fl_prefl",
1229 "isp_flash_as_gpio", "isp_flash_as_trigger_out";
1230 pinctrl-0 = <&cif_clkout>;
1231 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1232 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1233 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1234 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1235 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
1236 pinctrl-6 = <&cif_clkout>;
1237 pinctrl-7 = <&cif_clkout &isp_prelight>;
1238 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
1239 pinctrl-9 = <&isp_flash_trigger>;
1240 rockchip,isp,mipiphy = <2>;
1241 rockchip,isp,cifphy = <1>;
1242 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1243 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1244 rockchip,grf = <&grf>;
1245 rockchip,cru = <&cru>;
1246 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
1247 rockchip,isp,iommu-enable = <1>;
1248 iommus = <&isp_mmu>;
1249 status = "disabled";
1252 isp_mmu: iommu@ff914000 {
1253 compatible = "rockchip,iommu";
1254 reg = <0x0 0xff914000 0x0 0x100>,
1255 <0x0 0xff915000 0x0 0x100>;
1256 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1257 interrupt-names = "isp_mmu";
1258 clocks = <&cru ACLK_RGA>, <&cru HCLK_ISP>;
1259 clock-names = "aclk", "hclk";
1260 rk_iommu,disable_reset_quirk;
1262 power-domains = <&power RK3368_PD_VIO>;
1263 status = "disabled";
1267 compatible = "rockchip,rk3368-vop";
1268 reg = <0x0 0xff930000 0x0 0x2fc>;
1269 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1270 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1271 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1272 assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1273 assigned-clock-rates = <400000000>, <200000000>;
1274 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1275 reset-names = "axi", "ahb", "dclk";
1276 power-domains = <&power RK3368_PD_VIO>;
1277 iommus = <&vop_mmu>;
1278 status = "disabled";
1281 #address-cells = <1>;
1284 vop_out_mipi: endpoint@0 {
1286 remote-endpoint = <&mipi_in_vop>;
1289 vop_out_edp: endpoint@1 {
1291 remote-endpoint = <&edp_in_vop>;
1296 display_subsystem: display-subsystem {
1297 compatible = "rockchip,display-subsystem";
1299 status = "disabled";
1302 vop_mmu: iommu@ff930300 {
1303 compatible = "rockchip,iommu";
1304 reg = <0x0 0xff930300 0x0 0x100>;
1305 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1306 interrupt-names = "vop_mmu";
1307 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1308 clock-names = "aclk", "hclk";
1309 power-domains = <&power RK3368_PD_VIO>;
1311 status = "disabled";
1314 mipi_dsi_host: mipi-dsi-host@ff960000 {
1315 compatible = "rockchip,rk3368-mipi-dsi";
1316 reg = <0x0 0xff960000 0x0 0x4000>;
1317 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1318 clocks = <&cru PCLK_MIPI_DSI0>;
1319 clock-names = "pclk";
1320 phys = <&mipi_dphy>;
1321 phy-names = "mipi_dphy";
1322 rockchip,grf = <&grf>;
1323 power-domains = <&power RK3368_PD_VIO>;
1324 #address-cells = <1>;
1326 status = "disabled";
1329 #address-cells = <1>;
1334 #address-cells = <1>;
1337 mipi_in_vop: endpoint@0 {
1339 remote-endpoint = <&vop_out_mipi>;
1345 mipi_dphy: mipi-dphy@ff968000 {
1346 compatible = "rockchip,rk3368-mipi-dphy";
1347 reg = <0x0 0xff968000 0x0 0x4000>;
1349 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
1350 clock-names = "ref", "pclk";
1351 status = "disabled";
1355 compatible = "rockchip,rk3368-edp";
1356 reg = <0x0 0xff970000 0x0 0x8000>;
1357 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1358 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1359 clock-names = "dp", "pclk";
1360 resets = <&cru SRST_EDP>;
1362 power-domains = <&power RK3368_PD_VIO>;
1363 rockchip,grf = <&grf>;
1366 pinctrl-names = "default";
1367 pinctrl-0 = <&edp_hpd>;
1368 status = "disabled";
1371 #address-cells = <1>;
1377 edp_in_vop: endpoint {
1378 remote-endpoint = <&vop_out_edp>;
1384 hevc_mmu: iommu@ff9a0440 {
1385 compatible = "rockchip,iommu";
1386 reg = <0x0 0xff9a0440 0x0 0x40>,
1387 <0x0 0xff9a0480 0x0 0x40>;
1388 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1389 interrupt-names = "hevc_mmu";
1390 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1391 clock-names = "aclk", "hclk";
1392 power-domains = <&power RK3368_PD_VIDEO>;
1394 status = "disabled";
1397 vpu_mmu: iommu@ff9a0800 {
1398 compatible = "rockchip,iommu";
1399 reg = <0x0 0xff9a0800 0x0 0x100>;
1400 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1401 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1402 interrupt-names = "vepu_mmu", "vdpu_mmu";
1403 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1404 clock-names = "aclk", "hclk";
1405 power-domains = <&power RK3368_PD_VIDEO>;
1407 status = "disabled";
1411 compatible = "rockchip,vpu_sub";
1412 iommu_enabled = <1>;
1413 iommus = <&vpu_mmu>;
1414 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1415 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1416 interrupt-names = "irq_enc","irq_dec";
1418 name = "vpu_service";
1422 hevc: hevc_service {
1423 compatible = "rockchip,hevc_sub";
1424 iommu_enabled = <1>;
1425 iommus = <&hevc_mmu>;
1426 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1427 interrupt-names = "irq_dec";
1429 name = "hevc_service";
1433 vpu_combo: vpu_combo@ff9a0000 {
1434 compatible = "rockchip,vpu_combo";
1435 reg = <0x0 0xff9a0000 0x0 0x440>;
1436 rockchip,grf = <&grf>;
1438 rockchip,sub = <&vpu>, <&hevc>;
1439 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>,
1440 <&cru SCLK_HEVC_CORE>, <&cru SCLK_HEVC_CABAC>;
1441 clock-names = "aclk_vcodec", "hclk_vcodec",
1442 "clk_core", "clk_cabac";
1443 resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>,
1445 reset-names = "video_a", "video_h", "video";
1447 mode_ctrl = <0x418>;
1449 power-domains = <&power RK3368_PD_VIDEO>;
1450 status = "disabled";
1453 gic: interrupt-controller@ffb71000 {
1454 compatible = "arm,gic-400";
1455 interrupt-controller;
1456 #interrupt-cells = <3>;
1457 #address-cells = <0>;
1459 reg = <0x0 0xffb71000 0x0 0x1000>,
1460 <0x0 0xffb72000 0x0 0x2000>,
1461 <0x0 0xffb74000 0x0 0x2000>,
1462 <0x0 0xffb76000 0x0 0x2000>;
1463 interrupts = <GIC_PPI 9
1464 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1467 gpu: rogue-g6110@ffa30000 {
1468 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1469 reg = <0x0 0xffa30000 0x0 0x10000>;
1471 <&cru SCLK_GPU_CORE>,
1472 <&cru ACLK_GPU_MEM>,
1473 <&cru ACLK_GPU_CFG>;
1478 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1479 interrupt-names = "rogue-g6110-irq";
1480 power-domains = <&power RK3368_PD_GPU_1>;
1481 operating-points-v2 = <&gpu_opp_table>;
1482 #cooling-cells = <2>; /* min followed by max */
1483 gpu_power_model: power_model {
1484 compatible = "arm,mali-simple-power-model";
1487 static-power = <300>;
1488 dynamic-power = <396>;
1489 ts = <32000 4700 (-80) 2>;
1490 thermal-zone = "gpu-thermal";
1494 gpu_opp_table: gpu_opp_table {
1495 compatible = "operating-points-v2";
1499 opp-hz = /bits/ 64 <200000000>;
1500 opp-microvolt = <1100000>;
1503 opp-hz = /bits/ 64 <288000000>;
1504 opp-microvolt = <1100000>;
1507 opp-hz = /bits/ 64 <400000000>;
1508 opp-microvolt = <1100000>;
1511 opp-hz = /bits/ 64 <576000000>;
1512 opp-microvolt = <1200000>;
1516 efuse: efuse@ffb00000 {
1517 compatible = "rockchip,rk3368-efuse";
1518 reg = <0x0 0xffb00000 0x0 0x20>;
1519 #address-cells = <1>;
1521 clocks = <&cru PCLK_EFUSE256>;
1522 clock-names = "pclk_efuse";
1525 cpu_leakage: cpu-leakage@17 {
1528 temp_adjust: temp-adjust@1f {
1534 compatible = "rockchip,rk3368-pinctrl";
1535 rockchip,grf = <&grf>;
1536 rockchip,pmu = <&pmugrf>;
1537 #address-cells = <0x2>;
1538 #size-cells = <0x2>;
1541 gpio0: gpio0@ff750000 {
1542 compatible = "rockchip,gpio-bank";
1543 reg = <0x0 0xff750000 0x0 0x100>;
1544 clocks = <&cru PCLK_GPIO0>;
1545 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1548 #gpio-cells = <0x2>;
1550 interrupt-controller;
1551 #interrupt-cells = <0x2>;
1554 gpio1: gpio1@ff780000 {
1555 compatible = "rockchip,gpio-bank";
1556 reg = <0x0 0xff780000 0x0 0x100>;
1557 clocks = <&cru PCLK_GPIO1>;
1558 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1561 #gpio-cells = <0x2>;
1563 interrupt-controller;
1564 #interrupt-cells = <0x2>;
1567 gpio2: gpio2@ff790000 {
1568 compatible = "rockchip,gpio-bank";
1569 reg = <0x0 0xff790000 0x0 0x100>;
1570 clocks = <&cru PCLK_GPIO2>;
1571 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1574 #gpio-cells = <0x2>;
1576 interrupt-controller;
1577 #interrupt-cells = <0x2>;
1580 gpio3: gpio3@ff7a0000 {
1581 compatible = "rockchip,gpio-bank";
1582 reg = <0x0 0xff7a0000 0x0 0x100>;
1583 clocks = <&cru PCLK_GPIO3>;
1584 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1587 #gpio-cells = <0x2>;
1589 interrupt-controller;
1590 #interrupt-cells = <0x2>;
1593 pcfg_pull_up: pcfg-pull-up {
1597 pcfg_pull_down: pcfg-pull-down {
1601 pcfg_pull_none: pcfg-pull-none {
1605 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1607 drive-strength = <12>;
1612 rockchip,pins = <2 23 RK_FUNC_2 &pcfg_pull_none>;
1617 emmc_clk: emmc-clk {
1618 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1621 emmc_cmd: emmc-cmd {
1622 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1625 emmc_pwr: emmc-pwr {
1626 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1629 emmc_bus1: emmc-bus1 {
1630 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1633 emmc_bus4: emmc-bus4 {
1634 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1635 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1636 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1637 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1640 emmc_bus8: emmc-bus8 {
1641 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1642 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1643 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1644 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1645 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1646 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1647 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1648 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1653 rgmii_pins: rgmii-pins {
1654 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1655 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1656 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1657 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1658 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1659 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1660 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1661 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1662 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1663 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1664 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1665 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1666 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1667 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1668 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1671 rmii_pins: rmii-pins {
1672 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1673 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1674 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1675 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1676 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1677 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1678 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1679 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1680 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1681 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1686 i2c0_xfer: i2c0-xfer {
1687 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1688 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1693 i2c1_xfer: i2c1-xfer {
1694 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1695 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1700 i2c2_xfer: i2c2-xfer {
1701 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1702 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1707 i2c3_xfer: i2c3-xfer {
1708 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1709 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1714 i2c4_xfer: i2c4-xfer {
1715 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1716 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1721 i2c5_xfer: i2c5-xfer {
1722 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1723 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1728 i2s_8ch_bus: i2s-8ch-bus {
1729 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1730 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1731 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1732 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1733 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1734 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1735 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1736 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1737 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1742 pwm0_pin: pwm0-pin {
1743 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1746 vop_pwm_pin: vop-pwm {
1747 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1752 pwm1_pin: pwm1-pin {
1753 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1758 pwm3_pin: pwm3-pin {
1759 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1764 sdio0_bus1: sdio0-bus1 {
1765 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1768 sdio0_bus4: sdio0-bus4 {
1769 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1770 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1771 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1772 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1775 sdio0_cmd: sdio0-cmd {
1776 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1779 sdio0_clk: sdio0-clk {
1780 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1783 sdio0_cd: sdio0-cd {
1784 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1787 sdio0_wp: sdio0-wp {
1788 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1791 sdio0_pwr: sdio0-pwr {
1792 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1795 sdio0_bkpwr: sdio0-bkpwr {
1796 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1799 sdio0_int: sdio0-int {
1800 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1805 sdmmc_clk: sdmmc-clk {
1806 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1809 sdmmc_cmd: sdmmc-cmd {
1810 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1813 sdmmc_cd: sdmmc-cd {
1814 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1817 sdmmc_bus1: sdmmc-bus1 {
1818 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1821 sdmmc_bus4: sdmmc-bus4 {
1822 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1823 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1824 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1825 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1830 spi0_clk: spi0-clk {
1831 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1833 spi0_cs0: spi0-cs0 {
1834 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1836 spi0_cs1: spi0-cs1 {
1837 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1840 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1843 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1848 spi1_clk: spi1-clk {
1849 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1851 spi1_cs0: spi1-cs0 {
1852 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1854 spi1_cs1: spi1-cs1 {
1855 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1858 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1861 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1866 spi2_clk: spi2-clk {
1867 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1869 spi2_cs0: spi2-cs0 {
1870 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1873 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1876 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1881 uart0_xfer: uart0-xfer {
1882 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1883 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1886 uart0_cts: uart0-cts {
1887 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1890 uart0_rts: uart0-rts {
1891 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1896 uart1_xfer: uart1-xfer {
1897 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1898 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1901 uart1_cts: uart1-cts {
1902 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1905 uart1_rts: uart1-rts {
1906 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1911 uart2_xfer: uart2-xfer {
1912 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1913 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1915 /* no rts / cts for uart2 */
1919 uart3_xfer: uart3-xfer {
1920 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1921 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1924 uart3_cts: uart3-cts {
1925 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1928 uart3_rts: uart3-rts {
1929 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1934 uart4_xfer: uart4-xfer {
1935 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1936 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1939 uart4_cts: uart4-cts {
1940 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1943 uart4_rts: uart4-rts {
1944 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1949 cif_clkout: cif-clkout {
1950 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1953 isp_dvp_d2d9: isp-dvp-d2d9 {
1955 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1956 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1957 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1958 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1959 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1960 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1961 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1962 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1963 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1964 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1965 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1966 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1969 isp_dvp_d0d1: isp-dvp-d0d1 {
1971 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1972 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1975 isp_dvp_d10d11:isp_d10d11 {
1977 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1978 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1981 isp_dvp_d0d7: isp-dvp-d0d7 {
1983 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1984 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1985 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1986 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1987 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1988 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1989 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1990 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1993 isp_dvp_d4d11: isp-dvp-d4d11 {
1995 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1996 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1997 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1998 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1999 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2000 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2001 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2002 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2005 isp_shutter: isp-shutter {
2007 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2008 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2011 isp_flash_trigger: isp-flash-trigger {
2012 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2015 isp_prelight: isp-prelight {
2016 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2019 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2020 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU