2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
49 #include <dt-bindings/display/mipi_dsi.h>
50 #include <dt-bindings/power/rk3368-power.h>
51 #include <dt-bindings/soc/rockchip_boot-mode.h>
54 compatible = "rockchip,rk3368";
55 interrupt-parent = <&gic>;
78 #address-cells = <0x2>;
114 entry-method = "psci";
116 cpu_sleep: cpu-sleep-0 {
117 compatible = "arm,idle-state";
118 arm,psci-suspend-param = <0x1010000>;
119 entry-latency-us = <0x3fffffff>;
120 exit-latency-us = <0x40000000>;
121 min-residency-us = <0xffffffff>;
127 compatible = "arm,cortex-a53", "arm,armv8";
129 cpu-idle-states = <&cpu_sleep>;
130 enable-method = "psci";
131 clocks = <&cru ARMCLKL>;
132 operating-points-v2 = <&cluster1_opp>;
137 compatible = "arm,cortex-a53", "arm,armv8";
139 cpu-idle-states = <&cpu_sleep>;
140 enable-method = "psci";
141 clocks = <&cru ARMCLKL>;
142 operating-points-v2 = <&cluster1_opp>;
147 compatible = "arm,cortex-a53", "arm,armv8";
149 cpu-idle-states = <&cpu_sleep>;
150 enable-method = "psci";
151 clocks = <&cru ARMCLKL>;
152 operating-points-v2 = <&cluster1_opp>;
157 compatible = "arm,cortex-a53", "arm,armv8";
159 cpu-idle-states = <&cpu_sleep>;
160 enable-method = "psci";
161 clocks = <&cru ARMCLKL>;
162 operating-points-v2 = <&cluster1_opp>;
167 compatible = "arm,cortex-a53", "arm,armv8";
169 cpu-idle-states = <&cpu_sleep>;
170 enable-method = "psci";
171 clocks = <&cru ARMCLKB>;
172 operating-points-v2 = <&cluster0_opp>;
177 compatible = "arm,cortex-a53", "arm,armv8";
179 cpu-idle-states = <&cpu_sleep>;
180 enable-method = "psci";
181 clocks = <&cru ARMCLKB>;
182 operating-points-v2 = <&cluster0_opp>;
187 compatible = "arm,cortex-a53", "arm,armv8";
189 cpu-idle-states = <&cpu_sleep>;
190 enable-method = "psci";
191 clocks = <&cru ARMCLKB>;
192 operating-points-v2 = <&cluster0_opp>;
197 compatible = "arm,cortex-a53", "arm,armv8";
199 cpu-idle-states = <&cpu_sleep>;
200 enable-method = "psci";
201 clocks = <&cru ARMCLKB>;
202 operating-points-v2 = <&cluster0_opp>;
206 cluster0_opp: opp_table0 {
207 compatible = "operating-points-v2";
211 opp-hz = /bits/ 64 <408000000>;
212 opp-microvolt = <1200000>;
213 clock-latency-ns = <40000>;
217 opp-hz = /bits/ 64 <600000000>;
218 opp-microvolt = <1200000>;
221 opp-hz = /bits/ 64 <816000000>;
222 opp-microvolt = <1200000>;
225 opp-hz = /bits/ 64 <1008000000>;
226 opp-microvolt = <1200000>;
229 opp-hz = /bits/ 64 <1200000000>;
230 opp-microvolt = <1200000>;
234 cluster1_opp: opp_table1 {
235 compatible = "operating-points-v2";
239 opp-hz = /bits/ 64 <408000000>;
240 opp-microvolt = <1200000>;
241 clock-latency-ns = <40000>;
245 opp-hz = /bits/ 64 <600000000>;
246 opp-microvolt = <1200000>;
249 opp-hz = /bits/ 64 <816000000>;
250 opp-microvolt = <1200000>;
253 opp-hz = /bits/ 64 <1008000000>;
254 opp-microvolt = <1200000>;
259 compatible = "arm,armv8-pmuv3";
260 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
268 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
269 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
270 <&cpu_b2>, <&cpu_b3>;
274 compatible = "arm,amba-bus";
275 #address-cells = <2>;
279 dmac_peri: dma-controller@ff250000 {
280 compatible = "arm,pl330", "arm,primecell";
281 reg = <0x0 0xff250000 0x0 0x4000>;
282 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&cru ACLK_DMAC_PERI>;
286 clock-names = "apb_pclk";
287 arm,pl330-broken-no-flushp;
288 peripherals-req-type-burst;
291 dmac_bus: dma-controller@ff600000 {
292 compatible = "arm,pl330", "arm,primecell";
293 reg = <0x0 0xff600000 0x0 0x4000>;
294 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&cru ACLK_DMAC_BUS>;
298 clock-names = "apb_pclk";
299 arm,pl330-broken-no-flushp;
300 peripherals-req-type-burst;
305 compatible = "arm,psci-0.2";
310 compatible = "arm,armv8-timer";
311 interrupts = <GIC_PPI 13
312 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
314 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
316 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
318 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
322 compatible = "fixed-clock";
323 clock-frequency = <24000000>;
324 clock-output-names = "xin24m";
328 sdmmc: rksdmmc@ff0c0000 {
329 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
330 reg = <0x0 0xff0c0000 0x0 0x4000>;
331 clock-freq-min-max = <400000 150000000>;
332 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
333 clock-names = "biu", "ciu";
334 fifo-depth = <0x100>;
335 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
339 sdio0: dwmmc@ff0d0000 {
340 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
341 reg = <0x0 0xff0d0000 0x0 0x4000>;
342 clock-freq-min-max = <400000 150000000>;
343 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
344 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
345 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
346 fifo-depth = <0x100>;
347 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
351 emmc: rksdmmc@ff0f0000 {
352 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
353 reg = <0x0 0xff0f0000 0x0 0x4000>;
354 clock-freq-min-max = <400000 150000000>;
355 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
356 clock-names = "biu", "ciu";
357 fifo-depth = <0x100>;
358 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
362 saradc: saradc@ff100000 {
363 compatible = "rockchip,saradc";
364 reg = <0x0 0xff100000 0x0 0x100>;
365 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
366 #io-channel-cells = <1>;
367 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
368 clock-names = "saradc", "apb_pclk";
373 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
374 reg = <0x0 0xff110000 0x0 0x1000>;
375 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
376 clock-names = "spiclk", "apb_pclk";
377 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
378 pinctrl-names = "default";
379 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
380 #address-cells = <1>;
386 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
387 reg = <0x0 0xff120000 0x0 0x1000>;
388 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
389 clock-names = "spiclk", "apb_pclk";
390 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
393 #address-cells = <1>;
399 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
400 reg = <0x0 0xff130000 0x0 0x1000>;
401 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
402 clock-names = "spiclk", "apb_pclk";
403 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
404 pinctrl-names = "default";
405 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
406 #address-cells = <1>;
412 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
413 reg = <0x0 0xff650000 0x0 0x1000>;
414 clocks = <&cru PCLK_I2C0>;
416 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
417 pinctrl-names = "default";
418 pinctrl-0 = <&i2c0_xfer>;
419 #address-cells = <1>;
425 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
426 reg = <0x0 0xff140000 0x0 0x1000>;
427 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
428 #address-cells = <1>;
431 clocks = <&cru PCLK_I2C2>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&i2c2_xfer>;
438 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
439 reg = <0x0 0xff150000 0x0 0x1000>;
440 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
441 #address-cells = <1>;
444 clocks = <&cru PCLK_I2C3>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&i2c3_xfer>;
451 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
452 reg = <0x0 0xff160000 0x0 0x1000>;
453 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
454 #address-cells = <1>;
457 clocks = <&cru PCLK_I2C4>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&i2c4_xfer>;
464 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
465 reg = <0x0 0xff170000 0x0 0x1000>;
466 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
467 #address-cells = <1>;
470 clocks = <&cru PCLK_I2C5>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&i2c5_xfer>;
476 uart0: serial@ff180000 {
477 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
478 reg = <0x0 0xff180000 0x0 0x100>;
479 clock-frequency = <24000000>;
480 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
481 clock-names = "baudclk", "apb_pclk";
482 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
488 uart1: serial@ff190000 {
489 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
490 reg = <0x0 0xff190000 0x0 0x100>;
491 clock-frequency = <24000000>;
492 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
493 clock-names = "baudclk", "apb_pclk";
494 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
500 uart3: serial@ff1b0000 {
501 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
502 reg = <0x0 0xff1b0000 0x0 0x100>;
503 clock-frequency = <24000000>;
504 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
505 clock-names = "baudclk", "apb_pclk";
506 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
512 uart4: serial@ff1c0000 {
513 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
514 reg = <0x0 0xff1c0000 0x0 0x100>;
515 clock-frequency = <24000000>;
516 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
517 clock-names = "baudclk", "apb_pclk";
518 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
524 gmac: ethernet@ff290000 {
525 compatible = "rockchip,rk3368-gmac";
526 reg = <0x0 0xff290000 0x0 0x10000>;
527 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
528 interrupt-names = "macirq";
529 rockchip,grf = <&grf>;
530 clocks = <&cru SCLK_MAC>,
531 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
532 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
533 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
534 clock-names = "stmmaceth",
535 "mac_clk_rx", "mac_clk_tx",
536 "clk_mac_ref", "clk_mac_refout",
537 "aclk_mac", "pclk_mac";
541 nandc0: nandc@ff400000 {
542 compatible = "rockchip,rk-nandc";
543 reg = <0x0 0xff400000 0x0 0x4000>;
544 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
547 clock-names = "clk_nandc", "hclk_nandc";
551 usb_host0_ehci: usb@ff500000 {
552 compatible = "generic-ehci";
553 reg = <0x0 0xff500000 0x0 0x100>;
554 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&cru HCLK_HOST0>;
556 clock-names = "usbhost";
560 usb_otg: usb@ff580000 {
561 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
563 reg = <0x0 0xff580000 0x0 0x40000>;
564 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&cru HCLK_OTG0>;
568 g-np-tx-fifo-size = <16>;
569 g-rx-fifo-size = <275>;
570 g-tx-fifo-size = <256 128 128 64 64 32>;
575 ddrpctl: syscon@ff610000 {
576 compatible = "rockchip,rk3368-ddrpctl", "syscon";
577 reg = <0x0 0xff610000 0x0 0x400>;
581 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
582 reg = <0x0 0xff660000 0x0 0x1000>;
583 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
584 #address-cells = <1>;
587 clocks = <&cru PCLK_I2C1>;
588 pinctrl-names = "default";
589 pinctrl-0 = <&i2c1_xfer>;
594 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
595 reg = <0x0 0xff680000 0x0 0x10>;
597 pinctrl-names = "default";
598 pinctrl-0 = <&pwm0_pin>;
599 clocks = <&cru PCLK_PWM1>;
605 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
606 reg = <0x0 0xff680010 0x0 0x10>;
608 pinctrl-names = "default";
609 pinctrl-0 = <&pwm1_pin>;
610 clocks = <&cru PCLK_PWM1>;
616 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
617 reg = <0x0 0xff680020 0x0 0x10>;
619 clocks = <&cru PCLK_PWM1>;
625 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
626 reg = <0x0 0xff680030 0x0 0x10>;
628 pinctrl-names = "default";
629 pinctrl-0 = <&pwm3_pin>;
630 clocks = <&cru PCLK_PWM1>;
635 uart2: serial@ff690000 {
636 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
637 reg = <0x0 0xff690000 0x0 0x100>;
638 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
639 clock-names = "baudclk", "apb_pclk";
640 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
641 pinctrl-names = "default";
642 pinctrl-0 = <&uart2_xfer>;
648 pmu: power-management@ff730000 {
649 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
650 reg = <0x0 0xff730000 0x0 0x1000>;
652 power: power-controller {
654 compatible = "rockchip,rk3368-power-controller";
655 #power-domain-cells = <1>;
656 #address-cells = <1>;
660 * Note: Although SCLK_* are the working clocks
661 * of device without including on the NOC, needed for
664 * The clocks on the which NOC:
665 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
666 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
667 * ACLK_RGA is on ACLK_RGA_NIU.
668 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
670 * Which clock are device clocks:
672 * *_IEP IEP:Image Enhancement Processor
673 * *_ISP ISP:Image Signal Processing
674 * *_VIP VIP:Video Input Processor
675 * *_VOP* VOP:Visual Output Processor
683 reg = <RK3368_PD_VIO>;
684 clocks = <&cru ACLK_IEP>,
696 <&cru HCLK_VIO_HDCPMMU>,
697 <&cru PCLK_EDP_CTRL>,
698 <&cru PCLK_HDMI_CTRL>,
704 <&cru PCLK_MIPI_CSI>,
705 <&cru PCLK_MIPI_DSI0>,
706 <&cru SCLK_VOP0_PWM>,
712 <&cru SCLK_HDMI_CEC>,
713 <&cru SCLK_HDMI_HDCP>;
716 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
717 * (video endecoder & decoder) clocks that on the
718 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
721 reg = <RK3368_PD_VIDEO>;
722 clocks = <&cru ACLK_VIDEO>,
724 <&cru SCLK_HEVC_CABAC>,
725 <&cru SCLK_HEVC_CORE>;
728 * Note: ACLK_GPU is the GPU clock,
729 * and on the ACLK_GPU_NIU (NOC).
732 reg = <RK3368_PD_GPU_1>;
733 clocks = <&cru ACLK_GPU_CFG>,
735 <&cru SCLK_GPU_CORE>;
740 pmugrf: syscon@ff738000 {
741 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
742 reg = <0x0 0xff738000 0x0 0x1000>;
745 compatible = "syscon-reboot-mode";
747 mode-normal = <BOOT_NORMAL>;
748 mode-recovery = <BOOT_RECOVERY>;
749 mode-bootloader = <BOOT_FASTBOOT>;
750 mode-loader = <BOOT_LOADER>;
755 cru: clock-controller@ff760000 {
756 compatible = "rockchip,rk3368-cru";
757 reg = <0x0 0xff760000 0x0 0x1000>;
758 rockchip,grf = <&grf>;
762 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
764 <&cru ACLK_BUS>, <&cru ACLK_PERI>,
765 <&cru HCLK_BUS>, <&cru HCLK_PERI>,
766 <&cru PCLK_BUS>, <&cru PCLK_PERI>;
767 assigned-clock-rates =
768 <576000000>, <400000000>,
770 <300000000>, <300000000>,
771 <150000000>, <150000000>,
772 <75000000>, <75000000>;
775 grf: syscon@ff770000 {
776 compatible = "rockchip,rk3368-grf", "syscon";
777 reg = <0x0 0xff770000 0x0 0x1000>;
780 wdt: watchdog@ff800000 {
781 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
782 reg = <0x0 0xff800000 0x0 0x100>;
783 clocks = <&cru PCLK_WDT>;
784 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
788 gic: interrupt-controller@ffb71000 {
789 compatible = "arm,gic-400";
790 interrupt-controller;
791 #interrupt-cells = <3>;
792 #address-cells = <0>;
794 reg = <0x0 0xffb71000 0x0 0x1000>,
795 <0x0 0xffb72000 0x0 0x1000>,
796 <0x0 0xffb74000 0x0 0x2000>,
797 <0x0 0xffb76000 0x0 0x2000>;
798 interrupts = <GIC_PPI 9
799 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
802 gpu: rogue-g6110@ffa30000 {
803 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
804 reg = <0x0 0xffa30000 0x0 0x10000>;
806 <&cru SCLK_GPU_CORE>,
820 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
821 interrupt-names = "rogue-g6110-irq";
824 i2s_2ch: i2s-2ch@ff890000 {
825 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
826 reg = <0x0 0xff890000 0x0 0x1000>;
827 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
828 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
829 dma-names = "tx", "rx";
830 clock-names = "i2s_clk", "i2s_hclk";
831 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
835 i2s_8ch: i2s-8ch@ff898000 {
836 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
837 reg = <0x0 0xff898000 0x0 0x1000>;
838 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
839 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
840 dma-names = "tx", "rx";
841 clock-names = "i2s_clk", "i2s_hclk";
842 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
843 pinctrl-names = "default";
844 pinctrl-0 = <&i2s_8ch_bus>;
849 compatible = "rockchip,rk3368-isp", "rockchip,isp";
850 reg = <0x0 0xff910000 0x0 0x10000>;
851 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
852 /*power-domains = <&power PD_VIO>;*/
854 <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
855 <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
856 <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
857 <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
859 "aclk_isp", "hclk_isp", "clk_isp",
860 "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
861 "clk_cif_pll", "hclk_mipiphy1",
862 "pclk_dphyrx", "clk_vio0_noc";
864 "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
865 "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
866 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
867 "isp_flash_as_trigger_out";
868 pinctrl-0 = <&cif_clkout>;
869 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
870 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
871 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
872 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
873 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
874 pinctrl-6 = <&cif_clkout>;
875 pinctrl-7 = <&cif_clkout &isp_prelight>;
876 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
877 pinctrl-9 = <&isp_flash_trigger>;
878 rockchip,isp,mipiphy = <2>;
879 rockchip,isp,cifphy = <1>;
880 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
881 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
882 rockchip,grf = <&grf>;
883 rockchip,cru = <&cru>;
884 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
885 rockchip,isp,iommu_enable = <1>;
890 compatible = "rockchip,rga2";
892 reg = <0x0 0xff920000 0x0 0x1000>;
893 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
895 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
900 compatible = "rockchip,rk3368-pinctrl";
901 rockchip,grf = <&grf>;
902 rockchip,pmu = <&pmugrf>;
903 #address-cells = <0x2>;
907 gpio0: gpio0@ff750000 {
908 compatible = "rockchip,gpio-bank";
909 reg = <0x0 0xff750000 0x0 0x100>;
910 clocks = <&cru PCLK_GPIO0>;
911 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
916 interrupt-controller;
917 #interrupt-cells = <0x2>;
920 gpio1: gpio1@ff780000 {
921 compatible = "rockchip,gpio-bank";
922 reg = <0x0 0xff780000 0x0 0x100>;
923 clocks = <&cru PCLK_GPIO1>;
924 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
929 interrupt-controller;
930 #interrupt-cells = <0x2>;
933 gpio2: gpio2@ff790000 {
934 compatible = "rockchip,gpio-bank";
935 reg = <0x0 0xff790000 0x0 0x100>;
936 clocks = <&cru PCLK_GPIO2>;
937 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
942 interrupt-controller;
943 #interrupt-cells = <0x2>;
946 gpio3: gpio3@ff7a0000 {
947 compatible = "rockchip,gpio-bank";
948 reg = <0x0 0xff7a0000 0x0 0x100>;
949 clocks = <&cru PCLK_GPIO3>;
950 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
955 interrupt-controller;
956 #interrupt-cells = <0x2>;
959 pcfg_pull_up: pcfg-pull-up {
963 pcfg_pull_down: pcfg-pull-down {
967 pcfg_pull_none: pcfg-pull-none {
971 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
973 drive-strength = <12>;
978 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
982 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
986 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
989 emmc_bus1: emmc-bus1 {
990 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
993 emmc_bus4: emmc-bus4 {
994 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
995 <1 19 RK_FUNC_2 &pcfg_pull_up>,
996 <1 20 RK_FUNC_2 &pcfg_pull_up>,
997 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1000 emmc_bus8: emmc-bus8 {
1001 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1002 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1003 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1004 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1005 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1006 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1007 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1008 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1013 rgmii_pins: rgmii-pins {
1014 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1015 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1016 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1017 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1018 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1019 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1020 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1021 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1022 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1023 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1024 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1025 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1026 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1027 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1028 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1031 rmii_pins: rmii-pins {
1032 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1033 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1034 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1035 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1036 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1037 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1038 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1039 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1040 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1041 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1046 hdmii2c_xfer: hdmii2c-xfer {
1047 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
1048 <3 27 RK_FUNC_1 &pcfg_pull_none>;
1053 hdmi_cec: hdmi-cec {
1054 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
1059 i2c0_xfer: i2c0-xfer {
1060 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1061 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1066 i2c1_xfer: i2c1-xfer {
1067 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1068 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1073 i2c2_xfer: i2c2-xfer {
1074 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1075 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1080 i2c3_xfer: i2c3-xfer {
1081 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1082 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1087 i2c4_xfer: i2c4-xfer {
1088 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1089 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1094 i2c5_xfer: i2c5-xfer {
1095 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1096 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1098 i2c5_gpio: i2c5-gpio {
1099 rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
1100 <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
1105 i2s_8ch_bus: i2s-8ch-bus {
1106 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1107 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1108 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1109 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1110 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1111 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1112 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1113 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1114 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1119 sdio0_bus1: sdio0-bus1 {
1120 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1123 sdio0_bus4: sdio0-bus4 {
1124 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1125 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1126 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1127 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1130 sdio0_cmd: sdio0-cmd {
1131 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1134 sdio0_clk: sdio0-clk {
1135 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1138 sdio0_cd: sdio0-cd {
1139 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1142 sdio0_wp: sdio0-wp {
1143 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1146 sdio0_pwr: sdio0-pwr {
1147 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1150 sdio0_bkpwr: sdio0-bkpwr {
1151 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1154 sdio0_int: sdio0-int {
1155 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1160 sdmmc_clk: sdmmc-clk {
1161 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1164 sdmmc_cmd: sdmmc-cmd {
1165 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1168 sdmmc_cd: sdmcc-cd {
1169 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1172 sdmmc_bus1: sdmmc-bus1 {
1173 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1176 sdmmc_bus4: sdmmc-bus4 {
1177 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1178 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1179 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1180 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1185 spi0_clk: spi0-clk {
1186 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1188 spi0_cs0: spi0-cs0 {
1189 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1191 spi0_cs1: spi0-cs1 {
1192 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1195 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1198 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1203 spi1_clk: spi1-clk {
1204 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1206 spi1_cs0: spi1-cs0 {
1207 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1209 spi1_cs1: spi1-cs1 {
1210 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1213 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1216 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1221 spi2_clk: spi2-clk {
1222 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1224 spi2_cs0: spi2-cs0 {
1225 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1228 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1231 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1236 uart0_xfer: uart0-xfer {
1237 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1238 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1241 uart0_cts: uart0-cts {
1242 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1245 uart0_rts: uart0-rts {
1246 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1251 uart1_xfer: uart1-xfer {
1252 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1253 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1256 uart1_cts: uart1-cts {
1257 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1260 uart1_rts: uart1-rts {
1261 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1266 uart2_xfer: uart2-xfer {
1267 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1268 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1270 /* no rts / cts for uart2 */
1274 uart3_xfer: uart3-xfer {
1275 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1276 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1279 uart3_cts: uart3-cts {
1280 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1283 uart3_rts: uart3-rts {
1284 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1289 uart4_xfer: uart4-xfer {
1290 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1291 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1294 uart4_cts: uart4-cts {
1295 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1298 uart4_rts: uart4-rts {
1299 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1304 pwm0_pin: pwm0-pin {
1305 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1308 vop_pwm_pin: vop-pwm {
1309 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1314 pwm1_pin: pwm1-pin {
1315 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1320 pwm3_pin: pwm3-pin {
1321 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1326 lcdc_lcdc: lcdc-lcdc {
1328 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1329 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1330 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1331 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1332 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1333 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1334 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1335 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1336 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1337 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1338 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1339 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1340 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1341 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1342 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1343 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
1344 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1345 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1348 lcdc_gpio: lcdc-gpio {
1350 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1351 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1352 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1353 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1354 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1355 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1356 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1357 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1358 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1359 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1360 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1361 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1362 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1363 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1364 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1365 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1366 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1367 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1372 cif_clkout: cif-clkout {
1373 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1376 isp_dvp_d2d9: isp-dvp-d2d9 {
1378 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1379 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1380 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1381 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1382 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1383 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1384 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1385 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1386 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1387 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1388 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1389 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1392 isp_dvp_d0d1: isp-dvp-d0d1 {
1394 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1395 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1398 isp_dvp_d10d11:isp_d10d11 {
1400 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1401 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1404 isp_dvp_d0d7: isp-dvp-d0d7 {
1406 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1407 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1408 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1409 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1410 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1411 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1412 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1413 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1416 isp_dvp_d4d11: isp-dvp-d4d11 {
1418 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1419 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1420 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1421 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1422 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1423 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1424 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1425 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1428 isp_shutter: isp-shutter {
1430 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1431 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1434 isp_flash_trigger: isp-flash-trigger {
1435 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1438 isp_prelight: isp-prelight {
1439 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1442 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1443 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1449 compatible = "rockchip,rk-fb";
1450 rockchip,disp-mode = <NO_DUAL>;
1451 status = "disabled";
1455 compatible = "rockchip,screen";
1456 status = "disabled";
1459 lcdc: lcdc@ff930000 {
1460 compatible = "rockchip,rk3368-lcdc";
1461 rockchip,grf = <&grf>;
1462 rockchip,pmugrf = <&pmugrf>;
1463 rockchip,cru = <&cru>;
1464 rockchip,prop = <PRMRY>;
1465 rockchip,pwr18 = <0>;
1466 rockchip,iommu-enabled = <1>;
1467 reg = <0x0 0xff930000 0x0 0x10000>;
1468 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1469 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1470 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
1471 /*power-domains = <&power PD_VIO>;*/
1472 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1473 reset-names = "axi", "ahb", "dclk";
1474 status = "disabled";
1477 mipi: mipi@ff960000 {
1478 compatible = "rockchip,rk3368-dsi";
1479 rockchip,prop = <0>;
1480 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1481 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
1482 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1483 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1484 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
1485 /*power-domains = <&power PD_VIO>;*/
1486 status = "disabled";
1489 lvds: lvds@ff968000 {
1490 compatible = "rockchip,rk3368-lvds";
1491 rockchip,grf = <&grf>;
1492 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1493 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1494 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1495 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1496 /*power-domains = <&power PD_VIO>;*/
1497 status = "disabled";
1501 compatible = "rockchip,rk32-edp";
1502 reg = <0x0 0xff970000 0x0 0x4000>;
1503 rockchip,grf = <&grf>;
1504 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1505 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
1506 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
1507 /*power-domains = <&power PD_VIO>;*/
1508 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
1509 reset-names = "edp_24m", "edp_apb";
1510 status = "disabled";
1513 hdmi: hdmi@ff980000 {
1514 compatible = "rockchip,rk3368-hdmi";
1515 reg = <0x0 0xff980000 0x0 0x20000>;
1516 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1517 clocks = <&cru PCLK_HDMI_CTRL>,
1518 <&cru SCLK_HDMI_HDCP>,
1519 <&cru SCLK_HDMI_CEC>;
1520 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
1521 /*power-domains = <&power PD_VIO>;*/
1522 resets = <&cru SRST_HDMI>;
1523 reset-names = "hdmi";
1524 pinctrl-names = "default", "gpio";
1525 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
1526 pinctrl-1 = <&i2c5_gpio>;
1527 status = "disabled";
1532 compatible = "rockchip,iep_mmu";
1533 reg = <0x0 0xff900800 0x0 0x100>;
1534 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1535 interrupt-names = "iep_mmu";
1536 status = "disabled";
1541 compatible = "rockchip,vip_mmu";
1542 reg = <0x0 0xff950800 0x0 0x100>;
1543 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1544 interrupt-names = "vip_mmu";
1545 status = "disabled";
1548 vopb_mmu: vopb-mmu {
1550 compatible = "rockchip,vopb_mmu";
1551 reg = <0x0 0xff930300 0x0 0x100>;
1552 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1553 interrupt-names = "vop_mmu";
1554 status = "disabled";
1558 dbgname = "isp_mmu";
1559 compatible = "rockchip,isp_mmu";
1560 reg = <0x0 0xff914000 0x0 0x100>,
1561 <0x0 0xff915000 0x0 0x100>;
1562 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1563 interrupt-names = "isp_mmu";
1564 status = "disabled";
1567 hdcp_mmu: hdcp-mmu {
1568 dbgname = "hdcp_mmu";
1569 compatible = "rockchip,hdcp_mmu";
1570 reg = <0x0 0xff940000 0x0 0x100>;
1571 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1572 interrupt-names = "hdcp_mmu";
1573 status = "disabled";
1576 hevc_mmu: hevc-mmu {
1578 compatible = "rockchip,hevc_mmu";
1579 reg = <0x0 0xff9a0440 0x0 0x40>,
1580 <0x0 0xff9a0480 0x0 0x40>;
1581 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1582 interrupt-names = "hevc_mmu";
1583 status = "disabled";
1588 compatible = "rockchip,vpu_mmu";
1589 reg = <0x0 0xff9a0800 0x0 0x100>;
1590 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1591 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1592 interrupt-names = "vepu_mmu", "vdpu_mmu";
1593 status = "disabled";