2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3368-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
53 compatible = "rockchip,rk3368";
54 interrupt-parent = <&gic>;
77 #address-cells = <0x2>;
113 entry-method = "psci";
115 cpu_sleep: cpu-sleep-0 {
116 compatible = "arm,idle-state";
117 arm,psci-suspend-param = <0x1010000>;
118 entry-latency-us = <0x3fffffff>;
119 exit-latency-us = <0x40000000>;
120 min-residency-us = <0xffffffff>;
126 compatible = "arm,cortex-a53", "arm,armv8";
128 cpu-idle-states = <&cpu_sleep>;
129 enable-method = "psci";
130 clocks = <&cru ARMCLKL>;
131 operating-points-v2 = <&cluster1_opp>;
133 #cooling-cells = <2>; /* min followed by max */
138 compatible = "arm,cortex-a53", "arm,armv8";
140 cpu-idle-states = <&cpu_sleep>;
141 enable-method = "psci";
142 clocks = <&cru ARMCLKL>;
143 operating-points-v2 = <&cluster1_opp>;
148 compatible = "arm,cortex-a53", "arm,armv8";
150 cpu-idle-states = <&cpu_sleep>;
151 enable-method = "psci";
152 clocks = <&cru ARMCLKL>;
153 operating-points-v2 = <&cluster1_opp>;
158 compatible = "arm,cortex-a53", "arm,armv8";
160 cpu-idle-states = <&cpu_sleep>;
161 enable-method = "psci";
162 clocks = <&cru ARMCLKL>;
163 operating-points-v2 = <&cluster1_opp>;
168 compatible = "arm,cortex-a53", "arm,armv8";
170 cpu-idle-states = <&cpu_sleep>;
171 enable-method = "psci";
172 clocks = <&cru ARMCLKB>;
173 operating-points-v2 = <&cluster0_opp>;
175 #cooling-cells = <2>; /* min followed by max */
180 compatible = "arm,cortex-a53", "arm,armv8";
182 cpu-idle-states = <&cpu_sleep>;
183 enable-method = "psci";
184 clocks = <&cru ARMCLKB>;
185 operating-points-v2 = <&cluster0_opp>;
190 compatible = "arm,cortex-a53", "arm,armv8";
192 cpu-idle-states = <&cpu_sleep>;
193 enable-method = "psci";
194 clocks = <&cru ARMCLKB>;
195 operating-points-v2 = <&cluster0_opp>;
200 compatible = "arm,cortex-a53", "arm,armv8";
202 cpu-idle-states = <&cpu_sleep>;
203 enable-method = "psci";
204 clocks = <&cru ARMCLKB>;
205 operating-points-v2 = <&cluster0_opp>;
209 cluster0_opp: opp_table0 {
210 compatible = "operating-points-v2";
214 opp-hz = /bits/ 64 <408000000>;
215 opp-microvolt = <1200000>;
216 clock-latency-ns = <40000>;
220 opp-hz = /bits/ 64 <600000000>;
221 opp-microvolt = <1200000>;
224 opp-hz = /bits/ 64 <816000000>;
225 opp-microvolt = <1200000>;
228 opp-hz = /bits/ 64 <1008000000>;
229 opp-microvolt = <1200000>;
232 opp-hz = /bits/ 64 <1200000000>;
233 opp-microvolt = <1200000>;
237 cluster1_opp: opp_table1 {
238 compatible = "operating-points-v2";
242 opp-hz = /bits/ 64 <408000000>;
243 opp-microvolt = <1200000>;
244 clock-latency-ns = <40000>;
248 opp-hz = /bits/ 64 <600000000>;
249 opp-microvolt = <1200000>;
252 opp-hz = /bits/ 64 <816000000>;
253 opp-microvolt = <1200000>;
256 opp-hz = /bits/ 64 <1008000000>;
257 opp-microvolt = <1200000>;
262 compatible = "arm,armv8-pmuv3";
263 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
271 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
272 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
273 <&cpu_b2>, <&cpu_b3>;
277 compatible = "arm,amba-bus";
278 #address-cells = <2>;
282 dmac_peri: dma-controller@ff250000 {
283 compatible = "arm,pl330", "arm,primecell";
284 reg = <0x0 0xff250000 0x0 0x4000>;
285 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&cru ACLK_DMAC_PERI>;
289 clock-names = "apb_pclk";
290 arm,pl330-broken-no-flushp;
291 peripherals-req-type-burst;
294 dmac_bus: dma-controller@ff600000 {
295 compatible = "arm,pl330", "arm,primecell";
296 reg = <0x0 0xff600000 0x0 0x4000>;
297 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&cru ACLK_DMAC_BUS>;
301 clock-names = "apb_pclk";
302 arm,pl330-broken-no-flushp;
303 peripherals-req-type-burst;
308 compatible = "arm,psci-0.2";
313 compatible = "arm,armv8-timer";
314 interrupts = <GIC_PPI 13
315 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
317 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
319 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
321 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
325 compatible = "fixed-clock";
326 clock-frequency = <24000000>;
327 clock-output-names = "xin24m";
331 sdmmc: rksdmmc@ff0c0000 {
332 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
333 reg = <0x0 0xff0c0000 0x0 0x4000>;
334 clock-freq-min-max = <400000 150000000>;
335 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
336 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
337 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
338 fifo-depth = <0x100>;
339 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
343 sdio0: dwmmc@ff0d0000 {
344 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
345 reg = <0x0 0xff0d0000 0x0 0x4000>;
346 clock-freq-min-max = <400000 150000000>;
347 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
348 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
349 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
350 fifo-depth = <0x100>;
351 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
355 emmc: rksdmmc@ff0f0000 {
356 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
357 reg = <0x0 0xff0f0000 0x0 0x4000>;
358 clock-freq-min-max = <400000 150000000>;
359 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
360 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
361 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
362 fifo-depth = <0x100>;
363 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
367 saradc: saradc@ff100000 {
368 compatible = "rockchip,saradc";
369 reg = <0x0 0xff100000 0x0 0x100>;
370 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
371 #io-channel-cells = <1>;
372 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
373 clock-names = "saradc", "apb_pclk";
374 resets = <&cru SRST_SARADC>;
375 reset-names = "saradc-apb";
380 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
381 reg = <0x0 0xff110000 0x0 0x1000>;
382 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
383 clock-names = "spiclk", "apb_pclk";
384 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
387 #address-cells = <1>;
393 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
394 reg = <0x0 0xff120000 0x0 0x1000>;
395 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
396 clock-names = "spiclk", "apb_pclk";
397 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
400 #address-cells = <1>;
406 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
407 reg = <0x0 0xff130000 0x0 0x1000>;
408 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
409 clock-names = "spiclk", "apb_pclk";
410 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
413 #address-cells = <1>;
419 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
420 reg = <0x0 0xff650000 0x0 0x1000>;
421 clocks = <&cru PCLK_I2C0>;
423 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&i2c0_xfer>;
426 #address-cells = <1>;
432 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
433 reg = <0x0 0xff140000 0x0 0x1000>;
434 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
435 #address-cells = <1>;
438 clocks = <&cru PCLK_I2C2>;
439 pinctrl-names = "default";
440 pinctrl-0 = <&i2c2_xfer>;
445 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
446 reg = <0x0 0xff150000 0x0 0x1000>;
447 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
448 #address-cells = <1>;
451 clocks = <&cru PCLK_I2C3>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&i2c3_xfer>;
458 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
459 reg = <0x0 0xff160000 0x0 0x1000>;
460 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
461 #address-cells = <1>;
464 clocks = <&cru PCLK_I2C4>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&i2c4_xfer>;
471 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
472 reg = <0x0 0xff170000 0x0 0x1000>;
473 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
474 #address-cells = <1>;
477 clocks = <&cru PCLK_I2C5>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&i2c5_xfer>;
483 uart0: serial@ff180000 {
484 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
485 reg = <0x0 0xff180000 0x0 0x100>;
486 clock-frequency = <24000000>;
487 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
488 clock-names = "baudclk", "apb_pclk";
489 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
495 uart1: serial@ff190000 {
496 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
497 reg = <0x0 0xff190000 0x0 0x100>;
498 clock-frequency = <24000000>;
499 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
500 clock-names = "baudclk", "apb_pclk";
501 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
507 uart3: serial@ff1b0000 {
508 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
509 reg = <0x0 0xff1b0000 0x0 0x100>;
510 clock-frequency = <24000000>;
511 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
512 clock-names = "baudclk", "apb_pclk";
513 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
519 uart4: serial@ff1c0000 {
520 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
521 reg = <0x0 0xff1c0000 0x0 0x100>;
522 clock-frequency = <24000000>;
523 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
524 clock-names = "baudclk", "apb_pclk";
525 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
533 polling-delay-passive = <100>; /* milliseconds */
534 polling-delay = <5000>; /* milliseconds */
536 thermal-sensors = <&tsadc 0>;
539 cpu_alert0: cpu_alert0 {
540 temperature = <75000>; /* millicelsius */
541 hysteresis = <2000>; /* millicelsius */
544 cpu_alert1: cpu_alert1 {
545 temperature = <80000>; /* millicelsius */
546 hysteresis = <2000>; /* millicelsius */
550 temperature = <95000>; /* millicelsius */
551 hysteresis = <2000>; /* millicelsius */
558 trip = <&cpu_alert0>;
560 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
563 trip = <&cpu_alert1>;
565 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
571 polling-delay-passive = <100>; /* milliseconds */
572 polling-delay = <5000>; /* milliseconds */
574 thermal-sensors = <&tsadc 1>;
577 gpu_alert0: gpu_alert0 {
578 temperature = <80000>; /* millicelsius */
579 hysteresis = <2000>; /* millicelsius */
583 temperature = <115000>; /* millicelsius */
584 hysteresis = <2000>; /* millicelsius */
591 trip = <&gpu_alert0>;
593 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
599 tsadc: tsadc@ff280000 {
600 compatible = "rockchip,rk3368-tsadc";
601 reg = <0x0 0xff280000 0x0 0x100>;
602 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
604 clock-names = "tsadc", "apb_pclk";
605 resets = <&cru SRST_TSADC>;
606 reset-names = "tsadc-apb";
607 pinctrl-names = "init", "default", "sleep";
608 pinctrl-0 = <&otp_gpio>;
609 pinctrl-1 = <&otp_out>;
610 pinctrl-2 = <&otp_gpio>;
611 #thermal-sensor-cells = <1>;
612 rockchip,hw-tshut-temp = <95000>;
616 gmac: ethernet@ff290000 {
617 compatible = "rockchip,rk3368-gmac";
618 reg = <0x0 0xff290000 0x0 0x10000>;
619 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
620 interrupt-names = "macirq";
621 rockchip,grf = <&grf>;
622 clocks = <&cru SCLK_MAC>,
623 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
624 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
625 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
626 clock-names = "stmmaceth",
627 "mac_clk_rx", "mac_clk_tx",
628 "clk_mac_ref", "clk_mac_refout",
629 "aclk_mac", "pclk_mac";
633 nandc0: nandc@ff400000 {
634 compatible = "rockchip,rk-nandc";
635 reg = <0x0 0xff400000 0x0 0x4000>;
636 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
639 clock-names = "clk_nandc", "hclk_nandc";
643 usb_host0_ehci: usb@ff500000 {
644 compatible = "generic-ehci";
645 reg = <0x0 0xff500000 0x0 0x100>;
646 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&cru HCLK_HOST0>;
648 clock-names = "usbhost";
652 usb_otg: usb@ff580000 {
653 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
655 reg = <0x0 0xff580000 0x0 0x40000>;
656 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&cru HCLK_OTG0>;
660 g-np-tx-fifo-size = <16>;
661 g-rx-fifo-size = <275>;
662 g-tx-fifo-size = <256 128 128 64 64 32>;
667 ddrpctl: syscon@ff610000 {
668 compatible = "rockchip,rk3368-ddrpctl", "syscon";
669 reg = <0x0 0xff610000 0x0 0x400>;
673 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
674 reg = <0x0 0xff660000 0x0 0x1000>;
675 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
676 #address-cells = <1>;
679 clocks = <&cru PCLK_I2C1>;
680 pinctrl-names = "default";
681 pinctrl-0 = <&i2c1_xfer>;
686 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
687 reg = <0x0 0xff680000 0x0 0x10>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&pwm0_pin>;
691 clocks = <&cru PCLK_PWM1>;
697 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
698 reg = <0x0 0xff680010 0x0 0x10>;
700 pinctrl-names = "default";
701 pinctrl-0 = <&pwm1_pin>;
702 clocks = <&cru PCLK_PWM1>;
708 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
709 reg = <0x0 0xff680020 0x0 0x10>;
711 clocks = <&cru PCLK_PWM1>;
717 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
718 reg = <0x0 0xff680030 0x0 0x10>;
720 pinctrl-names = "default";
721 pinctrl-0 = <&pwm3_pin>;
722 clocks = <&cru PCLK_PWM1>;
727 uart2: serial@ff690000 {
728 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
729 reg = <0x0 0xff690000 0x0 0x100>;
730 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
731 clock-names = "baudclk", "apb_pclk";
732 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
733 pinctrl-names = "default";
734 pinctrl-0 = <&uart2_xfer>;
740 mbox: mbox@ff6b0000 {
741 compatible = "rockchip,rk3368-mailbox";
742 reg = <0x0 0xff6b0000 0x0 0x1000>;
743 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&cru PCLK_MAILBOX>;
748 clock-names = "pclk_mailbox";
753 mailbox: mailbox@ff6b0000 {
754 compatible = "rockchip,rk3368-mbox-legacy";
755 reg = <0x0 0xff6b0000 0x0 0x1000>,
756 <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
757 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&cru PCLK_MAILBOX>;
762 clock-names = "pclk_mailbox";
767 mailbox_scpi: mailbox-scpi {
768 compatible = "rockchip,rk3368-scpi-legacy";
769 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
774 pmu: power-management@ff730000 {
775 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
776 reg = <0x0 0xff730000 0x0 0x1000>;
778 power: power-controller {
780 compatible = "rockchip,rk3368-power-controller";
781 #power-domain-cells = <1>;
782 #address-cells = <1>;
786 * Note: Although SCLK_* are the working clocks
787 * of device without including on the NOC, needed for
790 * The clocks on the which NOC:
791 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
792 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
793 * ACLK_RGA is on ACLK_RGA_NIU.
794 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
796 * Which clock are device clocks:
798 * *_IEP IEP:Image Enhancement Processor
799 * *_ISP ISP:Image Signal Processing
800 * *_VIP VIP:Video Input Processor
801 * *_VOP* VOP:Visual Output Processor
809 reg = <RK3368_PD_VIO>;
810 clocks = <&cru ACLK_IEP>,
822 <&cru HCLK_VIO_HDCPMMU>,
823 <&cru PCLK_EDP_CTRL>,
824 <&cru PCLK_HDMI_CTRL>,
830 <&cru PCLK_MIPI_CSI>,
831 <&cru PCLK_MIPI_DSI0>,
832 <&cru SCLK_VOP0_PWM>,
838 <&cru SCLK_HDMI_CEC>,
839 <&cru SCLK_HDMI_HDCP>;
842 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
843 * (video endecoder & decoder) clocks that on the
844 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
847 reg = <RK3368_PD_VIDEO>;
848 clocks = <&cru ACLK_VIDEO>,
850 <&cru SCLK_HEVC_CABAC>,
851 <&cru SCLK_HEVC_CORE>;
854 * Note: ACLK_GPU is the GPU clock,
855 * and on the ACLK_GPU_NIU (NOC).
858 reg = <RK3368_PD_GPU_1>;
859 clocks = <&cru ACLK_GPU_CFG>,
861 <&cru SCLK_GPU_CORE>;
866 pmugrf: syscon@ff738000 {
867 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
868 reg = <0x0 0xff738000 0x0 0x1000>;
870 pmu_io_domains: io-domains {
871 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
876 compatible = "syscon-reboot-mode";
878 mode-normal = <BOOT_NORMAL>;
879 mode-recovery = <BOOT_RECOVERY>;
880 mode-bootloader = <BOOT_FASTBOOT>;
881 mode-loader = <BOOT_BL_DOWNLOAD>;
885 cru: clock-controller@ff760000 {
886 compatible = "rockchip,rk3368-cru";
887 reg = <0x0 0xff760000 0x0 0x1000>;
888 rockchip,grf = <&grf>;
892 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
894 <&cru ACLK_BUS>, <&cru ACLK_PERI>,
895 <&cru HCLK_BUS>, <&cru HCLK_PERI>,
896 <&cru PCLK_BUS>, <&cru PCLK_PERI>;
897 assigned-clock-rates =
898 <576000000>, <400000000>,
900 <300000000>, <300000000>,
901 <150000000>, <150000000>,
902 <75000000>, <75000000>;
905 grf: syscon@ff770000 {
906 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
907 reg = <0x0 0xff770000 0x0 0x1000>;
909 io_domains: io-domains {
910 compatible = "rockchip,rk3368-io-voltage-domain";
915 wdt: watchdog@ff800000 {
916 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
917 reg = <0x0 0xff800000 0x0 0x100>;
918 clocks = <&cru PCLK_WDT>;
919 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
924 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
925 reg = <0x0 0xff810000 0x0 0x20>;
926 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
929 i2s_2ch: i2s-2ch@ff890000 {
930 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
931 reg = <0x0 0xff890000 0x0 0x1000>;
932 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
933 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
934 dma-names = "tx", "rx";
935 clock-names = "i2s_clk", "i2s_hclk";
936 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
940 i2s_8ch: i2s-8ch@ff898000 {
941 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
942 reg = <0x0 0xff898000 0x0 0x1000>;
943 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
944 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
945 dma-names = "tx", "rx";
946 clock-names = "i2s_clk", "i2s_hclk";
947 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
948 pinctrl-names = "default";
949 pinctrl-0 = <&i2s_8ch_bus>;
953 gic: interrupt-controller@ffb71000 {
954 compatible = "arm,gic-400";
955 interrupt-controller;
956 #interrupt-cells = <3>;
957 #address-cells = <0>;
959 reg = <0x0 0xffb71000 0x0 0x1000>,
960 <0x0 0xffb72000 0x0 0x2000>,
961 <0x0 0xffb74000 0x0 0x2000>,
962 <0x0 0xffb76000 0x0 0x2000>;
963 interrupts = <GIC_PPI 9
964 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
967 gpu: rogue-g6110@ffa30000 {
968 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
969 reg = <0x0 0xffa30000 0x0 0x10000>;
971 <&cru SCLK_GPU_CORE>,
985 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
986 interrupt-names = "rogue-g6110-irq";
990 compatible = "rockchip,rk3368-pinctrl";
991 rockchip,grf = <&grf>;
992 rockchip,pmu = <&pmugrf>;
993 #address-cells = <0x2>;
997 gpio0: gpio0@ff750000 {
998 compatible = "rockchip,gpio-bank";
999 reg = <0x0 0xff750000 0x0 0x100>;
1000 clocks = <&cru PCLK_GPIO0>;
1001 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1004 #gpio-cells = <0x2>;
1006 interrupt-controller;
1007 #interrupt-cells = <0x2>;
1010 gpio1: gpio1@ff780000 {
1011 compatible = "rockchip,gpio-bank";
1012 reg = <0x0 0xff780000 0x0 0x100>;
1013 clocks = <&cru PCLK_GPIO1>;
1014 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1017 #gpio-cells = <0x2>;
1019 interrupt-controller;
1020 #interrupt-cells = <0x2>;
1023 gpio2: gpio2@ff790000 {
1024 compatible = "rockchip,gpio-bank";
1025 reg = <0x0 0xff790000 0x0 0x100>;
1026 clocks = <&cru PCLK_GPIO2>;
1027 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1030 #gpio-cells = <0x2>;
1032 interrupt-controller;
1033 #interrupt-cells = <0x2>;
1036 gpio3: gpio3@ff7a0000 {
1037 compatible = "rockchip,gpio-bank";
1038 reg = <0x0 0xff7a0000 0x0 0x100>;
1039 clocks = <&cru PCLK_GPIO3>;
1040 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1043 #gpio-cells = <0x2>;
1045 interrupt-controller;
1046 #interrupt-cells = <0x2>;
1049 pcfg_pull_up: pcfg-pull-up {
1053 pcfg_pull_down: pcfg-pull-down {
1057 pcfg_pull_none: pcfg-pull-none {
1061 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1063 drive-strength = <12>;
1067 emmc_clk: emmc-clk {
1068 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1071 emmc_cmd: emmc-cmd {
1072 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1075 emmc_pwr: emmc-pwr {
1076 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1079 emmc_bus1: emmc-bus1 {
1080 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1083 emmc_bus4: emmc-bus4 {
1084 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1085 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1086 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1087 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1090 emmc_bus8: emmc-bus8 {
1091 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1092 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1093 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1094 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1095 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1096 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1097 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1098 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1103 rgmii_pins: rgmii-pins {
1104 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1105 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1106 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1107 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1108 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1109 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1110 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1111 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1112 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1113 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1114 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1115 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1116 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1117 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1118 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1121 rmii_pins: rmii-pins {
1122 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1123 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1124 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1125 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1126 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1127 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1128 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1129 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1130 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1131 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1136 i2c0_xfer: i2c0-xfer {
1137 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1138 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1143 i2c1_xfer: i2c1-xfer {
1144 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1145 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1150 i2c2_xfer: i2c2-xfer {
1151 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1152 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1157 i2c3_xfer: i2c3-xfer {
1158 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1159 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1164 i2c4_xfer: i2c4-xfer {
1165 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1166 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1171 i2c5_xfer: i2c5-xfer {
1172 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1173 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1178 i2s_8ch_bus: i2s-8ch-bus {
1179 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1180 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1181 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1182 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1183 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1184 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1185 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1186 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1187 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1192 pwm0_pin: pwm0-pin {
1193 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1196 vop_pwm_pin: vop-pwm {
1197 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1202 pwm1_pin: pwm1-pin {
1203 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1208 pwm3_pin: pwm3-pin {
1209 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1214 sdio0_bus1: sdio0-bus1 {
1215 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1218 sdio0_bus4: sdio0-bus4 {
1219 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1220 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1221 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1222 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1225 sdio0_cmd: sdio0-cmd {
1226 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1229 sdio0_clk: sdio0-clk {
1230 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1233 sdio0_cd: sdio0-cd {
1234 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1237 sdio0_wp: sdio0-wp {
1238 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1241 sdio0_pwr: sdio0-pwr {
1242 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1245 sdio0_bkpwr: sdio0-bkpwr {
1246 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1249 sdio0_int: sdio0-int {
1250 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1255 sdmmc_clk: sdmmc-clk {
1256 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1259 sdmmc_cmd: sdmmc-cmd {
1260 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1263 sdmmc_cd: sdmmc-cd {
1264 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1267 sdmmc_bus1: sdmmc-bus1 {
1268 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1271 sdmmc_bus4: sdmmc-bus4 {
1272 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1273 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1274 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1275 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1280 spi0_clk: spi0-clk {
1281 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1283 spi0_cs0: spi0-cs0 {
1284 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1286 spi0_cs1: spi0-cs1 {
1287 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1290 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1293 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1298 spi1_clk: spi1-clk {
1299 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1301 spi1_cs0: spi1-cs0 {
1302 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1304 spi1_cs1: spi1-cs1 {
1305 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1308 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1311 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1316 spi2_clk: spi2-clk {
1317 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1319 spi2_cs0: spi2-cs0 {
1320 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1323 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1326 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1331 otp_gpio: otp-gpio {
1332 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1336 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1341 uart0_xfer: uart0-xfer {
1342 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1343 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1346 uart0_cts: uart0-cts {
1347 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1350 uart0_rts: uart0-rts {
1351 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1356 uart1_xfer: uart1-xfer {
1357 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1358 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1361 uart1_cts: uart1-cts {
1362 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1365 uart1_rts: uart1-rts {
1366 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1371 uart2_xfer: uart2-xfer {
1372 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1373 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1375 /* no rts / cts for uart2 */
1379 uart3_xfer: uart3-xfer {
1380 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1381 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1384 uart3_cts: uart3-cts {
1385 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1388 uart3_rts: uart3-rts {
1389 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1394 uart4_xfer: uart4-xfer {
1395 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1396 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1399 uart4_cts: uart4-cts {
1400 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1403 uart4_rts: uart4-rts {
1404 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;