2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
45 bootargs = "earlycon=uart8250,mmio32,0xff1b0000 swiotlb=1 firmware_class.path=/system/vendor/firmware";
48 fiq_debugger: fiq-debugger {
49 compatible = "rockchip,fiq-debugger";
50 rockchip,serial-id = <3>;
51 rockchip,signal-irq = <186>;
52 rockchip,wake-irq = <0>;
53 rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
54 rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
55 pinctrl-names = "default";
56 pinctrl-0 = <&uart3_xfer>;
64 drm_logo: drm-logo@00000000 {
65 compatible = "rockchip,drm-logo";
66 reg = <0x0 0x0 0x0 0x0>;
69 /* global autoconfigured region for contiguous allocations */
71 compatible = "shared-dma-pool";
73 size = <0x0 0x8000000>;
77 /* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
78 rockchip_logo: rockchip-logo@00000000 {
79 compatible = "rockchip,drm-logo";
80 reg = <0x0 0x0 0x0 0x0>;
85 compatible = "rockchip,ion";
90 reg = <0x00000000 0x02000000>;
98 compatible = "rockchip,rga2";
100 reg = <0x0 0xff920000 0x0 0x1000>;
101 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
102 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
103 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
108 hdmi: hdmi@ff980000 {
109 compatible = "rockchip,rk3368-hdmi";
110 reg = <0x0 0xff980000 0x0 0x20000>;
111 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&cru PCLK_HDMI_CTRL>,
113 <&cru SCLK_HDMI_HDCP>,
114 <&cru SCLK_HDMI_CEC>;
115 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
116 power-domains = <&power RK3368_PD_VIO>;
117 resets = <&cru SRST_HDMI>;
118 reset-names = "hdmi";
119 pinctrl-names = "default", "gpio";
120 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
121 pinctrl-1 = <&i2c5_gpio>;
125 dwc_control_usb: dwc-control-usb {
126 compatible = "rockchip,rk3368-dwc-control-usb";
129 rockchip,grf = <&grf>;
130 grf-offset = <0x04bc>; /* GRF_SOC_STATUS for USB2.0 OTG */
131 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
135 interrupt-names = "otg_id", "otg_bvalid",
136 "otg_linestate", "host0_linestate";
137 clocks = <&cru HCLK_USB_PERI>;
138 clock-names = "hclk_usb_peri";
140 otg_drv_gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
141 rockchip,remote_wakeup;
142 rockchip,usb_irq_wakeup;
145 compatible = "inno,phy";
146 regbase = &dwc_control_usb;
147 rk_usb,bvalid = <0x4bc 23 1>;
148 rk_usb,iddig = <0x4bc 26 1>;
149 rk_usb,vdmsrcen = <0x718 12 1>;
150 rk_usb,vdpsrcen = <0x718 11 1>;
151 rk_usb,rdmpden = <0x718 10 1>;
152 rk_usb,idpsrcen = <0x718 9 1>;
153 rk_usb,idmsinken = <0x718 8 1>;
154 rk_usb,idpsinken = <0x718 7 1>;
155 rk_usb,dpattach = <0x4b8 31 1>;
156 rk_usb,cpdet = <0x4b8 30 1>;
157 rk_usb,dcpattach = <0x4b8 29 1>;
165 memory-region = <&drm_logo>;
167 route_mipi: route-mipi {
169 logo,uboot = "logo.bmp";
170 logo,kernel = "logo_kernel.bmp";
171 logo,mode = "center";
172 charge_logo,mode = "center";
173 connect = <&vop_out_mipi>;
200 clocks = <&cru SCLK_OTGPHY0>, <&cru HCLK_OTG0>;
201 clock-names = "sclk_otgphy0", "otg";
202 resets = <&cru SRST_USBOTG_AHB>,
203 <&cru SRST_USBOTG_PHY>,
204 <&cru SRST_USBOTG_CON>;
205 reset-names = "otg_ahb", "otg_phy", "otg_controller";
206 /* 0 - Normal, 1 - Force Host, 2 - Force Device */
207 rockchip,usb-mode = <0>;
212 hdmii2c_xfer: hdmii2c-xfer {
213 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
214 <3 27 RK_FUNC_1 &pcfg_pull_none>;
220 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
225 i2c5_gpio: i2c5-gpio {
226 rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
227 <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
232 cif_clkout: cif-clkout {
233 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
236 isp_dvp_d2d9: isp-dvp-d2d9 {
238 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
239 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
240 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
241 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
242 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
243 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
244 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
245 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
246 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
247 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
248 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
249 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
252 isp_dvp_d0d1: isp-dvp-d0d1 {
254 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
255 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
258 isp_dvp_d10d11:isp_d10d11 {
260 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
261 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
264 isp_dvp_d0d7: isp-dvp-d0d7 {
266 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
267 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
268 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
269 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
270 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
271 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
272 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
273 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
276 isp_dvp_d4d11: isp-dvp-d4d11 {
278 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
279 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
280 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
281 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
282 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
283 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
284 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
285 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
288 isp_shutter: isp-shutter {
290 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
291 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
294 isp_flash_trigger: isp-flash-trigger {
295 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
298 isp_prelight: isp-prelight {
299 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
302 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
303 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU