arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49
  50 / {
  51         compatible = "rockchip,rk3366";
  52         interrupt-parent = <&gic>;
  53         #address-cells = <2>;
  54         #size-cells = <2>;
  55
  56         aliases {
  57                 i2c0 = &i2c0;
  58                 i2c1 = &i2c1;
  59                 i2c2 = &i2c2;
  60                 i2c3 = &i2c3;
  61                 i2c4 = &i2c4;
  62                 i2c5 = &i2c5;
  63                 serial0 = &uart0;
  64                 serial2 = &uart2;
  65                 serial3 = &uart3;
  66                 spi0 = &spi0;
  67                 spi1 = &spi1;
  68         };
  69
  70         cpus {
  71                 #address-cells = <0x2>;
  72                 #size-cells = <0x0>;
  73
  74                 cpu0: cpu@0 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a53","arm,armv8";
  77                         reg = <0x0 0x0>;
  78                         enable-method = "psci";
  79                 };
  80
  81                 cpu1: cpu@1 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a53","arm,armv8";
  84                         reg = <0x0 0x1>;
  85                         enable-method = "psci";
  86                 };
  87
  88                 cpu2: cpu@2 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a53","arm,armv8";
  91                         reg = <0x0 0x2>;
  92                         enable-method = "psci";
  93                 };
  94
  95                 cpu3: cpu@3 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a53","arm,armv8";
  98                         reg = <0x0 0x3>;
  99                         enable-method = "psci";
 100                 };
 101         };
 102
 103         psci {
 104                 compatible = "arm,psci-1.0";
 105                 method = "smc";
 106         };
 107
 108         timer {
 109                 compatible = "arm,armv8-timer";
 110                 interrupts = <
 111                                 GIC_PPI 13
 112                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 113                                 <GIC_PPI 14
 114                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 115                                 <GIC_PPI 11
 116                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 117                                 <GIC_PPI 10
 118                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 119                 clock-frequency = <24000000>;
 120         };
 121
 122         xin24m: xin24m {
 123                 compatible = "fixed-clock";
 124                 #clock-cells = <0>;
 125                 clock-frequency = <24000000>;
 126                 clock-output-names = "xin24m";
 127         };
 128
 129         gic: interrupt-controller@ffb71000 {
 130                 compatible = "arm,gic-400";
 131                 interrupt-controller;
 132                 #interrupt-cells = <3>;
 133                 #address-cells = <0>;
 134
 135                 reg = <0x0 0xffb71000 0x0 0x1000>,
 136                       <0x0 0xffb72000 0x0 0x1000>,
 137                       <0x0 0xffb74000 0x0 0x2000>,
 138                       <0x0 0xffb76000 0x0 0x2000>;
 139                 interrupts = <GIC_PPI 9
 140                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 141         };
 142
 143         nandc0: nandc@ff0c0000 {
 144                 compatible = "rockchip,rk-nandc";
 145                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 146                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 147                 nandc_id = <0>;
 148                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 149                 clock-names = "clk_nandc", "hclk_nandc";
 150                 status = "disabled";
 151         };
 152
 153         saradc: saradc@ff100000 {
 154                 compatible = "rockchip,saradc";
 155                 reg = <0x0 0xff100000 0x0 0x100>;
 156                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 157                 #io-channel-cells = <1>;
 158                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 159                 clock-names = "saradc", "apb_pclk";
 160                 status = "disabled";
 161         };
 162
 163         spi0: spi@ff110000 {
 164                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 165                 reg = <0x0 0xff110000 0x0 0x1000>;
 166                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 167                 clock-names = "spiclk", "apb_pclk";
 168                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 169                 pinctrl-names = "default";
 170                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 171                 #address-cells = <1>;
 172                 #size-cells = <0>;
 173                 status = "disabled";
 174         };
 175
 176         spi1: spi@ff120000 {
 177                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 178                 reg = <0x0 0xff120000 0x0 0x1000>;
 179                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 180                 clock-names = "spiclk", "apb_pclk";
 181                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 182                 pinctrl-names = "default";
 183                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 184                 #address-cells = <1>;
 185                 #size-cells = <0>;
 186                 status = "disabled";
 187         };
 188
 189         sdmmc: rksdmmc@ff400000 {
 190                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 191                 clock-freq-min-max = <400000 150000000>;
 192                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 193                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 194                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 195                 fifo-depth = <0x100>;
 196                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 197                 reg = <0x0 0xff400000 0x0 0x4000>;
 198                 status = "disabled";
 199         };
 200
 201         sdio: rksdmmc@ff410000 {
 202                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 203                 clock-freq-min-max = <400000 150000000>;
 204                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 205                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 206                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 207                 fifo-depth = <0x100>;
 208                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 209                 reg = <0x0 0xff410000 0x0 0x4000>;
 210                 status = "disabled";
 211         };
 212
 213         emmc: rksdmmc@ff420000 {
 214                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 215                 clock-freq-min-max = <400000 150000000>;
 216                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 217                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 218                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 219                 fifo-depth = <0x100>;
 220                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 221                 reg = <0x0 0xff420000 0x0 0x4000>;
 222                 status = "disabled";
 223         };
 224
 225         gmac: eth@ff440000 {
 226                 compatible = "rockchip,rk3366-gmac";
 227                 reg = <0x0 0xff440000 0x0 0x10000>;
 228                 rockchip,grf = <&grf>;
 229                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 230                 interrupt-names = "macirq";
 231                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 232                          <&cru SCLK_MAC_RX>, <&cru SCLK_MACREF>,
 233                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 234                          <&cru PCLK_GMAC>;
 235                 clock-names = "stmmaceth", "mac_clk_rx",
 236                               "mac_clk_tx", "clk_mac_ref",
 237                               "clk_mac_refout", "aclk_mac",
 238                               "pclk_mac";
 239                 resets = <&cru SRST_MAC>;
 240                 reset-names = "stmmaceth";
 241                 status = "disabled";
 242         };
 243
 244         i2c0: i2c@ff650000 {
 245                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 246                 reg = <0x0 0xff728000 0x0 0x1000>;
 247                 clocks = <&cru PCLK_I2C0>;
 248                 clock-names = "i2c";
 249                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 250                 pinctrl-names = "default";
 251                 pinctrl-0 = <&i2c0_xfer>;
 252                 #address-cells = <1>;
 253                 #size-cells = <0>;
 254                 status = "disabled";
 255         };
 256
 257         i2c2: i2c@ff140000 {
 258                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 259                 reg = <0x0 0xff140000 0x0 0x1000>;
 260                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 261                 #address-cells = <1>;
 262                 #size-cells = <0>;
 263                 clock-names = "i2c";
 264                 clocks = <&cru PCLK_I2C2>;
 265                 pinctrl-names = "default";
 266                 pinctrl-0 = <&i2c2_xfer>;
 267                 status = "disabled";
 268         };
 269
 270         i2c3: i2c@ff150000 {
 271                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 272                 reg = <0x0 0xff150000 0x0 0x1000>;
 273                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 274                 #address-cells = <1>;
 275                 #size-cells = <0>;
 276                 clock-names = "i2c";
 277                 clocks = <&cru PCLK_I2C3>;
 278                 pinctrl-names = "default";
 279                 pinctrl-0 = <&i2c3_xfer>;
 280                 status = "disabled";
 281         };
 282
 283         i2c4: i2c@ff160000 {
 284                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 285                 reg = <0x0 0xff160000 0x0 0x1000>;
 286                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 287                 #address-cells = <1>;
 288                 #size-cells = <0>;
 289                 clock-names = "i2c";
 290                 clocks = <&cru PCLK_I2C4>;
 291                 pinctrl-names = "default";
 292                 pinctrl-0 = <&i2c4_xfer>;
 293                 status = "disabled";
 294         };
 295
 296         i2c5: i2c@ff170000 {
 297                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 298                 reg = <0x0 0xff170000 0x0 0x1000>;
 299                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 300                 #address-cells = <1>;
 301                 #size-cells = <0>;
 302                 clock-names = "i2c";
 303                 clocks = <&cru PCLK_I2C5>;
 304                 pinctrl-names = "default";
 305                 pinctrl-0 = <&i2c5_xfer>;
 306                 status = "disabled";
 307         };
 308
 309         uart0: serial@ff180000 {
 310                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 311                 reg = <0x0 0xff180000 0x0 0x100>;
 312                 clock-frequency = <24000000>;
 313                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 314                 clock-names = "baudclk", "apb_pclk";
 315                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 316                 reg-shift = <2>;
 317                 reg-io-width = <4>;
 318                 pinctrl-names = "default";
 319                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 320                 status = "disabled";
 321         };
 322
 323         uart3: serial@ff1b0000 {
 324                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 325                 reg = <0x0 0xff1b0000 0x0 0x100>;
 326                 clock-frequency = <24000000>;
 327                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 328                 clock-names = "baudclk", "apb_pclk";
 329                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 330                 reg-shift = <2>;
 331                 reg-io-width = <4>;
 332                 pinctrl-names = "default";
 333                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 334                 status = "disabled";
 335         };
 336
 337         i2c1: i2c@ff660000 {
 338                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 339                 reg = <0x0 0xff660000 0x0 0x1000>;
 340                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 341                 #address-cells = <1>;
 342                 #size-cells = <0>;
 343                 clock-names = "i2c";
 344                 clocks = <&cru PCLK_I2C1>;
 345                 pinctrl-names = "default";
 346                 pinctrl-0 = <&i2c1_xfer>;
 347                 status = "disabled";
 348         };
 349
 350         pwm0: pwm@ff680000 {
 351                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 352                 reg = <0x0 0xff680000 0x0 0x10>;
 353                 #pwm-cells = <3>;
 354                 pinctrl-names = "default";
 355                 pinctrl-0 = <&pwm0_pin>;
 356                 clocks = <&cru PCLK_RKPWM>;
 357                 clock-names = "pwm";
 358                 status = "disabled";
 359         };
 360
 361         pwm1: pwm@ff680010 {
 362                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 363                 reg = <0x0 0xff680010 0x0 0x10>;
 364                 #pwm-cells = <3>;
 365                 pinctrl-names = "default";
 366                 pinctrl-0 = <&pwm1_pin>;
 367                 clocks = <&cru PCLK_RKPWM>;
 368                 clock-names = "pwm";
 369                 status = "disabled";
 370         };
 371
 372         pwm2: pwm@ff680020 {
 373                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 374                 reg = <0x0 0xff680020 0x0 0x10>;
 375                 #pwm-cells = <3>;
 376                 clocks = <&cru PCLK_RKPWM>;
 377                 clock-names = "pwm";
 378                 status = "disabled";
 379         };
 380
 381         pwm3: pwm@ff680030 {
 382                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 383                 reg = <0x0 0xff680030 0x0 0x10>;
 384                 #pwm-cells = <3>;
 385                 pinctrl-names = "default";
 386                 pinctrl-0 = <&pwm3_t2_pin>;
 387                 clocks = <&cru PCLK_RKPWM>;
 388                 clock-names = "pwm";
 389                 status = "disabled";
 390         };
 391
 392         uart2: serial@ff690000 {
 393                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 394                 reg = <0x0 0xff690000 0x0 0x100>;
 395                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 396                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 397                 clock-names = "baudclk", "apb_pclk";
 398                 reg-shift = <2>;
 399                 reg-io-width = <4>;
 400                 pinctrl-names = "default";
 401                 pinctrl-0 = <&uart2_t1_xfer>;
 402                 status = "disabled";
 403         };
 404
 405         pmugrf: syscon@ff738000 {
 406                 compatible = "rockchip,rk3366-pmugrf", "syscon";
 407                 reg = <0x0 0xff738000 0x0 0x1000>;
 408         };
 409
 410         amba {
 411                 compatible = "arm,amba-bus";
 412                 #address-cells = <2>;
 413                 #size-cells = <2>;
 414                 ranges;
 415
 416                 dmac_peri: dma-controller@ff250000 {
 417                         compatible = "arm,pl330", "arm,primecell";
 418                         reg = <0x0 0xff250000 0x0 0x4000>;
 419                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 420                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 421                         #dma-cells = <1>;
 422                         clocks = <&cru ACLK_DMAC_PERI>;
 423                         clock-names = "apb_pclk";
 424                 };
 425
 426                 dmac_bus: dma-controller@ff600000 {
 427                         compatible = "arm,pl330", "arm,primecell";
 428                         reg = <0x0 0xff600000 0x0 0x4000>;
 429                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 430                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 431                         #dma-cells = <1>;
 432                         clocks = <&cru ACLK_DMAC_BUS>;
 433                         clock-names = "apb_pclk";
 434                 };
 435         };
 436
 437         cru: clock-controller@ff760000 {
 438                 compatible = "rockchip,rk3366-cru";
 439                 reg = <0x0 0xff760000 0x0 0x1000>;
 440                 rockchip,grf = <&grf>;
 441                 #clock-cells = <1>;
 442                 #reset-cells = <1>;
 443         };
 444
 445         grf: syscon@ff770000 {
 446                 compatible = "rockchip,rk3366-grf", "syscon";
 447                 reg = <0x0 0xff770000 0x0 0x1000>;
 448         };
 449
 450         fb: fb {
 451                 compatible = "rockchip,rk-fb";
 452                 rockchip,disp-mode = <DUAL>;
 453                 status = "disabled";
 454         };
 455
 456         rk_screen: screen {
 457                 compatible = "rockchip,screen";
 458                 status = "disabled";
 459         };
 460
 461         vop_lite: vop@ff8f0000 {
 462                 compatible = "rockchip,rk3366-lcdc-lite";
 463                 rockchip,grf = <&grf>;
 464                 rockchip,pwr18 = <0>;
 465                 rockchip,iommu-enabled = <1>;
 466                 reg = <0x0 0xff8f0000 0x0 0x1000>;
 467                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 468                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 469                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 470                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
 471                 reset-names = "axi", "ahb", "dclk";
 472                 status = "disabled";
 473         };
 474
 475         vopl_mmu: vopl-mmu {
 476                 dbgname = "vop";
 477                 compatible = "rockchip,vopl_mmu";
 478                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 479                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 480                 interrupt-names = "vopl_mmu";
 481                 status = "disabled";
 482         };
 483
 484         vop_big: vop@ff930000 {
 485                 compatible = "rockchip,rk3366-lcdc-big";
 486                 rockchip,grf = <&grf>;
 487                 rockchip,prop = <PRMRY>;
 488                 rockchip,pwr18 = <0>;
 489                 rockchip,iommu-enabled = <1>;
 490                 reg = <0x0 0xff930000 0x0 0x23f0>;
 491                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 492                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
 493                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 494                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
 495                 reset-names = "axi", "ahb", "dclk";
 496                 status = "disabled";
 497         };
 498
 499         vopb_mmu: vopb-mmu {
 500                 dbgname = "vop";
 501                 compatible = "rockchip,vopb_mmu";
 502                 reg = <0x0 0xff932400 0x0 0x100>;
 503                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 504                 interrupt-names = "vop_mmu";
 505                 status = "disabled";
 506         };
 507
 508         dsihost0: mipi@ff960000 {
 509                 compatible = "rockchip,rk3368-dsi";
 510                 rockchip,prop = <0>;
 511                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 512                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 513                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 514                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 515                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 516                 status = "disabled";
 517         };
 518
 519         lvds: lvds@ff968000 {
 520                 compatible = "rockchip,rk3366-lvds";
 521                 rockchip,grf = <&grf>;
 522                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 523                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 524                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 525                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 526                 status = "disabled";
 527         };
 528
 529         pinctrl: pinctrl {
 530                 compatible = "rockchip,rk3366-pinctrl";
 531                 rockchip,grf = <&grf>;
 532                 rockchip,pmu = <&pmugrf>;
 533                 #address-cells = <0x2>;
 534                 #size-cells = <0x2>;
 535                 ranges;
 536
 537                 gpio0: gpio0@ff750000 {
 538                         compatible = "rockchip,gpio-bank";
 539                         reg = <0x0 0xff750000 0x0 0x100>;
 540                         clocks = <&cru PCLK_GPIO0>;
 541                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 542
 543                         gpio-controller;
 544                         #gpio-cells = <0x2>;
 545
 546                         interrupt-controller;
 547                         #interrupt-cells = <0x2>;
 548                 };
 549
 550                 gpio1: gpio1@ff780000 {
 551                         compatible = "rockchip,gpio-bank";
 552                         reg = <0x0 0xff758000 0x0 0x100>;
 553                         clocks = <&cru PCLK_GPIO1>;
 554                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 555
 556                         gpio-controller;
 557                         #gpio-cells = <0x2>;
 558
 559                         interrupt-controller;
 560                         #interrupt-cells = <0x2>;
 561                 };
 562
 563                 gpio2: gpio2@ff790000 {
 564                         compatible = "rockchip,gpio-bank";
 565                         reg = <0x0 0xff790000 0x0 0x100>;
 566                         clocks = <&cru PCLK_GPIO2>;
 567                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 568
 569                         gpio-controller;
 570                         #gpio-cells = <0x2>;
 571
 572                         interrupt-controller;
 573                         #interrupt-cells = <0x2>;
 574                 };
 575
 576                 gpio3: gpio3@ff7a0000 {
 577                         compatible = "rockchip,gpio-bank";
 578                         reg = <0x0 0xff7a0000 0x0 0x100>;
 579                         clocks = <&cru PCLK_GPIO3>;
 580                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 581
 582                         gpio-controller;
 583                         #gpio-cells = <0x2>;
 584
 585                         interrupt-controller;
 586                         #interrupt-cells = <0x2>;
 587                 };
 588
 589                 gpio4: gpio4@ff7b0000 {
 590                         compatible = "rockchip,gpio-bank";
 591                         reg = <0x0 0xff7b0000 0x0 0x100>;
 592                         clocks = <&cru PCLK_GPIO4>;
 593                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 594
 595                         gpio-controller;
 596                         #gpio-cells = <0x2>;
 597
 598                         interrupt-controller;
 599                         #interrupt-cells = <0x2>;
 600                 };
 601
 602                 gpio5: gpio5@ff7c0000 {
 603                         compatible = "rockchip,gpio-bank";
 604                         reg = <0x0 0xff7c0000 0x0 0x100>;
 605                         clocks = <&cru PCLK_GPIO5>;
 606                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 607
 608                         gpio-controller;
 609                         #gpio-cells = <0x2>;
 610
 611                         interrupt-controller;
 612                         #interrupt-cells = <0x2>;
 613                 };
 614
 615                 pcfg_pull_up: pcfg-pull-up {
 616                         bias-pull-up;
 617                 };
 618
 619                 pcfg_pull_down: pcfg-pull-down {
 620                         bias-pull-down;
 621                 };
 622
 623                 pcfg_pull_none: pcfg-pull-none {
 624                         bias-disable;
 625                 };
 626
 627                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 628                         bias-disable;
 629                         drive-strength = <12>;
 630                 };
 631
 632                 emmc {
 633                         emmc_clk: emmc-clk {
 634                                 rockchip,pins =
 635                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
 636                         };
 637
 638                         emmc_cmd: emmc-cmd {
 639                                 rockchip,pins =
 640                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
 641                         };
 642
 643                         emmc_pwr: emmc-pwr {
 644                                 rockchip,pins =
 645                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
 646                         };
 647
 648                         emmc_bus1: emmc-bus1 {
 649                                 rockchip,pins =
 650                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
 651                         };
 652
 653                         emmc_bus4: emmc-bus4 {
 654                                 rockchip,pins =
 655                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
 656                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
 657                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
 658                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
 659                         };
 660
 661                         emmc_bus8: emmc-bus8 {
 662                                 rockchip,pins =
 663                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
 664                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
 665                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
 666                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
 667                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
 668                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
 669                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
 670                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
 671                         };
 672                 };
 673
 674                 sdmmc {
 675                         sdmmc_cd: sdmmc-cd {
 676                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
 677                         };
 678
 679                         sdmmc_bus1: sdmmc-bus1 {
 680                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
 681                         };
 682
 683                         sdmmc_bus4: sdmmc-bus4 {
 684                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
 685                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
 686                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
 687                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
 688                         };
 689
 690                         sdmmc_clk: sdmmc-clk {
 691                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
 692                         };
 693
 694                         sdmmc_cmd: sdmmc-cmd {
 695                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
 696                         };
 697                 };
 698
 699                 sdio {
 700                         sdio_bus1: sdio-bus1 {
 701                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
 702                         };
 703
 704                         sdio_bus4: sdio-bus4 {
 705                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
 706                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
 707                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
 708                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
 709                         };
 710
 711                         sdio_cmd: sdio-cmd {
 712                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
 713                         };
 714
 715                         sdio_clk: sdio-clk {
 716                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
 717                         };
 718
 719                         sdio_cd: sdio-cd {
 720                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
 721                         };
 722
 723                         sdio_wp: sdio-wp {
 724                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
 725                         };
 726
 727                         sdio_int: sdio-int {
 728                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
 729                         };
 730
 731                         sdio_pwr: sdio-pwr {
 732                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
 733                         };
 734                 };
 735
 736                 i2c0 {
 737                         i2c0_xfer: i2c0-xfer {
 738                                 rockchip,pins =
 739                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
 740                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
 741                         };
 742                 };
 743
 744                 i2c1 {
 745                         i2c1_xfer: i2c1-xfer {
 746                                 rockchip,pins =
 747                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
 748                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
 749                         };
 750                 };
 751
 752                 i2c2 {
 753                         i2c2_xfer: i2c2-xfer {
 754                                 rockchip,pins =
 755                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
 756                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
 757                         };
 758                 };
 759
 760                 i2c3 {
 761                         i2c3_xfer: i2c3-xfer {
 762                                 rockchip,pins =
 763                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
 764                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
 765                         };
 766                 };
 767
 768                 i2c4 {
 769                         i2c4_xfer: i2c4-xfer {
 770                                 rockchip,pins =
 771                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
 772                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
 773                         };
 774                 };
 775
 776                 i2c5 {
 777                         i2c5_xfer: i2c5-xfer {
 778                                 rockchip,pins =
 779                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
 780                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
 781                         };
 782                 };
 783
 784                 i2s {
 785                         i2s_8ch_bus: i2s-8ch-bus {
 786                                 rockchip,pins =
 787                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
 788                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 789                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
 790                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
 791                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
 792                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
 793                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
 794                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
 795                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
 796                         };
 797                 };
 798
 799                 spi0 {
 800                         spi0_clk: spi0-clk {
 801                                 rockchip,pins =
 802                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
 803                         };
 804                         spi0_cs0: spi0-cs0 {
 805                                 rockchip,pins =
 806                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
 807                         };
 808                         spi0_cs1: spi0-cs1 {
 809                                 rockchip,pins =
 810                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
 811                         };
 812                         spi0_tx: spi0-tx {
 813                                 rockchip,pins =
 814                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
 815                         };
 816                         spi0_rx: spi0-rx {
 817                                 rockchip,pins =
 818                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
 819                         };
 820                 };
 821
 822                 spi1 {
 823                         spi1_clk: spi1-clk {
 824                                 rockchip,pins =
 825                                         <2 4 RK_FUNC_2 &pcfg_pull_up>;
 826                         };
 827                         spi1_cs0: spi1-cs0 {
 828                                 rockchip,pins =
 829                                         <2 5 RK_FUNC_2 &pcfg_pull_up>;
 830                         };
 831                         spi1_rx: spi1-rx {
 832                                 rockchip,pins =
 833                                         <2 6 RK_FUNC_2 &pcfg_pull_up>;
 834                         };
 835                         spi1_tx: spi1-tx {
 836                                 rockchip,pins =
 837                                         <2 7 RK_FUNC_2 &pcfg_pull_up>;
 838                         };
 839                 };
 840
 841                 uart0 {
 842                         uart0_xfer: uart0-xfer {
 843                                 rockchip,pins =
 844                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
 845                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
 846                         };
 847
 848                         uart0_cts: uart0-cts {
 849                                 rockchip,pins =
 850                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
 851                         };
 852
 853                         uart0_rts: uart0-rts {
 854                                 rockchip,pins =
 855                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
 856                         };
 857                 };
 858
 859                 uart2_t0 {
 860                         uart2_t0_xfer: uart2_t0-xfer {
 861                                 rockchip,pins =
 862                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
 863                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
 864                         };
 865                         /* no rts / cts for uart2 */
 866                 };
 867
 868                 uart2_t1 {
 869                         uart2_t1_xfer: uart2_t1-xfer {
 870                                 rockchip,pins =
 871                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
 872                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
 873                         };
 874                         /* no rts / cts for uart2 */
 875                 };
 876
 877                 uart2_t2 {
 878                         uart2_t2_xfer: uart2_t2-xfer {
 879                                 rockchip,pins =
 880                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
 881                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
 882                         };
 883                         /* no rts / cts for uart2 */
 884                 };
 885
 886                 uart3 {
 887                         uart3_xfer: uart3-xfer {
 888                                 rockchip,pins =
 889                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
 890                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
 891                         };
 892
 893                         uart3_cts: uart3-cts {
 894                                 rockchip,pins =
 895                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
 896                         };
 897
 898                         uart3_rts: uart3-rts {
 899                                 rockchip,pins =
 900                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
 901                         };
 902                 };
 903
 904                 pwm0 {
 905                         pwm0_pin: pwm0-pin {
 906                                 rockchip,pins =
 907                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
 908                         };
 909                 };
 910
 911                 pwm1 {
 912                         pwm1_pin: pwm1-pin {
 913                                 rockchip,pins =
 914                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
 915                         };
 916                 };
 917
 918                 pwm2_t0 {
 919                         pwm2_t0_pin: pwm2_t0-pin {
 920                                 rockchip,pins =
 921                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
 922                         };
 923                 };
 924
 925                 pwm2_t1 {
 926                         pwm2_t1_pin: pwm2_t1-pin {
 927                                 rockchip,pins =
 928                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
 929                         };
 930                 };
 931
 932                 pwm3_t0 {
 933                         pwm3_t0_pin: pwm3_t0-pin {
 934                                 rockchip,pins =
 935                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
 936                         };
 937                 };
 938
 939                 pwm3_t1 {
 940                         pwm3_t1_pin: pwm3_t1-pin {
 941                                 rockchip,pins =
 942                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
 943                         };
 944                 };
 945
 946                 pwm3_t2 {
 947                         pwm3_t2_pin: pwm3_t2-pin {
 948                                 rockchip,pins =
 949                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
 950                         };
 951                 };
 952
 953                 lcdc {
 954                         lcdc_lcdc: lcdc-lcdc {
 955                                 rockchip,pins =
 956                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
 957                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
 958                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
 959                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
 960                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
 961                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
 962                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
 963                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
 964                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
 965                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
 966                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
 967                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
 968                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
 969                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
 970                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
 971                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
 972                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
 973                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
 974                         };
 975
 976                         lcdc_gpio: lcdc-gpio {
 977                                 rockchip,pins =
 978                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
 979                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
 980                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
 981                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
 982                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
 983                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
 984                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
 985                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
 986                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
 987                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
 988                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
 989                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
 990                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
 991                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
 992                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
 993                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
 994                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
 995                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
 996                         };
 997                 };
 998
 999                 gmac {
1000                         rgmii_pins: rgmii-pins {
1001                                 rockchip,pins =
1002                                         /* mac_rxd3 */
1003                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1004                                         /* mac_rxd2 */
1005                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1006                                         /* mac_txd3 */
1007                                         <2 5  RK_FUNC_1 &pcfg_pull_none>,
1008                                         /* mac_txd2 */
1009                                         <2 4  RK_FUNC_1 &pcfg_pull_none>,
1010                                         /* mac_rxd1 */
1011                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1012                                         /* mac_rxd0 */
1013                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1014                                         /* mac_txd1 */
1015                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1016                                         /* mac_txd0 */
1017                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1018                                         /* mac_crs */
1019                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1020                                         /* mac_rxclkin */
1021                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1022                                         /* mac_mdio */
1023                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1024                                         /* mac_txen */
1025                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1026                                         /* mac_clk */
1027                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1028                                         /* mac_rxer */
1029                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1030                                         /* mac_rxdv */
1031                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1032                                         /* mac_mdc */
1033                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1034                         };
1035
1036                         rmii_pins: rmii-pins {
1037                                 rockchip,pins =
1038                                         /* mac_rxd1 */
1039                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1040                                         /* mac_rxd0 */
1041                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1042                                         /* mac_txd1 */
1043                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1044                                         /* mac_txd0 */
1045                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1046                                         /* mac_crs */
1047                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1048                                         /* mac_rxclkin */
1049                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1050                                         /* mac_mdio */
1051                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1052                                         /* mac_txen */
1053                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1054                                         /* mac_clk */
1055                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1056                                         /* mac_rxer */
1057                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1058                                         /* mac_rxdv */
1059                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1060                                         /* mac_mdc */
1061                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1062                         };
1063                 };
1064
1065                 eth_phy {
1066                         eth_phy_pwr: eth-phy-pwr {
1067                                 rockchip,pins =
1068                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
1069                         };
1070                 };
1071         };
1072 };