2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3366-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
49 #include <dt-bindings/power/rk3366-power.h>
52 compatible = "rockchip,rk3366";
53 interrupt-parent = <&gic>;
72 #address-cells = <0x2>;
77 compatible = "arm,cortex-a53","arm,armv8";
79 enable-method = "psci";
84 compatible = "arm,cortex-a53","arm,armv8";
86 enable-method = "psci";
91 compatible = "arm,cortex-a53","arm,armv8";
93 enable-method = "psci";
98 compatible = "arm,cortex-a53","arm,armv8";
100 enable-method = "psci";
105 compatible = "arm,psci-1.0";
110 compatible = "arm,armv8-timer";
113 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
115 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
117 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
119 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
120 clock-frequency = <24000000>;
124 compatible = "fixed-clock";
126 clock-frequency = <24000000>;
127 clock-output-names = "xin24m";
130 gic: interrupt-controller@ffb71000 {
131 compatible = "arm,gic-400";
132 interrupt-controller;
133 #interrupt-cells = <3>;
134 #address-cells = <0>;
136 reg = <0x0 0xffb71000 0x0 0x1000>,
137 <0x0 0xffb72000 0x0 0x1000>,
138 <0x0 0xffb74000 0x0 0x2000>,
139 <0x0 0xffb76000 0x0 0x2000>;
140 interrupts = <GIC_PPI 9
141 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
144 nandc0: nandc@ff0c0000 {
145 compatible = "rockchip,rk-nandc";
146 reg = <0x0 0xff0c0000 0x0 0x4000>;
147 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
149 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
150 clock-names = "clk_nandc", "hclk_nandc";
154 saradc: saradc@ff100000 {
155 compatible = "rockchip,saradc";
156 reg = <0x0 0xff100000 0x0 0x100>;
157 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
158 #io-channel-cells = <1>;
159 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
160 clock-names = "saradc", "apb_pclk";
165 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
166 reg = <0x0 0xff110000 0x0 0x1000>;
167 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
168 clock-names = "spiclk", "apb_pclk";
169 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
172 #address-cells = <1>;
178 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
179 reg = <0x0 0xff120000 0x0 0x1000>;
180 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
181 clock-names = "spiclk", "apb_pclk";
182 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
185 #address-cells = <1>;
190 sdmmc: rksdmmc@ff400000 {
191 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
192 clock-freq-min-max = <400000 150000000>;
193 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
194 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
195 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
196 fifo-depth = <0x100>;
197 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
198 reg = <0x0 0xff400000 0x0 0x4000>;
202 sdio: rksdmmc@ff410000 {
203 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
204 clock-freq-min-max = <400000 150000000>;
205 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
206 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
207 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
208 fifo-depth = <0x100>;
209 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
210 reg = <0x0 0xff410000 0x0 0x4000>;
214 emmc: rksdmmc@ff420000 {
215 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
216 clock-freq-min-max = <400000 150000000>;
217 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
218 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
219 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
220 fifo-depth = <0x100>;
221 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
222 reg = <0x0 0xff420000 0x0 0x4000>;
227 compatible = "rockchip,rk3366-gmac";
228 reg = <0x0 0xff440000 0x0 0x10000>;
229 rockchip,grf = <&grf>;
230 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
231 interrupt-names = "macirq";
232 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
233 <&cru SCLK_MAC_RX>, <&cru SCLK_MACREF>,
234 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
236 clock-names = "stmmaceth", "mac_clk_rx",
237 "mac_clk_tx", "clk_mac_ref",
238 "clk_mac_refout", "aclk_mac",
240 resets = <&cru SRST_MAC>;
241 reset-names = "stmmaceth";
246 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
247 reg = <0x0 0xff728000 0x0 0x1000>;
248 clocks = <&cru PCLK_I2C0>;
250 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&i2c0_xfer>;
253 #address-cells = <1>;
259 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
260 reg = <0x0 0xff140000 0x0 0x1000>;
261 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
262 #address-cells = <1>;
265 clocks = <&cru PCLK_I2C2>;
266 pinctrl-names = "default";
267 pinctrl-0 = <&i2c2_xfer>;
272 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
273 reg = <0x0 0xff150000 0x0 0x1000>;
274 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
275 #address-cells = <1>;
278 clocks = <&cru PCLK_I2C3>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&i2c3_xfer>;
285 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
286 reg = <0x0 0xff160000 0x0 0x1000>;
287 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
288 #address-cells = <1>;
291 clocks = <&cru PCLK_I2C4>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&i2c4_xfer>;
298 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
299 reg = <0x0 0xff170000 0x0 0x1000>;
300 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
301 #address-cells = <1>;
304 clocks = <&cru PCLK_I2C5>;
305 pinctrl-names = "default";
306 pinctrl-0 = <&i2c5_xfer>;
310 uart0: serial@ff180000 {
311 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
312 reg = <0x0 0xff180000 0x0 0x100>;
313 clock-frequency = <24000000>;
314 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
315 clock-names = "baudclk", "apb_pclk";
316 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
324 uart3: serial@ff1b0000 {
325 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
326 reg = <0x0 0xff1b0000 0x0 0x100>;
327 clock-frequency = <24000000>;
328 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
329 clock-names = "baudclk", "apb_pclk";
330 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
339 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
340 reg = <0x0 0xff660000 0x0 0x1000>;
341 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
342 #address-cells = <1>;
345 clocks = <&cru PCLK_I2C1>;
346 pinctrl-names = "default";
347 pinctrl-0 = <&i2c1_xfer>;
352 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
353 reg = <0x0 0xff680000 0x0 0x10>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&pwm0_pin>;
357 clocks = <&cru PCLK_RKPWM>;
363 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
364 reg = <0x0 0xff680010 0x0 0x10>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&pwm1_pin>;
368 clocks = <&cru PCLK_RKPWM>;
374 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
375 reg = <0x0 0xff680020 0x0 0x10>;
377 clocks = <&cru PCLK_RKPWM>;
383 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
384 reg = <0x0 0xff680030 0x0 0x10>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&pwm3_t2_pin>;
388 clocks = <&cru PCLK_RKPWM>;
393 uart2: serial@ff690000 {
394 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
395 reg = <0x0 0xff690000 0x0 0x100>;
396 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
398 clock-names = "baudclk", "apb_pclk";
401 pinctrl-names = "default";
402 pinctrl-0 = <&uart2_t1_xfer>;
406 pmu: power-management@ff730000 {
407 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
408 reg = <0x0 0xff730000 0x0 0x1000>;
410 power: power-controller {
412 compatible = "rockchip,rk3366-power-controller";
413 #power-domain-cells = <1>;
414 #address-cells = <1>;
418 * Note: Although SCLK_* are the working clocks
419 * of device without including on the NOC, needed for
422 * The clocks on the which NOC:
423 * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
424 * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
425 * ACLK_ISP is on ACLK_ISP_NIU.
426 * ACLK_HDCP is on ACLK_HDCP_NIU.
427 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
429 * Which clock are device clocks:
431 * *_IEP IEP:Image Enhancement Processor
432 * *_ISP ISP:Image Signal Processing
433 * *_VOP* VOP:Visual Output Processor
440 reg = <RK3366_PD_VIO>;
441 clocks = <&cru ACLK_IEP>,
445 <&cru ACLK_VOP_FULL>,
446 <&cru ACLK_VOP_LITE>,
448 <&cru DCLK_VOP_FULL>,
449 <&cru DCLK_VOP_LITE>,
453 <&cru HCLK_VOP_FULL>,
454 <&cru HCLK_VOP_LITE>,
455 <&cru HCLK_VIO_HDCPMMU>,
456 <&cru PCLK_HDMI_CTRL>,
458 <&cru PCLK_MIPI_DSI0>,
459 <&cru SCLK_VOP_FULL_PWM>,
463 <&cru SCLK_HDMI_CEC>,
464 <&cru SCLK_HDMI_HDCP>;
468 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
469 * (video endecoder & decoder) clocks that on the
470 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
473 reg = <RK3366_PD_VPU>;
474 clocks = <&cru ACLK_VIDEO>,
479 * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
480 * (video decoder) clocks that on the
481 * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
484 reg = <RK3366_PD_RKVDEC>;
485 clocks = <&cru ACLK_RKVDEC>,
490 reg = <RK3366_PD_VIDEO>;
491 clocks = <&cru ACLK_VIDEO>,
495 <&cru SCLK_HEVC_CABAC>,
496 <&cru SCLK_HEVC_CORE>;
500 * Note: ACLK_GPU is the GPU clock,
501 * and on the ACLK_GPU_NIU (NOC).
504 reg = <RK3366_PD_GPU>;
505 clocks = <&cru ACLK_GPU>;
510 pmugrf: syscon@ff738000 {
511 compatible = "rockchip,rk3366-pmugrf", "syscon";
512 reg = <0x0 0xff738000 0x0 0x1000>;
516 compatible = "arm,amba-bus";
517 #address-cells = <2>;
521 dmac_peri: dma-controller@ff250000 {
522 compatible = "arm,pl330", "arm,primecell";
523 reg = <0x0 0xff250000 0x0 0x4000>;
524 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&cru ACLK_DMAC_PERI>;
528 clock-names = "apb_pclk";
531 dmac_bus: dma-controller@ff600000 {
532 compatible = "arm,pl330", "arm,primecell";
533 reg = <0x0 0xff600000 0x0 0x4000>;
534 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&cru ACLK_DMAC_BUS>;
538 clock-names = "apb_pclk";
542 cru: clock-controller@ff760000 {
543 compatible = "rockchip,rk3366-cru";
544 reg = <0x0 0xff760000 0x0 0x1000>;
545 rockchip,grf = <&grf>;
550 grf: syscon@ff770000 {
551 compatible = "rockchip,rk3366-grf", "syscon";
552 reg = <0x0 0xff770000 0x0 0x1000>;
555 i2s_2ch: i2s-2ch@ff890000 {
556 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
557 reg = <0x0 0xff890000 0x0 0x1000>;
558 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
559 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
560 dma-names = "tx", "rx";
561 clock-names = "i2s_hclk", "i2s_clk";
562 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
566 i2s_8ch: i2s-8ch@ff898000 {
567 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
568 reg = <0x0 0xff898000 0x0 0x1000>;
569 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
570 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
571 dma-names = "tx", "rx";
572 clock-names = "i2s_hclk", "i2s_clk";
573 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
574 pinctrl-names = "default";
575 pinctrl-0 = <&i2s_8ch_bus>;
580 compatible = "rockchip,rk-fb";
581 rockchip,disp-mode = <DUAL>;
586 compatible = "rockchip,screen";
590 vop_lite: vop@ff8f0000 {
591 compatible = "rockchip,rk3366-lcdc-lite";
592 rockchip,grf = <&grf>;
593 rockchip,pwr18 = <0>;
594 rockchip,iommu-enabled = <1>;
595 reg = <0x0 0xff8f0000 0x0 0x1000>;
596 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
598 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
599 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
600 reset-names = "axi", "ahb", "dclk";
606 compatible = "rockchip,vopl_mmu";
607 reg = <0x0 0xff8f0f00 0x0 0x100>;
608 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
609 interrupt-names = "vopl_mmu";
613 vop_big: vop@ff930000 {
614 compatible = "rockchip,rk3366-lcdc-big";
615 rockchip,grf = <&grf>;
616 rockchip,prop = <PRMRY>;
617 rockchip,pwr18 = <0>;
618 rockchip,iommu-enabled = <1>;
619 reg = <0x0 0xff930000 0x0 0x23f0>;
620 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
622 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
623 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
624 reset-names = "axi", "ahb", "dclk";
630 compatible = "rockchip,vopb_mmu";
631 reg = <0x0 0xff932400 0x0 0x100>;
632 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
633 interrupt-names = "vop_mmu";
637 dsihost0: mipi@ff960000 {
638 compatible = "rockchip,rk3368-dsi";
640 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
641 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
642 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
644 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
648 lvds: lvds@ff968000 {
649 compatible = "rockchip,rk3366-lvds";
650 rockchip,grf = <&grf>;
651 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
652 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
653 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
654 clock-names = "pclk_lvds", "pclk_lvds_ctl";
658 hdmi: hdmi@ff980000 {
659 compatible = "rockchip,rk3366-hdmi";
660 reg = <0x0 0xff980000 0x0 0x20000>;
661 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&cru PCLK_HDMI_CTRL>,
664 <&cru SCLK_HDMI_HDCP>,
665 <&cru SCLK_HDMI_CEC>,
667 clock-names = "pclk_hdmi",
671 resets = <&cru SRST_HDMI>;
672 reset-names = "hdmi";
673 pinctrl-names = "default", "gpio";
674 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
675 pinctrl-1 = <&i2c5_gpio>;
680 compatible = "rockchip,rk3366-pinctrl";
681 rockchip,grf = <&grf>;
682 rockchip,pmu = <&pmugrf>;
683 #address-cells = <0x2>;
687 gpio0: gpio0@ff750000 {
688 compatible = "rockchip,gpio-bank";
689 reg = <0x0 0xff750000 0x0 0x100>;
690 clocks = <&cru PCLK_GPIO0>;
691 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
696 interrupt-controller;
697 #interrupt-cells = <0x2>;
700 gpio1: gpio1@ff780000 {
701 compatible = "rockchip,gpio-bank";
702 reg = <0x0 0xff758000 0x0 0x100>;
703 clocks = <&cru PCLK_GPIO1>;
704 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
709 interrupt-controller;
710 #interrupt-cells = <0x2>;
713 gpio2: gpio2@ff790000 {
714 compatible = "rockchip,gpio-bank";
715 reg = <0x0 0xff790000 0x0 0x100>;
716 clocks = <&cru PCLK_GPIO2>;
717 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
722 interrupt-controller;
723 #interrupt-cells = <0x2>;
726 gpio3: gpio3@ff7a0000 {
727 compatible = "rockchip,gpio-bank";
728 reg = <0x0 0xff7a0000 0x0 0x100>;
729 clocks = <&cru PCLK_GPIO3>;
730 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
735 interrupt-controller;
736 #interrupt-cells = <0x2>;
739 gpio4: gpio4@ff7b0000 {
740 compatible = "rockchip,gpio-bank";
741 reg = <0x0 0xff7b0000 0x0 0x100>;
742 clocks = <&cru PCLK_GPIO4>;
743 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
748 interrupt-controller;
749 #interrupt-cells = <0x2>;
752 gpio5: gpio5@ff7c0000 {
753 compatible = "rockchip,gpio-bank";
754 reg = <0x0 0xff7c0000 0x0 0x100>;
755 clocks = <&cru PCLK_GPIO5>;
756 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
761 interrupt-controller;
762 #interrupt-cells = <0x2>;
765 pcfg_pull_up: pcfg-pull-up {
769 pcfg_pull_down: pcfg-pull-down {
773 pcfg_pull_none: pcfg-pull-none {
777 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
779 drive-strength = <12>;
785 <3 4 RK_FUNC_2 &pcfg_pull_none>;
790 <2 26 RK_FUNC_2 &pcfg_pull_up>;
795 <2 27 RK_FUNC_2 &pcfg_pull_up>;
798 emmc_bus1: emmc-bus1 {
800 <2 18 RK_FUNC_2 &pcfg_pull_up>;
803 emmc_bus4: emmc-bus4 {
805 <2 18 RK_FUNC_2 &pcfg_pull_up>,
806 <2 19 RK_FUNC_2 &pcfg_pull_up>,
807 <2 20 RK_FUNC_2 &pcfg_pull_up>,
808 <2 21 RK_FUNC_2 &pcfg_pull_up>;
811 emmc_bus8: emmc-bus8 {
813 <2 18 RK_FUNC_2 &pcfg_pull_up>,
814 <2 19 RK_FUNC_2 &pcfg_pull_up>,
815 <2 20 RK_FUNC_2 &pcfg_pull_up>,
816 <2 21 RK_FUNC_2 &pcfg_pull_up>,
817 <2 22 RK_FUNC_2 &pcfg_pull_up>,
818 <2 23 RK_FUNC_2 &pcfg_pull_up>,
819 <2 24 RK_FUNC_2 &pcfg_pull_up>,
820 <2 25 RK_FUNC_2 &pcfg_pull_up>;
826 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
829 sdmmc_bus1: sdmmc-bus1 {
830 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
833 sdmmc_bus4: sdmmc-bus4 {
834 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
835 <5 1 RK_FUNC_1 &pcfg_pull_up>,
836 <5 2 RK_FUNC_1 &pcfg_pull_up>,
837 <5 3 RK_FUNC_1 &pcfg_pull_up>;
840 sdmmc_clk: sdmmc-clk {
841 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
844 sdmmc_cmd: sdmmc-cmd {
845 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
850 sdio_bus1: sdio-bus1 {
851 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
854 sdio_bus4: sdio-bus4 {
855 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
856 <3 13 RK_FUNC_1 &pcfg_pull_up>,
857 <3 14 RK_FUNC_1 &pcfg_pull_up>,
858 <3 15 RK_FUNC_1 &pcfg_pull_up>;
862 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
866 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
870 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
874 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
878 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
882 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
887 hdmii2c_xfer: hdmii2c-xfer {
889 <5 13 RK_FUNC_2 &pcfg_pull_none>,
890 <5 14 RK_FUNC_2 &pcfg_pull_none>;
897 <5 12 RK_FUNC_1 &pcfg_pull_none>;
902 i2c0_xfer: i2c0-xfer {
904 <0 3 RK_FUNC_1 &pcfg_pull_none>,
905 <0 4 RK_FUNC_1 &pcfg_pull_none>;
910 i2c1_xfer: i2c1-xfer {
912 <4 25 RK_FUNC_1 &pcfg_pull_none>,
913 <4 26 RK_FUNC_1 &pcfg_pull_none>;
918 i2c2_xfer: i2c2-xfer {
920 <5 15 RK_FUNC_2 &pcfg_pull_none>,
921 <5 16 RK_FUNC_2 &pcfg_pull_none>;
926 i2c3_xfer: i2c3-xfer {
928 <2 16 RK_FUNC_2 &pcfg_pull_none>,
929 <2 17 RK_FUNC_2 &pcfg_pull_none>;
934 i2c4_xfer: i2c4-xfer {
936 <5 8 RK_FUNC_1 &pcfg_pull_none>,
937 <5 9 RK_FUNC_1 &pcfg_pull_none>;
942 i2c5_xfer: i2c5-xfer {
944 <5 13 RK_FUNC_1 &pcfg_pull_none>,
945 <5 14 RK_FUNC_1 &pcfg_pull_none>;
947 i2c5_gpio: i2c5-gpio {
949 <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
950 <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
955 i2s_8ch_bus: i2s-8ch-bus {
957 <4 16 RK_FUNC_1 &pcfg_pull_none>,
958 <4 17 RK_FUNC_1 &pcfg_pull_none>,
959 <4 18 RK_FUNC_1 &pcfg_pull_none>,
960 <4 19 RK_FUNC_1 &pcfg_pull_none>,
961 <4 20 RK_FUNC_1 &pcfg_pull_none>,
962 <4 21 RK_FUNC_1 &pcfg_pull_none>,
963 <4 22 RK_FUNC_1 &pcfg_pull_none>,
964 <4 23 RK_FUNC_1 &pcfg_pull_none>,
965 <4 24 RK_FUNC_1 &pcfg_pull_none>;
972 <2 29 RK_FUNC_2 &pcfg_pull_up>;
976 <2 24 RK_FUNC_3 &pcfg_pull_up>;
980 <2 25 RK_FUNC_3 &pcfg_pull_up>;
984 <2 23 RK_FUNC_3 &pcfg_pull_up>;
988 <2 22 RK_FUNC_3 &pcfg_pull_up>;
995 <2 4 RK_FUNC_3 &pcfg_pull_up>;
999 <2 5 RK_FUNC_3 &pcfg_pull_up>;
1003 <2 6 RK_FUNC_3 &pcfg_pull_up>;
1007 <2 7 RK_FUNC_3 &pcfg_pull_up>;
1012 uart0_xfer: uart0-xfer {
1014 <3 8 RK_FUNC_1 &pcfg_pull_up>,
1015 <3 9 RK_FUNC_1 &pcfg_pull_none>;
1018 uart0_cts: uart0-cts {
1020 <3 10 RK_FUNC_1 &pcfg_pull_none>;
1023 uart0_rts: uart0-rts {
1025 <3 11 RK_FUNC_1 &pcfg_pull_none>;
1030 uart2_t0_xfer: uart2_t0-xfer {
1032 <0 22 RK_FUNC_1 &pcfg_pull_up>,
1033 <0 21 RK_FUNC_1 &pcfg_pull_none>;
1035 /* no rts / cts for uart2 */
1039 uart2_t1_xfer: uart2_t1-xfer {
1041 <5 0 RK_FUNC_2 &pcfg_pull_up>,
1042 <5 1 RK_FUNC_2 &pcfg_pull_none>;
1044 /* no rts / cts for uart2 */
1048 uart2_t2_xfer: uart2_t2-xfer {
1050 <5 14 RK_FUNC_3 &pcfg_pull_up>,
1051 <5 13 RK_FUNC_3 &pcfg_pull_none>;
1053 /* no rts / cts for uart2 */
1057 uart3_xfer: uart3-xfer {
1059 <5 15 RK_FUNC_1 &pcfg_pull_up>,
1060 <5 16 RK_FUNC_1 &pcfg_pull_none>;
1063 uart3_cts: uart3-cts {
1065 <5 17 RK_FUNC_1 &pcfg_pull_none>;
1068 uart3_rts: uart3-rts {
1070 <5 18 RK_FUNC_1 &pcfg_pull_none>;
1075 pwm0_pin: pwm0-pin {
1077 <0 8 RK_FUNC_1 &pcfg_pull_none>;
1082 pwm1_pin: pwm1-pin {
1084 <1 6 RK_FUNC_2 &pcfg_pull_none>;
1089 pwm2_t0_pin: pwm2_t0-pin {
1091 <2 15 RK_FUNC_3 &pcfg_pull_none>;
1096 pwm2_t1_pin: pwm2_t1-pin {
1098 <5 17 RK_FUNC_2 &pcfg_pull_none>;
1103 pwm3_t0_pin: pwm3_t0-pin {
1105 <1 0 RK_FUNC_2 &pcfg_pull_none>;
1110 pwm3_t1_pin: pwm3_t1-pin {
1112 <0 21 RK_FUNC_2 &pcfg_pull_none>;
1117 pwm3_t2_pin: pwm3_t2-pin {
1119 <5 18 RK_FUNC_2 &pcfg_pull_none>;
1124 lcdc_lcdc: lcdc-lcdc {
1126 <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1127 <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1128 <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1129 <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1130 <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1131 <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1132 <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1133 <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1134 <1 0 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1135 <1 1 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1136 <1 2 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1137 <1 3 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1138 <1 4 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1139 <1 5 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1140 <1 6 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1141 <1 7 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1142 <1 8 RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1143 <1 9 RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1146 lcdc_gpio: lcdc-gpio {
1148 <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1149 <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1150 <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1151 <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1152 <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1153 <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1154 <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1155 <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1156 <1 0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1157 <1 1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1158 <1 2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1159 <1 3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1160 <1 4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1161 <1 5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1162 <1 6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1163 <1 7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1164 <1 8 RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1165 <1 9 RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1170 rgmii_pins: rgmii-pins {
1173 <2 7 RK_FUNC_1 &pcfg_pull_none>,
1175 <2 6 RK_FUNC_1 &pcfg_pull_none>,
1177 <2 5 RK_FUNC_1 &pcfg_pull_none>,
1179 <2 4 RK_FUNC_1 &pcfg_pull_none>,
1181 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1183 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1185 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1187 <2 0 RK_FUNC_1 &pcfg_pull_none>,
1189 /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1191 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1193 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1195 <2 12 RK_FUNC_1 &pcfg_pull_none>,
1197 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1199 /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1201 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1203 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1206 rmii_pins: rmii-pins {
1209 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1211 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1213 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1215 <2 0 RK_FUNC_1 &pcfg_pull_none>,
1217 /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1219 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1221 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1223 <2 12 RK_FUNC_1 &pcfg_pull_none>,
1225 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1227 /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1229 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1231 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1236 eth_phy_pwr: eth-phy-pwr {
1238 <0 24 RK_FUNC_GPIO &pcfg_pull_none>;