arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/power/rk3366-power.h>
  50
  51 / {
  52         compatible = "rockchip,rk3366";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 serial0 = &uart0;
  65                 serial2 = &uart2;
  66                 serial3 = &uart3;
  67                 spi0 = &spi0;
  68                 spi1 = &spi1;
  69         };
  70
  71         cpus {
  72                 #address-cells = <0x2>;
  73                 #size-cells = <0x0>;
  74
  75                 cpu0: cpu@0 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a53","arm,armv8";
  78                         reg = <0x0 0x0>;
  79                         enable-method = "psci";
  80                 };
  81
  82                 cpu1: cpu@1 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53","arm,armv8";
  85                         reg = <0x0 0x1>;
  86                         enable-method = "psci";
  87                 };
  88
  89                 cpu2: cpu@2 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a53","arm,armv8";
  92                         reg = <0x0 0x2>;
  93                         enable-method = "psci";
  94                 };
  95
  96                 cpu3: cpu@3 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a53","arm,armv8";
  99                         reg = <0x0 0x3>;
 100                         enable-method = "psci";
 101                 };
 102         };
 103
 104         psci {
 105                 compatible = "arm,psci-1.0";
 106                 method = "smc";
 107         };
 108
 109         timer {
 110                 compatible = "arm,armv8-timer";
 111                 interrupts = <
 112                                 GIC_PPI 13
 113                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 114                                 <GIC_PPI 14
 115                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 116                                 <GIC_PPI 11
 117                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 118                                 <GIC_PPI 10
 119                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 120                 clock-frequency = <24000000>;
 121         };
 122
 123         xin24m: xin24m {
 124                 compatible = "fixed-clock";
 125                 #clock-cells = <0>;
 126                 clock-frequency = <24000000>;
 127                 clock-output-names = "xin24m";
 128         };
 129
 130         gic: interrupt-controller@ffb71000 {
 131                 compatible = "arm,gic-400";
 132                 interrupt-controller;
 133                 #interrupt-cells = <3>;
 134                 #address-cells = <0>;
 135
 136                 reg = <0x0 0xffb71000 0x0 0x1000>,
 137                       <0x0 0xffb72000 0x0 0x1000>,
 138                       <0x0 0xffb74000 0x0 0x2000>,
 139                       <0x0 0xffb76000 0x0 0x2000>;
 140                 interrupts = <GIC_PPI 9
 141                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 142         };
 143
 144         nandc0: nandc@ff0c0000 {
 145                 compatible = "rockchip,rk-nandc";
 146                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 147                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 148                 nandc_id = <0>;
 149                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 150                 clock-names = "clk_nandc", "hclk_nandc";
 151                 status = "disabled";
 152         };
 153
 154         saradc: saradc@ff100000 {
 155                 compatible = "rockchip,saradc";
 156                 reg = <0x0 0xff100000 0x0 0x100>;
 157                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 158                 #io-channel-cells = <1>;
 159                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 160                 clock-names = "saradc", "apb_pclk";
 161                 status = "disabled";
 162         };
 163
 164         spi0: spi@ff110000 {
 165                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 166                 reg = <0x0 0xff110000 0x0 0x1000>;
 167                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 168                 clock-names = "spiclk", "apb_pclk";
 169                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 170                 pinctrl-names = "default";
 171                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 172                 #address-cells = <1>;
 173                 #size-cells = <0>;
 174                 status = "disabled";
 175         };
 176
 177         spi1: spi@ff120000 {
 178                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 179                 reg = <0x0 0xff120000 0x0 0x1000>;
 180                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 181                 clock-names = "spiclk", "apb_pclk";
 182                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 183                 pinctrl-names = "default";
 184                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 185                 #address-cells = <1>;
 186                 #size-cells = <0>;
 187                 status = "disabled";
 188         };
 189
 190         sdmmc: rksdmmc@ff400000 {
 191                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 192                 clock-freq-min-max = <400000 150000000>;
 193                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 194                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 195                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 196                 fifo-depth = <0x100>;
 197                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 198                 reg = <0x0 0xff400000 0x0 0x4000>;
 199                 status = "disabled";
 200         };
 201
 202         sdio: rksdmmc@ff410000 {
 203                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 204                 clock-freq-min-max = <400000 150000000>;
 205                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 206                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 207                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 208                 fifo-depth = <0x100>;
 209                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 210                 reg = <0x0 0xff410000 0x0 0x4000>;
 211                 status = "disabled";
 212         };
 213
 214         emmc: rksdmmc@ff420000 {
 215                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 216                 clock-freq-min-max = <400000 150000000>;
 217                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 218                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 219                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 220                 fifo-depth = <0x100>;
 221                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 222                 reg = <0x0 0xff420000 0x0 0x4000>;
 223                 status = "disabled";
 224         };
 225
 226         gmac: eth@ff440000 {
 227                 compatible = "rockchip,rk3366-gmac";
 228                 reg = <0x0 0xff440000 0x0 0x10000>;
 229                 rockchip,grf = <&grf>;
 230                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 231                 interrupt-names = "macirq";
 232                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 233                          <&cru SCLK_MAC_RX>, <&cru SCLK_MACREF>,
 234                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 235                          <&cru PCLK_GMAC>;
 236                 clock-names = "stmmaceth", "mac_clk_rx",
 237                               "mac_clk_tx", "clk_mac_ref",
 238                               "clk_mac_refout", "aclk_mac",
 239                               "pclk_mac";
 240                 resets = <&cru SRST_MAC>;
 241                 reset-names = "stmmaceth";
 242                 status = "disabled";
 243         };
 244
 245         i2c0: i2c@ff650000 {
 246                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 247                 reg = <0x0 0xff728000 0x0 0x1000>;
 248                 clocks = <&cru PCLK_I2C0>;
 249                 clock-names = "i2c";
 250                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 251                 pinctrl-names = "default";
 252                 pinctrl-0 = <&i2c0_xfer>;
 253                 #address-cells = <1>;
 254                 #size-cells = <0>;
 255                 status = "disabled";
 256         };
 257
 258         i2c2: i2c@ff140000 {
 259                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 260                 reg = <0x0 0xff140000 0x0 0x1000>;
 261                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 262                 #address-cells = <1>;
 263                 #size-cells = <0>;
 264                 clock-names = "i2c";
 265                 clocks = <&cru PCLK_I2C2>;
 266                 pinctrl-names = "default";
 267                 pinctrl-0 = <&i2c2_xfer>;
 268                 status = "disabled";
 269         };
 270
 271         i2c3: i2c@ff150000 {
 272                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 273                 reg = <0x0 0xff150000 0x0 0x1000>;
 274                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 275                 #address-cells = <1>;
 276                 #size-cells = <0>;
 277                 clock-names = "i2c";
 278                 clocks = <&cru PCLK_I2C3>;
 279                 pinctrl-names = "default";
 280                 pinctrl-0 = <&i2c3_xfer>;
 281                 status = "disabled";
 282         };
 283
 284         i2c4: i2c@ff160000 {
 285                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 286                 reg = <0x0 0xff160000 0x0 0x1000>;
 287                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 288                 #address-cells = <1>;
 289                 #size-cells = <0>;
 290                 clock-names = "i2c";
 291                 clocks = <&cru PCLK_I2C4>;
 292                 pinctrl-names = "default";
 293                 pinctrl-0 = <&i2c4_xfer>;
 294                 status = "disabled";
 295         };
 296
 297         i2c5: i2c@ff170000 {
 298                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 299                 reg = <0x0 0xff170000 0x0 0x1000>;
 300                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303                 clock-names = "i2c";
 304                 clocks = <&cru PCLK_I2C5>;
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&i2c5_xfer>;
 307                 status = "disabled";
 308         };
 309
 310         uart0: serial@ff180000 {
 311                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 312                 reg = <0x0 0xff180000 0x0 0x100>;
 313                 clock-frequency = <24000000>;
 314                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 315                 clock-names = "baudclk", "apb_pclk";
 316                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 317                 reg-shift = <2>;
 318                 reg-io-width = <4>;
 319                 pinctrl-names = "default";
 320                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 321                 status = "disabled";
 322         };
 323
 324         uart3: serial@ff1b0000 {
 325                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 326                 reg = <0x0 0xff1b0000 0x0 0x100>;
 327                 clock-frequency = <24000000>;
 328                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 329                 clock-names = "baudclk", "apb_pclk";
 330                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 331                 reg-shift = <2>;
 332                 reg-io-width = <4>;
 333                 pinctrl-names = "default";
 334                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 335                 status = "disabled";
 336         };
 337
 338         i2c1: i2c@ff660000 {
 339                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 340                 reg = <0x0 0xff660000 0x0 0x1000>;
 341                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 342                 #address-cells = <1>;
 343                 #size-cells = <0>;
 344                 clock-names = "i2c";
 345                 clocks = <&cru PCLK_I2C1>;
 346                 pinctrl-names = "default";
 347                 pinctrl-0 = <&i2c1_xfer>;
 348                 status = "disabled";
 349         };
 350
 351         pwm0: pwm@ff680000 {
 352                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 353                 reg = <0x0 0xff680000 0x0 0x10>;
 354                 #pwm-cells = <3>;
 355                 pinctrl-names = "default";
 356                 pinctrl-0 = <&pwm0_pin>;
 357                 clocks = <&cru PCLK_RKPWM>;
 358                 clock-names = "pwm";
 359                 status = "disabled";
 360         };
 361
 362         pwm1: pwm@ff680010 {
 363                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 364                 reg = <0x0 0xff680010 0x0 0x10>;
 365                 #pwm-cells = <3>;
 366                 pinctrl-names = "default";
 367                 pinctrl-0 = <&pwm1_pin>;
 368                 clocks = <&cru PCLK_RKPWM>;
 369                 clock-names = "pwm";
 370                 status = "disabled";
 371         };
 372
 373         pwm2: pwm@ff680020 {
 374                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 375                 reg = <0x0 0xff680020 0x0 0x10>;
 376                 #pwm-cells = <3>;
 377                 clocks = <&cru PCLK_RKPWM>;
 378                 clock-names = "pwm";
 379                 status = "disabled";
 380         };
 381
 382         pwm3: pwm@ff680030 {
 383                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 384                 reg = <0x0 0xff680030 0x0 0x10>;
 385                 #pwm-cells = <3>;
 386                 pinctrl-names = "default";
 387                 pinctrl-0 = <&pwm3_t2_pin>;
 388                 clocks = <&cru PCLK_RKPWM>;
 389                 clock-names = "pwm";
 390                 status = "disabled";
 391         };
 392
 393         uart2: serial@ff690000 {
 394                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 395                 reg = <0x0 0xff690000 0x0 0x100>;
 396                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 397                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 398                 clock-names = "baudclk", "apb_pclk";
 399                 reg-shift = <2>;
 400                 reg-io-width = <4>;
 401                 pinctrl-names = "default";
 402                 pinctrl-0 = <&uart2_t1_xfer>;
 403                 status = "disabled";
 404         };
 405
 406         pmu: power-management@ff730000 {
 407                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
 408                 reg = <0x0 0xff730000 0x0 0x1000>;
 409
 410                 power: power-controller {
 411                         status = "disabled";
 412                         compatible = "rockchip,rk3366-power-controller";
 413                         #power-domain-cells = <1>;
 414                         #address-cells = <1>;
 415                         #size-cells = <0>;
 416
 417                         /*
 418                          * Note: Although SCLK_* are the working clocks
 419                          * of device without including on the NOC, needed for
 420                          * synchronous reset.
 421                          *
 422                          * The clocks on the which NOC:
 423                          * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 424                          * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
 425                          * ACLK_ISP is on ACLK_ISP_NIU.
 426                          * ACLK_HDCP is on ACLK_HDCP_NIU.
 427                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 428                          *
 429                          * Which clock are device clocks:
 430                          *      clocks          devices
 431                          *      *_IEP           IEP:Image Enhancement Processor
 432                          *      *_ISP           ISP:Image Signal Processing
 433                          *      *_VOP*          VOP:Visual Output Processor
 434                          *      *_RGA           RGA
 435                          *      *_DPHY*         LVDS
 436                          *      *_HDMI          HDMI
 437                          *      *_MIPI_*        MIPI
 438                          */
 439                         pd_vio {
 440                                 reg = <RK3366_PD_VIO>;
 441                                 clocks = <&cru ACLK_IEP>,
 442                                          <&cru ACLK_ISP>,
 443                                          <&cru ACLK_RGA>,
 444                                          <&cru ACLK_HDCP>,
 445                                          <&cru ACLK_VOP_FULL>,
 446                                          <&cru ACLK_VOP_LITE>,
 447                                          <&cru ACLK_VOP_IEP>,
 448                                          <&cru DCLK_VOP_FULL>,
 449                                          <&cru DCLK_VOP_LITE>,
 450                                          <&cru HCLK_IEP>,
 451                                          <&cru HCLK_ISP>,
 452                                          <&cru HCLK_RGA>,
 453                                          <&cru HCLK_VOP_FULL>,
 454                                          <&cru HCLK_VOP_LITE>,
 455                                          <&cru HCLK_VIO_HDCPMMU>,
 456                                          <&cru PCLK_HDMI_CTRL>,
 457                                          <&cru PCLK_HDCP>,
 458                                          <&cru PCLK_MIPI_DSI0>,
 459                                          <&cru SCLK_VOP_FULL_PWM>,
 460                                          <&cru SCLK_HDCP>,
 461                                          <&cru SCLK_ISP>,
 462                                          <&cru SCLK_RGA>,
 463                                          <&cru SCLK_HDMI_CEC>,
 464                                          <&cru SCLK_HDMI_HDCP>;
 465                         };
 466
 467                         /*
 468                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 469                          * (video endecoder & decoder) clocks that on the
 470                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 471                          */
 472                         pd_vpu {
 473                                 reg = <RK3366_PD_VPU>;
 474                                 clocks = <&cru ACLK_VIDEO>,
 475                                          <&cru HCLK_VIDEO>;
 476                         };
 477
 478                         /*
 479                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
 480                          * (video decoder) clocks that on the
 481                          * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
 482                          */
 483                         pd_rkvdec {
 484                                 reg = <RK3366_PD_RKVDEC>;
 485                                 clocks = <&cru ACLK_RKVDEC>,
 486                                          <&cru HCLK_RKVDEC>;
 487                         };
 488
 489                         pd_video {
 490                                 reg = <RK3366_PD_VIDEO>;
 491                                 clocks = <&cru ACLK_VIDEO>,
 492                                          <&cru ACLK_RKVDEC>,
 493                                          <&cru HCLK_VIDEO>,
 494                                          <&cru HCLK_RKVDEC>,
 495                                          <&cru SCLK_HEVC_CABAC>,
 496                                          <&cru SCLK_HEVC_CORE>;
 497                         };
 498
 499                         /*
 500                          * Note: ACLK_GPU is the GPU clock,
 501                          * and on the ACLK_GPU_NIU (NOC).
 502                          */
 503                         pd_gpu {
 504                                 reg = <RK3366_PD_GPU>;
 505                                 clocks = <&cru ACLK_GPU>;
 506                         };
 507                 };
 508         };
 509
 510         pmugrf: syscon@ff738000 {
 511                 compatible = "rockchip,rk3366-pmugrf", "syscon";
 512                 reg = <0x0 0xff738000 0x0 0x1000>;
 513         };
 514
 515         amba {
 516                 compatible = "arm,amba-bus";
 517                 #address-cells = <2>;
 518                 #size-cells = <2>;
 519                 ranges;
 520
 521                 dmac_peri: dma-controller@ff250000 {
 522                         compatible = "arm,pl330", "arm,primecell";
 523                         reg = <0x0 0xff250000 0x0 0x4000>;
 524                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 525                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 526                         #dma-cells = <1>;
 527                         clocks = <&cru ACLK_DMAC_PERI>;
 528                         clock-names = "apb_pclk";
 529                 };
 530
 531                 dmac_bus: dma-controller@ff600000 {
 532                         compatible = "arm,pl330", "arm,primecell";
 533                         reg = <0x0 0xff600000 0x0 0x4000>;
 534                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 535                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 536                         #dma-cells = <1>;
 537                         clocks = <&cru ACLK_DMAC_BUS>;
 538                         clock-names = "apb_pclk";
 539                 };
 540         };
 541
 542         cru: clock-controller@ff760000 {
 543                 compatible = "rockchip,rk3366-cru";
 544                 reg = <0x0 0xff760000 0x0 0x1000>;
 545                 rockchip,grf = <&grf>;
 546                 #clock-cells = <1>;
 547                 #reset-cells = <1>;
 548                 assigned-clocks =
 549                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 550                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
 551                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
 552                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
 553                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
 554                 assigned-clock-rates =
 555                         <750000000>, <576000000>,
 556                         <594000000>, <594000000>,
 557                         <480000000>, <520000000>,
 558                         <375000000>, <288000000>,
 559                         <100000000>, <100000000>;
 560         };
 561
 562         grf: syscon@ff770000 {
 563                 compatible = "rockchip,rk3366-grf", "syscon";
 564                 reg = <0x0 0xff770000 0x0 0x1000>;
 565         };
 566
 567         i2s_2ch: i2s-2ch@ff890000 {
 568                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 569                 reg = <0x0 0xff890000 0x0 0x1000>;
 570                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 571                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 572                 dma-names = "tx", "rx";
 573                 clock-names = "i2s_hclk", "i2s_clk";
 574                 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
 575                 status = "disabled";
 576         };
 577
 578         i2s_8ch: i2s-8ch@ff898000 {
 579                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 580                 reg = <0x0 0xff898000 0x0 0x1000>;
 581                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 582                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 583                 dma-names = "tx", "rx";
 584                 clock-names = "i2s_hclk", "i2s_clk";
 585                 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
 586                 pinctrl-names = "default";
 587                 pinctrl-0 = <&i2s_8ch_bus>;
 588                 status = "disabled";
 589         };
 590
 591         fb: fb {
 592                 compatible = "rockchip,rk-fb";
 593                 rockchip,disp-mode = <DUAL>;
 594                 status = "disabled";
 595         };
 596
 597         rk_screen: screen {
 598                 compatible = "rockchip,screen";
 599                 status = "disabled";
 600         };
 601
 602         vop_lite: vop@ff8f0000 {
 603                 compatible = "rockchip,rk3366-lcdc-lite";
 604                 rockchip,grf = <&grf>;
 605                 rockchip,pwr18 = <0>;
 606                 rockchip,iommu-enabled = <1>;
 607                 reg = <0x0 0xff8f0000 0x0 0x1000>;
 608                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 609                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 610                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 611                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
 612                 reset-names = "axi", "ahb", "dclk";
 613                 status = "disabled";
 614         };
 615
 616         vopl_mmu: vopl-mmu {
 617                 dbgname = "vop";
 618                 compatible = "rockchip,vopl_mmu";
 619                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 620                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 621                 interrupt-names = "vopl_mmu";
 622                 status = "disabled";
 623         };
 624
 625         rga: rga@ff920000 {
 626                 compatible = "rockchip,rga2";
 627                 dev_mode = <1>;
 628                 reg = <0x0 0xff920000 0x0 0x1000>;
 629                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 630                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 631                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 632                 status = "disabled";
 633         };
 634
 635         vop_big: vop@ff930000 {
 636                 compatible = "rockchip,rk3366-lcdc-big";
 637                 rockchip,grf = <&grf>;
 638                 rockchip,prop = <PRMRY>;
 639                 rockchip,pwr18 = <0>;
 640                 rockchip,iommu-enabled = <1>;
 641                 reg = <0x0 0xff930000 0x0 0x23f0>;
 642                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 643                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
 644                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 645                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
 646                 reset-names = "axi", "ahb", "dclk";
 647                 status = "disabled";
 648         };
 649
 650         vopb_mmu: vopb-mmu {
 651                 dbgname = "vop";
 652                 compatible = "rockchip,vopb_mmu";
 653                 reg = <0x0 0xff932400 0x0 0x100>;
 654                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 655                 interrupt-names = "vop_mmu";
 656                 status = "disabled";
 657         };
 658
 659         dsihost0: mipi@ff960000 {
 660                 compatible = "rockchip,rk3368-dsi";
 661                 rockchip,prop = <0>;
 662                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 663                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 664                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 665                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 666                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 667                 status = "disabled";
 668         };
 669
 670         lvds: lvds@ff968000 {
 671                 compatible = "rockchip,rk3366-lvds";
 672                 rockchip,grf = <&grf>;
 673                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 674                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 675                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 676                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 677                 status = "disabled";
 678         };
 679
 680         hdmi: hdmi@ff980000 {
 681                 compatible = "rockchip,rk3366-hdmi";
 682                 reg = <0x0 0xff980000 0x0 0x20000>;
 683                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 684                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 685                 clocks = <&cru PCLK_HDMI_CTRL>,
 686                          <&cru SCLK_HDMI_HDCP>,
 687                          <&cru SCLK_HDMI_CEC>,
 688                          <&cru DCLK_HDMIPHY>;
 689                 clock-names = "pclk_hdmi",
 690                               "hdcp_clk_hdmi",
 691                               "cec_clk_hdmi",
 692                               "dclk_hdmi_phy";
 693                 resets = <&cru SRST_HDMI>;
 694                 reset-names = "hdmi";
 695                 pinctrl-names = "default", "gpio";
 696                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 697                 pinctrl-1 = <&i2c5_gpio>;
 698                 status = "disabled";
 699         };
 700
 701         pinctrl: pinctrl {
 702                 compatible = "rockchip,rk3366-pinctrl";
 703                 rockchip,grf = <&grf>;
 704                 rockchip,pmu = <&pmugrf>;
 705                 #address-cells = <0x2>;
 706                 #size-cells = <0x2>;
 707                 ranges;
 708
 709                 gpio0: gpio0@ff750000 {
 710                         compatible = "rockchip,gpio-bank";
 711                         reg = <0x0 0xff750000 0x0 0x100>;
 712                         clocks = <&cru PCLK_GPIO0>;
 713                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 714
 715                         gpio-controller;
 716                         #gpio-cells = <0x2>;
 717
 718                         interrupt-controller;
 719                         #interrupt-cells = <0x2>;
 720                 };
 721
 722                 gpio1: gpio1@ff780000 {
 723                         compatible = "rockchip,gpio-bank";
 724                         reg = <0x0 0xff758000 0x0 0x100>;
 725                         clocks = <&cru PCLK_GPIO1>;
 726                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 727
 728                         gpio-controller;
 729                         #gpio-cells = <0x2>;
 730
 731                         interrupt-controller;
 732                         #interrupt-cells = <0x2>;
 733                 };
 734
 735                 gpio2: gpio2@ff790000 {
 736                         compatible = "rockchip,gpio-bank";
 737                         reg = <0x0 0xff790000 0x0 0x100>;
 738                         clocks = <&cru PCLK_GPIO2>;
 739                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 740
 741                         gpio-controller;
 742                         #gpio-cells = <0x2>;
 743
 744                         interrupt-controller;
 745                         #interrupt-cells = <0x2>;
 746                 };
 747
 748                 gpio3: gpio3@ff7a0000 {
 749                         compatible = "rockchip,gpio-bank";
 750                         reg = <0x0 0xff7a0000 0x0 0x100>;
 751                         clocks = <&cru PCLK_GPIO3>;
 752                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 753
 754                         gpio-controller;
 755                         #gpio-cells = <0x2>;
 756
 757                         interrupt-controller;
 758                         #interrupt-cells = <0x2>;
 759                 };
 760
 761                 gpio4: gpio4@ff7b0000 {
 762                         compatible = "rockchip,gpio-bank";
 763                         reg = <0x0 0xff7b0000 0x0 0x100>;
 764                         clocks = <&cru PCLK_GPIO4>;
 765                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 766
 767                         gpio-controller;
 768                         #gpio-cells = <0x2>;
 769
 770                         interrupt-controller;
 771                         #interrupt-cells = <0x2>;
 772                 };
 773
 774                 gpio5: gpio5@ff7c0000 {
 775                         compatible = "rockchip,gpio-bank";
 776                         reg = <0x0 0xff7c0000 0x0 0x100>;
 777                         clocks = <&cru PCLK_GPIO5>;
 778                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 779
 780                         gpio-controller;
 781                         #gpio-cells = <0x2>;
 782
 783                         interrupt-controller;
 784                         #interrupt-cells = <0x2>;
 785                 };
 786
 787                 pcfg_pull_up: pcfg-pull-up {
 788                         bias-pull-up;
 789                 };
 790
 791                 pcfg_pull_down: pcfg-pull-down {
 792                         bias-pull-down;
 793                 };
 794
 795                 pcfg_pull_none: pcfg-pull-none {
 796                         bias-disable;
 797                 };
 798
 799                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 800                         bias-disable;
 801                         drive-strength = <12>;
 802                 };
 803
 804                 emmc {
 805                         emmc_clk: emmc-clk {
 806                                 rockchip,pins =
 807                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
 808                         };
 809
 810                         emmc_cmd: emmc-cmd {
 811                                 rockchip,pins =
 812                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
 813                         };
 814
 815                         emmc_pwr: emmc-pwr {
 816                                 rockchip,pins =
 817                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
 818                         };
 819
 820                         emmc_bus1: emmc-bus1 {
 821                                 rockchip,pins =
 822                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
 823                         };
 824
 825                         emmc_bus4: emmc-bus4 {
 826                                 rockchip,pins =
 827                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
 828                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
 829                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
 830                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
 831                         };
 832
 833                         emmc_bus8: emmc-bus8 {
 834                                 rockchip,pins =
 835                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
 836                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
 837                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
 838                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
 839                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
 840                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
 841                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
 842                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
 843                         };
 844                 };
 845
 846                 sdmmc {
 847                         sdmmc_cd: sdmmc-cd {
 848                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
 849                         };
 850
 851                         sdmmc_bus1: sdmmc-bus1 {
 852                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
 853                         };
 854
 855                         sdmmc_bus4: sdmmc-bus4 {
 856                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
 857                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
 858                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
 859                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
 860                         };
 861
 862                         sdmmc_clk: sdmmc-clk {
 863                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
 864                         };
 865
 866                         sdmmc_cmd: sdmmc-cmd {
 867                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
 868                         };
 869                 };
 870
 871                 sdio {
 872                         sdio_bus1: sdio-bus1 {
 873                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
 874                         };
 875
 876                         sdio_bus4: sdio-bus4 {
 877                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
 878                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
 879                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
 880                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
 881                         };
 882
 883                         sdio_cmd: sdio-cmd {
 884                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
 885                         };
 886
 887                         sdio_clk: sdio-clk {
 888                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
 889                         };
 890
 891                         sdio_cd: sdio-cd {
 892                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
 893                         };
 894
 895                         sdio_wp: sdio-wp {
 896                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
 897                         };
 898
 899                         sdio_int: sdio-int {
 900                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
 901                         };
 902
 903                         sdio_pwr: sdio-pwr {
 904                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
 905                         };
 906                 };
 907
 908                 hdmi_i2c {
 909                         hdmii2c_xfer: hdmii2c-xfer {
 910                                 rockchip,pins =
 911                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
 912                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
 913                         };
 914                 };
 915
 916                 hdmi_pin {
 917                         hdmi_cec: hdmi-cec {
 918                                 rockchip,pins =
 919                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
 920                         };
 921                 };
 922
 923                 i2c0 {
 924                         i2c0_xfer: i2c0-xfer {
 925                                 rockchip,pins =
 926                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
 927                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
 928                         };
 929                 };
 930
 931                 i2c1 {
 932                         i2c1_xfer: i2c1-xfer {
 933                                 rockchip,pins =
 934                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
 935                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
 936                         };
 937                 };
 938
 939                 i2c2 {
 940                         i2c2_xfer: i2c2-xfer {
 941                                 rockchip,pins =
 942                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
 943                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
 944                         };
 945                 };
 946
 947                 i2c3 {
 948                         i2c3_xfer: i2c3-xfer {
 949                                 rockchip,pins =
 950                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
 951                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
 952                         };
 953                 };
 954
 955                 i2c4 {
 956                         i2c4_xfer: i2c4-xfer {
 957                                 rockchip,pins =
 958                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
 959                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
 960                         };
 961                 };
 962
 963                 i2c5 {
 964                         i2c5_xfer: i2c5-xfer {
 965                                 rockchip,pins =
 966                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
 967                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
 968                         };
 969                         i2c5_gpio: i2c5-gpio {
 970                                 rockchip,pins =
 971                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
 972                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
 973                         };
 974                 };
 975
 976                 i2s {
 977                         i2s_8ch_bus: i2s-8ch-bus {
 978                                 rockchip,pins =
 979                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
 980                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 981                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
 982                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
 983                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
 984                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
 985                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
 986                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
 987                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
 988                         };
 989                 };
 990
 991                 spi0 {
 992                         spi0_clk: spi0-clk {
 993                                 rockchip,pins =
 994                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
 995                         };
 996                         spi0_cs0: spi0-cs0 {
 997                                 rockchip,pins =
 998                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
 999                         };
1000                         spi0_cs1: spi0-cs1 {
1001                                 rockchip,pins =
1002                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1003                         };
1004                         spi0_tx: spi0-tx {
1005                                 rockchip,pins =
1006                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1007                         };
1008                         spi0_rx: spi0-rx {
1009                                 rockchip,pins =
1010                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1011                         };
1012                 };
1013
1014                 spi1 {
1015                         spi1_clk: spi1-clk {
1016                                 rockchip,pins =
1017                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1018                         };
1019                         spi1_cs0: spi1-cs0 {
1020                                 rockchip,pins =
1021                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1022                         };
1023                         spi1_tx: spi1-tx {
1024                                 rockchip,pins =
1025                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1026                         };
1027                         spi1_rx: spi1-rx {
1028                                 rockchip,pins =
1029                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1030                         };
1031                 };
1032
1033                 uart0 {
1034                         uart0_xfer: uart0-xfer {
1035                                 rockchip,pins =
1036                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1037                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1038                         };
1039
1040                         uart0_cts: uart0-cts {
1041                                 rockchip,pins =
1042                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1043                         };
1044
1045                         uart0_rts: uart0-rts {
1046                                 rockchip,pins =
1047                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1048                         };
1049                 };
1050
1051                 uart2_t0 {
1052                         uart2_t0_xfer: uart2_t0-xfer {
1053                                 rockchip,pins =
1054                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1055                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1056                         };
1057                         /* no rts / cts for uart2 */
1058                 };
1059
1060                 uart2_t1 {
1061                         uart2_t1_xfer: uart2_t1-xfer {
1062                                 rockchip,pins =
1063                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1064                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1065                         };
1066                         /* no rts / cts for uart2 */
1067                 };
1068
1069                 uart2_t2 {
1070                         uart2_t2_xfer: uart2_t2-xfer {
1071                                 rockchip,pins =
1072                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1073                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1074                         };
1075                         /* no rts / cts for uart2 */
1076                 };
1077
1078                 uart3 {
1079                         uart3_xfer: uart3-xfer {
1080                                 rockchip,pins =
1081                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1082                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1083                         };
1084
1085                         uart3_cts: uart3-cts {
1086                                 rockchip,pins =
1087                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1088                         };
1089
1090                         uart3_rts: uart3-rts {
1091                                 rockchip,pins =
1092                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1093                         };
1094                 };
1095
1096                 pwm0 {
1097                         pwm0_pin: pwm0-pin {
1098                                 rockchip,pins =
1099                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1100                         };
1101                 };
1102
1103                 pwm1 {
1104                         pwm1_pin: pwm1-pin {
1105                                 rockchip,pins =
1106                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1107                         };
1108                 };
1109
1110                 pwm2_t0 {
1111                         pwm2_t0_pin: pwm2_t0-pin {
1112                                 rockchip,pins =
1113                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1114                         };
1115                 };
1116
1117                 pwm2_t1 {
1118                         pwm2_t1_pin: pwm2_t1-pin {
1119                                 rockchip,pins =
1120                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1121                         };
1122                 };
1123
1124                 pwm3_t0 {
1125                         pwm3_t0_pin: pwm3_t0-pin {
1126                                 rockchip,pins =
1127                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1128                         };
1129                 };
1130
1131                 pwm3_t1 {
1132                         pwm3_t1_pin: pwm3_t1-pin {
1133                                 rockchip,pins =
1134                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1135                         };
1136                 };
1137
1138                 pwm3_t2 {
1139                         pwm3_t2_pin: pwm3_t2-pin {
1140                                 rockchip,pins =
1141                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1142                         };
1143                 };
1144
1145                 lcdc {
1146                         lcdc_lcdc: lcdc-lcdc {
1147                                 rockchip,pins =
1148                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1149                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1150                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1151                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1152                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1153                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1154                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1155                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1156                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1157                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1158                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1159                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1160                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1161                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1162                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1163                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1164                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1165                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1166                         };
1167
1168                         lcdc_gpio: lcdc-gpio {
1169                                 rockchip,pins =
1170                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1171                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1172                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1173                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1174                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1175                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1176                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1177                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1178                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1179                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1180                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1181                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1182                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1183                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1184                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1185                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1186                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1187                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1188                         };
1189                 };
1190
1191                 gmac {
1192                         rgmii_pins: rgmii-pins {
1193                                 rockchip,pins =
1194                                         /* mac_rxd3 */
1195                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1196                                         /* mac_rxd2 */
1197                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1198                                         /* mac_txd3 */
1199                                         <2 5  RK_FUNC_1 &pcfg_pull_none>,
1200                                         /* mac_txd2 */
1201                                         <2 4  RK_FUNC_1 &pcfg_pull_none>,
1202                                         /* mac_rxd1 */
1203                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1204                                         /* mac_rxd0 */
1205                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1206                                         /* mac_txd1 */
1207                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1208                                         /* mac_txd0 */
1209                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1210                                         /* mac_crs */
1211                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1212                                         /* mac_rxclkin */
1213                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1214                                         /* mac_mdio */
1215                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1216                                         /* mac_txen */
1217                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1218                                         /* mac_clk */
1219                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1220                                         /* mac_rxer */
1221                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1222                                         /* mac_rxdv */
1223                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1224                                         /* mac_mdc */
1225                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1226                         };
1227
1228                         rmii_pins: rmii-pins {
1229                                 rockchip,pins =
1230                                         /* mac_rxd1 */
1231                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1232                                         /* mac_rxd0 */
1233                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1234                                         /* mac_txd1 */
1235                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1236                                         /* mac_txd0 */
1237                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1238                                         /* mac_crs */
1239                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1240                                         /* mac_rxclkin */
1241                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1242                                         /* mac_mdio */
1243                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1244                                         /* mac_txen */
1245                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1246                                         /* mac_clk */
1247                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1248                                         /* mac_rxer */
1249                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1250                                         /* mac_rxdv */
1251                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1252                                         /* mac_mdc */
1253                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1254                         };
1255                 };
1256
1257                 eth_phy {
1258                         eth_phy_pwr: eth-phy-pwr {
1259                                 rockchip,pins =
1260                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
1261                         };
1262                 };
1263         };
1264 };