2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3366-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
49 #include <dt-bindings/display/mipi_dsi.h>
50 #include <dt-bindings/power/rk3366-power.h>
51 #include <dt-bindings/soc/rockchip_boot-mode.h>
54 compatible = "rockchip,rk3366";
55 interrupt-parent = <&gic>;
74 #address-cells = <0x2>;
79 compatible = "arm,cortex-a53","arm,armv8";
81 enable-method = "psci";
82 clocks = <&cru ARMCLK>;
83 operating-points-v2 = <&cpu0_opp_table>;
84 cpu-idle-states = <&cpu_sleep>;
89 compatible = "arm,cortex-a53","arm,armv8";
91 enable-method = "psci";
92 operating-points-v2 = <&cpu0_opp_table>;
93 cpu-idle-states = <&cpu_sleep>;
98 compatible = "arm,cortex-a53","arm,armv8";
100 enable-method = "psci";
101 operating-points-v2 = <&cpu0_opp_table>;
102 cpu-idle-states = <&cpu_sleep>;
107 compatible = "arm,cortex-a53","arm,armv8";
109 enable-method = "psci";
110 operating-points-v2 = <&cpu0_opp_table>;
111 cpu-idle-states = <&cpu_sleep>;
115 entry-method = "psci";
116 cpu_sleep: cpu-sleep-0 {
117 compatible = "arm,idle-state";
119 arm,psci-suspend-param = <0x0010000>;
120 entry-latency-us = <350>;
121 exit-latency-us = <600>;
122 min-residency-us = <1150>;
127 cpu0_opp_table: opp_table0 {
128 compatible = "operating-points-v2";
132 opp-hz = /bits/ 64 <408000000>;
133 opp-microvolt = <950000>;
134 clock-latency-ns = <40000>;
138 opp-hz = /bits/ 64 <600000000>;
139 opp-microvolt = <950000>;
142 opp-hz = /bits/ 64 <816000000>;
143 opp-microvolt = <1000000>;
146 opp-hz = /bits/ 64 <1008000000>;
147 opp-microvolt = <1075000>;
150 opp-hz = /bits/ 64 <1200000000>;
151 opp-microvolt = <1175000>;
154 opp-hz = /bits/ 64 <1296000000>;
155 opp-microvolt = <1250000>;
160 compatible = "arm,psci-1.0";
165 compatible = "arm,armv8-timer";
166 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
167 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
168 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
169 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
173 compatible = "arm,cortex-a53-pmu";
174 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-affinity = <&cpu0>,
185 compatible = "fixed-clock";
187 clock-frequency = <24000000>;
188 clock-output-names = "xin24m";
191 gic: interrupt-controller@ffb71000 {
192 compatible = "arm,gic-400";
193 interrupt-controller;
194 #interrupt-cells = <3>;
195 #address-cells = <0>;
197 reg = <0x0 0xffb71000 0x0 0x1000>,
198 <0x0 0xffb72000 0x0 0x1000>,
199 <0x0 0xffb74000 0x0 0x2000>,
200 <0x0 0xffb76000 0x0 0x2000>;
201 interrupts = <GIC_PPI 9
202 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
205 nandc0: nandc@ff0c0000 {
206 compatible = "rockchip,rk-nandc";
207 reg = <0x0 0xff0c0000 0x0 0x4000>;
208 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
211 clock-names = "clk_nandc", "hclk_nandc";
215 saradc: saradc@ff100000 {
216 compatible = "rockchip,saradc";
217 reg = <0x0 0xff100000 0x0 0x100>;
218 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
219 #io-channel-cells = <1>;
220 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
221 clock-names = "saradc", "apb_pclk";
226 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
227 reg = <0x0 0xff110000 0x0 0x1000>;
228 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
229 clock-names = "spiclk", "apb_pclk";
230 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
233 #address-cells = <1>;
239 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
240 reg = <0x0 0xff120000 0x0 0x1000>;
241 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
242 clock-names = "spiclk", "apb_pclk";
243 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
244 pinctrl-names = "default";
245 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
246 #address-cells = <1>;
251 scr: rkscr@ff1d0000 {
252 compatible = "rockchip-scr";
253 reg = <0x0 0xff1d0000 0x0 0x10000>;
254 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
255 #address-cells = <1>;
257 pinctrl-names = "default";
258 pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
259 clocks = <&cru PCLK_SIM>;
260 clock-names = "g_pclk_sim_card";
264 sdmmc: rksdmmc@ff400000 {
265 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
266 clock-freq-min-max = <400000 150000000>;
267 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
268 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
269 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
270 fifo-depth = <0x100>;
271 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
272 reg = <0x0 0xff400000 0x0 0x4000>;
276 sdio: rksdmmc@ff410000 {
277 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
278 clock-freq-min-max = <400000 150000000>;
279 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
280 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
281 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
282 fifo-depth = <0x100>;
283 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
284 reg = <0x0 0xff410000 0x0 0x4000>;
288 emmc: rksdmmc@ff420000 {
289 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
290 clock-freq-min-max = <400000 150000000>;
291 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
292 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
293 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
294 fifo-depth = <0x100>;
295 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
296 reg = <0x0 0xff420000 0x0 0x4000>;
301 compatible = "rockchip,rk3366-gmac";
302 reg = <0x0 0xff440000 0x0 0x10000>;
303 rockchip,grf = <&grf>;
304 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
305 interrupt-names = "macirq";
306 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
307 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
308 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
310 clock-names = "stmmaceth", "mac_clk_rx",
311 "mac_clk_tx", "clk_mac_ref",
312 "clk_mac_refout", "aclk_mac",
314 resets = <&cru SRST_MAC>;
315 reset-names = "stmmaceth";
320 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
321 reg = <0x0 0xff728000 0x0 0x1000>;
322 clocks = <&cru PCLK_I2C0>;
324 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&i2c0_xfer>;
327 #address-cells = <1>;
333 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
334 reg = <0x0 0xff140000 0x0 0x1000>;
335 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
336 #address-cells = <1>;
339 clocks = <&cru PCLK_I2C2>;
340 pinctrl-names = "default";
341 pinctrl-0 = <&i2c2_xfer>;
346 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
347 reg = <0x0 0xff150000 0x0 0x1000>;
348 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
349 #address-cells = <1>;
352 clocks = <&cru PCLK_I2C3>;
353 pinctrl-names = "default";
354 pinctrl-0 = <&i2c3_xfer>;
359 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
360 reg = <0x0 0xff160000 0x0 0x1000>;
361 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
362 #address-cells = <1>;
365 clocks = <&cru PCLK_I2C4>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&i2c4_xfer>;
372 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
373 reg = <0x0 0xff170000 0x0 0x1000>;
374 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
375 #address-cells = <1>;
378 clocks = <&cru PCLK_I2C5>;
379 pinctrl-names = "default";
380 pinctrl-0 = <&i2c5_xfer>;
384 uart0: serial@ff180000 {
385 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
386 reg = <0x0 0xff180000 0x0 0x100>;
387 clock-frequency = <24000000>;
388 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
389 clock-names = "baudclk", "apb_pclk";
390 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
398 uart3: serial@ff1b0000 {
399 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
400 reg = <0x0 0xff1b0000 0x0 0x100>;
401 clock-frequency = <24000000>;
402 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
403 clock-names = "baudclk", "apb_pclk";
404 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
407 pinctrl-names = "default";
408 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
413 compatible = "rockchip,rk336x-usb-phy";
414 rockchip,grf = <&grf>;
415 #address-cells = <1>;
431 usb_host0_echi: usb@ff480000 {
432 compatible = "generic-ehci";
433 reg = <0x0 0xff480000 0x0 0x20000>;
434 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
436 clock-names = "sclk_otgphy0", "hclk_host0";
442 usb_host0_ohci: usb@ff4a0000 {
443 compatible = "generic-ohci";
444 reg = <0x0 0xff4a0000 0x0 0x20000>;
445 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
447 clock-names = "sclk_otgphy0", "hclk_host0";
451 usb_otg: usb@ff4c0000 {
452 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
454 reg = <0x0 0xff4c0000 0x0 0x40000>;
455 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&cru HCLK_OTG>;
459 g-np-tx-fifo-size = <16>;
460 g-rx-fifo-size = <275>;
461 g-tx-fifo-size = <256 128 128 64 64 32>;
467 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
468 reg = <0x0 0xff660000 0x0 0x1000>;
469 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
470 #address-cells = <1>;
473 clocks = <&cru PCLK_I2C1>;
474 pinctrl-names = "default";
475 pinctrl-0 = <&i2c1_xfer>;
480 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
481 reg = <0x0 0xff680000 0x0 0x10>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&pwm0_pin>;
485 clocks = <&cru PCLK_RKPWM>;
491 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
492 reg = <0x0 0xff680010 0x0 0x10>;
494 pinctrl-names = "default";
495 pinctrl-0 = <&pwm1_pin>;
496 clocks = <&cru PCLK_RKPWM>;
502 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
503 reg = <0x0 0xff680020 0x0 0x10>;
505 clocks = <&cru PCLK_RKPWM>;
511 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
512 reg = <0x0 0xff680030 0x0 0x10>;
514 pinctrl-names = "default";
515 pinctrl-0 = <&pwm3_t2_pin>;
516 clocks = <&cru PCLK_RKPWM>;
521 uart2: serial@ff690000 {
522 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
523 reg = <0x0 0xff690000 0x0 0x100>;
524 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
526 clock-names = "baudclk", "apb_pclk";
529 pinctrl-names = "default";
530 pinctrl-0 = <&uart2_t1_xfer>;
534 pmu: power-management@ff730000 {
535 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
536 reg = <0x0 0xff730000 0x0 0x1000>;
538 power: power-controller {
540 compatible = "rockchip,rk3366-power-controller";
541 #power-domain-cells = <1>;
542 #address-cells = <1>;
546 * Note: Although SCLK_* are the working clocks
547 * of device without including on the NOC, needed for
550 * The clocks on the which NOC:
551 * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
552 * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
553 * ACLK_ISP is on ACLK_ISP_NIU.
554 * ACLK_HDCP is on ACLK_HDCP_NIU.
555 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
557 * Which clock are device clocks:
559 * *_IEP IEP:Image Enhancement Processor
560 * *_ISP ISP:Image Signal Processing
561 * *_VOP* VOP:Visual Output Processor
568 reg = <RK3366_PD_VIO>;
569 clocks = <&cru ACLK_IEP>,
573 <&cru ACLK_VOP_FULL>,
574 <&cru ACLK_VOP_LITE>,
576 <&cru DCLK_VOP_FULL>,
577 <&cru DCLK_VOP_LITE>,
581 <&cru HCLK_VOP_FULL>,
582 <&cru HCLK_VOP_LITE>,
583 <&cru HCLK_VIO_HDCPMMU>,
584 <&cru PCLK_HDMI_CTRL>,
586 <&cru PCLK_MIPI_DSI0>,
587 <&cru SCLK_VOP_FULL_PWM>,
591 <&cru SCLK_HDMI_CEC>,
592 <&cru SCLK_HDMI_HDCP>;
596 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
597 * (video endecoder & decoder) clocks that on the
598 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
601 reg = <RK3366_PD_VPU>;
602 clocks = <&cru ACLK_VIDEO>,
607 * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
608 * (video decoder) clocks that on the
609 * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
612 reg = <RK3366_PD_RKVDEC>;
613 clocks = <&cru ACLK_RKVDEC>,
618 reg = <RK3366_PD_VIDEO>;
619 clocks = <&cru ACLK_VIDEO>,
623 <&cru SCLK_HEVC_CABAC>,
624 <&cru SCLK_HEVC_CORE>;
628 * Note: ACLK_GPU is the GPU clock,
629 * and on the ACLK_GPU_NIU (NOC).
632 reg = <RK3366_PD_GPU>;
633 clocks = <&cru ACLK_GPU>;
638 pmugrf: syscon@ff738000 {
639 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
640 reg = <0x0 0xff738000 0x0 0x1000>;
643 compatible = "syscon-reboot-mode";
645 mode-normal = <BOOT_NORMAL>;
646 mode-recovery = <BOOT_RECOVERY>;
647 mode-fastboot = <BOOT_FASTBOOT>;
648 mode-loader = <BOOT_LOADER>;
653 compatible = "arm,amba-bus";
654 #address-cells = <2>;
658 dmac_peri: dma-controller@ff250000 {
659 compatible = "arm,pl330", "arm,primecell";
660 reg = <0x0 0xff250000 0x0 0x4000>;
661 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&cru ACLK_DMAC_PERI>;
665 clock-names = "apb_pclk";
668 dmac_bus: dma-controller@ff600000 {
669 compatible = "arm,pl330", "arm,primecell";
670 reg = <0x0 0xff600000 0x0 0x4000>;
671 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&cru ACLK_DMAC_BUS>;
675 clock-names = "apb_pclk";
679 cru: clock-controller@ff760000 {
680 compatible = "rockchip,rk3366-cru";
681 reg = <0x0 0xff760000 0x0 0x1000>;
682 rockchip,grf = <&grf>;
687 <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
688 <&cru PLL_CPLL>, <&cru PLL_GPLL>,
689 <&cru PLL_NPLL>, <&cru PLL_MPLL>,
690 <&cru PLL_WPLL>, <&cru PLL_BPLL>,
691 <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
692 <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
693 <&cru ACLK_BUS>, <&cru ACLK_PERI0>,
695 assigned-clock-rates =
698 <750000000>, <576000000>,
699 <594000000>, <594000000>,
700 <960000000>, <520000000>,
701 <375000000>, <288000000>,
702 <100000000>, <100000000>,
703 <288000000>, <288000000>,
705 assigned-clock-parents =
706 <&cru SCLK_32K_INTR>,
707 <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;
710 grf: syscon@ff770000 {
711 compatible = "rockchip,rk3366-grf", "syscon";
712 reg = <0x0 0xff770000 0x0 0x1000>;
715 wdt: watchdog@ff800000 {
716 compatible = "snps,dw-wdt";
717 reg = <0x0 0xff800000 0x0 0x100>;
718 clocks = <&cru PCLK_WDT>;
719 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
723 spdif: spdif@ff880000 {
724 compatible = "rockchip,rk3366-spdif";
725 reg = <0x0 0xff880000 0x0 0x1000>;
726 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
727 dmas = <&dmac_bus 3>;
729 clock-names = "mclk", "hclk";
730 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
731 pinctrl-names = "default";
732 pinctrl-0 = <&spdif_bus>;
736 i2s_2ch: i2s-2ch@ff890000 {
737 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
738 reg = <0x0 0xff890000 0x0 0x1000>;
739 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
740 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
741 dma-names = "tx", "rx";
742 clock-names = "i2s_clk", "i2s_hclk";
743 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
747 i2s_8ch: i2s-8ch@ff898000 {
748 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
749 reg = <0x0 0xff898000 0x0 0x1000>;
750 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
751 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
752 dma-names = "tx", "rx";
753 clock-names = "i2s_clk", "i2s_hclk";
754 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
755 pinctrl-names = "default";
756 pinctrl-0 = <&i2s_8ch_bus>;
761 compatible = "rockchip,rk-fb";
762 rockchip,disp-mode = <DUAL>;
767 compatible = "rockchip,screen";
771 vop_lite: vop@ff8f0000 {
772 compatible = "rockchip,rk3366-lcdc-lite";
773 rockchip,grf = <&grf>;
774 rockchip,pwr18 = <0>;
775 rockchip,iommu-enabled = <1>;
776 reg = <0x0 0xff8f0000 0x0 0x1000>;
777 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
779 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
780 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
781 reset-names = "axi", "ahb", "dclk";
787 compatible = "rockchip,vopl_mmu";
788 reg = <0x0 0xff8f0f00 0x0 0x100>;
789 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
790 interrupt-names = "vopl_mmu";
795 compatible = "rockchip,iep";
797 reg = <0x0 0xff900000 0x0 0x800>;
798 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
800 clock-names = "aclk_iep", "hclk_iep";
806 compatible = "rockchip,rga2";
808 reg = <0x0 0xff920000 0x0 0x1000>;
809 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
811 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
815 vop_big: vop@ff930000 {
816 compatible = "rockchip,rk3366-lcdc-big";
817 rockchip,grf = <&grf>;
818 rockchip,prop = <PRMRY>;
819 rockchip,pwr18 = <0>;
820 rockchip,iommu-enabled = <1>;
821 reg = <0x0 0xff930000 0x0 0x23f0>;
822 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
824 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
825 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
826 reset-names = "axi", "ahb", "dclk";
832 compatible = "rockchip,vopb_mmu";
833 reg = <0x0 0xff932400 0x0 0x100>;
834 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "vop_mmu";
841 compatible = "rockchip,iep_mmu";
842 reg = <0x0 0xff900800 0x0 0x100>;
843 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
844 interrupt-names = "iep_mmu";
850 compatible = "rockchip,vpu_mmu";
851 reg = <0x0 0xff9a0800 0x0 0x100>;
852 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
853 interrupt-names = "vpu_mmu";
859 compatible = "rockchip,vdec_mmu";
860 reg = <0x0 0xff9b0480 0x0 0x40>,
861 <0x0 0xff9b04c0 0x0 0x40>;
862 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
863 interrupt-names = "vdec_mmu";
867 dsihost0: mipi@ff960000 {
868 compatible = "rockchip,rk3366-dsi";
870 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
871 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
872 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
874 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
878 lvds: lvds@ff968000 {
879 compatible = "rockchip,rk3366-lvds";
880 rockchip,grf = <&grf>;
881 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
882 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
883 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
884 clock-names = "pclk_lvds", "pclk_lvds_ctl";
888 hdmi: hdmi@ff980000 {
889 compatible = "rockchip,rk3366-hdmi";
890 reg = <0x0 0xff980000 0x0 0x20000>;
891 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
892 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&cru PCLK_HDMI_CTRL>,
894 <&cru SCLK_HDMI_HDCP>,
895 <&cru SCLK_HDMI_CEC>,
897 clock-names = "pclk_hdmi",
901 resets = <&cru SRST_HDMI>;
902 reset-names = "hdmi";
903 pinctrl-names = "default", "gpio";
904 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
905 pinctrl-1 = <&i2c5_gpio>;
909 vpu: vpu_service@ff9a0000 {
910 compatible = "rockchip,vpu_service";
911 rockchip,grf = <&grf>;
913 reg = <0x0 0xff9a0000 0x0 0x800>;
914 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
915 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
916 interrupt-names = "irq_dec", "irq_enc";
917 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
918 clock-names = "aclk_vcodec", "hclk_vcodec";
919 resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
920 reset-names = "video_h", "video_a";
921 name = "vpu_service";
926 rkvdec: rkvdec@ff9b0000 {
927 compatible = "rockchip,rkvdec";
928 rockchip,grf = <&grf>;
930 reg = <0x0 0xff9b0000 0x0 0x400>;
931 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
932 interrupt-names = "irq_dec";
933 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
934 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
935 resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
936 reset-names = "video_h", "video_a";
943 compatible = "rockchip,rk3366-pinctrl";
944 rockchip,grf = <&grf>;
945 rockchip,pmu = <&pmugrf>;
946 #address-cells = <0x2>;
950 gpio0: gpio0@ff750000 {
951 compatible = "rockchip,gpio-bank";
952 reg = <0x0 0xff750000 0x0 0x100>;
953 clocks = <&cru PCLK_GPIO0>;
954 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
959 interrupt-controller;
960 #interrupt-cells = <0x2>;
963 gpio1: gpio1@ff780000 {
964 compatible = "rockchip,gpio-bank";
965 reg = <0x0 0xff758000 0x0 0x100>;
966 clocks = <&cru PCLK_GPIO1>;
967 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
972 interrupt-controller;
973 #interrupt-cells = <0x2>;
976 gpio2: gpio2@ff790000 {
977 compatible = "rockchip,gpio-bank";
978 reg = <0x0 0xff790000 0x0 0x100>;
979 clocks = <&cru PCLK_GPIO2>;
980 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
985 interrupt-controller;
986 #interrupt-cells = <0x2>;
989 gpio3: gpio3@ff7a0000 {
990 compatible = "rockchip,gpio-bank";
991 reg = <0x0 0xff7a0000 0x0 0x100>;
992 clocks = <&cru PCLK_GPIO3>;
993 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
998 interrupt-controller;
999 #interrupt-cells = <0x2>;
1002 gpio4: gpio4@ff7b0000 {
1003 compatible = "rockchip,gpio-bank";
1004 reg = <0x0 0xff7b0000 0x0 0x100>;
1005 clocks = <&cru PCLK_GPIO4>;
1006 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1009 #gpio-cells = <0x2>;
1011 interrupt-controller;
1012 #interrupt-cells = <0x2>;
1015 gpio5: gpio5@ff7c0000 {
1016 compatible = "rockchip,gpio-bank";
1017 reg = <0x0 0xff7c0000 0x0 0x100>;
1018 clocks = <&cru PCLK_GPIO5>;
1019 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1022 #gpio-cells = <0x2>;
1024 interrupt-controller;
1025 #interrupt-cells = <0x2>;
1028 pcfg_pull_up: pcfg-pull-up {
1032 pcfg_pull_down: pcfg-pull-down {
1036 pcfg_pull_none: pcfg-pull-none {
1040 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1042 drive-strength = <12>;
1046 emmc_clk: emmc-clk {
1048 <3 4 RK_FUNC_2 &pcfg_pull_none>;
1051 emmc_cmd: emmc-cmd {
1053 <2 26 RK_FUNC_2 &pcfg_pull_up>;
1056 emmc_pwr: emmc-pwr {
1058 <2 27 RK_FUNC_2 &pcfg_pull_up>;
1061 emmc_bus1: emmc-bus1 {
1063 <2 18 RK_FUNC_2 &pcfg_pull_up>;
1066 emmc_bus4: emmc-bus4 {
1068 <2 18 RK_FUNC_2 &pcfg_pull_up>,
1069 <2 19 RK_FUNC_2 &pcfg_pull_up>,
1070 <2 20 RK_FUNC_2 &pcfg_pull_up>,
1071 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1074 emmc_bus8: emmc-bus8 {
1076 <2 18 RK_FUNC_2 &pcfg_pull_up>,
1077 <2 19 RK_FUNC_2 &pcfg_pull_up>,
1078 <2 20 RK_FUNC_2 &pcfg_pull_up>,
1079 <2 21 RK_FUNC_2 &pcfg_pull_up>,
1080 <2 22 RK_FUNC_2 &pcfg_pull_up>,
1081 <2 23 RK_FUNC_2 &pcfg_pull_up>,
1082 <2 24 RK_FUNC_2 &pcfg_pull_up>,
1083 <2 25 RK_FUNC_2 &pcfg_pull_up>;
1088 sdmmc_cd: sdmmc-cd {
1089 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
1092 sdmmc_bus1: sdmmc-bus1 {
1093 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
1096 sdmmc_bus4: sdmmc-bus4 {
1097 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
1098 <5 1 RK_FUNC_1 &pcfg_pull_up>,
1099 <5 2 RK_FUNC_1 &pcfg_pull_up>,
1100 <5 3 RK_FUNC_1 &pcfg_pull_up>;
1103 sdmmc_clk: sdmmc-clk {
1104 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
1107 sdmmc_cmd: sdmmc-cmd {
1108 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
1113 sdio_bus1: sdio-bus1 {
1114 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
1117 sdio_bus4: sdio-bus4 {
1118 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
1119 <3 13 RK_FUNC_1 &pcfg_pull_up>,
1120 <3 14 RK_FUNC_1 &pcfg_pull_up>,
1121 <3 15 RK_FUNC_1 &pcfg_pull_up>;
1124 sdio_cmd: sdio-cmd {
1125 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
1128 sdio_clk: sdio-clk {
1129 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
1133 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
1137 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
1140 sdio_int: sdio-int {
1141 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
1144 sdio_pwr: sdio-pwr {
1145 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
1150 hdmii2c_xfer: hdmii2c-xfer {
1152 <5 13 RK_FUNC_2 &pcfg_pull_none>,
1153 <5 14 RK_FUNC_2 &pcfg_pull_none>;
1158 hdmi_cec: hdmi-cec {
1160 <5 12 RK_FUNC_1 &pcfg_pull_none>;
1165 i2c0_xfer: i2c0-xfer {
1167 <0 3 RK_FUNC_1 &pcfg_pull_none>,
1168 <0 4 RK_FUNC_1 &pcfg_pull_none>;
1173 i2c1_xfer: i2c1-xfer {
1175 <4 25 RK_FUNC_1 &pcfg_pull_none>,
1176 <4 26 RK_FUNC_1 &pcfg_pull_none>;
1181 i2c2_xfer: i2c2-xfer {
1183 <5 15 RK_FUNC_2 &pcfg_pull_none>,
1184 <5 16 RK_FUNC_2 &pcfg_pull_none>;
1187 i2c2_gpio: i2c2-gpio {
1189 <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1190 <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1195 i2c3_xfer: i2c3-xfer {
1197 <2 16 RK_FUNC_2 &pcfg_pull_none>,
1198 <2 17 RK_FUNC_2 &pcfg_pull_none>;
1203 i2c4_xfer: i2c4-xfer {
1205 <5 8 RK_FUNC_1 &pcfg_pull_none>,
1206 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1209 i2c4_gpio: i2c4-gpio {
1211 <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1212 <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1217 i2c5_xfer: i2c5-xfer {
1219 <5 13 RK_FUNC_1 &pcfg_pull_none>,
1220 <5 14 RK_FUNC_1 &pcfg_pull_none>;
1222 i2c5_gpio: i2c5-gpio {
1224 <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1225 <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1230 i2s_8ch_bus: i2s-8ch-bus {
1232 <4 16 RK_FUNC_1 &pcfg_pull_none>,
1233 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1234 <4 18 RK_FUNC_1 &pcfg_pull_none>,
1235 <4 19 RK_FUNC_1 &pcfg_pull_none>,
1236 <4 20 RK_FUNC_1 &pcfg_pull_none>,
1237 <4 21 RK_FUNC_1 &pcfg_pull_none>,
1238 <4 22 RK_FUNC_1 &pcfg_pull_none>,
1239 <4 23 RK_FUNC_1 &pcfg_pull_none>,
1240 <4 24 RK_FUNC_1 &pcfg_pull_none>;
1245 spdif_bus: spdif-bus {
1247 <5 19 RK_FUNC_1 &pcfg_pull_none>;
1252 spi0_clk: spi0-clk {
1254 <2 29 RK_FUNC_2 &pcfg_pull_up>;
1256 spi0_cs0: spi0-cs0 {
1258 <2 24 RK_FUNC_3 &pcfg_pull_up>;
1260 spi0_cs1: spi0-cs1 {
1262 <2 25 RK_FUNC_3 &pcfg_pull_up>;
1266 <2 23 RK_FUNC_3 &pcfg_pull_up>;
1270 <2 22 RK_FUNC_3 &pcfg_pull_up>;
1275 spi1_clk: spi1-clk {
1277 <2 4 RK_FUNC_3 &pcfg_pull_up>;
1279 spi1_cs0: spi1-cs0 {
1281 <2 5 RK_FUNC_3 &pcfg_pull_up>;
1285 <2 6 RK_FUNC_3 &pcfg_pull_up>;
1289 <2 7 RK_FUNC_3 &pcfg_pull_up>;
1296 <5 8 RK_FUNC_2 &pcfg_pull_none>;
1301 <5 9 RK_FUNC_2 &pcfg_pull_up>;
1306 <5 10 RK_FUNC_1 &pcfg_pull_none>;
1309 scr_detect: scr-detect {
1311 <5 11 RK_FUNC_1 &pcfg_pull_none>;
1316 uart0_xfer: uart0-xfer {
1318 <3 8 RK_FUNC_1 &pcfg_pull_up>,
1319 <3 9 RK_FUNC_1 &pcfg_pull_none>;
1322 uart0_cts: uart0-cts {
1324 <3 10 RK_FUNC_1 &pcfg_pull_none>;
1327 uart0_rts: uart0-rts {
1329 <3 11 RK_FUNC_1 &pcfg_pull_none>;
1334 uart2_t0_xfer: uart2_t0-xfer {
1336 <0 22 RK_FUNC_1 &pcfg_pull_up>,
1337 <0 21 RK_FUNC_1 &pcfg_pull_none>;
1339 /* no rts / cts for uart2 */
1343 uart2_t1_xfer: uart2_t1-xfer {
1345 <5 0 RK_FUNC_2 &pcfg_pull_up>,
1346 <5 1 RK_FUNC_2 &pcfg_pull_none>;
1348 /* no rts / cts for uart2 */
1352 uart2_t2_xfer: uart2_t2-xfer {
1354 <5 14 RK_FUNC_3 &pcfg_pull_up>,
1355 <5 13 RK_FUNC_3 &pcfg_pull_none>;
1357 /* no rts / cts for uart2 */
1361 uart3_xfer: uart3-xfer {
1363 <5 15 RK_FUNC_1 &pcfg_pull_up>,
1364 <5 16 RK_FUNC_1 &pcfg_pull_none>;
1367 uart3_cts: uart3-cts {
1369 <5 17 RK_FUNC_1 &pcfg_pull_none>;
1372 uart3_rts: uart3-rts {
1374 <5 18 RK_FUNC_1 &pcfg_pull_none>;
1379 pwm0_pin: pwm0-pin {
1381 <0 8 RK_FUNC_1 &pcfg_pull_none>;
1386 pwm1_pin: pwm1-pin {
1388 <1 6 RK_FUNC_2 &pcfg_pull_none>;
1393 pwm2_t0_pin: pwm2_t0-pin {
1395 <2 15 RK_FUNC_3 &pcfg_pull_none>;
1400 pwm2_t1_pin: pwm2_t1-pin {
1402 <5 17 RK_FUNC_2 &pcfg_pull_none>;
1407 pwm3_t0_pin: pwm3_t0-pin {
1409 <1 0 RK_FUNC_2 &pcfg_pull_none>;
1414 pwm3_t1_pin: pwm3_t1-pin {
1416 <0 21 RK_FUNC_2 &pcfg_pull_none>;
1421 pwm3_t2_pin: pwm3_t2-pin {
1423 <5 18 RK_FUNC_2 &pcfg_pull_none>;
1428 lcdc_lcdc: lcdc-lcdc {
1430 <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1431 <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1432 <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1433 <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1434 <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1435 <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1436 <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1437 <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1438 <1 0 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1439 <1 1 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1440 <1 2 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1441 <1 3 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1442 <1 4 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1443 <1 5 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1444 <1 6 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1445 <1 7 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1446 <1 8 RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1447 <1 9 RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1450 lcdc_gpio: lcdc-gpio {
1452 <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1453 <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1454 <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1455 <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1456 <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1457 <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1458 <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1459 <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1460 <1 0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1461 <1 1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1462 <1 2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1463 <1 3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1464 <1 4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1465 <1 5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1466 <1 6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1467 <1 7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1468 <1 8 RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1469 <1 9 RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1474 rgmii_pins: rgmii-pins {
1477 <2 7 RK_FUNC_1 &pcfg_pull_none>,
1479 <2 6 RK_FUNC_1 &pcfg_pull_none>,
1481 <2 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1483 <2 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1485 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1487 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1489 <2 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
1491 <2 0 RK_FUNC_1 &pcfg_pull_none>,
1493 <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1495 /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1497 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1499 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1501 <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1503 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1505 /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1507 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1509 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1512 rmii_pins: rmii-pins {
1515 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1517 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1519 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1521 <2 0 RK_FUNC_1 &pcfg_pull_none>,
1523 /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1525 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1527 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1529 <2 12 RK_FUNC_1 &pcfg_pull_none>,
1531 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1533 /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1535 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1537 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1542 eth_phy_pwr: eth-phy-pwr {
1544 <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1550 compatible = "arm,malit764",
1555 reg = <0x0 0xffa30000 0 0x10000>;
1557 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1558 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1559 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1560 interrupt-names = "GPU", "MMU", "JOB";
1562 clocks = <&cru ACLK_GPU>;
1563 clock-names = "clk_mali";
1564 operating-points-v2 = <&gpu_opp_table>;
1565 status = "disabled";
1568 gpu_opp_table: gpu_opp_table {
1569 compatible = "operating-points-v2";
1573 opp-hz = /bits/ 64 <96000000>;
1574 opp-microvolt = <1100000>;
1577 opp-hz = /bits/ 64 <192000000>;
1578 opp-microvolt = <1100000>;
1581 opp-hz = /bits/ 64 <288000000>;
1582 opp-microvolt = <1100000>;
1585 opp-hz = /bits/ 64 <375000000>;
1586 opp-microvolt = <1125000>;
1589 opp-hz = /bits/ 64 <480000000>;
1590 opp-microvolt = <1200000>;