2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3366-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
49 #include <dt-bindings/power/rk3366-power.h>
50 #include <dt-bindings/soc/rockchip_boot-mode.h>
53 compatible = "rockchip,rk3366";
54 interrupt-parent = <&gic>;
73 #address-cells = <0x2>;
78 compatible = "arm,cortex-a53","arm,armv8";
80 enable-method = "psci";
81 clocks = <&cru ARMCLK>;
82 operating-points-v2 = <&cpu0_opp_table>;
87 compatible = "arm,cortex-a53","arm,armv8";
89 enable-method = "psci";
90 operating-points-v2 = <&cpu0_opp_table>;
95 compatible = "arm,cortex-a53","arm,armv8";
97 enable-method = "psci";
98 operating-points-v2 = <&cpu0_opp_table>;
103 compatible = "arm,cortex-a53","arm,armv8";
105 enable-method = "psci";
106 operating-points-v2 = <&cpu0_opp_table>;
110 cpu0_opp_table: opp_table0 {
111 compatible = "operating-points-v2";
115 opp-hz = /bits/ 64 <408000000>;
116 opp-microvolt = <1200000>;
117 clock-latency-ns = <40000>;
121 opp-hz = /bits/ 64 <600000000>;
122 opp-microvolt = <1200000>;
125 opp-hz = /bits/ 64 <816000000>;
126 opp-microvolt = <1200000>;
129 opp-hz = /bits/ 64 <1008000000>;
130 opp-microvolt = <1200000>;
133 opp-hz = /bits/ 64 <1200000000>;
134 opp-microvolt = <1200000>;
139 compatible = "arm,psci-1.0";
144 compatible = "arm,armv8-timer";
145 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
146 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
147 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
148 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
152 compatible = "arm,cortex-a53-pmu";
153 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
157 interrupt-affinity = <&cpu0>,
164 compatible = "fixed-clock";
166 clock-frequency = <24000000>;
167 clock-output-names = "xin24m";
170 gic: interrupt-controller@ffb71000 {
171 compatible = "arm,gic-400";
172 interrupt-controller;
173 #interrupt-cells = <3>;
174 #address-cells = <0>;
176 reg = <0x0 0xffb71000 0x0 0x1000>,
177 <0x0 0xffb72000 0x0 0x1000>,
178 <0x0 0xffb74000 0x0 0x2000>,
179 <0x0 0xffb76000 0x0 0x2000>;
180 interrupts = <GIC_PPI 9
181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
184 nandc0: nandc@ff0c0000 {
185 compatible = "rockchip,rk-nandc";
186 reg = <0x0 0xff0c0000 0x0 0x4000>;
187 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
190 clock-names = "clk_nandc", "hclk_nandc";
194 saradc: saradc@ff100000 {
195 compatible = "rockchip,saradc";
196 reg = <0x0 0xff100000 0x0 0x100>;
197 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
198 #io-channel-cells = <1>;
199 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
200 clock-names = "saradc", "apb_pclk";
205 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
206 reg = <0x0 0xff110000 0x0 0x1000>;
207 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
208 clock-names = "spiclk", "apb_pclk";
209 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
212 #address-cells = <1>;
218 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
219 reg = <0x0 0xff120000 0x0 0x1000>;
220 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
221 clock-names = "spiclk", "apb_pclk";
222 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
225 #address-cells = <1>;
230 scr: rkscr@ff1d0000 {
231 compatible = "rockchip-scr";
232 reg = <0x0 0xff1d0000 0x0 0x10000>;
233 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
234 #address-cells = <1>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
238 clocks = <&cru PCLK_SIM>;
239 clock-names = "g_pclk_sim_card";
243 sdmmc: rksdmmc@ff400000 {
244 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
245 clock-freq-min-max = <400000 150000000>;
246 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
247 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
248 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
249 fifo-depth = <0x100>;
250 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
251 reg = <0x0 0xff400000 0x0 0x4000>;
255 sdio: rksdmmc@ff410000 {
256 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
257 clock-freq-min-max = <400000 150000000>;
258 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
259 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
260 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
261 fifo-depth = <0x100>;
262 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
263 reg = <0x0 0xff410000 0x0 0x4000>;
267 emmc: rksdmmc@ff420000 {
268 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
269 clock-freq-min-max = <400000 150000000>;
270 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
271 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
272 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
273 fifo-depth = <0x100>;
274 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
275 reg = <0x0 0xff420000 0x0 0x4000>;
280 compatible = "rockchip,rk3366-gmac";
281 reg = <0x0 0xff440000 0x0 0x10000>;
282 rockchip,grf = <&grf>;
283 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "macirq";
285 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
286 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
287 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
289 clock-names = "stmmaceth", "mac_clk_rx",
290 "mac_clk_tx", "clk_mac_ref",
291 "clk_mac_refout", "aclk_mac",
293 resets = <&cru SRST_MAC>;
294 reset-names = "stmmaceth";
299 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
300 reg = <0x0 0xff728000 0x0 0x1000>;
301 clocks = <&cru PCLK_I2C0>;
303 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&i2c0_xfer>;
306 #address-cells = <1>;
312 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
313 reg = <0x0 0xff140000 0x0 0x1000>;
314 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
315 #address-cells = <1>;
318 clocks = <&cru PCLK_I2C2>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&i2c2_xfer>;
325 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
326 reg = <0x0 0xff150000 0x0 0x1000>;
327 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
328 #address-cells = <1>;
331 clocks = <&cru PCLK_I2C3>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&i2c3_xfer>;
338 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
339 reg = <0x0 0xff160000 0x0 0x1000>;
340 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
341 #address-cells = <1>;
344 clocks = <&cru PCLK_I2C4>;
345 pinctrl-names = "default";
346 pinctrl-0 = <&i2c4_xfer>;
351 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
352 reg = <0x0 0xff170000 0x0 0x1000>;
353 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
354 #address-cells = <1>;
357 clocks = <&cru PCLK_I2C5>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&i2c5_xfer>;
363 uart0: serial@ff180000 {
364 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
365 reg = <0x0 0xff180000 0x0 0x100>;
366 clock-frequency = <24000000>;
367 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
368 clock-names = "baudclk", "apb_pclk";
369 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
377 uart3: serial@ff1b0000 {
378 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
379 reg = <0x0 0xff1b0000 0x0 0x100>;
380 clock-frequency = <24000000>;
381 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
382 clock-names = "baudclk", "apb_pclk";
383 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
392 compatible = "rockchip,rk336x-usb-phy";
393 rockchip,grf = <&grf>;
394 #address-cells = <1>;
410 usb_host0_echi: usb@ff480000 {
411 compatible = "generic-ehci";
412 reg = <0x0 0xff480000 0x0 0x20000>;
413 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
415 clock-names = "sclk_otgphy0", "hclk_host0";
421 usb_host0_ohci: usb@ff4a0000 {
422 compatible = "generic-ohci";
423 reg = <0x0 0xff4a0000 0x0 0x20000>;
424 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
426 clock-names = "sclk_otgphy0", "hclk_host0";
430 usb_otg: usb@ff4c0000 {
431 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
433 reg = <0x0 0xff4c0000 0x0 0x40000>;
434 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&cru HCLK_OTG>;
438 g-np-tx-fifo-size = <16>;
439 g-rx-fifo-size = <275>;
440 g-tx-fifo-size = <256 128 128 64 64 32>;
446 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
447 reg = <0x0 0xff660000 0x0 0x1000>;
448 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
449 #address-cells = <1>;
452 clocks = <&cru PCLK_I2C1>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&i2c1_xfer>;
459 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
460 reg = <0x0 0xff680000 0x0 0x10>;
462 pinctrl-names = "default";
463 pinctrl-0 = <&pwm0_pin>;
464 clocks = <&cru PCLK_RKPWM>;
470 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
471 reg = <0x0 0xff680010 0x0 0x10>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&pwm1_pin>;
475 clocks = <&cru PCLK_RKPWM>;
481 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
482 reg = <0x0 0xff680020 0x0 0x10>;
484 clocks = <&cru PCLK_RKPWM>;
490 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
491 reg = <0x0 0xff680030 0x0 0x10>;
493 pinctrl-names = "default";
494 pinctrl-0 = <&pwm3_t2_pin>;
495 clocks = <&cru PCLK_RKPWM>;
500 uart2: serial@ff690000 {
501 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
502 reg = <0x0 0xff690000 0x0 0x100>;
503 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
505 clock-names = "baudclk", "apb_pclk";
508 pinctrl-names = "default";
509 pinctrl-0 = <&uart2_t1_xfer>;
513 pmu: power-management@ff730000 {
514 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
515 reg = <0x0 0xff730000 0x0 0x1000>;
517 power: power-controller {
519 compatible = "rockchip,rk3366-power-controller";
520 #power-domain-cells = <1>;
521 #address-cells = <1>;
525 * Note: Although SCLK_* are the working clocks
526 * of device without including on the NOC, needed for
529 * The clocks on the which NOC:
530 * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
531 * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
532 * ACLK_ISP is on ACLK_ISP_NIU.
533 * ACLK_HDCP is on ACLK_HDCP_NIU.
534 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
536 * Which clock are device clocks:
538 * *_IEP IEP:Image Enhancement Processor
539 * *_ISP ISP:Image Signal Processing
540 * *_VOP* VOP:Visual Output Processor
547 reg = <RK3366_PD_VIO>;
548 clocks = <&cru ACLK_IEP>,
552 <&cru ACLK_VOP_FULL>,
553 <&cru ACLK_VOP_LITE>,
555 <&cru DCLK_VOP_FULL>,
556 <&cru DCLK_VOP_LITE>,
560 <&cru HCLK_VOP_FULL>,
561 <&cru HCLK_VOP_LITE>,
562 <&cru HCLK_VIO_HDCPMMU>,
563 <&cru PCLK_HDMI_CTRL>,
565 <&cru PCLK_MIPI_DSI0>,
566 <&cru SCLK_VOP_FULL_PWM>,
570 <&cru SCLK_HDMI_CEC>,
571 <&cru SCLK_HDMI_HDCP>;
575 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
576 * (video endecoder & decoder) clocks that on the
577 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
580 reg = <RK3366_PD_VPU>;
581 clocks = <&cru ACLK_VIDEO>,
586 * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
587 * (video decoder) clocks that on the
588 * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
591 reg = <RK3366_PD_RKVDEC>;
592 clocks = <&cru ACLK_RKVDEC>,
597 reg = <RK3366_PD_VIDEO>;
598 clocks = <&cru ACLK_VIDEO>,
602 <&cru SCLK_HEVC_CABAC>,
603 <&cru SCLK_HEVC_CORE>;
607 * Note: ACLK_GPU is the GPU clock,
608 * and on the ACLK_GPU_NIU (NOC).
611 reg = <RK3366_PD_GPU>;
612 clocks = <&cru ACLK_GPU>;
617 pmugrf: syscon@ff738000 {
618 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
619 reg = <0x0 0xff738000 0x0 0x1000>;
622 compatible = "syscon-reboot-mode";
624 mode-normal = <BOOT_NORMAL>;
625 mode-recovery = <BOOT_RECOVERY>;
626 mode-fastboot = <BOOT_FASTBOOT>;
627 mode-loader = <BOOT_LOADER>;
632 compatible = "arm,amba-bus";
633 #address-cells = <2>;
637 dmac_peri: dma-controller@ff250000 {
638 compatible = "arm,pl330", "arm,primecell";
639 reg = <0x0 0xff250000 0x0 0x4000>;
640 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&cru ACLK_DMAC_PERI>;
644 clock-names = "apb_pclk";
647 dmac_bus: dma-controller@ff600000 {
648 compatible = "arm,pl330", "arm,primecell";
649 reg = <0x0 0xff600000 0x0 0x4000>;
650 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&cru ACLK_DMAC_BUS>;
654 clock-names = "apb_pclk";
658 cru: clock-controller@ff760000 {
659 compatible = "rockchip,rk3366-cru";
660 reg = <0x0 0xff760000 0x0 0x1000>;
661 rockchip,grf = <&grf>;
665 <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
666 <&cru PLL_CPLL>, <&cru PLL_GPLL>,
667 <&cru PLL_NPLL>, <&cru PLL_MPLL>,
668 <&cru PLL_WPLL>, <&cru PLL_BPLL>,
669 <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
670 <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
671 assigned-clock-rates =
673 <750000000>, <576000000>,
674 <594000000>, <594000000>,
675 <960000000>, <520000000>,
676 <375000000>, <288000000>,
677 <100000000>, <100000000>;
678 assigned-clock-parents =
679 <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;
682 grf: syscon@ff770000 {
683 compatible = "rockchip,rk3366-grf", "syscon";
684 reg = <0x0 0xff770000 0x0 0x1000>;
687 wdt: watchdog@ff800000 {
688 compatible = "snps,dw-wdt";
689 reg = <0x0 0xff800000 0x0 0x100>;
690 clocks = <&cru PCLK_WDT>;
691 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
695 spdif: spdif@ff880000 {
696 compatible = "rockchip,rk3366-spdif";
697 reg = <0x0 0xff880000 0x0 0x1000>;
698 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
699 dmas = <&dmac_bus 3>;
701 clock-names = "hclk", "mclk";
702 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
703 pinctrl-names = "default";
704 pinctrl-0 = <&spdif_bus>;
708 i2s_2ch: i2s-2ch@ff890000 {
709 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
710 reg = <0x0 0xff890000 0x0 0x1000>;
711 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
712 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
713 dma-names = "tx", "rx";
714 clock-names = "i2s_hclk", "i2s_clk";
715 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
719 i2s_8ch: i2s-8ch@ff898000 {
720 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
721 reg = <0x0 0xff898000 0x0 0x1000>;
722 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
723 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
724 dma-names = "tx", "rx";
725 clock-names = "i2s_hclk", "i2s_clk";
726 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
727 pinctrl-names = "default";
728 pinctrl-0 = <&i2s_8ch_bus>;
733 compatible = "rockchip,rk-fb";
734 rockchip,disp-mode = <DUAL>;
739 compatible = "rockchip,screen";
743 vop_lite: vop@ff8f0000 {
744 compatible = "rockchip,rk3366-lcdc-lite";
745 rockchip,grf = <&grf>;
746 rockchip,pwr18 = <0>;
747 rockchip,iommu-enabled = <1>;
748 reg = <0x0 0xff8f0000 0x0 0x1000>;
749 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
751 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
752 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
753 reset-names = "axi", "ahb", "dclk";
759 compatible = "rockchip,vopl_mmu";
760 reg = <0x0 0xff8f0f00 0x0 0x100>;
761 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
762 interrupt-names = "vopl_mmu";
767 compatible = "rockchip,iep";
769 reg = <0x0 0xff900000 0x0 0x800>;
770 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
771 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
772 clock-names = "aclk_iep", "hclk_iep";
778 compatible = "rockchip,rga2";
780 reg = <0x0 0xff920000 0x0 0x1000>;
781 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
783 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
787 vop_big: vop@ff930000 {
788 compatible = "rockchip,rk3366-lcdc-big";
789 rockchip,grf = <&grf>;
790 rockchip,prop = <PRMRY>;
791 rockchip,pwr18 = <0>;
792 rockchip,iommu-enabled = <1>;
793 reg = <0x0 0xff930000 0x0 0x23f0>;
794 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
796 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
797 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
798 reset-names = "axi", "ahb", "dclk";
804 compatible = "rockchip,vopb_mmu";
805 reg = <0x0 0xff932400 0x0 0x100>;
806 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
807 interrupt-names = "vop_mmu";
813 compatible = "rockchip,iep_mmu";
814 reg = <0x0 0xff900800 0x0 0x100>;
815 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
816 interrupt-names = "iep_mmu";
822 compatible = "rockchip,vpu_mmu";
823 reg = <0x0 0xff9a0800 0x0 0x100>;
824 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
825 interrupt-names = "vpu_mmu";
831 compatible = "rockchip,vdec_mmu";
832 reg = <0x0 0xff9b0480 0x0 0x40>,
833 <0x0 0xff9b04c0 0x0 0x40>;
834 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "vdec_mmu";
839 dsihost0: mipi@ff960000 {
840 compatible = "rockchip,rk3368-dsi";
842 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
843 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
844 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
846 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
850 lvds: lvds@ff968000 {
851 compatible = "rockchip,rk3366-lvds";
852 rockchip,grf = <&grf>;
853 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
854 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
855 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
856 clock-names = "pclk_lvds", "pclk_lvds_ctl";
860 hdmi: hdmi@ff980000 {
861 compatible = "rockchip,rk3366-hdmi";
862 reg = <0x0 0xff980000 0x0 0x20000>;
863 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
864 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&cru PCLK_HDMI_CTRL>,
866 <&cru SCLK_HDMI_HDCP>,
867 <&cru SCLK_HDMI_CEC>,
869 clock-names = "pclk_hdmi",
873 resets = <&cru SRST_HDMI>;
874 reset-names = "hdmi";
875 pinctrl-names = "default", "gpio";
876 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
877 pinctrl-1 = <&i2c5_gpio>;
881 vpu: vpu_service@ff9a0000 {
882 compatible = "rockchip,vpu_service";
883 rockchip,grf = <&grf>;
885 reg = <0x0 0xff9a0000 0x0 0x800>;
886 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
887 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
888 interrupt-names = "irq_dec", "irq_enc";
889 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
890 clock-names = "aclk_vcodec", "hclk_vcodec";
891 resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
892 reset-names = "video_h", "video_a";
893 name = "vpu_service";
898 rkvdec: rkvdec@ff9b0000 {
899 compatible = "rockchip,rkvdec";
900 rockchip,grf = <&grf>;
902 reg = <0x0 0xff9b0000 0x0 0x400>;
903 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
904 interrupt-names = "irq_dec";
905 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
906 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
907 resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
908 reset-names = "video_h", "video_a";
915 compatible = "rockchip,rk3366-pinctrl";
916 rockchip,grf = <&grf>;
917 rockchip,pmu = <&pmugrf>;
918 #address-cells = <0x2>;
922 gpio0: gpio0@ff750000 {
923 compatible = "rockchip,gpio-bank";
924 reg = <0x0 0xff750000 0x0 0x100>;
925 clocks = <&cru PCLK_GPIO0>;
926 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
931 interrupt-controller;
932 #interrupt-cells = <0x2>;
935 gpio1: gpio1@ff780000 {
936 compatible = "rockchip,gpio-bank";
937 reg = <0x0 0xff758000 0x0 0x100>;
938 clocks = <&cru PCLK_GPIO1>;
939 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
944 interrupt-controller;
945 #interrupt-cells = <0x2>;
948 gpio2: gpio2@ff790000 {
949 compatible = "rockchip,gpio-bank";
950 reg = <0x0 0xff790000 0x0 0x100>;
951 clocks = <&cru PCLK_GPIO2>;
952 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
957 interrupt-controller;
958 #interrupt-cells = <0x2>;
961 gpio3: gpio3@ff7a0000 {
962 compatible = "rockchip,gpio-bank";
963 reg = <0x0 0xff7a0000 0x0 0x100>;
964 clocks = <&cru PCLK_GPIO3>;
965 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
970 interrupt-controller;
971 #interrupt-cells = <0x2>;
974 gpio4: gpio4@ff7b0000 {
975 compatible = "rockchip,gpio-bank";
976 reg = <0x0 0xff7b0000 0x0 0x100>;
977 clocks = <&cru PCLK_GPIO4>;
978 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
983 interrupt-controller;
984 #interrupt-cells = <0x2>;
987 gpio5: gpio5@ff7c0000 {
988 compatible = "rockchip,gpio-bank";
989 reg = <0x0 0xff7c0000 0x0 0x100>;
990 clocks = <&cru PCLK_GPIO5>;
991 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
996 interrupt-controller;
997 #interrupt-cells = <0x2>;
1000 pcfg_pull_up: pcfg-pull-up {
1004 pcfg_pull_down: pcfg-pull-down {
1008 pcfg_pull_none: pcfg-pull-none {
1012 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1014 drive-strength = <12>;
1018 emmc_clk: emmc-clk {
1020 <3 4 RK_FUNC_2 &pcfg_pull_none>;
1023 emmc_cmd: emmc-cmd {
1025 <2 26 RK_FUNC_2 &pcfg_pull_up>;
1028 emmc_pwr: emmc-pwr {
1030 <2 27 RK_FUNC_2 &pcfg_pull_up>;
1033 emmc_bus1: emmc-bus1 {
1035 <2 18 RK_FUNC_2 &pcfg_pull_up>;
1038 emmc_bus4: emmc-bus4 {
1040 <2 18 RK_FUNC_2 &pcfg_pull_up>,
1041 <2 19 RK_FUNC_2 &pcfg_pull_up>,
1042 <2 20 RK_FUNC_2 &pcfg_pull_up>,
1043 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1046 emmc_bus8: emmc-bus8 {
1048 <2 18 RK_FUNC_2 &pcfg_pull_up>,
1049 <2 19 RK_FUNC_2 &pcfg_pull_up>,
1050 <2 20 RK_FUNC_2 &pcfg_pull_up>,
1051 <2 21 RK_FUNC_2 &pcfg_pull_up>,
1052 <2 22 RK_FUNC_2 &pcfg_pull_up>,
1053 <2 23 RK_FUNC_2 &pcfg_pull_up>,
1054 <2 24 RK_FUNC_2 &pcfg_pull_up>,
1055 <2 25 RK_FUNC_2 &pcfg_pull_up>;
1060 sdmmc_cd: sdmmc-cd {
1061 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
1064 sdmmc_bus1: sdmmc-bus1 {
1065 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
1068 sdmmc_bus4: sdmmc-bus4 {
1069 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
1070 <5 1 RK_FUNC_1 &pcfg_pull_up>,
1071 <5 2 RK_FUNC_1 &pcfg_pull_up>,
1072 <5 3 RK_FUNC_1 &pcfg_pull_up>;
1075 sdmmc_clk: sdmmc-clk {
1076 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
1079 sdmmc_cmd: sdmmc-cmd {
1080 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
1085 sdio_bus1: sdio-bus1 {
1086 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
1089 sdio_bus4: sdio-bus4 {
1090 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
1091 <3 13 RK_FUNC_1 &pcfg_pull_up>,
1092 <3 14 RK_FUNC_1 &pcfg_pull_up>,
1093 <3 15 RK_FUNC_1 &pcfg_pull_up>;
1096 sdio_cmd: sdio-cmd {
1097 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
1100 sdio_clk: sdio-clk {
1101 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
1105 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
1109 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
1112 sdio_int: sdio-int {
1113 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
1116 sdio_pwr: sdio-pwr {
1117 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
1122 hdmii2c_xfer: hdmii2c-xfer {
1124 <5 13 RK_FUNC_2 &pcfg_pull_none>,
1125 <5 14 RK_FUNC_2 &pcfg_pull_none>;
1130 hdmi_cec: hdmi-cec {
1132 <5 12 RK_FUNC_1 &pcfg_pull_none>;
1137 i2c0_xfer: i2c0-xfer {
1139 <0 3 RK_FUNC_1 &pcfg_pull_none>,
1140 <0 4 RK_FUNC_1 &pcfg_pull_none>;
1145 i2c1_xfer: i2c1-xfer {
1147 <4 25 RK_FUNC_1 &pcfg_pull_none>,
1148 <4 26 RK_FUNC_1 &pcfg_pull_none>;
1153 i2c2_xfer: i2c2-xfer {
1155 <5 15 RK_FUNC_2 &pcfg_pull_none>,
1156 <5 16 RK_FUNC_2 &pcfg_pull_none>;
1159 i2c2_gpio: i2c2-gpio {
1161 <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1162 <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1167 i2c3_xfer: i2c3-xfer {
1169 <2 16 RK_FUNC_2 &pcfg_pull_none>,
1170 <2 17 RK_FUNC_2 &pcfg_pull_none>;
1175 i2c4_xfer: i2c4-xfer {
1177 <5 8 RK_FUNC_1 &pcfg_pull_none>,
1178 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1181 i2c4_gpio: i2c4-gpio {
1183 <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1184 <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1189 i2c5_xfer: i2c5-xfer {
1191 <5 13 RK_FUNC_1 &pcfg_pull_none>,
1192 <5 14 RK_FUNC_1 &pcfg_pull_none>;
1194 i2c5_gpio: i2c5-gpio {
1196 <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1197 <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1202 i2s_8ch_bus: i2s-8ch-bus {
1204 <4 16 RK_FUNC_1 &pcfg_pull_none>,
1205 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1206 <4 18 RK_FUNC_1 &pcfg_pull_none>,
1207 <4 19 RK_FUNC_1 &pcfg_pull_none>,
1208 <4 20 RK_FUNC_1 &pcfg_pull_none>,
1209 <4 21 RK_FUNC_1 &pcfg_pull_none>,
1210 <4 22 RK_FUNC_1 &pcfg_pull_none>,
1211 <4 23 RK_FUNC_1 &pcfg_pull_none>,
1212 <4 24 RK_FUNC_1 &pcfg_pull_none>;
1217 spdif_bus: spdif-bus {
1219 <5 19 RK_FUNC_1 &pcfg_pull_none>;
1224 spi0_clk: spi0-clk {
1226 <2 29 RK_FUNC_2 &pcfg_pull_up>;
1228 spi0_cs0: spi0-cs0 {
1230 <2 24 RK_FUNC_3 &pcfg_pull_up>;
1232 spi0_cs1: spi0-cs1 {
1234 <2 25 RK_FUNC_3 &pcfg_pull_up>;
1238 <2 23 RK_FUNC_3 &pcfg_pull_up>;
1242 <2 22 RK_FUNC_3 &pcfg_pull_up>;
1247 spi1_clk: spi1-clk {
1249 <2 4 RK_FUNC_3 &pcfg_pull_up>;
1251 spi1_cs0: spi1-cs0 {
1253 <2 5 RK_FUNC_3 &pcfg_pull_up>;
1257 <2 6 RK_FUNC_3 &pcfg_pull_up>;
1261 <2 7 RK_FUNC_3 &pcfg_pull_up>;
1268 <5 8 RK_FUNC_2 &pcfg_pull_none>;
1273 <5 9 RK_FUNC_2 &pcfg_pull_up>;
1278 <5 10 RK_FUNC_1 &pcfg_pull_none>;
1281 scr_detect: scr-detect {
1283 <5 11 RK_FUNC_1 &pcfg_pull_none>;
1288 uart0_xfer: uart0-xfer {
1290 <3 8 RK_FUNC_1 &pcfg_pull_up>,
1291 <3 9 RK_FUNC_1 &pcfg_pull_none>;
1294 uart0_cts: uart0-cts {
1296 <3 10 RK_FUNC_1 &pcfg_pull_none>;
1299 uart0_rts: uart0-rts {
1301 <3 11 RK_FUNC_1 &pcfg_pull_none>;
1306 uart2_t0_xfer: uart2_t0-xfer {
1308 <0 22 RK_FUNC_1 &pcfg_pull_up>,
1309 <0 21 RK_FUNC_1 &pcfg_pull_none>;
1311 /* no rts / cts for uart2 */
1315 uart2_t1_xfer: uart2_t1-xfer {
1317 <5 0 RK_FUNC_2 &pcfg_pull_up>,
1318 <5 1 RK_FUNC_2 &pcfg_pull_none>;
1320 /* no rts / cts for uart2 */
1324 uart2_t2_xfer: uart2_t2-xfer {
1326 <5 14 RK_FUNC_3 &pcfg_pull_up>,
1327 <5 13 RK_FUNC_3 &pcfg_pull_none>;
1329 /* no rts / cts for uart2 */
1333 uart3_xfer: uart3-xfer {
1335 <5 15 RK_FUNC_1 &pcfg_pull_up>,
1336 <5 16 RK_FUNC_1 &pcfg_pull_none>;
1339 uart3_cts: uart3-cts {
1341 <5 17 RK_FUNC_1 &pcfg_pull_none>;
1344 uart3_rts: uart3-rts {
1346 <5 18 RK_FUNC_1 &pcfg_pull_none>;
1351 pwm0_pin: pwm0-pin {
1353 <0 8 RK_FUNC_1 &pcfg_pull_none>;
1358 pwm1_pin: pwm1-pin {
1360 <1 6 RK_FUNC_2 &pcfg_pull_none>;
1365 pwm2_t0_pin: pwm2_t0-pin {
1367 <2 15 RK_FUNC_3 &pcfg_pull_none>;
1372 pwm2_t1_pin: pwm2_t1-pin {
1374 <5 17 RK_FUNC_2 &pcfg_pull_none>;
1379 pwm3_t0_pin: pwm3_t0-pin {
1381 <1 0 RK_FUNC_2 &pcfg_pull_none>;
1386 pwm3_t1_pin: pwm3_t1-pin {
1388 <0 21 RK_FUNC_2 &pcfg_pull_none>;
1393 pwm3_t2_pin: pwm3_t2-pin {
1395 <5 18 RK_FUNC_2 &pcfg_pull_none>;
1400 lcdc_lcdc: lcdc-lcdc {
1402 <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1403 <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1404 <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1405 <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1406 <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1407 <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1408 <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1409 <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1410 <1 0 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1411 <1 1 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1412 <1 2 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1413 <1 3 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1414 <1 4 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1415 <1 5 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1416 <1 6 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1417 <1 7 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1418 <1 8 RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1419 <1 9 RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1422 lcdc_gpio: lcdc-gpio {
1424 <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1425 <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1426 <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1427 <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1428 <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1429 <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1430 <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1431 <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1432 <1 0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1433 <1 1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1434 <1 2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1435 <1 3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1436 <1 4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1437 <1 5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1438 <1 6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1439 <1 7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1440 <1 8 RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1441 <1 9 RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1446 rgmii_pins: rgmii-pins {
1449 <2 7 RK_FUNC_1 &pcfg_pull_none>,
1451 <2 6 RK_FUNC_1 &pcfg_pull_none>,
1453 <2 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1455 <2 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1457 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1459 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1461 <2 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
1463 <2 0 RK_FUNC_1 &pcfg_pull_none>,
1465 <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1467 /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1469 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1471 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1473 <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1475 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1477 /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1479 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1481 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1484 rmii_pins: rmii-pins {
1487 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1489 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1491 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1493 <2 0 RK_FUNC_1 &pcfg_pull_none>,
1495 /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1497 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1499 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1501 <2 12 RK_FUNC_1 &pcfg_pull_none>,
1503 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1505 /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1507 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1509 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1514 eth_phy_pwr: eth-phy-pwr {
1516 <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1522 compatible = "arm,malit764",
1527 reg = <0x0 0xffa30000 0 0x10000>;
1529 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1532 interrupt-names = "GPU", "MMU", "JOB";
1534 clocks = <&cru ACLK_GPU>;
1535 clock-names = "clk_mali";
1536 operating-points-v2 = <&gpu_opp_table>;
1537 status = "disabled";
1540 gpu_opp_table: gpu_opp_table {
1541 compatible = "operating-points-v2";
1545 opp-hz = /bits/ 64 <96000000>;
1546 opp-microvolt = <1150000>;
1549 opp-hz = /bits/ 64 <192000000>;
1550 opp-microvolt = <1150000>;
1553 opp-hz = /bits/ 64 <288000000>;
1554 opp-microvolt = <1150000>;
1557 opp-hz = /bits/ 64 <375000000>;
1558 opp-microvolt = <1150000>;
1561 opp-hz = /bits/ 64 <480000000>;
1562 opp-microvolt = <1150000>;