2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3328-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/soc/rockchip,boot-mode.h>
49 #include <dt-bindings/power/rk3328-power.h>
52 compatible = "rockchip,rk3328";
54 interrupt-parent = <&gic>;
74 compatible = "arm,cortex-a53", "arm,armv8";
76 enable-method = "psci";
77 // clocks = <&cru ARMCLK>;
78 operating-points-v2 = <&cpu0_opp_table>;
82 compatible = "arm,cortex-a53", "arm,armv8";
84 enable-method = "psci";
88 compatible = "arm,cortex-a53", "arm,armv8";
90 enable-method = "psci";
94 compatible = "arm,cortex-a53", "arm,armv8";
96 enable-method = "psci";
100 cpu0_opp_table: opp_table0 {
101 compatible = "operating-points-v2";
105 opp-hz = /bits/ 64 <408000000>;
106 opp-microvolt = <950000>;
107 clock-latency-ns = <40000>;
111 opp-hz = /bits/ 64 <600000000>;
112 opp-microvolt = <950000>;
113 clock-latency-ns = <40000>;
116 opp-hz = /bits/ 64 <816000000>;
117 opp-microvolt = <1000000>;
118 clock-latency-ns = <40000>;
121 opp-hz = /bits/ 64 <1008000000>;
122 opp-microvolt = <1100000>;
123 clock-latency-ns = <40000>;
126 opp-hz = /bits/ 64 <1200000000>;
127 opp-microvolt = <1225000>;
128 clock-latency-ns = <40000>;
131 opp-hz = /bits/ 64 <1296000000>;
132 opp-microvolt = <1300000>;
133 clock-latency-ns = <40000>;
138 compatible = "arm,cortex-a53-pmu";
139 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
143 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
147 compatible = "arm,psci-1.0";
152 compatible = "arm,armv8-timer";
153 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
154 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
155 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
156 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
160 compatible = "fixed-clock";
162 clock-frequency = <24000000>;
163 clock-output-names = "xin24m";
167 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
168 reg = <0x0 0xff000000 0x0 0x1000>;
169 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
171 clock-names = "i2s_clk", "i2s_hclk";
172 dmas = <&dmac 11>, <&dmac 12>;
174 dma-names = "tx", "rx";
179 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
180 reg = <0x0 0xff010000 0x0 0x1000>;
181 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
183 clock-names = "i2s_clk", "i2s_hclk";
184 dmas = <&dmac 14>, <&dmac 15>;
186 dma-names = "tx", "rx";
191 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
192 reg = <0x0 0xff020000 0x0 0x1000>;
193 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
195 clock-names = "i2s_clk", "i2s_hclk";
196 dmas = <&dmac 0>, <&dmac 1>;
198 dma-names = "tx", "rx";
199 pinctrl-names = "default", "sleep";
200 pinctrl-0 = <&i2s2m0_mclk
206 pinctrl-1 = <&i2s2m0_sleep>;
210 spdif: spdif@ff030000 {
211 compatible = "rockchip,rk3328-spdif";
212 reg = <0x0 0xff030000 0x0 0x1000>;
213 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
215 clock-names = "mclk", "hclk";
219 pinctrl-names = "default";
220 pinctrl-0 = <&spdifm2_tx>;
224 grf: syscon@ff100000 {
225 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
226 reg = <0x0 0xff100000 0x0 0x1000>;
227 #address-cells = <1>;
230 io_domains: io-domains {
231 compatible = "rockchip,rk3328-io-voltage-domain";
235 power: power-controller {
236 compatible = "rockchip,rk3328-power-controller";
237 #power-domain-cells = <1>;
238 #address-cells = <1>;
242 pd_hevc@RK3328_PD_HEVC {
243 reg = <RK3328_PD_HEVC>;
245 pd_video@RK3328_PD_VIDEO {
246 reg = <RK3328_PD_VIDEO>;
248 pd_vpu@RK3328_PD_VPU {
249 reg = <RK3328_PD_VPU>;
254 compatible = "syscon-reboot-mode";
256 mode-bootloader = <BOOT_BL_DOWNLOAD>;
257 mode-charge = <BOOT_CHARGING>;
258 mode-fastboot = <BOOT_FASTBOOT>;
259 mode-loader = <BOOT_BL_DOWNLOAD>;
260 mode-normal = <BOOT_NORMAL>;
261 mode-recovery = <BOOT_RECOVERY>;
262 mode-ums = <BOOT_UMS>;
266 uart0: serial@ff110000 {
267 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
268 reg = <0x0 0xff110000 0x0 0x100>;
269 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
271 clock-names = "baudclk", "apb_pclk";
274 dmas = <&dmac 2>, <&dmac 3>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
281 uart1: serial@ff120000 {
282 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
283 reg = <0x0 0xff120000 0x0 0x100>;
284 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
286 clock-names = "sclk_uart", "pclk_uart";
289 dmas = <&dmac 4>, <&dmac 5>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
296 uart2: serial@ff130000 {
297 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
298 reg = <0x0 0xff130000 0x0 0x100>;
299 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
301 clock-names = "baudclk", "apb_pclk";
304 dmas = <&dmac 6>, <&dmac 7>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&uart2m1_xfer>;
311 pmu: power-management@ff140000 {
312 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
313 reg = <0x0 0xff140000 0x0 0x1000>;
317 compatible = "rockchip,rk3328-i2c";
318 reg = <0x0 0xff150000 0x0 0x1000>;
319 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
320 #address-cells = <1>;
322 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
323 clock-names = "i2c", "pclk";
324 pinctrl-names = "default";
325 pinctrl-0 = <&i2c0_xfer>;
330 compatible = "rockchip,rk3328-i2c";
331 reg = <0x0 0xff160000 0x0 0x1000>;
332 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
333 #address-cells = <1>;
335 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
336 clock-names = "i2c", "pclk";
337 pinctrl-names = "default";
338 pinctrl-0 = <&i2c1_xfer>;
343 compatible = "rockchip,rk3328-i2c";
344 reg = <0x0 0xff170000 0x0 0x1000>;
345 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
346 #address-cells = <1>;
348 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
349 clock-names = "i2c", "pclk";
350 pinctrl-names = "default";
351 pinctrl-0 = <&i2c2_xfer>;
356 compatible = "rockchip,rk3328-i2c";
357 reg = <0x0 0xff180000 0x0 0x1000>;
358 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
361 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
362 clock-names = "i2c", "pclk";
363 pinctrl-names = "default";
364 pinctrl-0 = <&i2c3_xfer>;
369 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
370 reg = <0x0 0xff190000 0x0 0x1000>;
371 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
372 #address-cells = <1>;
374 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
375 clock-names = "spiclk", "apb_pclk";
376 dmas = <&dmac 8>, <&dmac 9>;
378 dma-names = "tx", "rx";
379 pinctrl-names = "default";
380 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
384 wdt: watchdog@ff1a0000 {
385 compatible = "snps,dw-wdt";
386 reg = <0x0 0xff1a0000 0x0 0x100>;
387 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
392 compatible = "simple-bus";
393 #address-cells = <2>;
397 dmac: dmac@ff1f0000 {
398 compatible = "arm,pl330", "arm,primecell";
399 reg = <0x0 0xff1f0000 0x0 0x4000>;
400 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&cru ACLK_DMAC>;
403 clock-names = "apb_pclk";
408 saradc: saradc@ff280000 {
409 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
410 reg = <0x0 0xff280000 0x0 0x100>;
411 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
412 #io-channel-cells = <1>;
413 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
414 clock-names = "saradc", "apb_pclk";
415 resets = <&cru SRST_SARADC_P>;
416 reset-names = "saradc-apb";
420 cru: clock-controller@ff440000 {
421 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
422 reg = <0x0 0xff440000 0x0 0x1000>;
423 rockchip,grf = <&grf>;
427 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
428 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
429 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
430 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
431 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
432 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
433 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
434 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
435 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
436 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
437 <&cru SCLK_WIFI>, <&cru ARMCLK>,
438 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
439 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
440 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
441 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
442 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
443 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
444 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
445 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
446 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
447 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
448 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
449 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
450 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
451 assigned-clock-parents =
452 <&cru HDMIPHY>, <&cru PLL_APLL>,
453 <&cru PLL_GPLL>, <&xin24m>,
454 <&xin24m>, <&xin24m>;
455 assigned-clock-rates =
458 <24000000>, <24000000>,
459 <15000000>, <15000000>,
460 <100000000>, <100000000>,
461 <100000000>, <100000000>,
462 <50000000>, <100000000>,
463 <100000000>, <100000000>,
464 <50000000>, <50000000>,
465 <50000000>, <50000000>,
466 <24000000>, <600000000>,
467 <491520000>, <1200000000>,
468 <150000000>, <75000000>,
469 <75000000>, <150000000>,
470 <75000000>, <75000000>,
471 <300000000>, <100000000>,
472 <300000000>, <200000000>,
473 <400000000>, <500000000>,
474 <200000000>, <300000000>,
475 <300000000>, <250000000>,
476 <200000000>, <100000000>,
477 <24000000>, <100000000>,
478 <150000000>, <50000000>,
482 sdmmc: rksdmmc@ff500000 {
483 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
484 reg = <0x0 0xff500000 0x0 0x4000>;
485 clock-freq-min-max = <400000 150000000>;
486 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
487 clock-names = "biu", "ciu";
488 fifo-depth = <0x100>;
489 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
493 sdio: dwmmc@ff510000 {
494 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
495 reg = <0x0 0xff510000 0x0 0x4000>;
496 clock-freq-min-max = <400000 150000000>;
497 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
498 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
499 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
500 fifo-depth = <0x100>;
501 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
505 emmc: rksdmmc@ff520000 {
506 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
507 reg = <0x0 0xff520000 0x0 0x4000>;
508 clock-freq-min-max = <400000 150000000>;
509 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
510 clock-names = "biu", "ciu";
511 fifo-depth = <0x100>;
512 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
516 usb20_otg: usb@ff580000 {
517 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
519 reg = <0x0 0xff580000 0x0 0x40000>;
520 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
522 clock-names = "otg", "otg_pmu";
524 g-np-tx-fifo-size = <16>;
525 g-rx-fifo-size = <275>;
526 g-tx-fifo-size = <256 128 128 64 64 32>;
531 sdmmc_ext: rksdmmc@ff5f0000 {
532 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
533 reg = <0x0 0xff5f0000 0x0 0x4000>;
534 clock-freq-min-max = <400000 150000000>;
535 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
536 clock-names = "biu", "ciu";
537 fifo-depth = <0x100>;
538 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
542 gic: interrupt-controller@ff811000 {
543 compatible = "arm,gic-400";
544 #interrupt-cells = <3>;
545 #address-cells = <0>;
546 interrupt-controller;
547 reg = <0x0 0xff811000 0 0x1000>,
548 <0x0 0xff812000 0 0x2000>,
549 <0x0 0xff814000 0 0x2000>,
550 <0x0 0xff816000 0 0x2000>;
551 interrupts = <GIC_PPI 9
552 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
556 compatible = "rockchip,rk3328-pinctrl";
557 rockchip,grf = <&grf>;
558 #address-cells = <2>;
562 gpio0: gpio0@ff210000 {
563 compatible = "rockchip,gpio-bank";
564 reg = <0x0 0xff210000 0x0 0x100>;
565 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&cru PCLK_GPIO0>;
571 interrupt-controller;
572 #interrupt-cells = <2>;
575 gpio1: gpio1@ff220000 {
576 compatible = "rockchip,gpio-bank";
577 reg = <0x0 0xff220000 0x0 0x100>;
578 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&cru PCLK_GPIO1>;
584 interrupt-controller;
585 #interrupt-cells = <2>;
588 gpio2: gpio2@ff230000 {
589 compatible = "rockchip,gpio-bank";
590 reg = <0x0 0xff230000 0x0 0x100>;
591 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&cru PCLK_GPIO2>;
597 interrupt-controller;
598 #interrupt-cells = <2>;
601 gpio3: gpio3@ff240000 {
602 compatible = "rockchip,gpio-bank";
603 reg = <0x0 0xff240000 0x0 0x100>;
604 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&cru PCLK_GPIO3>;
610 interrupt-controller;
611 #interrupt-cells = <2>;
614 pcfg_pull_up: pcfg-pull-up {
618 pcfg_pull_down: pcfg-pull-down {
622 pcfg_pull_none: pcfg-pull-none {
626 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
628 drive-strength = <2>;
631 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
633 drive-strength = <2>;
636 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
638 drive-strength = <4>;
641 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
643 drive-strength = <4>;
646 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
648 drive-strength = <4>;
651 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
653 drive-strength = <8>;
656 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
658 drive-strength = <8>;
661 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
663 drive-strength = <12>;
666 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
668 drive-strength = <12>;
671 pcfg_output_high: pcfg-output-high {
675 pcfg_output_low: pcfg-output-low {
679 pcfg_input_high: pcfg-input-high {
684 pcfg_input: pcfg-input {
689 i2c0_xfer: i2c0-xfer {
691 <2 24 RK_FUNC_1 &pcfg_pull_none>,
692 <2 25 RK_FUNC_1 &pcfg_pull_none>;
697 i2c1_xfer: i2c1-xfer {
699 <2 4 RK_FUNC_2 &pcfg_pull_none>,
700 <2 5 RK_FUNC_2 &pcfg_pull_none>;
705 i2c2_xfer: i2c2-xfer {
707 <2 13 RK_FUNC_1 &pcfg_pull_none>,
708 <2 14 RK_FUNC_1 &pcfg_pull_none>;
713 i2c3_xfer: i2c3-xfer {
715 <0 5 RK_FUNC_2 &pcfg_pull_none>,
716 <0 6 RK_FUNC_2 &pcfg_pull_none>;
718 i2c3_gpio: i2c3-gpio {
720 <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
721 <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
726 hdmii2c_xfer: hdmii2c-xfer {
728 <0 5 RK_FUNC_1 &pcfg_pull_none>,
729 <0 6 RK_FUNC_1 &pcfg_pull_none>;
734 uart0_xfer: uart0-xfer {
736 <1 9 RK_FUNC_1 &pcfg_pull_up>,
737 <1 8 RK_FUNC_1 &pcfg_pull_none>;
740 uart0_cts: uart0-cts {
742 <1 11 RK_FUNC_1 &pcfg_pull_none>;
745 uart0_rts: uart0-rts {
747 <1 10 RK_FUNC_1 &pcfg_pull_none>;
750 uart0_rts_gpio: uart0-rts-gpio {
752 <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
757 uart1_xfer: uart1-xfer {
759 <3 4 RK_FUNC_4 &pcfg_pull_up>,
760 <3 6 RK_FUNC_4 &pcfg_pull_none>;
763 uart1_cts: uart1-cts {
765 <3 7 RK_FUNC_4 &pcfg_pull_none>;
768 uart1_rts: uart1-rts {
770 <3 5 RK_FUNC_4 &pcfg_pull_none>;
773 uart1_rts_gpio: uart1-rts-gpio {
775 <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
780 uart2m0_xfer: uart2m0-xfer {
782 <1 0 RK_FUNC_2 &pcfg_pull_up>,
783 <1 1 RK_FUNC_2 &pcfg_pull_none>;
788 uart2m1_xfer: uart2m1-xfer {
790 <2 0 RK_FUNC_1 &pcfg_pull_up>,
791 <2 1 RK_FUNC_1 &pcfg_pull_none>;
796 spi0m0_clk: spi0m0-clk {
798 <2 8 RK_FUNC_1 &pcfg_pull_up>;
801 spi0m0_cs0: spi0m0-cs0 {
803 <2 11 RK_FUNC_1 &pcfg_pull_up>;
806 spi0m0_tx: spi0m0-tx {
808 <2 9 RK_FUNC_1 &pcfg_pull_up>;
811 spi0m0_rx: spi0m0-rx {
813 <2 10 RK_FUNC_1 &pcfg_pull_up>;
816 spi0m0_cs1: spi0m0-cs1 {
818 <2 12 RK_FUNC_1 &pcfg_pull_up>;
823 spi0m1_clk: spi0m1-clk {
825 <3 23 RK_FUNC_2 &pcfg_pull_up>;
828 spi0m1_cs0: spi0m1-cs0 {
830 <3 26 RK_FUNC_2 &pcfg_pull_up>;
833 spi0m1_tx: spi0m1-tx {
835 <3 25 RK_FUNC_2 &pcfg_pull_up>;
838 spi0m1_rx: spi0m1-rx {
840 <3 24 RK_FUNC_2 &pcfg_pull_up>;
843 spi0m1_cs1: spi0m1-cs1 {
845 <3 27 RK_FUNC_2 &pcfg_pull_up>;
850 spi0m2_clk: spi0m2-clk {
852 <3 0 RK_FUNC_4 &pcfg_pull_up>;
855 spi0m2_cs0: spi0m2-cs0 {
857 <3 8 RK_FUNC_3 &pcfg_pull_up>;
860 spi0m2_tx: spi0m2-tx {
862 <3 1 RK_FUNC_4 &pcfg_pull_up>;
865 spi0m2_rx: spi0m2-rx {
867 <3 2 RK_FUNC_4 &pcfg_pull_up>;
872 i2s1_mclk: i2s1-mclk {
874 <2 15 RK_FUNC_1 &pcfg_pull_none>;
877 i2s1_sclk: i2s1-sclk {
879 <2 18 RK_FUNC_1 &pcfg_pull_none>;
882 i2s1_lrckrx: i2s1-lrckrx {
884 <2 16 RK_FUNC_1 &pcfg_pull_none>;
887 i2s1_lrcktx: i2s1-lrcktx {
889 <2 17 RK_FUNC_1 &pcfg_pull_none>;
894 <2 19 RK_FUNC_1 &pcfg_pull_none>;
899 <2 23 RK_FUNC_1 &pcfg_pull_none>;
902 i2s1_sdio1: i2s1-sdio1 {
904 <2 20 RK_FUNC_1 &pcfg_pull_none>;
907 i2s1_sdio2: i2s1-sdio2 {
909 <2 21 RK_FUNC_1 &pcfg_pull_none>;
912 i2s1_sdio3: i2s1-sdio3 {
914 <2 22 RK_FUNC_1 &pcfg_pull_none>;
917 i2s1_sleep: i2s1-sleep {
919 <2 15 RK_FUNC_GPIO &pcfg_input_high>,
920 <2 16 RK_FUNC_GPIO &pcfg_input_high>,
921 <2 17 RK_FUNC_GPIO &pcfg_input_high>,
922 <2 18 RK_FUNC_GPIO &pcfg_input_high>,
923 <2 19 RK_FUNC_GPIO &pcfg_input_high>,
924 <2 20 RK_FUNC_GPIO &pcfg_input_high>,
925 <2 21 RK_FUNC_GPIO &pcfg_input_high>,
926 <2 22 RK_FUNC_GPIO &pcfg_input_high>,
927 <2 23 RK_FUNC_GPIO &pcfg_input_high>;
932 i2s2m0_mclk: i2s2m0-mclk {
934 <1 21 RK_FUNC_1 &pcfg_pull_none>;
937 i2s2m0_sclk: i2s2m0-sclk {
939 <1 22 RK_FUNC_1 &pcfg_pull_none>;
942 i2s2m0_lrckrx: i2s2m0-lrckrx {
944 <1 26 RK_FUNC_1 &pcfg_pull_none>;
947 i2s2m0_lrcktx: i2s2m0-lrcktx {
949 <1 23 RK_FUNC_1 &pcfg_pull_none>;
952 i2s2m0_sdi: i2s2m0-sdi {
954 <1 24 RK_FUNC_1 &pcfg_pull_none>;
957 i2s2m0_sdo: i2s2m0-sdo {
959 <1 25 RK_FUNC_1 &pcfg_pull_none>;
962 i2s2m0_sleep: i2s2m0-sleep {
964 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
965 <1 22 RK_FUNC_GPIO &pcfg_input_high>,
966 <1 26 RK_FUNC_GPIO &pcfg_input_high>,
967 <1 23 RK_FUNC_GPIO &pcfg_input_high>,
968 <1 24 RK_FUNC_GPIO &pcfg_input_high>,
969 <1 25 RK_FUNC_GPIO &pcfg_input_high>;
974 i2s2m1_mclk: i2s2m1-mclk {
976 <1 21 RK_FUNC_1 &pcfg_pull_none>;
979 i2s2m1_sclk: i2s2m1-sclk {
981 <3 0 RK_FUNC_6 &pcfg_pull_none>;
984 i2s2m1_lrckrx: i2sm1-lrckrx {
986 <3 8 RK_FUNC_6 &pcfg_pull_none>;
989 i2s2m1_lrcktx: i2s2m1-lrcktx {
991 <3 8 RK_FUNC_4 &pcfg_pull_none>;
994 i2s2m1_sdi: i2s2m1-sdi {
996 <3 2 RK_FUNC_6 &pcfg_pull_none>;
999 i2s2m1_sdo: i2s2m1-sdo {
1001 <3 1 RK_FUNC_6 &pcfg_pull_none>;
1004 i2s2m1_sleep: i2s2m1-sleep {
1006 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1007 <3 0 RK_FUNC_GPIO &pcfg_input_high>,
1008 <3 8 RK_FUNC_GPIO &pcfg_input_high>,
1009 <3 2 RK_FUNC_GPIO &pcfg_input_high>,
1010 <3 1 RK_FUNC_GPIO &pcfg_input_high>;
1015 spdifm0_tx: spdifm0-tx {
1017 <0 27 RK_FUNC_1 &pcfg_pull_none>;
1022 spdifm1_tx: spdifm1-tx {
1024 <2 17 RK_FUNC_2 &pcfg_pull_none>;
1029 spdifm2_tx: spdifm2-tx {
1031 <0 2 RK_FUNC_2 &pcfg_pull_none>;
1036 sdmmc0m0_pwren: sdmmc0m0-pwren {
1038 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1041 sdmmc0m0_gpio: sdmmc0m0-gpio {
1043 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1048 sdmmc0m1_pwren: sdmmc0m1-pwren {
1050 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1053 sdmmc0m1_gpio: sdmmc0m1-gpio {
1055 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1060 sdmmc0_clk: sdmmc0-clk {
1062 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1065 sdmmc0_cmd: sdmmc0-cmd {
1067 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1070 sdmmc0_dectn: sdmmc0-dectn {
1072 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1075 sdmmc0_wrprt: sdmmc0-wrprt {
1077 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1080 sdmmc0_bus1: sdmmc0-bus1 {
1082 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1085 sdmmc0_bus4: sdmmc0-bus4 {
1087 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1088 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1089 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1090 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1093 sdmmc0_gpio: sdmmc0-gpio {
1095 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1096 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1097 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1098 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1099 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1100 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1101 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1102 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1107 sdmmc0ext_clk: sdmmc0ext-clk {
1109 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1112 sdmmc0ext_cmd: sdmmc0ext-cmd {
1114 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1117 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1119 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1122 sdmmc0ext_dectn: sdmmc0ext-dectn {
1124 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1127 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1129 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1132 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1134 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1135 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1136 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1137 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1140 sdmmc0ext_gpio: sdmmc0ext-gpio {
1142 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1143 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1144 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1145 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1146 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1147 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1148 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1149 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1154 sdmmc1_clk: sdmmc1-clk {
1156 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1159 sdmmc1_cmd: sdmmc1-cmd {
1161 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1164 sdmmc1_pwren: sdmmc1-pwren {
1166 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1169 sdmmc1_wrprt: sdmmc1-wrprt {
1171 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1174 sdmmc1_dectn: sdmmc1-dectn {
1176 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1179 sdmmc1_bus1: sdmmc1-bus1 {
1181 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1184 sdmmc1_bus4: sdmmc1-bus4 {
1186 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1187 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1188 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1189 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1192 sdmmc1_gpio: sdmmc1-gpio {
1194 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1195 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1196 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1197 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1198 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1199 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1200 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1201 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1202 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1207 emmc_clk: emmc-clk {
1209 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1212 emmc_cmd: emmc-cmd {
1214 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1217 emmc_pwren: emmc-pwren {
1219 <3 22 RK_FUNC_2 &pcfg_pull_none>;
1222 emmc_rstnout: emmc-rstnout {
1224 <3 20 RK_FUNC_2 &pcfg_pull_none>;
1227 emmc_bus1: emmc-bus1 {
1229 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1232 emmc_bus4: emmc-bus4 {
1234 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1235 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1236 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1237 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1240 emmc_bus8: emmc-bus8 {
1242 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1243 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1244 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1245 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1246 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1247 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1248 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1249 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1254 pwm0_pin: pwm0-pin {
1256 <2 4 RK_FUNC_1 &pcfg_pull_none>;
1261 pwm1_pin: pwm1-pin {
1263 <2 5 RK_FUNC_1 &pcfg_pull_none>;
1268 pwm2_pin: pwm2-pin {
1270 <2 6 RK_FUNC_1 &pcfg_pull_none>;
1275 pwmir_pin: pwmir-pin {
1277 <2 2 RK_FUNC_1 &pcfg_pull_none>;
1282 rgmiim0_pins: rgmiim0-pins {
1285 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1287 <0 10 RK_FUNC_1 &pcfg_pull_none>,
1289 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1291 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1293 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1295 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1297 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1299 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1301 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1303 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1305 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1307 <0 20 RK_FUNC_1 &pcfg_pull_none>,
1309 <0 21 RK_FUNC_1 &pcfg_pull_none>,
1311 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1313 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1316 rmiim0_pins: rmiim0-pins {
1319 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1321 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1323 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1325 <0 13 RK_FUNC_1 &pcfg_pull_none>,
1327 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1329 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1331 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1333 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1335 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1337 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1342 rgmiim1_pins: rgmiim1-pins {
1345 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1347 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1349 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1351 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1353 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1355 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1357 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1359 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1361 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1363 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1365 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1367 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1369 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1371 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1373 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1376 <0 8 RK_FUNC_1 &pcfg_pull_none>,
1378 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1380 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1382 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1384 <0 17 RK_FUNC_1 &pcfg_pull_none>,
1386 <0 23 RK_FUNC_1 &pcfg_pull_none>,
1388 <0 22 RK_FUNC_1 &pcfg_pull_none>;
1391 rmiim1_pins: rmiim1-pins {
1394 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1396 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1398 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1400 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1402 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1404 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1406 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1408 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1410 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1412 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1415 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1417 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1419 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1421 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1423 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1425 <0 17 RK_FUNC_1 &pcfg_pull_none>;
1430 fephyled_speed100: fephyled-speed100 {
1432 <0 31 RK_FUNC_1 &pcfg_pull_none>;
1435 fephyled_speed10: fephyled-speed10 {
1437 <0 30 RK_FUNC_1 &pcfg_pull_none>;
1440 fephyled_duplex: fephyled-duplex {
1442 <0 30 RK_FUNC_2 &pcfg_pull_none>;
1445 fephyled_rxm0: fephyled-rxm0 {
1447 <0 29 RK_FUNC_1 &pcfg_pull_none>;
1450 fephyled_txm0: fephyled-txm0 {
1452 <0 29 RK_FUNC_2 &pcfg_pull_none>;
1455 fephyled_linkm0: fephyled-linkm0 {
1457 <0 28 RK_FUNC_1 &pcfg_pull_none>;
1460 fephyled_rxm1: fephyled-rxm1 {
1462 <2 25 RK_FUNC_2 &pcfg_pull_none>;
1465 fephyled_txm1: fephyled-txm1 {
1467 <2 25 RK_FUNC_3 &pcfg_pull_none>;
1470 fephyled_linkm1: fephyled-linkm1 {
1472 <2 24 RK_FUNC_2 &pcfg_pull_none>;
1477 tsadc_int: tsadc-int {
1479 <2 13 RK_FUNC_2 &pcfg_pull_none>;
1481 tsadc_gpio: tsadc-gpio {
1483 <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1488 hdmi_cec: hdmi-cec {
1490 <0 3 RK_FUNC_1 &pcfg_pull_none>;
1493 hdmi_hpd: hdmi-hpd {
1495 <0 4 RK_FUNC_1 &pcfg_pull_down>;
1500 dvp_d2d9_m0:dvp-d2d9-m0 {
1503 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1505 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1507 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1509 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1511 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1513 <3 9 RK_FUNC_2 &pcfg_pull_none>,
1515 <3 10 RK_FUNC_2 &pcfg_pull_none>,
1517 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1519 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1521 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1523 <3 3 RK_FUNC_2 &pcfg_pull_none>,
1525 <3 2 RK_FUNC_2 &pcfg_pull_none>;
1530 dvp_d2d9_m1:dvp-d2d9-m1 {
1533 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1535 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1537 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1539 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1541 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1543 <2 16 RK_FUNC_4 &pcfg_pull_none>,
1545 <2 17 RK_FUNC_4 &pcfg_pull_none>,
1547 <2 18 RK_FUNC_4 &pcfg_pull_none>,
1549 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1551 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1553 <2 15 RK_FUNC_4 &pcfg_pull_none>,
1555 <3 2 RK_FUNC_2 &pcfg_pull_none>;