2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3328-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/soc/rockchip,boot-mode.h>
49 #include <dt-bindings/power/rk3328-power.h>
52 compatible = "rockchip,rk3328";
54 interrupt-parent = <&gic>;
74 compatible = "arm,cortex-a53", "arm,armv8";
76 enable-method = "psci";
77 // clocks = <&cru ARMCLK>;
78 operating-points-v2 = <&cpu0_opp_table>;
82 compatible = "arm,cortex-a53", "arm,armv8";
84 enable-method = "psci";
88 compatible = "arm,cortex-a53", "arm,armv8";
90 enable-method = "psci";
94 compatible = "arm,cortex-a53", "arm,armv8";
96 enable-method = "psci";
100 cpu0_opp_table: opp_table0 {
101 compatible = "operating-points-v2";
105 opp-hz = /bits/ 64 <408000000>;
106 opp-microvolt = <950000>;
107 clock-latency-ns = <40000>;
111 opp-hz = /bits/ 64 <600000000>;
112 opp-microvolt = <950000>;
113 clock-latency-ns = <40000>;
116 opp-hz = /bits/ 64 <816000000>;
117 opp-microvolt = <1000000>;
118 clock-latency-ns = <40000>;
121 opp-hz = /bits/ 64 <1008000000>;
122 opp-microvolt = <1100000>;
123 clock-latency-ns = <40000>;
126 opp-hz = /bits/ 64 <1200000000>;
127 opp-microvolt = <1225000>;
128 clock-latency-ns = <40000>;
131 opp-hz = /bits/ 64 <1296000000>;
132 opp-microvolt = <1300000>;
133 clock-latency-ns = <40000>;
138 compatible = "arm,cortex-a53-pmu";
139 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
143 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
147 compatible = "arm,psci-1.0";
152 compatible = "arm,armv8-timer";
153 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
154 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
155 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
156 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
160 compatible = "fixed-clock";
162 clock-frequency = <24000000>;
163 clock-output-names = "xin24m";
167 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
168 reg = <0x0 0xff000000 0x0 0x1000>;
169 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
171 clock-names = "i2s_clk", "i2s_hclk";
172 dmas = <&dmac 11>, <&dmac 12>;
174 dma-names = "tx", "rx";
179 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
180 reg = <0x0 0xff010000 0x0 0x1000>;
181 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
183 clock-names = "i2s_clk", "i2s_hclk";
184 dmas = <&dmac 14>, <&dmac 15>;
186 dma-names = "tx", "rx";
191 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
192 reg = <0x0 0xff020000 0x0 0x1000>;
193 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
195 clock-names = "i2s_clk", "i2s_hclk";
196 dmas = <&dmac 0>, <&dmac 1>;
198 dma-names = "tx", "rx";
199 pinctrl-names = "default", "sleep";
200 pinctrl-0 = <&i2s2m0_mclk
206 pinctrl-1 = <&i2s2m0_sleep>;
210 spdif: spdif@ff030000 {
211 compatible = "rockchip,rk3328-spdif";
212 reg = <0x0 0xff030000 0x0 0x1000>;
213 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
215 clock-names = "mclk", "hclk";
219 pinctrl-names = "default";
220 pinctrl-0 = <&spdifm2_tx>;
224 grf: syscon@ff100000 {
225 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
226 reg = <0x0 0xff100000 0x0 0x1000>;
227 #address-cells = <1>;
230 io_domains: io-domains {
231 compatible = "rockchip,rk3328-io-voltage-domain";
235 power: power-controller {
236 compatible = "rockchip,rk3328-power-controller";
237 #power-domain-cells = <1>;
238 #address-cells = <1>;
242 pd_hevc@RK3328_PD_HEVC {
243 reg = <RK3328_PD_HEVC>;
245 pd_video@RK3328_PD_VIDEO {
246 reg = <RK3328_PD_VIDEO>;
248 pd_vpu@RK3328_PD_VPU {
249 reg = <RK3328_PD_VPU>;
254 compatible = "syscon-reboot-mode";
256 mode-bootloader = <BOOT_BL_DOWNLOAD>;
257 mode-charge = <BOOT_CHARGING>;
258 mode-fastboot = <BOOT_FASTBOOT>;
259 mode-loader = <BOOT_BL_DOWNLOAD>;
260 mode-normal = <BOOT_NORMAL>;
261 mode-recovery = <BOOT_RECOVERY>;
262 mode-ums = <BOOT_UMS>;
266 uart0: serial@ff110000 {
267 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
268 reg = <0x0 0xff110000 0x0 0x100>;
269 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
271 clock-names = "baudclk", "apb_pclk";
274 dmas = <&dmac 2>, <&dmac 3>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
281 uart1: serial@ff120000 {
282 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
283 reg = <0x0 0xff120000 0x0 0x100>;
284 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
286 clock-names = "sclk_uart", "pclk_uart";
289 dmas = <&dmac 4>, <&dmac 5>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
296 uart2: serial@ff130000 {
297 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
298 reg = <0x0 0xff130000 0x0 0x100>;
299 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
301 clock-names = "baudclk", "apb_pclk";
304 dmas = <&dmac 6>, <&dmac 7>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&uart2m1_xfer>;
311 pmu: power-management@ff140000 {
312 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
313 reg = <0x0 0xff140000 0x0 0x1000>;
317 compatible = "rockchip,rk3328-i2c";
318 reg = <0x0 0xff150000 0x0 0x1000>;
319 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
320 #address-cells = <1>;
322 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
323 clock-names = "i2c", "pclk";
324 pinctrl-names = "default";
325 pinctrl-0 = <&i2c0_xfer>;
330 compatible = "rockchip,rk3328-i2c";
331 reg = <0x0 0xff160000 0x0 0x1000>;
332 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
333 #address-cells = <1>;
335 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
336 clock-names = "i2c", "pclk";
337 pinctrl-names = "default";
338 pinctrl-0 = <&i2c1_xfer>;
343 compatible = "rockchip,rk3328-i2c";
344 reg = <0x0 0xff170000 0x0 0x1000>;
345 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
346 #address-cells = <1>;
348 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
349 clock-names = "i2c", "pclk";
350 pinctrl-names = "default";
351 pinctrl-0 = <&i2c2_xfer>;
356 compatible = "rockchip,rk3328-i2c";
357 reg = <0x0 0xff180000 0x0 0x1000>;
358 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
361 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
362 clock-names = "i2c", "pclk";
363 pinctrl-names = "default";
364 pinctrl-0 = <&i2c3_xfer>;
369 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
370 reg = <0x0 0xff190000 0x0 0x1000>;
371 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
372 #address-cells = <1>;
374 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
375 clock-names = "spiclk", "apb_pclk";
376 dmas = <&dmac 8>, <&dmac 9>;
378 dma-names = "tx", "rx";
379 pinctrl-names = "default";
380 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
384 wdt: watchdog@ff1a0000 {
385 compatible = "snps,dw-wdt";
386 reg = <0x0 0xff1a0000 0x0 0x100>;
387 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
392 compatible = "simple-bus";
393 #address-cells = <2>;
397 dmac: dmac@ff1f0000 {
398 compatible = "arm,pl330", "arm,primecell";
399 reg = <0x0 0xff1f0000 0x0 0x4000>;
400 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&cru ACLK_DMAC>;
403 clock-names = "apb_pclk";
408 saradc: saradc@ff280000 {
409 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
410 reg = <0x0 0xff280000 0x0 0x100>;
411 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
412 #io-channel-cells = <1>;
413 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
414 clock-names = "saradc", "apb_pclk";
415 resets = <&cru SRST_SARADC_P>;
416 reset-names = "saradc-apb";
420 cru: clock-controller@ff440000 {
421 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
422 reg = <0x0 0xff440000 0x0 0x1000>;
423 rockchip,grf = <&grf>;
427 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
428 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
429 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
430 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
431 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
432 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
433 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
434 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
435 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
436 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
437 <&cru SCLK_WIFI>, <&cru ARMCLK>,
438 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
439 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
440 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
441 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
442 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
443 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
444 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
445 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
446 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
447 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
448 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
449 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
450 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
451 assigned-clock-parents =
452 <&cru HDMIPHY>, <&cru PLL_APLL>,
453 <&cru PLL_GPLL>, <&xin24m>,
454 <&xin24m>, <&xin24m>;
455 assigned-clock-rates =
458 <24000000>, <24000000>,
459 <15000000>, <15000000>,
460 <100000000>, <100000000>,
461 <100000000>, <100000000>,
462 <50000000>, <100000000>,
463 <100000000>, <100000000>,
464 <50000000>, <50000000>,
465 <50000000>, <50000000>,
466 <24000000>, <600000000>,
467 <491520000>, <1200000000>,
468 <150000000>, <75000000>,
469 <75000000>, <150000000>,
470 <75000000>, <75000000>,
471 <300000000>, <100000000>,
472 <300000000>, <200000000>,
473 <400000000>, <500000000>,
474 <200000000>, <300000000>,
475 <300000000>, <250000000>,
476 <200000000>, <100000000>,
477 <24000000>, <100000000>,
478 <150000000>, <50000000>,
482 sdmmc: rksdmmc@ff500000 {
483 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
484 reg = <0x0 0xff500000 0x0 0x4000>;
485 clock-freq-min-max = <400000 150000000>;
486 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
487 clock-names = "biu", "ciu";
488 fifo-depth = <0x100>;
489 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
493 sdio: dwmmc@ff510000 {
494 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
495 reg = <0x0 0xff510000 0x0 0x4000>;
496 clock-freq-min-max = <400000 150000000>;
497 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
498 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
499 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
500 fifo-depth = <0x100>;
501 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
505 emmc: rksdmmc@ff520000 {
506 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
507 reg = <0x0 0xff520000 0x0 0x4000>;
508 clock-freq-min-max = <400000 150000000>;
509 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
510 clock-names = "biu", "ciu";
511 fifo-depth = <0x100>;
512 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
516 sdmmc_ext: rksdmmc@ff5f0000 {
517 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
518 reg = <0x0 0xff5f0000 0x0 0x4000>;
519 clock-freq-min-max = <400000 150000000>;
520 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
521 clock-names = "biu", "ciu";
522 fifo-depth = <0x100>;
523 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
527 gic: interrupt-controller@ff811000 {
528 compatible = "arm,gic-400";
529 #interrupt-cells = <3>;
530 #address-cells = <0>;
531 interrupt-controller;
532 reg = <0x0 0xff811000 0 0x1000>,
533 <0x0 0xff812000 0 0x2000>,
534 <0x0 0xff814000 0 0x2000>,
535 <0x0 0xff816000 0 0x2000>;
536 interrupts = <GIC_PPI 9
537 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
541 compatible = "rockchip,rk3328-pinctrl";
542 rockchip,grf = <&grf>;
543 #address-cells = <2>;
547 gpio0: gpio0@ff210000 {
548 compatible = "rockchip,gpio-bank";
549 reg = <0x0 0xff210000 0x0 0x100>;
550 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&cru PCLK_GPIO0>;
556 interrupt-controller;
557 #interrupt-cells = <2>;
560 gpio1: gpio1@ff220000 {
561 compatible = "rockchip,gpio-bank";
562 reg = <0x0 0xff220000 0x0 0x100>;
563 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&cru PCLK_GPIO1>;
569 interrupt-controller;
570 #interrupt-cells = <2>;
573 gpio2: gpio2@ff230000 {
574 compatible = "rockchip,gpio-bank";
575 reg = <0x0 0xff230000 0x0 0x100>;
576 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&cru PCLK_GPIO2>;
582 interrupt-controller;
583 #interrupt-cells = <2>;
586 gpio3: gpio3@ff240000 {
587 compatible = "rockchip,gpio-bank";
588 reg = <0x0 0xff240000 0x0 0x100>;
589 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cru PCLK_GPIO3>;
595 interrupt-controller;
596 #interrupt-cells = <2>;
599 pcfg_pull_up: pcfg-pull-up {
603 pcfg_pull_down: pcfg-pull-down {
607 pcfg_pull_none: pcfg-pull-none {
611 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
613 drive-strength = <2>;
616 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
618 drive-strength = <2>;
621 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
623 drive-strength = <4>;
626 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
628 drive-strength = <4>;
631 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
633 drive-strength = <4>;
636 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
638 drive-strength = <8>;
641 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
643 drive-strength = <8>;
646 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
648 drive-strength = <12>;
651 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
653 drive-strength = <12>;
656 pcfg_output_high: pcfg-output-high {
660 pcfg_output_low: pcfg-output-low {
664 pcfg_input_high: pcfg-input-high {
669 pcfg_input: pcfg-input {
674 i2c0_xfer: i2c0-xfer {
676 <2 24 RK_FUNC_1 &pcfg_pull_none>,
677 <2 25 RK_FUNC_1 &pcfg_pull_none>;
682 i2c1_xfer: i2c1-xfer {
684 <2 4 RK_FUNC_2 &pcfg_pull_none>,
685 <2 5 RK_FUNC_2 &pcfg_pull_none>;
690 i2c2_xfer: i2c2-xfer {
692 <2 13 RK_FUNC_1 &pcfg_pull_none>,
693 <2 14 RK_FUNC_1 &pcfg_pull_none>;
698 i2c3_xfer: i2c3-xfer {
700 <0 5 RK_FUNC_2 &pcfg_pull_none>,
701 <0 6 RK_FUNC_2 &pcfg_pull_none>;
703 i2c3_gpio: i2c3-gpio {
705 <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
706 <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
711 hdmii2c_xfer: hdmii2c-xfer {
713 <0 5 RK_FUNC_1 &pcfg_pull_none>,
714 <0 6 RK_FUNC_1 &pcfg_pull_none>;
719 uart0_xfer: uart0-xfer {
721 <1 9 RK_FUNC_1 &pcfg_pull_up>,
722 <1 8 RK_FUNC_1 &pcfg_pull_none>;
725 uart0_cts: uart0-cts {
727 <1 11 RK_FUNC_1 &pcfg_pull_none>;
730 uart0_rts: uart0-rts {
732 <1 10 RK_FUNC_1 &pcfg_pull_none>;
735 uart0_rts_gpio: uart0-rts-gpio {
737 <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
742 uart1_xfer: uart1-xfer {
744 <3 4 RK_FUNC_4 &pcfg_pull_up>,
745 <3 6 RK_FUNC_4 &pcfg_pull_none>;
748 uart1_cts: uart1-cts {
750 <3 7 RK_FUNC_4 &pcfg_pull_none>;
753 uart1_rts: uart1-rts {
755 <3 5 RK_FUNC_4 &pcfg_pull_none>;
758 uart1_rts_gpio: uart1-rts-gpio {
760 <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
765 uart2m0_xfer: uart2m0-xfer {
767 <1 0 RK_FUNC_2 &pcfg_pull_up>,
768 <1 1 RK_FUNC_2 &pcfg_pull_none>;
773 uart2m1_xfer: uart2m1-xfer {
775 <2 0 RK_FUNC_1 &pcfg_pull_up>,
776 <2 1 RK_FUNC_1 &pcfg_pull_none>;
781 spi0m0_clk: spi0m0-clk {
783 <2 8 RK_FUNC_1 &pcfg_pull_up>;
786 spi0m0_cs0: spi0m0-cs0 {
788 <2 11 RK_FUNC_1 &pcfg_pull_up>;
791 spi0m0_tx: spi0m0-tx {
793 <2 9 RK_FUNC_1 &pcfg_pull_up>;
796 spi0m0_rx: spi0m0-rx {
798 <2 10 RK_FUNC_1 &pcfg_pull_up>;
801 spi0m0_cs1: spi0m0-cs1 {
803 <2 12 RK_FUNC_1 &pcfg_pull_up>;
808 spi0m1_clk: spi0m1-clk {
810 <3 23 RK_FUNC_2 &pcfg_pull_up>;
813 spi0m1_cs0: spi0m1-cs0 {
815 <3 26 RK_FUNC_2 &pcfg_pull_up>;
818 spi0m1_tx: spi0m1-tx {
820 <3 25 RK_FUNC_2 &pcfg_pull_up>;
823 spi0m1_rx: spi0m1-rx {
825 <3 24 RK_FUNC_2 &pcfg_pull_up>;
828 spi0m1_cs1: spi0m1-cs1 {
830 <3 27 RK_FUNC_2 &pcfg_pull_up>;
835 spi0m2_clk: spi0m2-clk {
837 <3 0 RK_FUNC_4 &pcfg_pull_up>;
840 spi0m2_cs0: spi0m2-cs0 {
842 <3 8 RK_FUNC_3 &pcfg_pull_up>;
845 spi0m2_tx: spi0m2-tx {
847 <3 1 RK_FUNC_4 &pcfg_pull_up>;
850 spi0m2_rx: spi0m2-rx {
852 <3 2 RK_FUNC_4 &pcfg_pull_up>;
857 i2s1_mclk: i2s1-mclk {
859 <2 15 RK_FUNC_1 &pcfg_pull_none>;
862 i2s1_sclk: i2s1-sclk {
864 <2 18 RK_FUNC_1 &pcfg_pull_none>;
867 i2s1_lrckrx: i2s1-lrckrx {
869 <2 16 RK_FUNC_1 &pcfg_pull_none>;
872 i2s1_lrcktx: i2s1-lrcktx {
874 <2 17 RK_FUNC_1 &pcfg_pull_none>;
879 <2 19 RK_FUNC_1 &pcfg_pull_none>;
884 <2 23 RK_FUNC_1 &pcfg_pull_none>;
887 i2s1_sdio1: i2s1-sdio1 {
889 <2 20 RK_FUNC_1 &pcfg_pull_none>;
892 i2s1_sdio2: i2s1-sdio2 {
894 <2 21 RK_FUNC_1 &pcfg_pull_none>;
897 i2s1_sdio3: i2s1-sdio3 {
899 <2 22 RK_FUNC_1 &pcfg_pull_none>;
902 i2s1_sleep: i2s1-sleep {
904 <2 15 RK_FUNC_GPIO &pcfg_input_high>,
905 <2 16 RK_FUNC_GPIO &pcfg_input_high>,
906 <2 17 RK_FUNC_GPIO &pcfg_input_high>,
907 <2 18 RK_FUNC_GPIO &pcfg_input_high>,
908 <2 19 RK_FUNC_GPIO &pcfg_input_high>,
909 <2 20 RK_FUNC_GPIO &pcfg_input_high>,
910 <2 21 RK_FUNC_GPIO &pcfg_input_high>,
911 <2 22 RK_FUNC_GPIO &pcfg_input_high>,
912 <2 23 RK_FUNC_GPIO &pcfg_input_high>;
917 i2s2m0_mclk: i2s2m0-mclk {
919 <1 21 RK_FUNC_1 &pcfg_pull_none>;
922 i2s2m0_sclk: i2s2m0-sclk {
924 <1 22 RK_FUNC_1 &pcfg_pull_none>;
927 i2s2m0_lrckrx: i2s2m0-lrckrx {
929 <1 26 RK_FUNC_1 &pcfg_pull_none>;
932 i2s2m0_lrcktx: i2s2m0-lrcktx {
934 <1 23 RK_FUNC_1 &pcfg_pull_none>;
937 i2s2m0_sdi: i2s2m0-sdi {
939 <1 24 RK_FUNC_1 &pcfg_pull_none>;
942 i2s2m0_sdo: i2s2m0-sdo {
944 <1 25 RK_FUNC_1 &pcfg_pull_none>;
947 i2s2m0_sleep: i2s2m0-sleep {
949 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
950 <1 22 RK_FUNC_GPIO &pcfg_input_high>,
951 <1 26 RK_FUNC_GPIO &pcfg_input_high>,
952 <1 23 RK_FUNC_GPIO &pcfg_input_high>,
953 <1 24 RK_FUNC_GPIO &pcfg_input_high>,
954 <1 25 RK_FUNC_GPIO &pcfg_input_high>;
959 i2s2m1_mclk: i2s2m1-mclk {
961 <1 21 RK_FUNC_1 &pcfg_pull_none>;
964 i2s2m1_sclk: i2s2m1-sclk {
966 <3 0 RK_FUNC_6 &pcfg_pull_none>;
969 i2s2m1_lrckrx: i2sm1-lrckrx {
971 <3 8 RK_FUNC_6 &pcfg_pull_none>;
974 i2s2m1_lrcktx: i2s2m1-lrcktx {
976 <3 8 RK_FUNC_4 &pcfg_pull_none>;
979 i2s2m1_sdi: i2s2m1-sdi {
981 <3 2 RK_FUNC_6 &pcfg_pull_none>;
984 i2s2m1_sdo: i2s2m1-sdo {
986 <3 1 RK_FUNC_6 &pcfg_pull_none>;
989 i2s2m1_sleep: i2s2m1-sleep {
991 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
992 <3 0 RK_FUNC_GPIO &pcfg_input_high>,
993 <3 8 RK_FUNC_GPIO &pcfg_input_high>,
994 <3 2 RK_FUNC_GPIO &pcfg_input_high>,
995 <3 1 RK_FUNC_GPIO &pcfg_input_high>;
1000 spdifm0_tx: spdifm0-tx {
1002 <0 27 RK_FUNC_1 &pcfg_pull_none>;
1007 spdifm1_tx: spdifm1-tx {
1009 <2 17 RK_FUNC_2 &pcfg_pull_none>;
1014 spdifm2_tx: spdifm2-tx {
1016 <0 2 RK_FUNC_2 &pcfg_pull_none>;
1021 sdmmc0m0_pwren: sdmmc0m0-pwren {
1023 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1026 sdmmc0m0_gpio: sdmmc0m0-gpio {
1028 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1033 sdmmc0m1_pwren: sdmmc0m1-pwren {
1035 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1038 sdmmc0m1_gpio: sdmmc0m1-gpio {
1040 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1045 sdmmc0_clk: sdmmc0-clk {
1047 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1050 sdmmc0_cmd: sdmmc0-cmd {
1052 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1055 sdmmc0_dectn: sdmmc0-dectn {
1057 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1060 sdmmc0_wrprt: sdmmc0-wrprt {
1062 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1065 sdmmc0_bus1: sdmmc0-bus1 {
1067 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1070 sdmmc0_bus4: sdmmc0-bus4 {
1072 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1073 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1074 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1075 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1078 sdmmc0_gpio: sdmmc0-gpio {
1080 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1081 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1082 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1083 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1084 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1085 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1086 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1087 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1092 sdmmc0ext_clk: sdmmc0ext-clk {
1094 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1097 sdmmc0ext_cmd: sdmmc0ext-cmd {
1099 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1102 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1104 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1107 sdmmc0ext_dectn: sdmmc0ext-dectn {
1109 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1112 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1114 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1117 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1119 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1120 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1121 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1122 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1125 sdmmc0ext_gpio: sdmmc0ext-gpio {
1127 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1128 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1129 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1130 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1131 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1132 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1133 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1134 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1139 sdmmc1_clk: sdmmc1-clk {
1141 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1144 sdmmc1_cmd: sdmmc1-cmd {
1146 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1149 sdmmc1_pwren: sdmmc1-pwren {
1151 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1154 sdmmc1_wrprt: sdmmc1-wrprt {
1156 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1159 sdmmc1_dectn: sdmmc1-dectn {
1161 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1164 sdmmc1_bus1: sdmmc1-bus1 {
1166 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1169 sdmmc1_bus4: sdmmc1-bus4 {
1171 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1172 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1173 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1174 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1177 sdmmc1_gpio: sdmmc1-gpio {
1179 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1180 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1181 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1182 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1183 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1184 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1185 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1186 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1187 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1192 emmc_clk: emmc-clk {
1194 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1197 emmc_cmd: emmc-cmd {
1199 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1202 emmc_pwren: emmc-pwren {
1204 <3 22 RK_FUNC_2 &pcfg_pull_none>;
1207 emmc_rstnout: emmc-rstnout {
1209 <3 20 RK_FUNC_2 &pcfg_pull_none>;
1212 emmc_bus1: emmc-bus1 {
1214 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1217 emmc_bus4: emmc-bus4 {
1219 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1220 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1221 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1222 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1225 emmc_bus8: emmc-bus8 {
1227 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1228 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1229 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1230 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1231 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1232 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1233 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1234 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1239 pwm0_pin: pwm0-pin {
1241 <2 4 RK_FUNC_1 &pcfg_pull_none>;
1246 pwm1_pin: pwm1-pin {
1248 <2 5 RK_FUNC_1 &pcfg_pull_none>;
1253 pwm2_pin: pwm2-pin {
1255 <2 6 RK_FUNC_1 &pcfg_pull_none>;
1260 pwmir_pin: pwmir-pin {
1262 <2 2 RK_FUNC_1 &pcfg_pull_none>;
1267 rgmiim0_pins: rgmiim0-pins {
1270 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1272 <0 10 RK_FUNC_1 &pcfg_pull_none>,
1274 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1276 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1278 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1280 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1282 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1284 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1286 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1288 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1290 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1292 <0 20 RK_FUNC_1 &pcfg_pull_none>,
1294 <0 21 RK_FUNC_1 &pcfg_pull_none>,
1296 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1298 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1301 rmiim0_pins: rmiim0-pins {
1304 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1306 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1308 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1310 <0 13 RK_FUNC_1 &pcfg_pull_none>,
1312 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1314 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1316 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1318 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1320 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1322 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1327 rgmiim1_pins: rgmiim1-pins {
1330 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1332 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1334 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1336 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1338 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1340 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1342 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1344 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1346 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1348 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1350 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1352 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1354 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1356 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1358 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1361 <0 8 RK_FUNC_1 &pcfg_pull_none>,
1363 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1365 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1367 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1369 <0 17 RK_FUNC_1 &pcfg_pull_none>,
1371 <0 23 RK_FUNC_1 &pcfg_pull_none>,
1373 <0 22 RK_FUNC_1 &pcfg_pull_none>;
1376 rmiim1_pins: rmiim1-pins {
1379 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1381 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1383 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1385 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1387 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1389 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1391 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1393 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1395 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1397 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1400 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1402 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1404 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1406 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1408 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1410 <0 17 RK_FUNC_1 &pcfg_pull_none>;
1415 fephyled_speed100: fephyled-speed100 {
1417 <0 31 RK_FUNC_1 &pcfg_pull_none>;
1420 fephyled_speed10: fephyled-speed10 {
1422 <0 30 RK_FUNC_1 &pcfg_pull_none>;
1425 fephyled_duplex: fephyled-duplex {
1427 <0 30 RK_FUNC_2 &pcfg_pull_none>;
1430 fephyled_rxm0: fephyled-rxm0 {
1432 <0 29 RK_FUNC_1 &pcfg_pull_none>;
1435 fephyled_txm0: fephyled-txm0 {
1437 <0 29 RK_FUNC_2 &pcfg_pull_none>;
1440 fephyled_linkm0: fephyled-linkm0 {
1442 <0 28 RK_FUNC_1 &pcfg_pull_none>;
1445 fephyled_rxm1: fephyled-rxm1 {
1447 <2 25 RK_FUNC_2 &pcfg_pull_none>;
1450 fephyled_txm1: fephyled-txm1 {
1452 <2 25 RK_FUNC_3 &pcfg_pull_none>;
1455 fephyled_linkm1: fephyled-linkm1 {
1457 <2 24 RK_FUNC_2 &pcfg_pull_none>;
1462 tsadc_int: tsadc-int {
1464 <2 13 RK_FUNC_2 &pcfg_pull_none>;
1466 tsadc_gpio: tsadc-gpio {
1468 <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1473 hdmi_cec: hdmi-cec {
1475 <0 3 RK_FUNC_1 &pcfg_pull_none>;
1478 hdmi_hpd: hdmi-hpd {
1480 <0 4 RK_FUNC_1 &pcfg_pull_down>;
1485 dvp_d2d9_m0:dvp-d2d9-m0 {
1488 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1490 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1492 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1494 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1496 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1498 <3 9 RK_FUNC_2 &pcfg_pull_none>,
1500 <3 10 RK_FUNC_2 &pcfg_pull_none>,
1502 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1504 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1506 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1508 <3 3 RK_FUNC_2 &pcfg_pull_none>,
1510 <3 2 RK_FUNC_2 &pcfg_pull_none>;
1515 dvp_d2d9_m1:dvp-d2d9-m1 {
1518 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1520 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1522 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1524 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1526 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1528 <2 16 RK_FUNC_4 &pcfg_pull_none>,
1530 <2 17 RK_FUNC_4 &pcfg_pull_none>,
1532 <2 18 RK_FUNC_4 &pcfg_pull_none>,
1534 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1536 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1538 <2 15 RK_FUNC_4 &pcfg_pull_none>,
1540 <3 2 RK_FUNC_2 &pcfg_pull_none>;