arch/arm64/boot/dts/rk3368.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-rk3368.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/sensor-dev.h>
   6 #include <dt-bindings/clock/rk_system_status.h>
   7
   8 #include "rk3368-clocks.dtsi"
   9 #include <rk3368_dram_default_timing.dtsi>
  10
  11 / {
  12         compatible = "rockchip,rk3368";
  13
  14         rockchip,sram = <&sram>;
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 serial0 = &uart_bt;
  21                 serial1 = &uart_bb;
  22                 serial2 = &uart_dbg;
  23                 serial3 = &uart_gps;
  24                 serial4 = &uart_exp;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 i2c2 = &i2c2;
  28                 i2c3 = &i2c3;
  29                 i2c4 = &i2c4;
  30                 i2c5 = &i2c5;
  31                 spi0 = &spi0;
  32                 spi1 = &spi1;
  33                 spi2 = &spi2;
  34                 lcdc = &lcdc;
  35         };
  36
  37         cpus {
  38                 #address-cells = <2>;
  39                 #size-cells = <0>;
  40
  41                 idle-states {
  42                         entry-method = "arm,psci";
  43                         CPU_SLEEP_0: cpu-sleep-0 {
  44                                 compatible = "arm,idle-state";
  45                                 arm,psci-suspend-param = <0x1010000>;
  46                                 entry-latency-us = <0x3fffffff>;
  47                                 exit-latency-us = <0x40000000>;
  48                                 min-residency-us = <0xffffffff>;
  49                         };
  50                 };
  51
  52                 little0: cpu@0 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a53", "arm,armv8";
  55                         reg = <0x0 0x0>;
  56                         enable-method = "psci";
  57                         cpu-idle-states = <&CPU_SLEEP_0>;
  58                 };
  59                 little1: cpu@1 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a53", "arm,armv8";
  62                         reg = <0x0 0x1>;
  63                         enable-method = "psci";
  64                         cpu-idle-states = <&CPU_SLEEP_0>;
  65                 };
  66                 little2: cpu@2 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a53", "arm,armv8";
  69                         reg = <0x0 0x2>;
  70                         enable-method = "psci";
  71                         cpu-idle-states = <&CPU_SLEEP_0>;
  72                 };
  73                 little3: cpu@3 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a53", "arm,armv8";
  76                         reg = <0x0 0x3>;
  77                         enable-method = "psci";
  78                         cpu-idle-states = <&CPU_SLEEP_0>;
  79                 };
  80                 big0: cpu@100 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a53", "arm,armv8";
  83                         reg = <0x0 0x100>;
  84                         enable-method = "psci";
  85                         cpu-idle-states = <&CPU_SLEEP_0>;
  86                 };
  87                 big1: cpu@101 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a53", "arm,armv8";
  90                         reg = <0x0 0x101>;
  91                         enable-method = "psci";
  92                         cpu-idle-states = <&CPU_SLEEP_0>;
  93                 };
  94                 big2: cpu@102 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a53", "arm,armv8";
  97                         reg = <0x0 0x102>;
  98                         enable-method = "psci";
  99                         cpu-idle-states = <&CPU_SLEEP_0>;
 100                 };
 101                 big3: cpu@103 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a53", "arm,armv8";
 104                         reg = <0x0 0x103>;
 105                         enable-method = "psci";
 106                         cpu-idle-states = <&CPU_SLEEP_0>;
 107                 };
 108
 109                 cpu-map {
 110                         cluster0 {
 111                                 core0 {
 112                                         cpu = <&big0>;
 113                                 };
 114                                 core1 {
 115                                         cpu = <&big1>;
 116                                 };
 117                                 core2 {
 118                                         cpu = <&big2>;
 119                                 };
 120                                 core3 {
 121                                         cpu = <&big3>;
 122                                 };
 123                         };
 124                         cluster1 {
 125                                 core0 {
 126                                         cpu = <&little0>;
 127                                 };
 128                                 core1 {
 129                                         cpu = <&little1>;
 130                                 };
 131                                 core2 {
 132                                         cpu = <&little2>;
 133                                 };
 134                                 core3 {
 135                                         cpu = <&little3>;
 136                                 };
 137                         };
 138                 };
 139         };
 140
 141         psci {
 142                 compatible = "arm,psci-0.2";
 143                 method = "smc";
 144         };
 145
 146         gic: interrupt-controller@ffb70000 {
 147                 compatible = "arm,cortex-a15-gic";
 148                 #interrupt-cells = <3>;
 149                 #address-cells = <0>;
 150                 interrupt-controller;
 151                 reg = <0x0 0xffb71000 0 0x1000>,
 152                       <0x0 0xffb72000 0 0x1000>;
 153         };
 154
 155         ddrpctl: syscon@ff610000 {
 156                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 157                 reg = <0x0 0xff610000 0x0 0x400>;
 158         };
 159
 160         pmu: syscon@ff730000 {
 161                 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
 162                 reg = <0x0 0xff730000 0x0 0x1000>;
 163         };
 164
 165         pmugrf: syscon@ff738000 {
 166                 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
 167                 reg = <0x0 0xff738000 0x0 0x1000>;
 168         };
 169
 170         sgrf: syscon@ff740000 {
 171                 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
 172                 reg = <0x0 0xff740000 0x0 0x1000>;
 173
 174         };
 175
 176         cru: syscon@ff760000 {
 177                 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
 178                 reg = <0x0 0xff760000 0x0 0x1000>;
 179         };
 180
 181         grf: syscon@ff770000 {
 182                 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
 183                 reg = <0x0 0xff770000 0x0 0x1000>;
 184         };
 185
 186         msch: syscon@ffac0000 {
 187                 compatible = "rockchip,rk3368-msch", "rockchip,msch", "syscon";
 188                 reg = <0x0 0xffac0000 0x0 0x3000>;
 189         };
 190
 191         arm-pmu {
 192                 compatible = "arm,armv8-pmuv3";
 193                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 200                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 201         };
 202
 203         cpu_axi_bus: cpu_axi_bus {
 204                 compatible = "rockchip,cpu_axi_bus";
 205                 #address-cells = <2>;
 206                 #size-cells = <2>;
 207                 ranges;
 208
 209                 qos {
 210                         #address-cells = <2>;
 211                         #size-cells = <2>;
 212                         ranges;
 213
 214                         dmac {
 215                                 reg = <0x0 0xffa80000 0x0 0x20>;
 216                         };
 217                         crypto {
 218                                 reg = <0x0 0xffa80080 0x0 0x20>;
 219                         };
 220                         tsp {
 221                                 reg = <0x0 0xffa80280 0x0 0x20>;
 222                         };
 223                         bus_cpup {
 224                                 reg = <0x0 0xffa90000 0x0 0x20>;
 225                         };
 226                         cci_r {
 227                                 reg = <0x0 0xffaa0000 0x0 0x20>;
 228                         };
 229                         cci_w {
 230                                 reg = <0x0 0xffaa0080 0x0 0x20>;
 231                         };
 232                         peri {
 233                                 reg = <0x0 0xffab0000 0x0 0x20>;
 234                                 rockchip,priority = <2 2>;
 235                         };
 236                         iep {
 237                                 reg = <0x0 0xffad0000 0x0 0x20>;
 238                         };
 239                         isp_r0 {
 240                                 reg = <0x0 0xffad0080 0x0 0x20>;
 241                         };
 242                         isp_r1 {
 243                                 reg = <0x0 0xffad0100 0x0 0x20>;
 244                         };
 245                         isp_w0 {
 246                                 reg = <0x0 0xffad0180 0x0 0x20>;
 247                                 rockchip,priority = <2 2>;
 248                         };
 249                         isp_w1 {
 250                                 reg = <0x0 0xffad0200 0x0 0x20>;
 251                                 rockchip,priority = <2 2>;
 252                         };
 253                         vip {
 254                                 reg = <0x0 0xffad0280 0x0 0x20>;
 255                         };
 256                         vop {
 257                                 reg = <0x0 0xffad0300 0x0 0x20>;
 258                                 rockchip,priority = <2 2>;
 259                         };
 260                         rga_r {
 261                                 reg = <0x0 0xffad0380 0x0 0x20>;
 262                         };
 263                         rga_w {
 264                                 reg = <0x0 0xffad0400 0x0 0x20>;
 265                         };
 266                         hevc_r {
 267                                 reg = <0x0 0xffae0000 0x0 0x20>;
 268                         };
 269                         vpu_r {
 270                                 reg = <0x0 0xffae0100 0x0 0x20>;
 271                         };
 272                         vpu_w {
 273                                 reg = <0x0 0xffae0180 0x0 0x20>;
 274                         };
 275                         gpu {
 276                                 reg = <0x0 0xffaf0000 0x0 0x20>;
 277                         };
 278                 };
 279
 280                 msch {
 281                         #address-cells = <2>;
 282                         #size-cells = <2>;
 283                         ranges;
 284
 285                         msch {
 286                                 reg = <0x0 0xffac0000 0x0 0x3c>;
 287                                 rockchip,read-latency = <0x34>;
 288                         };
 289                 };
 290         };
 291
 292         efuse_256@ffb00000 {
 293                 compatible = "rockchip,rk3368-efuse-256";
 294                 reg = <0x0 0xffb00000 0x0 0x8>;
 295         };
 296
 297         timer {
 298                 compatible = "arm,armv8-timer";
 299                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 300                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 301                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 302                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 303                 clock-frequency = <24000000>;
 304         };
 305
 306         timer@ff810000 {
 307                 compatible = "rockchip,timer";
 308                 reg = <0x0 0xff810000 0x0 0x20>;
 309                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 310                 rockchip,broadcast = <1>;
 311         };
 312
 313         timer@ff810020 {
 314                 compatible = "rockchip,timer";
 315                 reg = <0x0 0xff810020 0x0 0x20>;
 316                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 317                 rockchip,percpu = <0>;
 318         };
 319
 320         sram: sram@ff8c0000 {
 321                 compatible = "mmio-sram";
 322                 reg = <0x0 0xff8c0000 0x0 0xf000>; /* 60K (reserved 4K for mailbox)*/
 323                 map-exec;
 324         };
 325
 326         watchdog: wdt@ff800000 {
 327                 compatible = "rockchip,watch dog";
 328                 reg = <0x0 0xff800000 0x0 0x100>;
 329                 clocks = <&pclk_alive_pre>;
 330                 clock-names = "pclk_wdt";
 331                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 332                 rockchip,irq = <1>;
 333                 rockchip,timeout = <60>;
 334                 rockchip,atboot = <1>;
 335                 rockchip,debug = <0>;
 336                 status = "disabled";
 337         };
 338
 339         amba {
 340                 #address-cells = <2>;
 341                 #size-cells = <2>;
 342                 compatible = "arm,amba-bus";
 343                 interrupt-parent = <&gic>;
 344                 ranges;
 345
 346                 pdma0: pdma@ff600000 {
 347                         compatible = "arm,pl330", "arm,primecell";
 348                         reg = <0x0 0xff600000 0x0 0x4000>;
 349                         clocks = <&clk_gates12 11>;
 350                         clock-names = "apb_pclk";
 351                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 352                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 353                         #dma-cells = <1>;
 354
 355                 };
 356
 357                 pdma1: pdma@ff250000 {
 358                         compatible = "arm,pl330", "arm,primecell";
 359                         reg = <0x0 0xff250000 0x0 0x4000>;
 360                         clocks = <&clk_gates19 3>;
 361                         clock-names = "apb_pclk";
 362                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 363                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 364                         #dma-cells = <1>;
 365                 };
 366         };
 367
 368         reset: reset@ff760300{
 369                 compatible = "rockchip,reset";
 370                 reg = <0x0 0xff760300 0x0 0x38>;
 371                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 372                 #reset-cells = <1>;
 373         };
 374
 375         nandc0: nandc@ff400000 {
 376                 compatible = "rockchip,rk-nandc";
 377                 reg = <0x0 0xff400000 0x0 0x4000>;
 378                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 379                 nandc_id = <0>;
 380                 clocks = <&clk_nandc0>, <&clk_gates20 9>, <&clk_gates20 11>;
 381                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 382         };
 383
 384         nandc0reg: nandc0@ff400000 {
 385                 compatible = "rockchip,rk-nandc";
 386                 reg = <0x0 0xff400000 0x0 0x4000>;
 387         };
 388
 389         emmc: rksdmmc@ff0f0000 {
 390                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 391                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 392                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
 396                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 397                 rockchip,grf = <&grf>;
 398                 rockchip,cru = <&cru>;
 399                 num-slots = <1>;
 400                 fifo-depth = <0x100>;
 401                 bus-width = <8>;
 402                 tune_regsbase = <0x418>;
 403                 cru_regsbase = <0x320>;
 404                 cru_reset_offset = <3>;
 405         };
 406
 407         sdmmc: rksdmmc@ff0c0000 {
 408                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 409                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 410                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 411                 #address-cells = <1>;
 412                 #size-cells = <0>;
 413                 pinctrl-names = "default", "idle", "udbg";
 414                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 415                 pinctrl-1 = <&sdmmc_gpio>;
 416                 pinctrl-2 = <&uart2_xfer &cpu_jtag &mcu_jtag &sdmmc_dectn>;
 417                 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 418                 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
 419                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 420                 rockchip,grf = <&grf>;
 421                 rockchip,cru = <&cru>;
 422                 num-slots = <1>;
 423                 fifo-depth = <0x100>;
 424                 bus-width = <4>;
 425                 tune_regsbase = <0x400>;
 426                 cru_regsbase = <0x320>;
 427                 cru_reset_offset = <0>;
 428         };
 429
 430         sdio: rksdmmc@ff0d0000 {
 431                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 432                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 433                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 434                 #address-cells = <1>;
 435                 #size-cells = <0>;
 436                 pinctrl-names = "default","idle";
 437                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
 438                 pinctrl-1 = <&sdio0_gpio>;
 439                 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
 440                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 441                 rockchip,grf = <&grf>;
 442                 rockchip,cru = <&cru>;
 443                 num-slots = <1>;
 444                 fifo-depth = <0x100>;
 445                 bus-width = <4>;
 446                 tune_regsbase = <0x408>;
 447                 cru_regsbase = <0x320>;
 448                 cru_reset_offset = <1>;
 449         };
 450
 451         spi0: spi@ff110000 {
 452                 compatible = "rockchip,rockchip-spi";
 453                 reg = <0x0 0xff110000 0x0 0x1000>;
 454                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 455                 #address-cells = <1>;
 456                 #size-cells = <0>;
 457                 pinctrl-names = "default";
 458                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 459                 rockchip,spi-src-clk = <0>;
 460                 num-cs = <2>;
 461                 clocks =<&clk_spi0>, <&clk_gates19 4>;
 462                 clock-names = "spi", "pclk_spi0";
 463                 //dmas = <&pdma1 11>, <&pdma1 12>;
 464                 //#dma-cells = <2>;
 465                 //dma-names = "tx", "rx";
 466                 status = "disabled";
 467         };
 468
 469         spi1: spi@ff120000 {
 470                 compatible = "rockchip,rockchip-spi";
 471                 reg = <0x0 0xff120000 0x0 0x1000>;
 472                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 pinctrl-names = "default";
 476                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0 &spi1_cs1>;
 477                 rockchip,spi-src-clk = <1>;
 478                 num-cs = <2>;
 479                 clocks = <&clk_spi1>, <&clk_gates19 5>;
 480                 clock-names = "spi", "pclk_spi1";
 481                 //dmas = <&pdma1 13>, <&pdma1 14>;
 482                 //#dma-cells = <2>;
 483                 //dma-names = "tx", "rx";
 484                 status = "disabled";
 485         };
 486
 487         spi2: spi@ff130000 {
 488                 compatible = "rockchip,rockchip-spi";
 489                 reg = <0x0 0xff130000 0x0 0x1000>;
 490                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 491                 #address-cells = <1>;
 492                 #size-cells = <0>;
 493                 pinctrl-names = "default";
 494                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 495                 rockchip,spi-src-clk = <2>;
 496                 num-cs = <1>;
 497                 clocks = <&clk_spi2>, <&clk_gates19 6>;
 498                 clock-names = "spi", "pclk_spi2";
 499                 //dmas = <&pdma1 15>, <&pdma1 16>;
 500                 //#dma-cells = <2>;
 501                 //dma-names = "tx", "rx";
 502                 status = "disabled";
 503         };
 504
 505         uart_bt: serial@ff180000 {
 506                 compatible = "rockchip,serial";
 507                 reg = <0x0 0xff180000 0x0 0x100>;
 508                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 509                 clock-frequency = <24000000>;
 510                 clocks = <&clk_uart0>, <&clk_gates19 7>;
 511                 clock-names = "sclk_uart", "pclk_uart";
 512                 reg-shift = <2>;
 513                 reg-io-width = <4>;
 514                 //dmas = <&pdma1 1>, <&pdma1 2>;
 515                 //#dma-cells = <2>;
 516                 pinctrl-names = "default";
 517                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 518                 status = "disabled";
 519         };
 520
 521         uart_bb: serial@ff190000 {
 522                 compatible = "rockchip,serial";
 523                 reg = <0x0 0xff190000 0x0 0x100>;
 524                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 525                 clock-frequency = <24000000>;
 526                 clocks = <&clk_uart1>, <&clk_gates19 8>;
 527                 clock-names = "sclk_uart", "pclk_uart";
 528                 reg-shift = <2>;
 529                 reg-io-width = <4>;
 530                 //dmas = <&pdma1 3>, <&pdma1 4>;
 531                 //#dma-cells = <2>;
 532                 pinctrl-names = "default";
 533                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 534                 status = "disabled";
 535         };
 536
 537         uart_dbg: serial@ff690000 {
 538                 compatible = "rockchip,serial";
 539                 reg = <0x0 0xff690000 0x0 0x100>;
 540                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 541                 clock-frequency = <24000000>;
 542                 clocks = <&clk_uart2>, <&clk_gates13 5>;
 543                 clock-names = "sclk_uart", "pclk_uart";
 544                 reg-shift = <2>;
 545                 reg-io-width = <4>;
 546                 //dmas = <&pdma0 4>, <&pdma0 5>;
 547                 //#dma-cells = <2>;
 548                 //pinctrl-names = "default";
 549                 //pinctrl-0 = <&uart2_xfer>;
 550                 status = "disabled";
 551         };
 552
 553         uart_gps: serial@ff1b0000 {
 554                 compatible = "rockchip,serial";
 555                 reg = <0x0 0xff1b0000 0x0 0x100>;
 556                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 557                 clock-frequency = <24000000>;
 558                 clocks = <&clk_uart3>, <&clk_gates19 9>;
 559                 clock-names = "sclk_uart", "pclk_uart";
 560                 current-speed = <115200>;
 561                 reg-shift = <2>;
 562                 reg-io-width = <4>;
 563                 //dmas = <&pdma1 7>, <&pdma1 8>;
 564                 //#dma-cells = <2>;
 565                 pinctrl-names = "default";
 566                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 567                 status = "disabled";
 568         };
 569
 570         uart_exp: serial@ff1c0000 {
 571                 compatible = "rockchip,serial";
 572                 reg = <0x0 0xff1c0000 0x0 0x100>;
 573                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 574                 clock-frequency = <24000000>;
 575                 clocks = <&clk_uart4>, <&clk_gates19 10>;
 576                 clock-names = "sclk_uart", "pclk_uart";
 577                 reg-shift = <2>;
 578                 reg-io-width = <4>;
 579                 //dmas = <&pdma1 9>, <&pdma1 10>;
 580                 //#dma-cells = <2>;
 581                 pinctrl-names = "default";
 582                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 583                 status = "disabled";
 584         };
 585
 586         fiq-debugger {
 587                 compatible = "rockchip,fiq-debugger";
 588                 rockchip,serial-id = <2>;
 589                 rockchip,signal-irq = <186>;
 590                 rockchip,wake-irq = <0>;
 591                 rockchip,irq-mode-enable = <0>;  /* If enable uart uses irq instead of fiq */
 592                 rockchip,baudrate = <115200>;  /* Only 115200 and 1500000 */
 593                 status = "disabled";
 594         };
 595
 596         mbox: mbox@ff6b0000 {
 597                 compatible = "rockchip,rk3368-mailbox";
 598                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 599                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 600                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 601                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 602                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 603                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 604                 clocks = <&clk_gates12 1>;
 605                 clock-names = "pclk_mailbox";
 606                 #mbox-cells = <1>;
 607         };
 608
 609         mbox_scpi: mbox-scpi {
 610                 compatible = "rockchip,mbox-scpi";
 611                 mboxes = <&mbox 0 &mbox 1 &mbox 2>;
 612                 chan-nums = <3>;
 613         };
 614
 615         ddr: ddr {
 616                 compatible = "rockchip,rk3368-ddr";
 617                 status = "okay";
 618                 rockchip,ddrpctl = <&ddrpctl>;
 619                 rockchip,grf = <&grf>;
 620                 rockchip,msch = <&msch>;
 621                 rockchip,ddr_timing = <&ddr_timing>;
 622         };
 623
 624         rockchip_clocks_init: clocks-init{
 625                 compatible = "rockchip,clocks-init";
 626                 rockchip,clocks-init-parent =
 627                         <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
 628                         <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
 629                         <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
 630                         <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
 631                 rockchip,clocks-init-rate =
 632                         <&clk_gpll 576000000>,          <&clk_core_b 792000000>,
 633                         <&clk_core_l 600000000>,        <&clk_cpll 400000000>,
 634                         /*<&clk_npll 500000000>,*/      <&aclk_bus 300000000>,
 635                         <&hclk_bus 150000000>,          <&pclk_bus 75000000>,
 636                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 637                         <&hclk_peri 150000000>,         <&pclk_peri 75000000>,
 638                         <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
 639                         <&clk_cs 300000000>,            <&clkin_trace 300000000>,
 640                         <&aclk_cci 600000000>,          <&clk_mac 125000000>,
 641                         <&aclk_vio0 400000000>,         <&hclk_vio 100000000>,
 642                         <&aclk_rga_pre 400000000>,      <&clk_rga 400000000>,
 643                         <&clk_isp 400000000>,           <&clk_edp 200000000>,
 644                         <&clk_gpu_core 400000000>,      <&aclk_gpu_mem 400000000>,
 645                         <&aclk_gpu_cfg 400000000>,      <&aclk_vepu 400000000>,
 646                         <&aclk_vdpu 400000000>,         <&clk_hevc_core 300000000>,
 647                         <&clk_hevc_cabac 300000000>;
 648 /*
 649                 rockchip,clocks-uboot-has-init =
 650                         <&aclk_vio0>;
 651 */
 652         };
 653
 654         rockchip_clocks_enable: clocks-enable {
 655                 compatible = "rockchip,clocks-enable";
 656                 clocks =
 657                         /*PLL*/
 658                         <&clk_apllb>,
 659                         <&clk_aplll>,
 660                         <&clk_dpll>,
 661                         <&clk_gpll>,
 662                         <&clk_cpll>,
 663
 664                         /*PD_CORE*/
 665                         <&clk_cs>,
 666                         <&clkin_trace>,
 667                         <&aclk_cci>,
 668
 669                         /*PD_BUS*/
 670                         <&aclk_bus>,
 671                         <&hclk_bus>,
 672                         <&pclk_bus>,
 673                         <&clk_gates12 12>,/*aclk_strc_sys*/
 674                         <&clk_gates12 6>,/*aclk_intmem1*/
 675                         <&clk_gates12 5>,/*aclk_intmem0*/
 676                         <&clk_gates12 4>,/*aclk_intmem*/
 677                         <&clk_gates13 9>,/*aclk_gic400*/
 678                         <&clk_gates12 9>,/*hclk_rom*/
 679
 680                         /*PD_ALIVE*/
 681                         <&clk_gates22 12>,/*pclk_timer0*/
 682                         <&clk_gates22 9>,/*pclk_alive_niu*/
 683                         <&clk_gates22 8>,/*pclk_grf*/
 684
 685                         /*PD_PMU*/
 686                         <&clk_gates23 5>,/*pclk_pmugrf*/
 687                         <&clk_gates23 3>,/*pclk_sgrf*/
 688                         <&clk_gates23 2>,/*pclk_pmu_noc*/
 689                         <&clk_gates23 1>,/*pclk_intmem1*/
 690                         <&clk_gates23 0>,/*pclk_pmu*/
 691
 692                         /*PD_PERI*/
 693                         <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
 694                         <&clk_gates20 8>,/*aclk_peri_niu*/
 695                         <&clk_gates21 4>,/*aclk_peri_mmu*/
 696                         <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
 697                         <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
 698                         <&clk_gates19 1>,/*pclk_peri_axi_matrix*/
 699
 700                         <&clk_gates24 0>, /* g_clk_timer0 */
 701                         <&clk_gates24 1>, /* g_clk_timer1 */
 702
 703                         <&fclk_mcu>,
 704                         <&stclk_mcu>,
 705                         <&clk_gates7 0>;/*clk_jtag*/
 706         };
 707
 708         /* I2C_PMU */
 709         i2c0: i2c@ff650000 {
 710                 compatible = "rockchip,rk30-i2c";
 711                 reg = <0x0 0xff650000 0x0 0x1000>;
 712                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 713                 #address-cells = <1>;
 714                 #size-cells = <0>;
 715                 pinctrl-names = "default", "gpio", "sleep";
 716                 pinctrl-0 = <&i2c0_xfer>;
 717                 pinctrl-1 = <&i2c0_gpio>;
 718                 pinctrl-2 = <&i2c0_sleep>;
 719                 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
 720                 clocks = <&clk_gates12 2>;
 721                 rockchip,check-idle = <1>;
 722                 status = "disabled";
 723         };
 724
 725         /* I2C_AUDIO */
 726         i2c1: i2c@ff660000 {
 727                 compatible = "rockchip,rk30-i2c";
 728                 reg = <0x0 0xff660000 0x0 0x1000>;
 729                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 730                 #address-cells = <1>;
 731                 #size-cells = <0>;
 732                 pinctrl-names = "default", "gpio", "sleep";
 733                 pinctrl-0 = <&i2c1_xfer>;
 734                 pinctrl-1 = <&i2c1_gpio>;
 735                 pinctrl-2 = <&i2c1_sleep>;
 736                 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
 737                 clocks = <&clk_gates12 3>;
 738                 rockchip,check-idle = <1>;
 739                 status = "disabled";
 740         };
 741
 742         /* I2C_SENSOR */
 743         i2c2: i2c@ff140000 {
 744                 compatible = "rockchip,rk30-i2c";
 745                 reg = <0x0 0xff140000 0x0 0x1000>;
 746                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 747                 #address-cells = <1>;
 748                 #size-cells = <0>;
 749                 pinctrl-names = "default", "gpio", "sleep";
 750                 pinctrl-0 = <&i2c2_xfer>;
 751                 pinctrl-1 = <&i2c2_gpio>;
 752                 pinctrl-2 = <&i2c2_sleep>;
 753                 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 754                 clocks = <&clk_gates19 11>;
 755                 rockchip,check-idle = <1>;
 756                 status = "disabled";
 757         };
 758
 759         /* I2C_CAM */
 760         i2c3: i2c@ff150000 {
 761                 compatible = "rockchip,rk30-i2c";
 762                 reg = <0x0 0xff150000 0x0 0x1000>;
 763                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 764                 #address-cells = <1>;
 765                 #size-cells = <0>;
 766                 pinctrl-names = "default", "gpio", "sleep";
 767                 pinctrl-0 = <&i2c3_xfer>;
 768                 pinctrl-1 = <&i2c3_gpio>;
 769                 pinctrl-2 = <&i2c3_sleep>;
 770                 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
 771                 clocks = <&clk_gates19 12>;
 772                 rockchip,check-idle = <1>;
 773                 status = "disabled";
 774         };
 775
 776         /* I2C_TP */
 777         i2c4: i2c@ff160000 {
 778                 compatible = "rockchip,rk30-i2c";
 779                 reg = <0x0 0xff160000 0x0 0x1000>;
 780                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 781                 #address-cells = <1>;
 782                 #size-cells = <0>;
 783                 pinctrl-names = "default", "gpio", "sleep";
 784                 pinctrl-0 = <&i2c4_xfer>;
 785                 pinctrl-1 = <&i2c4_gpio>;
 786                 pinctrl-2 = <&i2c4_sleep>;
 787                 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
 788                 clocks = <&clk_gates19 13>;
 789                 rockchip,check-idle = <1>;
 790                 status = "disabled";
 791         };
 792
 793         /* I2C_HDMI */
 794         i2c5: i2c@ff170000 {
 795                 compatible = "rockchip,rk30-i2c";
 796                 reg = <0x0 0xff170000 0x0 0x1000>;
 797                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 798                 #address-cells = <1>;
 799                 #size-cells = <0>;
 800                 pinctrl-names = "default", "gpio", "sleep";
 801                 pinctrl-0 = <&i2c5_xfer>;
 802                 pinctrl-1 = <&i2c5_gpio>;
 803                 pinctrl-2 = <&i2c5_sleep>;
 804                 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
 805                 clocks = <&clk_gates19 14>;
 806                 rockchip,check-idle = <1>;
 807                 status = "disabled";
 808         };
 809
 810         fb: fb {
 811                 compatible = "rockchip,rk-fb";
 812                 rockchip,disp-mode = <NO_DUAL>;
 813         };
 814
 815
 816         rk_screen: rk_screen {
 817                 compatible = "rockchip,screen";
 818         };
 819
 820         dsihost0: mipi@ff960000{
 821                 compatible = "rockchip,rk3368-dsi";
 822                 rockchip,prop = <0>;
 823                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 824                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 825                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 826                 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>, <&pd_mipidsi>;
 827                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host", "pd_mipi_dsi";
 828                 status = "disabled";
 829         };
 830
 831         lvds: lvds@ff968000 {
 832                 compatible = "rockchip,rk3368-lvds";
 833                 rockchip,grf = <&grf>;
 834                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 835                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 836                 clocks = <&clk_gates22 10>, <&clk_gates17 3>, <&pd_lvds>;
 837                 clock-names = "pclk_lvds", "pclk_lvds_ctl", "pd_lvds";
 838                 status = "disabled";
 839         };
 840
 841         edp: edp@ff970000 {
 842                 compatible = "rockchip,rk32-edp";
 843                 reg = <0x0 0xff970000 0x0 0x4000>;
 844                 rockchip,grf = <&grf>;
 845                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 846                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
 847                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 848                 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
 849                 reset-names = "edp_24m", "edp_apb";
 850         };
 851
 852         hdmi: hdmi@ff980000 {
 853                 compatible = "rockchip,rk3368-hdmi";
 854                 reg = <0x0 0xff980000 0x0 0x20000>;
 855                 rockchip,grf = <&grf>;
 856                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 857                 pinctrl-names = "default", "gpio";
 858                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 859                 pinctrl-1 = <&i2c5_gpio>;
 860                 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
 861                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 862                 status = "disabled";
 863         };
 864
 865         hdmi_hdcp2: hdmi_hdcp2@ff978000 {
 866                 compatible = "rockchip,rk3368-hdmi-hdcp2";
 867                 reg = <0x0 0xff978000 0x0 0x2000>;
 868                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 869                 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
 870                 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
 871                 status = "disabled";
 872         };
 873
 874         lcdc: lcdc@ff930000 {
 875                  compatible = "rockchip,rk3368-lcdc";
 876                  rockchip,grf = <&grf>;
 877                  rockchip,pmugrf = <&pmugrf>;
 878                  rockchip,cru = <&cru>;
 879                  rockchip,prop = <PRMRY>;
 880                  rockchip,pwr18 = <0>;
 881                  rockchip,iommu-enabled = <1>;
 882                  reg = <0x0 0xff930000 0x0 0x10000>;
 883                  interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 884                 /*pinctrl-names = "default", "gpio";
 885                  *pinctrl-0 = <&lcdc_lcdc>;
 886                  *pinctrl-1 = <&lcdc_gpio>;
 887                  */
 888                  status = "disabled";
 889                  clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>, <&pd_vop>;
 890                  clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll", "pd_lcdc";
 891         };
 892
 893         adc: adc@ff100000 {
 894                 compatible = "rockchip,saradc";
 895                 reg = <0x0 0xff100000 0x0 0x100>;
 896                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 897                 #io-channel-cells = <1>;
 898                 io-channel-ranges;
 899                 rockchip,adc-vref = <1800>;
 900                 clock-frequency = <1000000>;
 901                 clocks = <&clk_saradc>, <&clk_gates19 15>;
 902                 clock-names = "saradc", "pclk_saradc";
 903                 status = "disabled";
 904         };
 905
 906         rga@ff920000 {
 907                 compatible = "rockchip,rga2";
 908                 dev_mode = <1>;
 909                 reg = <0x0 0xff920000 0x0 0x1000>;
 910                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 911                 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
 912                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 913         };
 914
 915         i2s0: i2s0@ff898000 {
 916                 compatible = "rockchip-i2s";
 917                 reg = <0x0 0xff898000 0x0 0x1000>;
 918                 i2s-id = <0>;
 919                 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 920                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 921                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 922                 dmas = <&pdma0 0>, <&pdma0 1>;
 923                 #dma-cells = <2>;
 924                 dma-names = "tx", "rx";
 925                 pinctrl-names = "default", "sleep";
 926                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 927                 pinctrl-1 = <&i2s_gpio>;
 928         };
 929
 930         i2s1: i2s1@ff890000 {
 931                 compatible = "rockchip-i2s";
 932                 reg = <0x0 0xff890000 0x0 0x1000>;
 933                 i2s-id = <1>;
 934                 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
 935                 clock-names = "i2s_clk", "i2s_hclk";
 936                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 937                 dmas = <&pdma0 6>, <&pdma0 7>;
 938                 #dma-cells = <2>;
 939                 dma-names = "tx", "rx";
 940         };
 941
 942         spdif: spdif@ff880000 {
 943                 compatible = "rockchip-spdif";
 944                 reg = <0x0 0xff880000 0x0 0x1000>;
 945                 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
 946                 clock-names = "spdif_mclk", "spdif_hclk";
 947                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 948                 dmas = <&pdma0 3>;
 949                 #dma-cells = <1>;
 950                 dma-names = "tx";
 951                 pinctrl-names = "default";
 952                 pinctrl-0 = <&spdif_tx>;
 953         };
 954
 955         pwm0: pwm@ff680000 {
 956                 compatible = "rockchip,rk-pwm";
 957                 reg = <0x0 0xff680000 0x0 0x10>;
 958                 #pwm-cells = <2>;
 959                 pinctrl-names = "default";
 960                 pinctrl-0 = <&pwm0_pin>;
 961                 clocks = <&clk_gates13 6>;
 962                 clock-names = "pclk_pwm";
 963                 status = "disabled";
 964         };
 965
 966         pwm1: pwm@ff680010 {
 967                 compatible = "rockchip,rk-pwm";
 968                 reg = <0x0 0xff680010 0x0 0x10>;
 969                 #pwm-cells = <2>;
 970                 pinctrl-names = "default";
 971                 pinctrl-0 = <&pwm1_pin>;
 972                 clocks = <&clk_gates13 6>;
 973                 clock-names = "pclk_pwm";
 974                 status = "disabled";
 975         };
 976
 977         pwm2: pwm@ff680020 {
 978                 compatible = "rockchip,rk-pwm";
 979                 reg = <0x0 0xff680020 0x0 0x10>;
 980                 #pwm-cells = <2>;
 981                 //pinctrl-names = "default";
 982                 //pinctrl-0 = <&pwm1_pin>;
 983                 clocks = <&clk_gates13 6>;
 984                 clock-names = "pclk_pwm";
 985                 status = "disabled";
 986         };
 987
 988         pwm3: pwm@ff680030 {
 989                 compatible = "rockchip,rk-pwm";
 990                 reg = <0x0 0xff680030 0x0 0x10>;
 991                 #pwm-cells = <2>;
 992                 pinctrl-names = "default";
 993                 pinctrl-0 = <&pwm3_pin>;
 994                 clocks = <&clk_gates13 6>;
 995                 clock-names = "pclk_pwm";
 996                 status = "disabled";
 997         };
 998
 999         remotectl: pwm@ff680030 {
1000                 compatible = "rockchip,remotectl-pwm";
1001                 reg = <0x0 0xff680030 0x0 0x50>;
1002                 #pwm-cells = <2>;
1003                 pinctrl-names = "default";
1004                 pinctrl-0 = <&pwm3_pin>;
1005                 clocks = <&clk_gates13 6>;
1006                 clock-names = "pclk_pwm";
1007                 dmas = <&pdma0 2>;
1008                 #dma-cells = <2>;
1009                 dma-names = "rx";
1010                 remote_pwm_id = <3>;
1011                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1012                 status = "disabled";
1013         };
1014
1015         voppwm: pwm@ff9301a0 {
1016                 compatible = "rockchip,vop-pwm";
1017                 reg = <0x0 0xff9301a0 0x0 0x10>;
1018                 #pwm-cells = <2>;
1019                 pinctrl-names = "default";
1020                 pinctrl-0 = <&vop_pwm_pin>;
1021                 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
1022                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
1023                 status = "disabled";
1024         };
1025
1026         pvtm {
1027                 compatible = "rockchip,rk3368-pvtm";
1028                 rockchip,grf = <&grf>;
1029                 rockchip,pmugrf = <&pmugrf>;
1030                 rockchip,pvtm-clk-out = <1>;
1031         };
1032
1033         cpufreq {
1034                 compatible = "rockchip,rk3368-cpufreq";
1035                 rockchip,grf = <&grf>;
1036         };
1037
1038         dvfs {
1039
1040                 vd_arm: vd_arm {
1041                         regulator_name = "vdd_arm";
1042                         suspend_volt = <1000>; //mV
1043                         pd_core {
1044                                 clk_core_b_dvfs_table: clk_core_b {
1045                                         operating-points = <
1046                                                 /* KHz    uV */
1047                                                 312000 1200000
1048                                                 504000 1200000
1049                                                 816000 1200000
1050                                                 1008000 1200000
1051                                                 >;
1052                                         status = "okay";
1053                                         cluster = <0>;
1054                                         temp-limit-enable = <1>;
1055                                         target-temp = <80>;
1056                                         min_temp_limit = <216000>;
1057                                         normal-temp-limit = <
1058                                         /*delta-temp    delta-freq*/
1059                                                 3       96000
1060                                                 6       144000
1061                                                 9       192000
1062                                                 15      384000
1063                                                 >;
1064                                         performance-temp-limit = <
1065                                                 /*temp    freq*/
1066                                                 100     816000
1067                                                 >;
1068                                         lkg_adjust_volt_en = <1>;
1069                                         channel = <0>;
1070                                         def_table_lkg = <25>;
1071                                         min_adjust_freq = <216000>;
1072                                         lkg_adjust_volt_table = <
1073                                                 /*lkg(mA)  volt(uV)*/
1074                                                 0         25000
1075                                                 >;
1076                                         pvtm_min_temp = <25>;
1077                                 };
1078                                 clk_core_l_dvfs_table: clk_core_l {
1079                                         operating-points = <
1080                                                 /* KHz    uV */
1081                                                 312000 1200000
1082                                                 504000 1200000
1083                                                 816000 1200000
1084                                                 1008000 1200000
1085                                                 >;
1086                                         status = "okay";
1087                                         cluster = <1>;
1088                                         temp-limit-enable = <1>;
1089                                         target-temp = <80>;
1090                                         min_temp_limit = <216000>;
1091                                         normal-temp-limit = <
1092                                         /*delta-temp    delta-freq*/
1093                                                 3       96000
1094                                                 6       144000
1095                                                 9       192000
1096                                                 15      384000
1097                                                 >;
1098                                         performance-temp-limit = <
1099                                                 /*temp    freq*/
1100                                                 100     816000
1101                                                 >;
1102                                         lkg_adjust_volt_en = <1>;
1103                                         channel = <0>;
1104                                         def_table_lkg = <25>;
1105                                         min_adjust_freq = <216000>;
1106                                         lkg_adjust_volt_table = <
1107                                                 /*lkg(mA)  volt(uV)*/
1108                                                 0         25000
1109                                                 >;
1110                                         pvtm_min_temp = <25>;
1111                                 };
1112                         };
1113                 };
1114
1115                 vd_logic: vd_logic {
1116                         regulator_name = "vdd_logic";
1117                         suspend_volt = <1000>; //mV
1118                         pd_ddr {
1119                                 clk_ddr_dvfs_table: clk_ddr {
1120                                         operating-points = <
1121                                                 /* KHz    uV */
1122                                                 200000 1200000
1123                                                 300000 1200000
1124                                                 400000 1200000
1125                                                 >;
1126                                         bd-freq-table = <
1127                                                 /* bandwidth   freq */
1128                                                 2700           792000
1129                                                 2600           600000
1130                                                 2280           456000
1131                                                 1560           396000
1132                                                 1020           324000
1133                                                 720            240000
1134                                                 >;
1135                                         high_load = <70>;
1136                                         low_load = <60>;
1137                                         auto_freq_interval = <20>; /* ms */
1138                                         down_rate_delay = <500>;   /* ms */
1139                                         channel = <2>;
1140                                         status = "disabled";
1141                                 };
1142                         };
1143
1144                         pd_gpu {
1145                                 clk_gpu_dvfs_table: clk_gpu {
1146                                         operating-points = <
1147                                                 /* KHz    uV */
1148                                                 200000 1200000
1149                                                 300000 1200000
1150                                                 400000 1200000
1151                                                 >;
1152                                         channel = <1>;
1153                                         status = "okay";
1154                                         regu-mode-table = <
1155                                                 /*freq     mode*/
1156                                                 200000     4
1157                                                 0          3
1158                                         >;
1159                                         regu-mode-en = <0>;
1160                                 };
1161                         };
1162                 };
1163         };
1164
1165         ion {
1166                 compatible = "rockchip,ion";
1167                 #address-cells = <1>;
1168                 #size-cells = <0>;
1169
1170                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1171                         compatible = "rockchip,ion-heap";
1172                         rockchip,ion_heap = <4>;
1173                         reg = <0x00000000 0x00000000>; /* 0MB */
1174                 };
1175                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1176                         compatible = "rockchip,ion-heap";
1177                         rockchip,ion_heap = <0>;
1178                 };
1179         };
1180
1181         vpu: vpu_service {
1182                 compatible = "rockchip,vpu_sub";
1183                 iommu_enabled = <1>;
1184                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1185                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1186                 interrupt-names = "irq_enc", "irq_dec";
1187                 dev_mode = <0>;
1188                 name = "vpu_service";
1189         };
1190
1191         hevc: hevc_service {
1192                 compatible = "rockchip,hevc_sub";
1193                 iommu_enabled = <1>;
1194                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1195                 interrupt-names = "irq_dec";
1196                 dev_mode = <1>;
1197                 name = "hevc_service";
1198         };
1199
1200         vpu_combo: vpu_combo@ff9a0000 {
1201                 compatible = "rockchip,vpu_combo";
1202                 reg = <0x0 0xff9a0000 0x0 0x800>;
1203                 rockchip,grf = <&grf>;
1204                 subcnt = <2>;
1205                 rockchip,sub = <&vpu>, <&hevc>;
1206                 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1207                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1208                 resets = <&reset RK3368_SRST_VIDEO_H>, <&reset RK3368_SRST_VIDEO_A>,
1209                         <&reset RK3368_SRST_VIDEO>;
1210                 reset-names = "video_h", "video_a", "video";
1211                 mode_bit = <12>;
1212                 mode_ctrl = <0x418>;
1213                 name = "vpu_combo";
1214                 status = "okay";
1215         };
1216
1217         iep: iep@ff900000 {
1218                 compatible = "rockchip,iep";
1219                 iommu_enabled = <1>;
1220                 reg = <0x0 0xff900000 0x0 0x800>;
1221                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1222                 clocks = <&clk_gates16 2>, <&clk_gates16 3>;
1223                 clock-names = "aclk_iep", "hclk_iep";
1224                 version = <2>;
1225                 status = "okay";
1226         };
1227
1228         gmac: eth@ff290000 {
1229                 compatible = "rockchip,rk3368-gmac";
1230                 reg = <0x0 0xff290000 0x0 0x10000>;
1231                 rockchip,grf = <&grf>;
1232                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1233                 interrupt-names = "macirq";
1234
1235                 clocks = <&clk_mac>, <&clk_gates7 4>,
1236                          <&clk_gates7 5>, <&clk_gates7 6>,
1237                          <&clk_gates7 7>, <&clk_gates20 13>,
1238                          <&clk_gates20 14>;
1239                 clock-names = "clk_mac", "mac_clk_rx",
1240                               "mac_clk_tx", "clk_mac_ref",
1241                               "clk_mac_refout", "aclk_mac",
1242                               "pclk_mac";
1243
1244                 phy-mode = "rgmii";
1245                 pinctrl-names = "default";
1246                 pinctrl-0 = <&rgmii_pins>;
1247                 status = "disabled";
1248         };
1249
1250         gpu {
1251                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1252                 reg = <0x0 0xffa30000 0x0 0x10000>;
1253                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1254                 interrupt-names = "GPU";
1255         };
1256
1257         iep_mmu {
1258                 dbgname = "iep";
1259                 compatible = "rockchip,iep_mmu";
1260                 reg = <0x0 0xff900800 0x0 0x100>;
1261                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1262                 interrupt-names = "iep_mmu";
1263         };
1264
1265         vip_mmu {
1266                 dbgname = "vip";
1267                 compatible = "rockchip,vip_mmu";
1268                 reg = <0x0 0xff950800 0x0 0x100>;
1269                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1270                 interrupt-names = "vip_mmu";
1271         };
1272
1273         vop_mmu {
1274                 dbgname = "vop";
1275                 compatible = "rockchip,vopb_mmu";
1276                 reg = <0x0 0xff930300 0x0 0x100>;
1277                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1278                 interrupt-names = "vop_mmu";
1279         };
1280
1281         isp_mmu {
1282                 dbgname = "isp_mmu";
1283                 compatible = "rockchip,isp_mmu";
1284                 reg = <0x0 0xff914000 0x0 0x100>,
1285                 <0x0 0xff915000 0x0 0x100>;
1286                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1287                 interrupt-names = "isp_mmu";
1288         };
1289
1290         hdcp_mmu {
1291                 dbgname = "hdcp_mmu";
1292                 compatible = "rockchip,hdcp_mmu";
1293                 reg = <0x0 0xff940000 0x0 0x100>;
1294                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1295                 interrupt-names = "hdcp_mmu";
1296         };
1297
1298         hevc_mmu {
1299                 dbgname = "hevc";
1300                 compatible = "rockchip,hevc_mmu";
1301                 reg = <0x0 0xff9a0440 0x0 0x40>,                      /*need to fix*/
1302                           <0x0 0xff9a0480 0x0 0x40>;
1303                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;        /*need to fix*/
1304                 interrupt-names = "hevc_mmu";
1305         };
1306
1307         vpu_mmu {
1308                 dbgname = "vpu";
1309                 compatible = "rockchip,vpu_mmu";
1310                 reg = <0x0 0xff9a0800 0x0 0x100>;                    /*need to fix*/
1311                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,        /*need to fix*/
1312                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1313                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1314         };
1315
1316         rockchip_suspend: rockchip_suspend {
1317                 rockchip,ctrbits = <
1318                         (0
1319                         | RKPM_SLP_ARMOFF
1320                         | RKPM_SLP_PMU_PLLS_PWRDN
1321                         /*| RKPM_SLP_PMU_PMUALIVE_32K
1322                         | RKPM_SLP_SFT_PLLS_DEEP
1323                         | RKPM_SLP_PMU_DIS_OSC */
1324                         | RKPM_SLP_SFT_PD_NBSCUS
1325                         )
1326                         >;
1327         };
1328
1329         isp: isp@ff910000{
1330                 compatible = "rockchip,isp";
1331                 reg = <0x0 0xff910000 0x0 0x10000>;
1332                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1333                 clocks = <&clk_gates16 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>, <&pd_isp>, <&clk_gates16 9>;
1334                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx", "pd_isp", "clk_vio0_noc";
1335                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1336                 pinctrl-0 = <&cif_clkout>;
1337                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1338                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1339                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1340                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1341                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
1342                 pinctrl-6 = <&cif_clkout>;
1343                 pinctrl-7 = <&cif_clkout &isp_prelight>;
1344                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
1345                 pinctrl-9 = <&isp_flash_trigger>;
1346                 rockchip,isp,mipiphy = <2>;
1347                 rockchip,isp,cifphy = <1>;
1348                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1349                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1350                 rockchip,grf = <&grf>;
1351                 rockchip,cru = <&cru>;
1352                 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1353                 rockchip,isp,iommu_enable = <1>;
1354                 status = "okay";
1355         };
1356
1357         cif: cif@ff950000 {
1358                 compatible = "rockchip,cif";
1359                 reg = <0x0 0xff950000 0x0 0x10000>;
1360                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1361                 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1362                 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1363                 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1364                 pinctrl-names = "cif_pin_all";
1365                 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1366                 rockchip,grf = <&grf>;
1367                 rockchip,cru = <&cru>;
1368                 status = "okay";
1369         };
1370
1371 /*
1372         thermal-zones {
1373                 #include "rk3368-thermal.dtsi"
1374         };
1375 */
1376
1377         tsadc: tsadc@ff280000 {
1378                 compatible = "rockchip,rk3368-tsadc";
1379                 reg = <0x0 0xff280000 0x0 0x100>;
1380                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1381                 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1382                 rockchip,grf = <&grf>;
1383                 rockchip,cru = <&cru>;
1384                 rockchip,pmu = <&pmu>;
1385                 clock-names = "tsadc", "apb_pclk";
1386                 clock-frequency = <32000>;
1387                 resets = <&reset RK3368_SRST_TSADC_P>;
1388                 reset-names = "tsadc-apb";
1389                 //pinctrl-names = "default";
1390                 //pinctrl-0 = <&tsadc_int>;
1391                 #thermal-sensor-cells = <1>;
1392                 hw-shut-temp = <120000>;
1393                 status = "disabled";
1394         };
1395
1396         tsp: tsp@FF8B0000 {
1397                 compatible = "rockchip,rk3368-tsp";
1398                 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1399                 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1400                 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1401                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1402                 interrupt-names = "irq_tsp";
1403                 // pinctrl-names = "default";
1404                 // pinctrl-0 = <&isp_hsadc>;
1405                 status = "okay";
1406         };
1407
1408         crypto: crypto@FF8A0000{
1409                 compatible = "rockchip,rk3368-crypto";
1410                 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1411                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1412                 interrupt-names = "irq_crypto";
1413                         clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1414                 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1415                 status = "okay";
1416         };
1417
1418         dwc_control_usb: dwc-control-usb {
1419                 compatible = "rockchip,rk3368-dwc-control-usb";
1420                 rockchip,grf = <&grf>;
1421                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1422                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1423                 interrupt-names = "otg_id", "otg_bvalid",
1424                                   "otg_linestate", "host0_linestate";
1425                 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1426                 clock-names = "hclk_usb_peri", "usbphy_480m";
1427                 //resets = <&reset RK3128_RST_USBPOR>;
1428                 //reset-names = "usbphy_por";
1429                 usb_bc{
1430                         compatible = "inno,phy";
1431                         regbase = &dwc_control_usb;
1432                         rk_usb,bvalid     = <0x4bc 23 1>;
1433                         rk_usb,iddig      = <0x4bc 26 1>;
1434                         rk_usb,vdmsrcen   = <0x718 12 1>;
1435                         rk_usb,vdpsrcen   = <0x718 11 1>;
1436                         rk_usb,rdmpden    = <0x718 10 1>;
1437                         rk_usb,idpsrcen   = <0x718  9 1>;
1438                         rk_usb,idmsinken  = <0x718  8 1>;
1439                         rk_usb,idpsinken  = <0x718  7 1>;
1440                         rk_usb,dpattach   = <0x4b8 31 1>;
1441                         rk_usb,cpdet      = <0x4b8 30 1>;
1442                         rk_usb,dcpattach  = <0x4b8 29 1>;
1443                 };
1444         };
1445
1446         usbphy: phy {
1447                 compatible = "rockchip,rk3368-usb-phy";
1448                 rockchip,grf = <&grf>;
1449                 #address-cells = <1>;
1450                 #size-cells = <0>;
1451
1452                 usbphy0: usb-phy0 {
1453                         #phy-cells = <0>;
1454                         reg = <0x700>;
1455                 };
1456
1457                 usbphy1: usb-phy1 {
1458                         #phy-cells = <0>;
1459                         reg = <0x728>;
1460                 };
1461         };
1462
1463         usb0: usb@ff580000 {
1464                 compatible = "rockchip,rk3368_usb20_otg";
1465                 reg = <0x0 0xff580000 0x0 0x40000>;
1466                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1467                 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1468                 clock-names = "clk_usbphy0", "hclk_otg";
1469                 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1470                                 <&reset RK3368_SRST_USBOTGC0>;
1471                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1472                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1473                 rockchip,usb-mode = <0>;
1474         };
1475
1476         usb_ehci: usb@ff500000 {
1477                 compatible = "generic-ehci";
1478                 reg = <0x0 0xff500000 0x0 0x20000>;
1479                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1480                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1481                 clock-names = "clk_usbphy0", "hclk_ehci";
1482                 phys = <&usbphy1>;
1483                 phy-names = "usb";
1484                 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1485                 //              <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1486                 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1487         };
1488
1489         usb_ohci: usb@ff520000 {
1490                 compatible = "generic-ohci";
1491                 reg = <0x0 0xff520000 0x0 0x20000>;
1492                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1493                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1494                 clock-names =  "clk_usbphy0", "hclk_ohci";
1495         };
1496
1497         usb_ehci1: usb@ff5c0000 {
1498                 compatible = "rockchip,rk3288_rk_ehci1_host";
1499                 reg = <0x0 0xff5c0000 0x0 0x40000>;
1500                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1501 /*
1502                 clocks = <&ehci1phy_480m>, <&clk_gates7 8>,
1503                          <&ehci1phy_12m>, <&usbphy_480m>,
1504                          <&otgphy1_480m>, <&otgphy2_480m>;
1505                 clock-names = "ehci1phy_480m", "hclk_ehci1",
1506                               "ehci1phy_12m", "usbphy_480m",
1507                               "ehci1_usbphy1", "ehci1_usbphy2";
1508                 resets = <&reset RK3368_SRST_EHCI1>, <&reset RK3368_SRST_EHCI1_AUX>,
1509                                 <&reset RK3368_SRST_EHCI1PHY>;
1510                 reset-names = "ehci1_ahb", "ehci1_aux", "ehci1_phy";
1511 */
1512                 status = "disabled";
1513         };
1514
1515         pinctrl: pinctrl {
1516                 compatible = "rockchip,rk3368-pinctrl";
1517                 rockchip,grf = <&grf>;
1518                 rockchip,pmugrf = <&pmugrf>;
1519                 #address-cells = <2>;
1520                 #size-cells = <2>;
1521                 ranges;
1522
1523                 gpio0: gpio0@ff750000 {
1524                         compatible = "rockchip,gpio-bank";
1525                         reg =   <0x0 0xff750000 0x0 0x100>;
1526                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1527                         clocks = <&clk_gates23 4>;
1528
1529                         gpio-controller;
1530                         #gpio-cells = <2>;
1531
1532                         interrupt-controller;
1533                         #interrupt-cells = <2>;
1534                 };
1535
1536                 gpio1: gpio1@ff780000 {
1537                         compatible = "rockchip,gpio-bank";
1538                         reg = <0x0 0xff780000 0x0 0x100>;
1539                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1540                         clocks = <&clk_gates22 1>;
1541
1542                         gpio-controller;
1543                         #gpio-cells = <2>;
1544
1545                         interrupt-controller;
1546                         #interrupt-cells = <2>;
1547                 };
1548
1549                 gpio2: gpio2@ff790000 {
1550                         compatible = "rockchip,gpio-bank";
1551                         reg = <0x0 0xff790000 0x0 0x100>;
1552                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1553                         clocks = <&clk_gates22 2>;
1554
1555                         gpio-controller;
1556                         #gpio-cells = <2>;
1557
1558                         interrupt-controller;
1559                         #interrupt-cells = <2>;
1560                 };
1561
1562                 gpio3: gpio3@ff7a0000 {
1563                         compatible = "rockchip,gpio-bank";
1564                         reg = <0x0 0xff7a0000 0x0 0x100>;
1565                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1566                         clocks = <&clk_gates22 3>;
1567
1568                         gpio-controller;
1569                         #gpio-cells = <2>;
1570
1571                         interrupt-controller;
1572                         #interrupt-cells = <2>;
1573                 };
1574
1575                 pcfg_pull_up: pcfg-pull-up {
1576                         bias-pull-up;
1577                 };
1578
1579                 pcfg_pull_down: pcfg-pull-down {
1580                         bias-pull-down;
1581                 };
1582
1583                 pcfg_pull_none: pcfg-pull-none {
1584                         bias-disable;
1585                 };
1586
1587                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1588                         drive-strength = <8>;
1589                 };
1590
1591                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1592                         drive-strength = <12>;
1593                 };
1594
1595                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1596                         bias-pull-up;
1597                         drive-strength = <8>;
1598                 };
1599
1600                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1601                         drive-strength = <4>;
1602                 };
1603
1604                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1605                         bias-pull-up;
1606                         drive-strength = <4>;
1607                 };
1608
1609                 pcfg_output_high: pcfg-output-high {
1610                         output-high;
1611                 };
1612
1613                 pcfg_output_low: pcfg-output-low {
1614                         output-low;
1615                 };
1616
1617                 pcfg_input_high: pcfg-input-high {
1618                         bias-pull-up;
1619                         input-enable;
1620                 };
1621
1622                 i2c0 {
1623                         i2c0_xfer: i2c0-xfer {
1624                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1625                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1626                         };
1627                         i2c0_gpio: i2c0-gpio {
1628                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1629                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1630                         };
1631                         i2c0_sleep: i2c0-sleep {
1632                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_input_high>,
1633                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_input_high>;
1634                         };
1635                 };
1636
1637                 i2c1 {
1638                         i2c1_xfer: i2c1-xfer {
1639                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1640                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1641                         };
1642                         i2c1_gpio: i2c1-gpio {
1643                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1644                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1645                         };
1646                         i2c1_sleep: i2c1-sleep {
1647                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_input_high>,
1648                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_input_high>;
1649                         };
1650                 };
1651
1652                 i2c2 {
1653                         i2c2_xfer: i2c2-xfer {
1654                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1655                                                 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1656                         };
1657                         i2c2_gpio: i2c2-gpio {
1658                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1659                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1660                         };
1661                         i2c2_sleep: i2c2-sleep {
1662                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_input_high>,
1663                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_input_high>;
1664                         };
1665                 };
1666
1667                 i2c3 {
1668                         i2c3_xfer: i2c3-xfer {
1669                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1670                                                 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1671                         };
1672                         i2c3_gpio: i2c3-gpio {
1673                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1674                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1675                         };
1676                         i2c3_sleep: i2c3-sleep {
1677                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_input_high>,
1678                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_input_high>;
1679                         };
1680                 };
1681
1682                 i2c4 {
1683                         i2c4_xfer: i2c4-xfer {
1684                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1685                                                 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1686                         };
1687                         i2c4_gpio: i2c4-gpio {
1688                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1689                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1690                         };
1691                         i2c4_sleep: i2c4-sleep {
1692                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_input_high>,
1693                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_input_high>;
1694                         };
1695                 };
1696
1697                 i2c5 {
1698                         i2c5_xfer: i2c5-xfer {
1699                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1700                                                 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1701                         };
1702                         i2c5_gpio: i2c5-gpio {
1703                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1704                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1705                         };
1706                         i2c5_sleep: i2c5-sleep {
1707                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_input_high>,
1708                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_input_high>;
1709                         };
1710                 };
1711
1712                 uart0 {
1713                         uart0_xfer: uart0-xfer {
1714                                 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1715                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1716                         };
1717
1718                         uart0_cts: uart0-cts {
1719                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1720                         };
1721
1722                         uart0_rts: uart0-rts {
1723                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1724                         };
1725
1726                         uart0_rts_gpio: uart0-rts-gpio {
1727                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1728                         };
1729                 };
1730
1731                 uart1 {
1732                         uart1_xfer: uart1-xfer {
1733                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1734                                                 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1735                         };
1736
1737                         uart1_cts: uart1-cts {
1738                                 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1739                         };
1740
1741                         uart1_rts: uart1-rts {
1742                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1743                         };
1744                 };
1745
1746                 uart2 {
1747                         uart2_xfer: uart2-xfer {
1748                                 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1749                                                 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1750                         };
1751                 };
1752
1753                 uart3 {
1754                         uart3_xfer: uart3-xfer {
1755                                 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1756                                                 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1757                         };
1758
1759                         uart3_cts: uart3-cts {
1760                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1761                         };
1762
1763                         uart3_rts: uart3-rts {
1764                                 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1765                         };
1766                 };
1767
1768                 uart4 {
1769                         uart4_xfer: uart4-xfer {
1770                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1771                                                 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1772                         };
1773
1774                         uart4_cts: uart4-cts {
1775                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1776                         };
1777
1778                         uart4_rts: uart4-rts {
1779                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1780                         };
1781                 };
1782
1783                 spi0 {
1784                         spi0_clk: spi0-clk {
1785                                 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1786                         };
1787                         spi0_cs0: spi0-cs0 {
1788                                 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1789                         };
1790                         spi0_tx: spi0-tx {
1791                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1792                         };
1793                         spi0_rx: spi0-rx {
1794                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1795                         };
1796                         spi0_cs1: spi0-cs1 {
1797                                 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1798                         };
1799                 };
1800
1801                 spi1 {
1802                         spi1_clk: spi1-clk {
1803                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1804                         };
1805                         spi1_cs0: spi1-cs0 {
1806                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1807                         };
1808                         spi1_rx: spi1-rx {
1809                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1810                         };
1811                         spi1_tx: spi1-tx {
1812                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1813                         };
1814                         spi1_cs1: spi1-cs1 {
1815                                 rockchip,pins = <3 GPIO_D4 RK_FUNC_2 &pcfg_pull_up>;
1816                         };
1817                 };
1818
1819                 spi2 {
1820                         spi2_clk: spi2-clk {
1821                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1822                         };
1823                         spi2_cs0: spi2-cs0 {
1824                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1825                         };
1826                         spi2_rx: spi2-rx {
1827                                 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1828                         };
1829                         spi2_tx: spi2-tx {
1830                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1831                         };
1832                 };
1833
1834                 i2s {
1835                         i2s_mclk: i2s-mclk {
1836                                 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1837                         };
1838
1839                         i2s_sclk:i2s-sclk {
1840                                 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1841                         };
1842
1843                         i2s_lrckrx:i2s-lrckrx {
1844                                 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1845                         };
1846
1847                         i2s_lrcktx:i2s-lrcktx {
1848                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1849                         };
1850
1851                         i2s_sdi:i2s-sdi {
1852                                 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1853                         };
1854
1855                         i2s_sdo0:i2s-sdo0 {
1856                                 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1857                         };
1858
1859                         i2s_sdo1:i2s-sdo1 {
1860                                 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1861                         };
1862
1863                         i2s_sdo2:i2s-sdo2 {
1864                                 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1865                         };
1866
1867                         i2s_sdo3:i2s-sdo3 {
1868                                 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1869                         };
1870
1871                         i2s_gpio: i2s-gpio {
1872                                 rockchip,pins = <2 GPIO_C4  RK_FUNC_GPIO &pcfg_pull_none>,
1873                                                 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1874                                                 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1875                                                 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1876                                                 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1877                                                 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1878                                                 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1879                                                 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1880                                                 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1881                         };
1882                 };
1883
1884                 spdif {
1885                         spdif_tx: spdif-tx {
1886                                 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1887                         };
1888                 };
1889
1890                 sdmmc {
1891                         sdmmc_clk: sdmmc-clk {
1892                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1893                         };
1894
1895                         sdmmc_cmd: sdmmc-cmd {
1896                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1897                         };
1898
1899                         sdmmc_dectn: sdmmc-dectn {
1900                                 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1901                         };
1902
1903                         sdmmc_bus1: sdmmc-bus1 {
1904                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1905                         };
1906
1907                         sdmmc_bus4: sdmmc-bus4 {
1908                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1909                                                 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1910                                                 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1911                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1912                         };
1913
1914                         sdmmc_gpio: sdmmc-gpio {
1915                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1916                                                 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1917                                                 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1918                                                 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1919                                                 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1920                                                 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1921                                                 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1922                         };
1923                 };
1924
1925                 sdio0 {
1926                         sdio0_bus1: sdio0-bus1 {
1927                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1928                         };
1929
1930                         sdio0_bus4: sdio0-bus4 {
1931                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1932                                                 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1933                                                 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1934                                                 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1935                         };
1936
1937                         sdio0_cmd: sdio0-cmd {
1938                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1939                         };
1940
1941                         sdio0_clk: sdio0-clk {
1942                                 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1943                         };
1944
1945                         sdio0_dectn: sdio0-dectn {
1946                                 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1947                         };
1948
1949                         sdio0_wrprt: sdio0-wrprt {
1950                                 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1951                         };
1952
1953                         sdio0_pwren: sdio0-pwren {
1954                                 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1955                         };
1956
1957                         sdio0_bkpwr: sdio0-bkpwr {
1958                                 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1959                         };
1960
1961                         sdio0_int: sdio0-int {
1962                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1963                         };
1964
1965                         sdio0_gpio: sdio0-gpio {
1966                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1967                                                 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1968                                                 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1969                                                 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1970                                                 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1971                                                 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1972                                                 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1973                                                 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1974                                                 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1975                                                 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1976                                                 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1977                         };
1978                 };
1979
1980                 emmc {
1981                         emmc_clk: emmc-clk {
1982                                 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1983                         };
1984
1985                         emmc_cmd: emmc-cmd {
1986                                 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1987                         };
1988
1989                         emmc_pwren: emmc-pwren {
1990                                 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1991                         };
1992
1993                         emmc_rstnout: emmc_rstnout {
1994                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1995                         };
1996
1997                         emmc_bus1: emmc-bus1 {
1998                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1999                         };
2000
2001                         emmc_bus4: emmc-bus4 {
2002                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
2003                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
2004                                                 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
2005                                                 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
2006                         };
2007                 };
2008
2009                 pwm0 {
2010                         pwm0_pin: pwm0-pin {
2011                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
2012                         };
2013
2014                         vop_pwm_pin:vop-pwm {
2015                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
2016                         };
2017                 };
2018
2019                 pwm1 {
2020                         pwm1_pin: pwm1-pin {
2021                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
2022                         };
2023                 };
2024
2025                 pwm3 {
2026                         pwm3_pin: pwm3-pin {
2027                                 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
2028                         };
2029                 };
2030
2031                 lcdc {
2032                         lcdc_lcdc: lcdc-lcdc {
2033                                 rockchip,pins =
2034                                                 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
2035                                                 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
2036                                                 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
2037                                                 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
2038                                                 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
2039                                                 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
2040                                                 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
2041                                                 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
2042                                                 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
2043                                                 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
2044                                                 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
2045                                                 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
2046                                                 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
2047                                                 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
2048                                                 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
2049                                                 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
2050                                                 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
2051                                                 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
2052                         };
2053
2054                         lcdc_gpio: lcdc-gpio {
2055                                 rockchip,pins =
2056                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
2057                                                 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
2058                                                 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
2059                                                 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
2060                                                 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
2061                                                 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
2062                                                 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
2063                                                 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
2064                                                 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
2065                                                 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
2066                                                 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
2067                                                 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
2068                                                 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
2069                                                 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
2070                                                 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
2071                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
2072                                                 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
2073                                                 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
2074                         };
2075                 };
2076
2077                 isp {
2078                         cif_clkout: cif-clkout {
2079                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2080                         };
2081
2082                         isp_dvp_d2d9: isp-dvp-d2d9 {
2083                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2084                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2085                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2086                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2087                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2088                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2089                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2090                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2091                                                 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
2092                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
2093                                                 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
2094                                                 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2095                         };
2096
2097                         isp_dvp_d0d1: isp-dvp-d0d1 {
2098                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2099                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
2100                         };
2101
2102                         isp_dvp_d10d11:isp_d10d11       {
2103                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2104                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2105                         };
2106
2107                         isp_dvp_d0d7: isp-dvp-d0d7 {
2108                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2109                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
2110                                                 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2111                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2112                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2113                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2114                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2115                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
2116                         };
2117
2118                         isp_dvp_d4d11: isp-dvp-d4d11 {
2119                                 rockchip,pins =
2120                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2121                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2122                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2123                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2124                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2125                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2126                                                 <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2127                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2128                         };
2129
2130                         isp_shutter: isp-shutter {
2131                                 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2132                                                 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2133                         };
2134
2135                         isp_flash_trigger: isp-flash-trigger {
2136                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2137                         };
2138
2139                         isp_prelight: isp-prelight {
2140                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2141                         };
2142
2143                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2144                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
2145                         };
2146                 };
2147
2148                 gps {
2149                         gps_mag: gps-mag {
2150                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
2151                         };
2152
2153                         gps_sig: gps-sig {
2154                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
2155
2156                         };
2157
2158                         gps_rfclk: gps-rfclk {
2159                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
2160                         };
2161                 };
2162
2163                 gmac {
2164                         rgmii_pins: rgmii-pins {
2165                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2166                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2167                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2168                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2169                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2170                                                 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
2171                                                 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
2172                                                 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
2173                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2174                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2175                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2176                                                 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
2177                                                 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
2178                                                 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
2179                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
2180                         };
2181
2182                         rmii_pins: rmii-pins {
2183                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2184                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2185                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2186                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2187                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2188                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2189                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2190                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2191                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
2192                                                 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
2193                         };
2194                 };
2195
2196                 tsadc_pin {
2197                         tsadc_int: tsadc-int {
2198                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
2199                         };
2200                         tsadc_gpio: tsadc-gpio {
2201                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
2202                         };
2203                 };
2204
2205                 hdmi_pin {
2206                         hdmi_cec: hdmi-cec {
2207                                 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
2208                         };
2209                 };
2210
2211                 hdmi_i2c {
2212                         hdmii2c_xfer: hdmii2c-xfer {
2213                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
2214                                                 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
2215                         };
2216                 };
2217
2218                 cpu_jtag {
2219                         cpu_jtag: cpu-jtag {
2220                                 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_up>,
2221                                                 <2 GPIO_B0 RK_FUNC_2 &pcfg_pull_up>;
2222                         };
2223                 };
2224
2225                 mcu_jtag {
2226                         mcu_jtag: mcu-jtag {
2227                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>,
2228                                                 <2 GPIO_B1 RK_FUNC_2 &pcfg_pull_up>;
2229                         };
2230                 };
2231         };
2232
2233         reboot {
2234                 compatible = "rockchip,rk3368-reboot";
2235                 rockchip,cru = <&cru>;
2236                 rockchip,pmugrf = <&pmugrf>;
2237         };
2238 };