arch/arm64/boot/dts/rk3368.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-rk3368.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/sensor-dev.h>
   6 #include <dt-bindings/clock/rk_system_status.h>
   7
   8 #include "rk3368-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk3368";
  12
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &uart_bt;
  20                 serial1 = &uart_bb;
  21                 serial2 = &uart_dbg;
  22                 serial3 = &uart_gps;
  23                 serial4 = &uart_exp;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &spi0;
  31                 spi1 = &spi1;
  32                 spi2 = &spi2;
  33                 lcdc = &lcdc;
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 idle-states {
  41                         entry-method = "arm,psci";
  42                         CPU_SLEEP_0: cpu-sleep-0 {
  43                                 compatible = "arm,idle-state";
  44                                 arm,psci-suspend-param = <0x1010000>;
  45                                 entry-latency-us = <0x3fffffff>;
  46                                 exit-latency-us = <0x40000000>;
  47                                 min-residency-us = <0xffffffff>;
  48                         };
  49                 };
  50
  51                 little0: cpu@0 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53", "arm,armv8";
  54                         reg = <0x0 0x0>;
  55                         enable-method = "psci";
  56                         cpu-idle-states = <&CPU_SLEEP_0>;
  57                 };
  58                 little1: cpu@1 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53", "arm,armv8";
  61                         reg = <0x0 0x1>;
  62                         enable-method = "psci";
  63                         cpu-idle-states = <&CPU_SLEEP_0>;
  64                 };
  65                 little2: cpu@2 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53", "arm,armv8";
  68                         reg = <0x0 0x2>;
  69                         enable-method = "psci";
  70                         cpu-idle-states = <&CPU_SLEEP_0>;
  71                 };
  72                 little3: cpu@3 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53", "arm,armv8";
  75                         reg = <0x0 0x3>;
  76                         enable-method = "psci";
  77                         cpu-idle-states = <&CPU_SLEEP_0>;
  78                 };
  79                 big0: cpu@100 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53", "arm,armv8";
  82                         reg = <0x0 0x100>;
  83                         enable-method = "psci";
  84                         cpu-idle-states = <&CPU_SLEEP_0>;
  85                 };
  86                 big1: cpu@101 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53", "arm,armv8";
  89                         reg = <0x0 0x101>;
  90                         enable-method = "psci";
  91                         cpu-idle-states = <&CPU_SLEEP_0>;
  92                 };
  93                 big2: cpu@102 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53", "arm,armv8";
  96                         reg = <0x0 0x102>;
  97                         enable-method = "psci";
  98                         cpu-idle-states = <&CPU_SLEEP_0>;
  99                 };
 100                 big3: cpu@103 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a53", "arm,armv8";
 103                         reg = <0x0 0x103>;
 104                         enable-method = "psci";
 105                         cpu-idle-states = <&CPU_SLEEP_0>;
 106                 };
 107
 108                 cpu-map {
 109                         cluster0 {
 110                                 core0 {
 111                                         cpu = <&big0>;
 112                                 };
 113                                 core1 {
 114                                         cpu = <&big1>;
 115                                 };
 116                                 core2 {
 117                                         cpu = <&big2>;
 118                                 };
 119                                 core3 {
 120                                         cpu = <&big3>;
 121                                 };
 122                         };
 123                         cluster1 {
 124                                 core0 {
 125                                         cpu = <&little0>;
 126                                 };
 127                                 core1 {
 128                                         cpu = <&little1>;
 129                                 };
 130                                 core2 {
 131                                         cpu = <&little2>;
 132                                 };
 133                                 core3 {
 134                                         cpu = <&little3>;
 135                                 };
 136                         };
 137                 };
 138         };
 139
 140         psci {
 141                 compatible = "arm,psci-0.2";
 142                 method = "smc";
 143         };
 144
 145         gic: interrupt-controller@ffb70000 {
 146                 compatible = "arm,cortex-a15-gic";
 147                 #interrupt-cells = <3>;
 148                 #address-cells = <0>;
 149                 interrupt-controller;
 150                 reg = <0x0 0xffb71000 0 0x1000>,
 151                       <0x0 0xffb72000 0 0x1000>;
 152         };
 153
 154         ddrpctl: syscon@ff610000 {
 155                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 156                 reg = <0x0 0xff610000 0x0 0x400>;
 157         };
 158
 159         pmu: syscon@ff730000 {
 160                 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
 161                 reg = <0x0 0xff730000 0x0 0x1000>;
 162         };
 163
 164         pmugrf: syscon@ff738000 {
 165                 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
 166                 reg = <0x0 0xff738000 0x0 0x1000>;
 167         };
 168
 169         sgrf: syscon@ff740000 {
 170                 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
 171                 reg = <0x0 0xff740000 0x0 0x1000>;
 172
 173         };
 174
 175         cru: syscon@ff760000 {
 176                 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
 177                 reg = <0x0 0xff760000 0x0 0x1000>;
 178         };
 179
 180         grf: syscon@ff770000 {
 181                 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
 182                 reg = <0x0 0xff770000 0x0 0x1000>;
 183         };
 184
 185         msch: syscon@ffac0000 {
 186                 compatible = "rockchip,rk3368-msch", "rockchip,msch", "syscon";
 187                 reg = <0x0 0xffac0000 0x0 0x3000>;
 188         };
 189
 190         arm-pmu {
 191                 compatible = "arm,armv8-pmuv3";
 192                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 200         };
 201
 202         cpu_axi_bus: cpu_axi_bus {
 203                 compatible = "rockchip,cpu_axi_bus";
 204                 #address-cells = <2>;
 205                 #size-cells = <2>;
 206                 ranges;
 207
 208                 qos {
 209                         #address-cells = <2>;
 210                         #size-cells = <2>;
 211                         ranges;
 212
 213                         dmac {
 214                                 reg = <0x0 0xffa80000 0x0 0x20>;
 215                         };
 216                         crypto {
 217                                 reg = <0x0 0xffa80080 0x0 0x20>;
 218                         };
 219                         tsp {
 220                                 reg = <0x0 0xffa80280 0x0 0x20>;
 221                         };
 222                         bus_cpup {
 223                                 reg = <0x0 0xffa90000 0x0 0x20>;
 224                         };
 225                         cci_r {
 226                                 reg = <0x0 0xffaa0000 0x0 0x20>;
 227                         };
 228                         cci_w {
 229                                 reg = <0x0 0xffaa0080 0x0 0x20>;
 230                         };
 231                         peri {
 232                                 reg = <0x0 0xffab0000 0x0 0x20>;
 233                                 rockchip,priority = <2 2>;
 234                         };
 235                         iep {
 236                                 reg = <0x0 0xffad0000 0x0 0x20>;
 237                         };
 238                         isp_r0 {
 239                                 reg = <0x0 0xffad0080 0x0 0x20>;
 240                         };
 241                         isp_r1 {
 242                                 reg = <0x0 0xffad0100 0x0 0x20>;
 243                         };
 244                         isp_w0 {
 245                                 reg = <0x0 0xffad0180 0x0 0x20>;
 246                                 rockchip,priority = <2 2>;
 247                         };
 248                         isp_w1 {
 249                                 reg = <0x0 0xffad0200 0x0 0x20>;
 250                                 rockchip,priority = <2 2>;
 251                         };
 252                         vip {
 253                                 reg = <0x0 0xffad0280 0x0 0x20>;
 254                         };
 255                         vop {
 256                                 reg = <0x0 0xffad0300 0x0 0x20>;
 257                                 rockchip,priority = <2 2>;
 258                         };
 259                         rga_r {
 260                                 reg = <0x0 0xffad0380 0x0 0x20>;
 261                         };
 262                         rga_w {
 263                                 reg = <0x0 0xffad0400 0x0 0x20>;
 264                         };
 265                         hevc_r {
 266                                 reg = <0x0 0xffae0000 0x0 0x20>;
 267                         };
 268                         vpu_r {
 269                                 reg = <0x0 0xffae0100 0x0 0x20>;
 270                         };
 271                         vpu_w {
 272                                 reg = <0x0 0xffae0180 0x0 0x20>;
 273                         };
 274                         gpu {
 275                                 reg = <0x0 0xffaf0000 0x0 0x20>;
 276                         };
 277                 };
 278
 279                 msch {
 280                         #address-cells = <2>;
 281                         #size-cells = <2>;
 282                         ranges;
 283
 284                         msch {
 285                                 reg = <0x0 0xffac0000 0x0 0x3c>;
 286                                 rockchip,read-latency = <0x34>;
 287                         };
 288                 };
 289         };
 290
 291         timer {
 292                 compatible = "arm,armv8-timer";
 293                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 294                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 295                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 296                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 297                 clock-frequency = <24000000>;
 298         };
 299
 300         timer@ff810000 {
 301                 compatible = "rockchip,timer";
 302                 reg = <0x0 0xff810000 0x0 0x20>;
 303                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 304                 rockchip,broadcast = <1>;
 305         };
 306
 307         timer@ff810020 {
 308                 compatible = "rockchip,timer";
 309                 reg = <0x0 0xff810020 0x0 0x20>;
 310                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 311                 rockchip,percpu = <0>;
 312         };
 313
 314         sram: sram@ff8c0000 {
 315                 compatible = "mmio-sram";
 316                 reg = <0x0 0xff8c0000 0x0 0xf000>; /* 60K (reserved 4K for mailbox)*/
 317                 map-exec;
 318         };
 319
 320         watchdog: wdt@ff800000 {
 321                 compatible = "rockchip,watch dog";
 322                 reg = <0x0 0xff800000 0x0 0x100>;
 323                 clocks = <&pclk_alive_pre>;
 324                 clock-names = "pclk_wdt";
 325                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 326                 rockchip,irq = <1>;
 327                 rockchip,timeout = <60>;
 328                 rockchip,atboot = <1>;
 329                 rockchip,debug = <0>;
 330                 status = "disabled";
 331         };
 332
 333         amba {
 334                 #address-cells = <2>;
 335                 #size-cells = <2>;
 336                 compatible = "arm,amba-bus";
 337                 interrupt-parent = <&gic>;
 338                 ranges;
 339
 340                 pdma0: pdma@ff600000 {
 341                         compatible = "arm,pl330", "arm,primecell";
 342                         reg = <0x0 0xff600000 0x0 0x4000>;
 343                         clocks = <&clk_gates12 11>;
 344                         clock-names = "apb_pclk";
 345                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 346                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 347                         #dma-cells = <1>;
 348
 349                 };
 350
 351                 pdma1: pdma@ff250000 {
 352                         compatible = "arm,pl330", "arm,primecell";
 353                         reg = <0x0 0xff250000 0x0 0x4000>;
 354                         clocks = <&clk_gates19 3>;
 355                         clock-names = "apb_pclk";
 356                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 357                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 358                         #dma-cells = <1>;
 359                 };
 360         };
 361
 362         reset: reset@ff760300{
 363                 compatible = "rockchip,reset";
 364                 reg = <0x0 0xff760300 0x0 0x38>;
 365                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 366                 #reset-cells = <1>;
 367         };
 368
 369         nandc0: nandc@ff400000 {
 370                 compatible = "rockchip,rk-nandc";
 371                 reg = <0x0 0xff400000 0x0 0x4000>;
 372                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 373                 nandc_id = <0>;
 374                 clocks = <&clk_nandc0>, <&clk_gates20 9>, <&clk_gates20 11>;
 375                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 376         };
 377
 378         nandc0reg: nandc0@ff400000 {
 379                 compatible = "rockchip,rk-nandc";
 380                 reg = <0x0 0xff400000 0x0 0x4000>;
 381         };
 382
 383         emmc: rksdmmc@ff0f0000 {
 384                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 385                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 386                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 387                 #address-cells = <1>;
 388                 #size-cells = <0>;
 389                 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
 390                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 391                 rockchip,grf = <&grf>;
 392                 num-slots = <1>;
 393                 fifo-depth = <0x100>;
 394                 bus-width = <8>;
 395         };
 396
 397         sdmmc: rksdmmc@ff0c0000 {
 398                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 399                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 400                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 401                 #address-cells = <1>;
 402                 #size-cells = <0>;
 403                 pinctrl-names = "default", "idle", "udbg";
 404                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 405                 pinctrl-1 = <&sdmmc_gpio>;
 406                 pinctrl-2 = <&uart2_xfer &cpu_jtag &mcu_jtag &sdmmc_dectn>;
 407                 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 408                 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
 409                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 410                 rockchip,grf = <&grf>;
 411                 num-slots = <1>;
 412                 fifo-depth = <0x100>;
 413                 bus-width = <4>;
 414         };
 415
 416         sdio: rksdmmc@ff0d0000 {
 417                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 418                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 419                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 420                 #address-cells = <1>;
 421                 #size-cells = <0>;
 422                 pinctrl-names = "default","idle";
 423                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
 424                 pinctrl-1 = <&sdio0_gpio>;
 425                 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
 426                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 427                 rockchip,grf = <&grf>;
 428                 num-slots = <1>;
 429                 fifo-depth = <0x100>;
 430                 bus-width = <4>;
 431         };
 432
 433         spi0: spi@ff110000 {
 434                 compatible = "rockchip,rockchip-spi";
 435                 reg = <0x0 0xff110000 0x0 0x1000>;
 436                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 437                 #address-cells = <1>;
 438                 #size-cells = <0>;
 439                 pinctrl-names = "default";
 440                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 441                 rockchip,spi-src-clk = <0>;
 442                 num-cs = <2>;
 443                 clocks =<&clk_spi0>, <&clk_gates19 4>;
 444                 clock-names = "spi", "pclk_spi0";
 445                 //dmas = <&pdma1 11>, <&pdma1 12>;
 446                 //#dma-cells = <2>;
 447                 //dma-names = "tx", "rx";
 448                 status = "disabled";
 449         };
 450
 451         spi1: spi@ff120000 {
 452                 compatible = "rockchip,rockchip-spi";
 453                 reg = <0x0 0xff120000 0x0 0x1000>;
 454                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 455                 #address-cells = <1>;
 456                 #size-cells = <0>;
 457                 pinctrl-names = "default";
 458                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0 &spi1_cs1>;
 459                 rockchip,spi-src-clk = <1>;
 460                 num-cs = <2>;
 461                 clocks = <&clk_spi1>, <&clk_gates19 5>;
 462                 clock-names = "spi", "pclk_spi1";
 463                 //dmas = <&pdma1 13>, <&pdma1 14>;
 464                 //#dma-cells = <2>;
 465                 //dma-names = "tx", "rx";
 466                 status = "disabled";
 467         };
 468
 469         spi2: spi@ff130000 {
 470                 compatible = "rockchip,rockchip-spi";
 471                 reg = <0x0 0xff130000 0x0 0x1000>;
 472                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 pinctrl-names = "default";
 476                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 477                 rockchip,spi-src-clk = <2>;
 478                 num-cs = <1>;
 479                 clocks = <&clk_spi2>, <&clk_gates19 6>;
 480                 clock-names = "spi", "pclk_spi2";
 481                 //dmas = <&pdma1 15>, <&pdma1 16>;
 482                 //#dma-cells = <2>;
 483                 //dma-names = "tx", "rx";
 484                 status = "disabled";
 485         };
 486
 487         uart_bt: serial@ff180000 {
 488                 compatible = "rockchip,serial";
 489                 reg = <0x0 0xff180000 0x0 0x100>;
 490                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 491                 clock-frequency = <24000000>;
 492                 clocks = <&clk_uart0>, <&clk_gates19 7>;
 493                 clock-names = "sclk_uart", "pclk_uart";
 494                 reg-shift = <2>;
 495                 reg-io-width = <4>;
 496                 //dmas = <&pdma1 1>, <&pdma1 2>;
 497                 //#dma-cells = <2>;
 498                 pinctrl-names = "default";
 499                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 500                 status = "disabled";
 501         };
 502
 503         uart_bb: serial@ff190000 {
 504                 compatible = "rockchip,serial";
 505                 reg = <0x0 0xff190000 0x0 0x100>;
 506                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 507                 clock-frequency = <24000000>;
 508                 clocks = <&clk_uart1>, <&clk_gates19 8>;
 509                 clock-names = "sclk_uart", "pclk_uart";
 510                 reg-shift = <2>;
 511                 reg-io-width = <4>;
 512                 //dmas = <&pdma1 3>, <&pdma1 4>;
 513                 //#dma-cells = <2>;
 514                 pinctrl-names = "default";
 515                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 516                 status = "disabled";
 517         };
 518
 519         uart_dbg: serial@ff690000 {
 520                 compatible = "rockchip,serial";
 521                 reg = <0x0 0xff690000 0x0 0x100>;
 522                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 523                 clock-frequency = <24000000>;
 524                 clocks = <&clk_uart2>, <&clk_gates13 5>;
 525                 clock-names = "sclk_uart", "pclk_uart";
 526                 reg-shift = <2>;
 527                 reg-io-width = <4>;
 528                 //dmas = <&pdma0 4>, <&pdma0 5>;
 529                 //#dma-cells = <2>;
 530                 //pinctrl-names = "default";
 531                 //pinctrl-0 = <&uart2_xfer>;
 532                 status = "disabled";
 533         };
 534
 535         uart_gps: serial@ff1b0000 {
 536                 compatible = "rockchip,serial";
 537                 reg = <0x0 0xff1b0000 0x0 0x100>;
 538                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 539                 clock-frequency = <24000000>;
 540                 clocks = <&clk_uart3>, <&clk_gates19 9>;
 541                 clock-names = "sclk_uart", "pclk_uart";
 542                 current-speed = <115200>;
 543                 reg-shift = <2>;
 544                 reg-io-width = <4>;
 545                 //dmas = <&pdma1 7>, <&pdma1 8>;
 546                 //#dma-cells = <2>;
 547                 pinctrl-names = "default";
 548                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 549                 status = "disabled";
 550         };
 551
 552         uart_exp: serial@ff1c0000 {
 553                 compatible = "rockchip,serial";
 554                 reg = <0x0 0xff1c0000 0x0 0x100>;
 555                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 556                 clock-frequency = <24000000>;
 557                 clocks = <&clk_uart4>, <&clk_gates19 10>;
 558                 clock-names = "sclk_uart", "pclk_uart";
 559                 reg-shift = <2>;
 560                 reg-io-width = <4>;
 561                 //dmas = <&pdma1 9>, <&pdma1 10>;
 562                 //#dma-cells = <2>;
 563                 pinctrl-names = "default";
 564                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 565                 status = "disabled";
 566         };
 567
 568         mbox: mbox@ff6b0000 {
 569                 compatible = "rockchip,rk3368-mailbox";
 570                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 571                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 572                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 573                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 574                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 575                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 576                 clocks = <&clk_gates12 1>;
 577                 clock-names = "pclk_mailbox";
 578                 #mbox-cells = <1>;
 579         };
 580
 581         mbox_scpi: mbox-scpi {
 582                 compatible = "rockchip,mbox-scpi";
 583                 mboxes = <&mbox 0 &mbox 1>;
 584         };
 585
 586         ddr {
 587                 compatible = "rockchip,rk3368-ddr";
 588                 status = "okay";
 589                 rockchip,ddrpctl = <&ddrpctl>;
 590                 rockchip,grf = <&grf>;
 591                 rockchip,msch = <&msch>;
 592         };
 593
 594         rockchip_clocks_init: clocks-init{
 595                 compatible = "rockchip,clocks-init";
 596                 rockchip,clocks-init-parent =
 597                         <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
 598                         <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
 599                         <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
 600                         <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
 601                 rockchip,clocks-init-rate =
 602                         <&clk_gpll 576000000>,          <&clk_core_b 792000000>,
 603                         <&clk_core_l 600000000>,        <&clk_cpll 400000000>,
 604                         /*<&clk_npll 500000000>,*/      <&aclk_bus 300000000>,
 605                         <&hclk_bus 150000000>,          <&pclk_bus 75000000>,
 606                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 607                         <&hclk_peri 150000000>,         <&pclk_peri 75000000>,
 608                         <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
 609                         <&clk_cs 300000000>,            <&clkin_trace 300000000>,
 610                         <&aclk_cci 600000000>,          <&clk_mac 125000000>,
 611                         <&aclk_vio0 400000000>,         <&hclk_vio 100000000>,
 612                         <&aclk_rga_pre 400000000>,      <&clk_rga 400000000>,
 613                         <&clk_isp 400000000>,           <&clk_edp 200000000>,
 614                         <&clk_gpu_core 400000000>,      <&aclk_gpu_mem 400000000>,
 615                         <&aclk_gpu_cfg 400000000>,      <&aclk_vepu 400000000>,
 616                         <&aclk_vdpu 400000000>,         <&clk_hevc_core 300000000>,
 617                         <&clk_hevc_cabac 300000000>;
 618 /*
 619                 rockchip,clocks-uboot-has-init =
 620                         <&aclk_vio0>;
 621 */
 622         };
 623
 624         rockchip_clocks_enable: clocks-enable {
 625                 compatible = "rockchip,clocks-enable";
 626                 clocks =
 627                         /*PLL*/
 628                         <&clk_apllb>,
 629                         <&clk_aplll>,
 630                         <&clk_dpll>,
 631                         <&clk_gpll>,
 632                         <&clk_cpll>,
 633
 634                         /*PD_CORE*/
 635                         <&clk_cs>,
 636                         <&clkin_trace>,
 637                         <&aclk_cci>,
 638
 639                         /*PD_BUS*/
 640                         <&aclk_bus>,
 641                         <&hclk_bus>,
 642                         <&pclk_bus>,
 643                         <&clk_gates12 12>,/*aclk_strc_sys*/
 644                         <&clk_gates12 6>,/*aclk_intmem1*/
 645                         <&clk_gates12 5>,/*aclk_intmem0*/
 646                         <&clk_gates12 4>,/*aclk_intmem*/
 647                         <&clk_gates13 9>,/*aclk_gic400*/
 648                         <&clk_gates12 9>,/*hclk_rom*/
 649
 650                         /*PD_ALIVE*/
 651                         <&clk_gates22 12>,/*pclk_timer0*/
 652                         <&clk_gates22 9>,/*pclk_alive_niu*/
 653                         <&clk_gates22 8>,/*pclk_grf*/
 654
 655                         /*PD_PMU*/
 656                         <&clk_gates23 5>,/*pclk_pmugrf*/
 657                         <&clk_gates23 3>,/*pclk_sgrf*/
 658                         <&clk_gates23 2>,/*pclk_pmu_noc*/
 659                         <&clk_gates23 1>,/*pclk_intmem1*/
 660                         <&clk_gates23 0>,/*pclk_pmu*/
 661
 662                         /*PD_PERI*/
 663                         <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
 664                         <&clk_gates20 8>,/*aclk_peri_niu*/
 665                         <&clk_gates21 4>,/*aclk_peri_mmu*/
 666                         <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
 667                         <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
 668                         <&clk_gates19 1>,/*pclk_peri_axi_matrix*/
 669
 670                         <&clk_gates24 0>, /* g_clk_timer0 */
 671                         <&clk_gates24 1>, /* g_clk_timer1 */
 672
 673                         <&fclk_mcu>,
 674                         <&stclk_mcu>,
 675                         <&clk_gates7 0>;/*clk_jtag*/
 676         };
 677
 678         /* I2C_PMU */
 679         i2c0: i2c@ff650000 {
 680                 compatible = "rockchip,rk30-i2c";
 681                 reg = <0x0 0xff650000 0x0 0x1000>;
 682                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 683                 #address-cells = <1>;
 684                 #size-cells = <0>;
 685                 pinctrl-names = "default", "gpio", "sleep";
 686                 pinctrl-0 = <&i2c0_xfer>;
 687                 pinctrl-1 = <&i2c0_gpio>;
 688                 pinctrl-2 = <&i2c0_sleep>;
 689                 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
 690                 clocks = <&clk_gates12 2>;
 691                 rockchip,check-idle = <1>;
 692                 status = "disabled";
 693         };
 694
 695         /* I2C_AUDIO */
 696         i2c1: i2c@ff660000 {
 697                 compatible = "rockchip,rk30-i2c";
 698                 reg = <0x0 0xff660000 0x0 0x1000>;
 699                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 700                 #address-cells = <1>;
 701                 #size-cells = <0>;
 702                 pinctrl-names = "default", "gpio", "sleep";
 703                 pinctrl-0 = <&i2c1_xfer>;
 704                 pinctrl-1 = <&i2c1_gpio>;
 705                 pinctrl-2 = <&i2c1_sleep>;
 706                 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
 707                 clocks = <&clk_gates12 3>;
 708                 rockchip,check-idle = <1>;
 709                 status = "disabled";
 710         };
 711
 712         /* I2C_SENSOR */
 713         i2c2: i2c@ff140000 {
 714                 compatible = "rockchip,rk30-i2c";
 715                 reg = <0x0 0xff140000 0x0 0x1000>;
 716                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 717                 #address-cells = <1>;
 718                 #size-cells = <0>;
 719                 pinctrl-names = "default", "gpio", "sleep";
 720                 pinctrl-0 = <&i2c2_xfer>;
 721                 pinctrl-1 = <&i2c2_gpio>;
 722                 pinctrl-2 = <&i2c2_sleep>;
 723                 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 724                 clocks = <&clk_gates19 11>;
 725                 rockchip,check-idle = <1>;
 726                 status = "disabled";
 727         };
 728
 729         /* I2C_CAM */
 730         i2c3: i2c@ff150000 {
 731                 compatible = "rockchip,rk30-i2c";
 732                 reg = <0x0 0xff150000 0x0 0x1000>;
 733                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 734                 #address-cells = <1>;
 735                 #size-cells = <0>;
 736                 pinctrl-names = "default", "gpio", "sleep";
 737                 pinctrl-0 = <&i2c3_xfer>;
 738                 pinctrl-1 = <&i2c3_gpio>;
 739                 pinctrl-2 = <&i2c3_sleep>;
 740                 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
 741                 clocks = <&clk_gates19 12>;
 742                 rockchip,check-idle = <1>;
 743                 status = "disabled";
 744         };
 745
 746         /* I2C_TP */
 747         i2c4: i2c@ff160000 {
 748                 compatible = "rockchip,rk30-i2c";
 749                 reg = <0x0 0xff160000 0x0 0x1000>;
 750                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 751                 #address-cells = <1>;
 752                 #size-cells = <0>;
 753                 pinctrl-names = "default", "gpio", "sleep";
 754                 pinctrl-0 = <&i2c4_xfer>;
 755                 pinctrl-1 = <&i2c4_gpio>;
 756                 pinctrl-2 = <&i2c4_sleep>;
 757                 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
 758                 clocks = <&clk_gates19 13>;
 759                 rockchip,check-idle = <1>;
 760                 status = "disabled";
 761         };
 762
 763         /* I2C_HDMI */
 764         i2c5: i2c@ff170000 {
 765                 compatible = "rockchip,rk30-i2c";
 766                 reg = <0x0 0xff170000 0x0 0x1000>;
 767                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 768                 #address-cells = <1>;
 769                 #size-cells = <0>;
 770                 pinctrl-names = "default", "gpio", "sleep";
 771                 pinctrl-0 = <&i2c5_xfer>;
 772                 pinctrl-1 = <&i2c5_gpio>;
 773                 pinctrl-2 = <&i2c5_sleep>;
 774                 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
 775                 clocks = <&clk_gates19 14>;
 776                 rockchip,check-idle = <1>;
 777                 status = "disabled";
 778         };
 779
 780         fb: fb {
 781                 compatible = "rockchip,rk-fb";
 782                 rockchip,disp-mode = <NO_DUAL>;
 783         };
 784
 785
 786         rk_screen: rk_screen {
 787                 compatible = "rockchip,screen";
 788         };
 789
 790         dsihost0: mipi@ff960000{
 791                 compatible = "rockchip,rk3368-dsi";
 792                 rockchip,prop = <0>;
 793                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 794                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 795                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 796                 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>, <&pd_mipidsi>;
 797                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host", "pd_mipi_dsi";
 798                 status = "disabled";
 799         };
 800
 801         lvds: lvds@ff968000 {
 802                 compatible = "rockchip,rk3368-lvds";
 803                 rockchip,grf = <&grf>;
 804                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 805                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 806                 clocks = <&clk_gates22 10>, <&clk_gates17 3>, <&pd_lvds>;
 807                 clock-names = "pclk_lvds", "pclk_lvds_ctl", "pd_lvds";
 808                 status = "disabled";
 809         };
 810
 811         edp: edp@ff970000 {
 812                 compatible = "rockchip,rk32-edp";
 813                 reg = <0x0 0xff970000 0x0 0x4000>;
 814                 rockchip,grf = <&grf>;
 815                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 816                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
 817                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 818                 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
 819                 reset-names = "edp_24m", "edp_apb";
 820         };
 821
 822         hdmi: hdmi@ff980000 {
 823                 compatible = "rockchip,rk3368-hdmi";
 824                 reg = <0x0 0xff980000 0x0 0x20000>;
 825                 rockchip,grf = <&grf>;
 826                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 827                 pinctrl-names = "default", "gpio";
 828                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 829                 pinctrl-1 = <&i2c5_gpio>;
 830                 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
 831                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 832                 status = "disabled";
 833         };
 834
 835         hdmi_hdcp2: hdmi_hdcp2@ff978000 {
 836                 compatible = "rockchip,rk3368-hdmi-hdcp2";
 837                 reg = <0x0 0xff978000 0x0 0x2000>;
 838                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 839                 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
 840                 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
 841                 status = "disabled";
 842         };
 843
 844         lcdc: lcdc@ff930000 {
 845                  compatible = "rockchip,rk3368-lcdc";
 846                  rockchip,grf = <&grf>;
 847                  rockchip,pmugrf = <&pmugrf>;
 848                  rockchip,cru = <&cru>;
 849                  rockchip,prop = <PRMRY>;
 850                  rockchip,pwr18 = <0>;
 851                  rockchip,iommu-enabled = <1>;
 852                  reg = <0x0 0xff930000 0x0 0x10000>;
 853                  interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 854                 /*pinctrl-names = "default", "gpio";
 855                  *pinctrl-0 = <&lcdc_lcdc>;
 856                  *pinctrl-1 = <&lcdc_gpio>;
 857                  */
 858                  status = "disabled";
 859                  clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>, <&pd_vop>;
 860                  clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll", "pd_lcdc";
 861         };
 862
 863         adc: adc@ff100000 {
 864                 compatible = "rockchip,saradc";
 865                 reg = <0x0 0xff100000 0x0 0x100>;
 866                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 867                 #io-channel-cells = <1>;
 868                 io-channel-ranges;
 869                 rockchip,adc-vref = <1800>;
 870                 clock-frequency = <1000000>;
 871                 clocks = <&clk_saradc>, <&clk_gates19 15>;
 872                 clock-names = "saradc", "pclk_saradc";
 873                 status = "disabled";
 874         };
 875
 876         rga@ff920000 {
 877                 compatible = "rockchip,rk3368-rga2";
 878                 reg = <0x0 0xff920000 0x0 0x1000>;
 879                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 880                 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
 881                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 882         };
 883
 884         i2s0: i2s0@ff898000 {
 885                 compatible = "rockchip-i2s";
 886                 reg = <0x0 0xff898000 0x0 0x1000>;
 887                 i2s-id = <0>;
 888                 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 889                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 890                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 891                 dmas = <&pdma0 0>, <&pdma0 1>;
 892                 #dma-cells = <2>;
 893                 dma-names = "tx", "rx";
 894                 pinctrl-names = "default", "sleep";
 895                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 896                 pinctrl-1 = <&i2s_gpio>;
 897         };
 898
 899         i2s1: i2s1@ff890000 {
 900                 compatible = "rockchip-i2s";
 901                 reg = <0x0 0xff890000 0x0 0x1000>;
 902                 i2s-id = <1>;
 903                 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
 904                 clock-names = "i2s_clk", "i2s_hclk";
 905                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 906                 dmas = <&pdma0 6>, <&pdma0 7>;
 907                 #dma-cells = <2>;
 908                 dma-names = "tx", "rx";
 909         };
 910
 911         spdif: spdif@ff880000 {
 912                 compatible = "rockchip-spdif";
 913                 reg = <0x0 0xff880000 0x0 0x1000>;
 914                 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
 915                 clock-names = "spdif_mclk", "spdif_hclk";
 916                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 917                 dmas = <&pdma0 3>;
 918                 #dma-cells = <1>;
 919                 dma-names = "tx";
 920                 pinctrl-names = "default";
 921                 pinctrl-0 = <&spdif_tx>;
 922         };
 923
 924         pwm0: pwm@ff680000 {
 925                 compatible = "rockchip,rk-pwm";
 926                 reg = <0x0 0xff680000 0x0 0x10>;
 927                 #pwm-cells = <2>;
 928                 pinctrl-names = "default";
 929                 pinctrl-0 = <&pwm0_pin>;
 930                 clocks = <&clk_gates13 6>;
 931                 clock-names = "pclk_pwm";
 932                 status = "disabled";
 933         };
 934
 935         pwm1: pwm@ff680010 {
 936                 compatible = "rockchip,rk-pwm";
 937                 reg = <0x0 0xff680010 0x0 0x10>;
 938                 #pwm-cells = <2>;
 939                 pinctrl-names = "default";
 940                 pinctrl-0 = <&pwm1_pin>;
 941                 clocks = <&clk_gates13 6>;
 942                 clock-names = "pclk_pwm";
 943                 status = "disabled";
 944         };
 945
 946         pwm2: pwm@ff680020 {
 947                 compatible = "rockchip,rk-pwm";
 948                 reg = <0x0 0xff680020 0x0 0x10>;
 949                 #pwm-cells = <2>;
 950                 //pinctrl-names = "default";
 951                 //pinctrl-0 = <&pwm1_pin>;
 952                 clocks = <&clk_gates13 6>;
 953                 clock-names = "pclk_pwm";
 954                 status = "disabled";
 955         };
 956
 957         pwm3: pwm@ff680030 {
 958                 compatible = "rockchip,rk-pwm";
 959                 reg = <0x0 0xff680030 0x0 0x10>;
 960                 #pwm-cells = <2>;
 961                 pinctrl-names = "default";
 962                 pinctrl-0 = <&pwm3_pin>;
 963                 clocks = <&clk_gates13 6>;
 964                 clock-names = "pclk_pwm";
 965                 status = "disabled";
 966         };
 967
 968         remotectl: pwm@ff680030 {
 969                 compatible = "rockchip,remotectl-pwm";
 970                 reg = <0x0 0xff680030 0x0 0x50>;
 971                 #pwm-cells = <2>;
 972                 pinctrl-names = "default";
 973                 pinctrl-0 = <&pwm3_pin>;
 974                 clocks = <&clk_gates13 6>;
 975                 clock-names = "pclk_pwm";
 976                 dmas = <&pdma0 2>;
 977                 #dma-cells = <2>;
 978                 dma-names = "rx";
 979                 remote_pwm_id = <3>;
 980                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 981                 status = "disabled";
 982         };
 983
 984         voppwm: pwm@ff9301a0 {
 985                 compatible = "rockchip,vop-pwm";
 986                 reg = <0x0 0xff9301a0 0x0 0x10>;
 987                 #pwm-cells = <2>;
 988                 pinctrl-names = "default";
 989                 pinctrl-0 = <&vop_pwm_pin>;
 990                 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
 991                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 992                 status = "disabled";
 993         };
 994
 995         pvtm {
 996                 compatible = "rockchip,rk3368-pvtm";
 997                 rockchip,grf = <&grf>;
 998                 rockchip,pmugrf = <&pmugrf>;
 999                 rockchip,pvtm-clk-out = <1>;
1000         };
1001
1002         cpufreq {
1003                 compatible = "rockchip,rk3368-cpufreq";
1004                 rockchip,grf = <&grf>;
1005         };
1006
1007         dvfs {
1008
1009                 vd_arm: vd_arm {
1010                         regulator_name = "vdd_arm";
1011                         suspend_volt = <1000>; //mV
1012                         pd_core {
1013                                 clk_core_b_dvfs_table: clk_core_b {
1014                                         operating-points = <
1015                                                 /* KHz    uV */
1016                                                 312000 1200000
1017                                                 504000 1200000
1018                                                 816000 1200000
1019                                                 1008000 1200000
1020                                                 >;
1021                                         status = "okay";
1022                                         temp-limit-enable = <1>;
1023                                         target-temp = <80>;
1024                                         min_temp_limit = <216>;
1025                                         normal-temp-limit = <
1026                                         /*delta-temp    delta-freq*/
1027                                                 3       96000
1028                                                 6       144000
1029                                                 9       192000
1030                                                 15      384000
1031                                                 >;
1032                                         performance-temp-limit = <
1033                                                 /*temp    freq*/
1034                                                 100     816000
1035                                                 >;
1036                                 };
1037                                 clk_core_l_dvfs_table: clk_core_l {
1038                                         operating-points = <
1039                                                 /* KHz    uV */
1040                                                 312000 1200000
1041                                                 504000 1200000
1042                                                 816000 1200000
1043                                                 1008000 1200000
1044                                                 >;
1045                                         status = "okay";
1046                                         temp-limit-enable = <1>;
1047                                         target-temp = <80>;
1048                                         min_temp_limit = <216>;
1049                                         normal-temp-limit = <
1050                                         /*delta-temp    delta-freq*/
1051                                                 3       96000
1052                                                 6       144000
1053                                                 9       192000
1054                                                 15      384000
1055                                                 >;
1056                                         performance-temp-limit = <
1057                                                 /*temp    freq*/
1058                                                 100     816000
1059                                                 >;
1060                                 };
1061                         };
1062                 };
1063
1064                 vd_logic: vd_logic {
1065                         regulator_name = "vdd_logic";
1066                         suspend_volt = <1000>; //mV
1067                         pd_ddr {
1068                                 clk_ddr_dvfs_table: clk_ddr {
1069                                         operating-points = <
1070                                                 /* KHz    uV */
1071                                                 200000 1200000
1072                                                 300000 1200000
1073                                                 400000 1200000
1074                                                 >;
1075                                         bd-freq-table = <
1076                                                 /* bandwidth   freq */
1077                                                 2700           792000
1078                                                 2600           600000
1079                                                 2280           456000
1080                                                 1560           396000
1081                                                 1020           324000
1082                                                 720            240000
1083                                                 >;
1084                                         channel = <2>;
1085                                         status = "disabled";
1086                                 };
1087                         };
1088
1089                         pd_gpu {
1090                                 clk_gpu_dvfs_table: clk_gpu {
1091                                         operating-points = <
1092                                                 /* KHz    uV */
1093                                                 200000 1200000
1094                                                 300000 1200000
1095                                                 400000 1200000
1096                                                 >;
1097                                         channel = <1>;
1098                                         status = "okay";
1099                                         regu-mode-table = <
1100                                                 /*freq     mode*/
1101                                                 200000     4
1102                                                 0          3
1103                                         >;
1104                                         regu-mode-en = <0>;
1105                                 };
1106                         };
1107                 };
1108         };
1109
1110         ion {
1111                 compatible = "rockchip,ion";
1112                 #address-cells = <1>;
1113                 #size-cells = <0>;
1114
1115                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1116                         compatible = "rockchip,ion-heap";
1117                         rockchip,ion_heap = <4>;
1118                         reg = <0x00000000 0x00000000>; /* 0MB */
1119                 };
1120                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1121                         compatible = "rockchip,ion-heap";
1122                         rockchip,ion_heap = <0>;
1123                 };
1124         };
1125
1126         vpu: vpu_service {
1127                 compatible = "rockchip,vpu_sub";
1128                 iommu_enabled = <1>;
1129                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1130                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1131                 interrupt-names = "irq_enc", "irq_dec";
1132                 dev_mode = <0>;
1133                 name = "vpu_service";
1134         };
1135
1136         hevc: hevc_service {
1137                 compatible = "rockchip,hevc_sub";
1138                 iommu_enabled = <1>;
1139                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1140                 interrupt-names = "irq_dec";
1141                 dev_mode = <1>;
1142                 name = "hevc_service";
1143         };
1144
1145         vpu_combo: vpu_combo@ff9a0000 {
1146                 compatible = "rockchip,vpu_combo";
1147                 reg = <0x0 0xff9a0000 0x0 0x800>;
1148                 rockchip,grf = <&grf>;
1149                 subcnt = <2>;
1150                 rockchip,sub = <&vpu>, <&hevc>;
1151                 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1152                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1153                 mode_bit = <12>;
1154                 mode_ctrl = <0x418>;
1155                 name = "vpu_combo";
1156                 status = "okay";
1157         };
1158
1159         iep: iep@ff900000 {
1160                 compatible = "rockchip,iep";
1161                 iommu_enabled = <1>;
1162                 reg = <0x0 0xff900000 0x0 0x800>;
1163                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1164                 clocks = <&clk_gates16 2>, <&clk_gates16 3>;
1165                 clock-names = "aclk_iep", "hclk_iep";
1166                 status = "okay";
1167         };
1168
1169         gmac: eth@ff290000 {
1170                 compatible = "rockchip,rk3368-gmac";
1171                 reg = <0x0 0xff290000 0x0 0x10000>;
1172                 rockchip,grf = <&grf>;
1173                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1174                 interrupt-names = "macirq";
1175
1176                 clocks = <&clk_mac>, <&clk_gates7 4>,
1177                          <&clk_gates7 5>, <&clk_gates7 6>,
1178                          <&clk_gates7 7>, <&clk_gates20 13>,
1179                          <&clk_gates20 14>;
1180                 clock-names = "clk_mac", "mac_clk_rx",
1181                               "mac_clk_tx", "clk_mac_ref",
1182                               "clk_mac_refout", "aclk_mac",
1183                               "pclk_mac";
1184
1185                 phy-mode = "rgmii";
1186                 pinctrl-names = "default";
1187                 pinctrl-0 = <&rgmii_pins>;
1188                 status = "disabled";
1189         };
1190
1191         gpu {
1192                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1193                 reg = <0x0 0xffa30000 0x0 0x10000>;
1194                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1195                 interrupt-names = "GPU";
1196         };
1197
1198         iep_mmu {
1199                 dbgname = "iep";
1200                 compatible = "rockchip,iep_mmu";
1201                 reg = <0x0 0xff900800 0x0 0x100>;
1202                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1203                 interrupt-names = "iep_mmu";
1204         };
1205
1206         vip_mmu {
1207                 dbgname = "vip";
1208                 compatible = "rockchip,vip_mmu";
1209                 reg = <0x0 0xff950800 0x0 0x100>;
1210                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1211                 interrupt-names = "vip_mmu";
1212         };
1213
1214         vop_mmu {
1215                 dbgname = "vop";
1216                 compatible = "rockchip,vopb_mmu";
1217                 reg = <0x0 0xff930300 0x0 0x100>;
1218                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1219                 interrupt-names = "vop_mmu";
1220         };
1221
1222         isp_mmu {
1223                 dbgname = "isp_mmu";
1224                 compatible = "rockchip,isp_mmu";
1225                 reg = <0x0 0xff914000 0x0 0x100>,
1226                 <0x0 0xff915000 0x0 0x100>;
1227                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1228                 interrupt-names = "isp_mmu";
1229         };
1230
1231         hdcp_mmu {
1232                 dbgname = "hdcp_mmu";
1233                 compatible = "rockchip,hdcp_mmu";
1234                 reg = <0x0 0xff940000 0x0 0x100>;
1235                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1236                 interrupt-names = "hdcp_mmu";
1237         };
1238
1239         hevc_mmu {
1240                 dbgname = "hevc";
1241                 compatible = "rockchip,hevc_mmu";
1242                 reg = <0x0 0xff9a0440 0x0 0x40>,                      /*need to fix*/
1243                           <0x0 0xff9a0480 0x0 0x40>;
1244                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;        /*need to fix*/
1245                 interrupt-names = "hevc_mmu";
1246         };
1247
1248         vpu_mmu {
1249                 dbgname = "vpu";
1250                 compatible = "rockchip,vpu_mmu";
1251                 reg = <0x0 0xff9a0800 0x0 0x100>;                    /*need to fix*/
1252                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,        /*need to fix*/
1253                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1254                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1255         };
1256
1257         rockchip_suspend: rockchip_suspend {
1258                 rockchip,ctrbits = <
1259                         (0
1260                         | RKPM_SLP_ARMOFF
1261                         | RKPM_SLP_PMU_PLLS_PWRDN
1262                         /*| RKPM_SLP_PMU_PMUALIVE_32K
1263                         | RKPM_SLP_SFT_PLLS_DEEP
1264                         | RKPM_SLP_PMU_DIS_OSC */
1265                         | RKPM_SLP_SFT_PD_NBSCUS
1266                         )
1267                         >;
1268         };
1269
1270         isp: isp@ff910000{
1271                 compatible = "rockchip,isp";
1272                 reg = <0x0 0xff910000 0x0 0x10000>;
1273                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1274                 clocks = <&clk_gates16 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>, <&pd_isp>;
1275                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx", "pd_isp";
1276                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1277                 pinctrl-0 = <&cif_clkout>;
1278                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1279                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1280                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1281                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1282                 pinctrl-5 = <&cif_clkout>;
1283                 pinctrl-6 = <&cif_clkout &isp_prelight>;
1284                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1285                 pinctrl-8 = <&isp_flash_trigger>;
1286                 rockchip,isp,mipiphy = <2>;
1287                 rockchip,isp,cifphy = <1>;
1288                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1289                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1290                 rockchip,grf = <&grf>;
1291                 rockchip,cru = <&cru>;
1292                 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1293                 rockchip,isp,iommu_enable = <1>;
1294                 status = "okay";
1295         };
1296
1297         cif: cif@ff950000 {
1298                 compatible = "rockchip,cif";
1299                 reg = <0x0 0xff950000 0x0 0x10000>;
1300                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1301                 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1302                 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1303                 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1304                 pinctrl-names = "cif_pin_all";
1305                 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1306                 rockchip,grf = <&grf>;
1307                 rockchip,cru = <&cru>;
1308                 status = "okay";
1309         };
1310
1311 /*
1312         thermal-zones {
1313                 #include "rk3368-thermal.dtsi"
1314         };
1315 */
1316
1317         tsadc: tsadc@ff280000 {
1318                 compatible = "rockchip,rk3368-tsadc";
1319                 reg = <0x0 0xff280000 0x0 0x100>;
1320                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1321                 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1322                 rockchip,grf = <&grf>;
1323                 rockchip,cru = <&cru>;
1324                 rockchip,pmu = <&pmu>;
1325                 clock-names = "tsadc", "apb_pclk";
1326                 clock-frequency = <32000>;
1327                 resets = <&reset RK3368_SRST_TSADC_P>;
1328                 reset-names = "tsadc-apb";
1329                 //pinctrl-names = "default";
1330                 //pinctrl-0 = <&tsadc_int>;
1331                 #thermal-sensor-cells = <1>;
1332                 hw-shut-temp = <120000>;
1333                 status = "disabled";
1334         };
1335
1336         tsp: tsp@FF8B0000 {
1337                 compatible = "rockchip,rk3368-tsp";
1338                 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1339                 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1340                 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1341                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1342                 interrupt-names = "irq_tsp";
1343                 // pinctrl-names = "default";
1344                 // pinctrl-0 = <&isp_hsadc>;
1345                 status = "okay";
1346         };
1347
1348         crypto: crypto@FF8A0000{
1349                 compatible = "rockchip,rk3368-crypto";
1350                 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1351                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1352                 interrupt-names = "irq_crypto";
1353                         clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1354                 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1355                 status = "okay";
1356         };
1357
1358         dwc_control_usb: dwc-control-usb {
1359                 compatible = "rockchip,rk3368-dwc-control-usb";
1360                 rockchip,grf = <&grf>;
1361                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1362                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1363                 interrupt-names = "otg_id", "otg_bvalid",
1364                                   "otg_linestate", "host0_linestate";
1365                 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1366                 clock-names = "hclk_usb_peri", "usbphy_480m";
1367                 //resets = <&reset RK3128_RST_USBPOR>;
1368                 //reset-names = "usbphy_por";
1369                 usb_bc{
1370                         compatible = "inno,phy";
1371                         regbase = &dwc_control_usb;
1372                         rk_usb,bvalid     = <0x4bc 23 1>;
1373                         rk_usb,iddig      = <0x4bc 26 1>;
1374                         rk_usb,vdmsrcen   = <0x718 12 1>;
1375                         rk_usb,vdpsrcen   = <0x718 11 1>;
1376                         rk_usb,rdmpden    = <0x718 10 1>;
1377                         rk_usb,idpsrcen   = <0x718  9 1>;
1378                         rk_usb,idmsinken  = <0x718  8 1>;
1379                         rk_usb,idpsinken  = <0x718  7 1>;
1380                         rk_usb,dpattach   = <0x4b8 31 1>;
1381                         rk_usb,cpdet      = <0x4b8 30 1>;
1382                         rk_usb,dcpattach  = <0x4b8 29 1>;
1383                 };
1384         };
1385
1386         usbphy: phy {
1387                 compatible = "rockchip,rk3368-usb-phy";
1388                 rockchip,grf = <&grf>;
1389                 #address-cells = <1>;
1390                 #size-cells = <0>;
1391
1392                 usbphy0: usb-phy0 {
1393                         #phy-cells = <0>;
1394                         reg = <0x700>;
1395                 };
1396
1397                 usbphy1: usb-phy1 {
1398                         #phy-cells = <0>;
1399                         reg = <0x728>;
1400                 };
1401         };
1402
1403         usb0: usb@ff580000 {
1404                 compatible = "rockchip,rk3368_usb20_otg";
1405                 reg = <0x0 0xff580000 0x0 0x40000>;
1406                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1407                 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1408                 clock-names = "clk_usbphy0", "hclk_otg";
1409                 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1410                                 <&reset RK3368_SRST_USBOTGC0>;
1411                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1412                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1413                 rockchip,usb-mode = <0>;
1414         };
1415
1416         usb_ehci: usb@ff500000 {
1417                 compatible = "generic-ehci";
1418                 reg = <0x0 0xff500000 0x0 0x20000>;
1419                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1420                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1421                 clock-names = "clk_usbphy0", "hclk_ehci";
1422                 phys = <&usbphy1>;
1423                 phy-names = "usb";
1424                 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1425                 //              <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1426                 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1427         };
1428
1429         usb_ohci: usb@ff520000 {
1430                 compatible = "generic-ohci";
1431                 reg = <0x0 0xff520000 0x0 0x20000>;
1432                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1433                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1434                 clock-names =  "clk_usbphy0", "hclk_ohci";
1435         };
1436
1437         usb_hsic: usb@ff5c0000 {
1438                 compatible = "rockchip,rk3288_rk_hsic_host";
1439                 reg = <0x0 0xff5c0000 0x0 0x40000>;
1440                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1441 /*
1442                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1443                          <&hsicphy_12m>, <&usbphy_480m>,
1444                          <&otgphy1_480m>, <&otgphy2_480m>;
1445                 clock-names = "hsicphy_480m", "hclk_hsic",
1446                               "hsicphy_12m", "usbphy_480m",
1447                               "hsic_usbphy1", "hsic_usbphy2";
1448                 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1449                                 <&reset RK3288_SOFT_RST_HSICPHY>;
1450                 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1451 */
1452                 status = "disabled";
1453         };
1454
1455         pinctrl: pinctrl {
1456                 compatible = "rockchip,rk3368-pinctrl";
1457                 rockchip,grf = <&grf>;
1458                 rockchip,pmugrf = <&pmugrf>;
1459                 #address-cells = <2>;
1460                 #size-cells = <2>;
1461                 ranges;
1462
1463                 gpio0: gpio0@ff750000 {
1464                         compatible = "rockchip,gpio-bank";
1465                         reg =   <0x0 0xff750000 0x0 0x100>;
1466                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1467                         clocks = <&clk_gates23 4>;
1468
1469                         gpio-controller;
1470                         #gpio-cells = <2>;
1471
1472                         interrupt-controller;
1473                         #interrupt-cells = <2>;
1474                 };
1475
1476                 gpio1: gpio1@ff780000 {
1477                         compatible = "rockchip,gpio-bank";
1478                         reg = <0x0 0xff780000 0x0 0x100>;
1479                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1480                         clocks = <&clk_gates22 1>;
1481
1482                         gpio-controller;
1483                         #gpio-cells = <2>;
1484
1485                         interrupt-controller;
1486                         #interrupt-cells = <2>;
1487                 };
1488
1489                 gpio2: gpio2@ff790000 {
1490                         compatible = "rockchip,gpio-bank";
1491                         reg = <0x0 0xff790000 0x0 0x100>;
1492                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1493                         clocks = <&clk_gates22 2>;
1494
1495                         gpio-controller;
1496                         #gpio-cells = <2>;
1497
1498                         interrupt-controller;
1499                         #interrupt-cells = <2>;
1500                 };
1501
1502                 gpio3: gpio3@ff7a0000 {
1503                         compatible = "rockchip,gpio-bank";
1504                         reg = <0x0 0xff7a0000 0x0 0x100>;
1505                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1506                         clocks = <&clk_gates22 3>;
1507
1508                         gpio-controller;
1509                         #gpio-cells = <2>;
1510
1511                         interrupt-controller;
1512                         #interrupt-cells = <2>;
1513                 };
1514
1515                 pcfg_pull_up: pcfg-pull-up {
1516                         bias-pull-up;
1517                 };
1518
1519                 pcfg_pull_down: pcfg-pull-down {
1520                         bias-pull-down;
1521                 };
1522
1523                 pcfg_pull_none: pcfg-pull-none {
1524                         bias-disable;
1525                 };
1526
1527                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1528                         drive-strength = <8>;
1529                 };
1530
1531                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1532                         drive-strength = <12>;
1533                 };
1534
1535                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1536                         bias-pull-up;
1537                         drive-strength = <8>;
1538                 };
1539
1540                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1541                         drive-strength = <4>;
1542                 };
1543
1544                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1545                         bias-pull-up;
1546                         drive-strength = <4>;
1547                 };
1548
1549                 pcfg_output_high: pcfg-output-high {
1550                         output-high;
1551                 };
1552
1553                 pcfg_output_low: pcfg-output-low {
1554                         output-low;
1555                 };
1556
1557                 pcfg_input_high: pcfg-input-high {
1558                         bias-pull-up;
1559                         input-enable;
1560                 };
1561
1562                 i2c0 {
1563                         i2c0_xfer: i2c0-xfer {
1564                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1565                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1566                         };
1567                         i2c0_gpio: i2c0-gpio {
1568                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1569                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1570                         };
1571                         i2c0_sleep: i2c0-sleep {
1572                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_input_high>,
1573                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_input_high>;
1574                         };
1575                 };
1576
1577                 i2c1 {
1578                         i2c1_xfer: i2c1-xfer {
1579                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1580                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1581                         };
1582                         i2c1_gpio: i2c1-gpio {
1583                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1584                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1585                         };
1586                         i2c1_sleep: i2c1-sleep {
1587                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_input_high>,
1588                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_input_high>;
1589                         };
1590                 };
1591
1592                 i2c2 {
1593                         i2c2_xfer: i2c2-xfer {
1594                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1595                                                 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1596                         };
1597                         i2c2_gpio: i2c2-gpio {
1598                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1599                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1600                         };
1601                         i2c2_sleep: i2c2-sleep {
1602                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_input_high>,
1603                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_input_high>;
1604                         };
1605                 };
1606
1607                 i2c3 {
1608                         i2c3_xfer: i2c3-xfer {
1609                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1610                                                 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1611                         };
1612                         i2c3_gpio: i2c3-gpio {
1613                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1614                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1615                         };
1616                         i2c3_sleep: i2c3-sleep {
1617                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_input_high>,
1618                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_input_high>;
1619                         };
1620                 };
1621
1622                 i2c4 {
1623                         i2c4_xfer: i2c4-xfer {
1624                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1625                                                 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1626                         };
1627                         i2c4_gpio: i2c4-gpio {
1628                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1629                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1630                         };
1631                         i2c4_sleep: i2c4-sleep {
1632                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_input_high>,
1633                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_input_high>;
1634                         };
1635                 };
1636
1637                 i2c5 {
1638                         i2c5_xfer: i2c5-xfer {
1639                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1640                                                 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1641                         };
1642                         i2c5_gpio: i2c5-gpio {
1643                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1644                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1645                         };
1646                         i2c5_sleep: i2c5-sleep {
1647                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_input_high>,
1648                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_input_high>;
1649                         };
1650                 };
1651
1652                 uart0 {
1653                         uart0_xfer: uart0-xfer {
1654                                 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1655                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1656                         };
1657
1658                         uart0_cts: uart0-cts {
1659                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1660                         };
1661
1662                         uart0_rts: uart0-rts {
1663                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1664                         };
1665
1666                         uart0_rts_gpio: uart0-rts-gpio {
1667                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1668                         };
1669                 };
1670
1671                 uart1 {
1672                         uart1_xfer: uart1-xfer {
1673                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1674                                                 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1675                         };
1676
1677                         uart1_cts: uart1-cts {
1678                                 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1679                         };
1680
1681                         uart1_rts: uart1-rts {
1682                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1683                         };
1684                 };
1685
1686                 uart2 {
1687                         uart2_xfer: uart2-xfer {
1688                                 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1689                                                 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1690                         };
1691                 };
1692
1693                 uart3 {
1694                         uart3_xfer: uart3-xfer {
1695                                 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1696                                                 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1697                         };
1698
1699                         uart3_cts: uart3-cts {
1700                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1701                         };
1702
1703                         uart3_rts: uart3-rts {
1704                                 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1705                         };
1706                 };
1707
1708                 uart4 {
1709                         uart4_xfer: uart4-xfer {
1710                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1711                                                 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1712                         };
1713
1714                         uart4_cts: uart4-cts {
1715                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1716                         };
1717
1718                         uart4_rts: uart4-rts {
1719                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1720                         };
1721                 };
1722
1723                 spi0 {
1724                         spi0_clk: spi0-clk {
1725                                 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1726                         };
1727                         spi0_cs0: spi0-cs0 {
1728                                 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1729                         };
1730                         spi0_tx: spi0-tx {
1731                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1732                         };
1733                         spi0_rx: spi0-rx {
1734                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1735                         };
1736                         spi0_cs1: spi0-cs1 {
1737                                 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1738                         };
1739                 };
1740
1741                 spi1 {
1742                         spi1_clk: spi1-clk {
1743                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1744                         };
1745                         spi1_cs0: spi1-cs0 {
1746                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1747                         };
1748                         spi1_rx: spi1-rx {
1749                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1750                         };
1751                         spi1_tx: spi1-tx {
1752                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1753                         };
1754                         spi1_cs1: spi1-cs1 {
1755                                 rockchip,pins = <3 GPIO_D4 RK_FUNC_2 &pcfg_pull_up>;
1756                         };
1757                 };
1758
1759                 spi2 {
1760                         spi2_clk: spi2-clk {
1761                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1762                         };
1763                         spi2_cs0: spi2-cs0 {
1764                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1765                         };
1766                         spi2_rx: spi2-rx {
1767                                 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1768                         };
1769                         spi2_tx: spi2-tx {
1770                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1771                         };
1772                 };
1773
1774                 i2s {
1775                         i2s_mclk: i2s-mclk {
1776                                 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1777                         };
1778
1779                         i2s_sclk:i2s-sclk {
1780                                 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1781                         };
1782
1783                         i2s_lrckrx:i2s-lrckrx {
1784                                 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1785                         };
1786
1787                         i2s_lrcktx:i2s-lrcktx {
1788                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1789                         };
1790
1791                         i2s_sdi:i2s-sdi {
1792                                 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1793                         };
1794
1795                         i2s_sdo0:i2s-sdo0 {
1796                                 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1797                         };
1798
1799                         i2s_sdo1:i2s-sdo1 {
1800                                 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1801                         };
1802
1803                         i2s_sdo2:i2s-sdo2 {
1804                                 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1805                         };
1806
1807                         i2s_sdo3:i2s-sdo3 {
1808                                 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1809                         };
1810
1811                         i2s_gpio: i2s-gpio {
1812                                 rockchip,pins = <2 GPIO_C4  RK_FUNC_GPIO &pcfg_pull_none>,
1813                                                 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1814                                                 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1815                                                 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1816                                                 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1817                                                 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1818                                                 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1819                                                 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1820                                                 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1821                         };
1822                 };
1823
1824                 spdif {
1825                         spdif_tx: spdif-tx {
1826                                 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1827                         };
1828                 };
1829
1830                 sdmmc {
1831                         sdmmc_clk: sdmmc-clk {
1832                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1833                         };
1834
1835                         sdmmc_cmd: sdmmc-cmd {
1836                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1837                         };
1838
1839                         sdmmc_dectn: sdmmc-dectn {
1840                                 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1841                         };
1842
1843                         sdmmc_bus1: sdmmc-bus1 {
1844                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1845                         };
1846
1847                         sdmmc_bus4: sdmmc-bus4 {
1848                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1849                                                 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1850                                                 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1851                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1852                         };
1853
1854                         sdmmc_gpio: sdmmc-gpio {
1855                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1856                                                 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1857                                                 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1858                                                 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1859                                                 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1860                                                 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1861                                                 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1862                         };
1863                 };
1864
1865                 sdio0 {
1866                         sdio0_bus1: sdio0-bus1 {
1867                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1868                         };
1869
1870                         sdio0_bus4: sdio0-bus4 {
1871                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1872                                                 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1873                                                 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1874                                                 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1875                         };
1876
1877                         sdio0_cmd: sdio0-cmd {
1878                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1879                         };
1880
1881                         sdio0_clk: sdio0-clk {
1882                                 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1883                         };
1884
1885                         sdio0_dectn: sdio0-dectn {
1886                                 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1887                         };
1888
1889                         sdio0_wrprt: sdio0-wrprt {
1890                                 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1891                         };
1892
1893                         sdio0_pwren: sdio0-pwren {
1894                                 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1895                         };
1896
1897                         sdio0_bkpwr: sdio0-bkpwr {
1898                                 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1899                         };
1900
1901                         sdio0_int: sdio0-int {
1902                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1903                         };
1904
1905                         sdio0_gpio: sdio0-gpio {
1906                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1907                                                 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1908                                                 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1909                                                 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1910                                                 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1911                                                 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1912                                                 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1913                                                 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1914                                                 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1915                                                 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1916                                                 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1917                         };
1918                 };
1919
1920                 emmc {
1921                         emmc_clk: emmc-clk {
1922                                 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1923                         };
1924
1925                         emmc_cmd: emmc-cmd {
1926                                 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1927                         };
1928
1929                         emmc_pwren: emmc-pwren {
1930                                 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1931                         };
1932
1933                         emmc_rstnout: emmc_rstnout {
1934                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1935                         };
1936
1937                         emmc_bus1: emmc-bus1 {
1938                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1939                         };
1940
1941                         emmc_bus4: emmc-bus4 {
1942                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1943                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1944                                                 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1945                                                 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1946                         };
1947                 };
1948
1949                 pwm0 {
1950                         pwm0_pin: pwm0-pin {
1951                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1952                         };
1953
1954                         vop_pwm_pin:vop-pwm {
1955                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1956                         };
1957                 };
1958
1959                 pwm1 {
1960                         pwm1_pin: pwm1-pin {
1961                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1962                         };
1963                 };
1964
1965                 pwm3 {
1966                         pwm3_pin: pwm3-pin {
1967                                 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1968                         };
1969                 };
1970
1971                 lcdc {
1972                         lcdc_lcdc: lcdc-lcdc {
1973                                 rockchip,pins =
1974                                                 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1975                                                 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1976                                                 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1977                                                 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1978                                                 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1979                                                 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1980                                                 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1981                                                 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1982                                                 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1983                                                 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1984                                                 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1985                                                 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1986                                                 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1987                                                 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1988                                                 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1989                                                 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1990                                                 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1991                                                 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1992                         };
1993
1994                         lcdc_gpio: lcdc-gpio {
1995                                 rockchip,pins =
1996                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1997                                                 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1998                                                 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1999                                                 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
2000                                                 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
2001                                                 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
2002                                                 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
2003                                                 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
2004                                                 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
2005                                                 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
2006                                                 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
2007                                                 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
2008                                                 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
2009                                                 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
2010                                                 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
2011                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
2012                                                 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
2013                                                 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
2014                         };
2015                 };
2016
2017                 isp {
2018                         cif_clkout: cif-clkout {
2019                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2020                         };
2021
2022                         isp_dvp_d2d9: isp-dvp-d2d9 {
2023                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2024                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2025                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2026                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2027                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2028                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2029                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2030                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2031                                                 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
2032                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
2033                                                 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
2034                                                 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2035                         };
2036
2037                         isp_dvp_d0d1: isp-dvp-d0d1 {
2038                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2039                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
2040                         };
2041
2042                         isp_dvp_d10d11:isp_d10d11       {
2043                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2044                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2045                         };
2046
2047                         isp_dvp_d0d7: isp-dvp-d0d7 {
2048                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2049                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
2050                                                 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2051                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2052                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2053                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2054                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2055                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
2056                         };
2057
2058                         isp_shutter: isp-shutter {
2059                                 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2060                                                 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2061                         };
2062
2063                         isp_flash_trigger: isp-flash-trigger {
2064                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2065                         };
2066
2067                         isp_prelight: isp-prelight {
2068                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2069                         };
2070
2071                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2072                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
2073                         };
2074                 };
2075
2076                 gps {
2077                         gps_mag: gps-mag {
2078                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
2079                         };
2080
2081                         gps_sig: gps-sig {
2082                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
2083
2084                         };
2085
2086                         gps_rfclk: gps-rfclk {
2087                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
2088                         };
2089                 };
2090
2091                 gmac {
2092                         rgmii_pins: rgmii-pins {
2093                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2094                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2095                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2096                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2097                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2098                                                 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
2099                                                 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
2100                                                 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
2101                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2102                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2103                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2104                                                 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
2105                                                 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
2106                                                 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
2107                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
2108                         };
2109
2110                         rmii_pins: rmii-pins {
2111                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2112                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2113                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2114                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2115                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2116                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2117                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2118                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2119                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
2120                                                 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
2121                         };
2122                 };
2123
2124                 tsadc_pin {
2125                         tsadc_int: tsadc-int {
2126                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
2127                         };
2128                         tsadc_gpio: tsadc-gpio {
2129                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
2130                         };
2131                 };
2132
2133                 hdmi_pin {
2134                         hdmi_cec: hdmi-cec {
2135                                 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
2136                         };
2137                 };
2138
2139                 hdmi_i2c {
2140                         hdmii2c_xfer: hdmii2c-xfer {
2141                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
2142                                                 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
2143                         };
2144                 };
2145
2146                 cpu_jtag {
2147                         cpu_jtag: cpu-jtag {
2148                                 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_up>,
2149                                                 <2 GPIO_B0 RK_FUNC_2 &pcfg_pull_up>;
2150                         };
2151                 };
2152
2153                 mcu_jtag {
2154                         mcu_jtag: mcu-jtag {
2155                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>,
2156                                                 <2 GPIO_B1 RK_FUNC_2 &pcfg_pull_up>;
2157                         };
2158                 };
2159         };
2160
2161         reboot {
2162                 compatible = "rockchip,rk3368-reboot";
2163                 rockchip,cru = <&cru>;
2164                 rockchip,pmugrf = <&pmugrf>;
2165         };
2166 };