1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include <dt-bindings/suspend/rockchip-rk3368.h>
3 #include <dt-bindings/pinctrl/rockchip.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/sensor-dev.h>
6 #include <dt-bindings/clock/rk_system_status.h>
8 #include "rk3368-clocks.dtsi"
11 compatible = "rockchip,rk3368";
13 rockchip,sram = <&sram>;
14 interrupt-parent = <&gic>;
41 entry-method = "arm,psci";
42 CPU_SLEEP_0: cpu-sleep-0 {
43 compatible = "arm,idle-state";
44 arm,psci-suspend-param = <0x1010000>;
45 entry-latency-us = <0x3fffffff>;
46 exit-latency-us = <0x40000000>;
47 min-residency-us = <0xffffffff>;
53 compatible = "arm,cortex-a53", "arm,armv8";
55 enable-method = "psci";
56 cpu-idle-states = <&CPU_SLEEP_0>;
60 compatible = "arm,cortex-a53", "arm,armv8";
62 enable-method = "psci";
63 cpu-idle-states = <&CPU_SLEEP_0>;
67 compatible = "arm,cortex-a53", "arm,armv8";
69 enable-method = "psci";
70 cpu-idle-states = <&CPU_SLEEP_0>;
74 compatible = "arm,cortex-a53", "arm,armv8";
76 enable-method = "psci";
77 cpu-idle-states = <&CPU_SLEEP_0>;
81 compatible = "arm,cortex-a53", "arm,armv8";
83 enable-method = "psci";
84 cpu-idle-states = <&CPU_SLEEP_0>;
88 compatible = "arm,cortex-a53", "arm,armv8";
90 enable-method = "psci";
91 cpu-idle-states = <&CPU_SLEEP_0>;
95 compatible = "arm,cortex-a53", "arm,armv8";
97 enable-method = "psci";
98 cpu-idle-states = <&CPU_SLEEP_0>;
102 compatible = "arm,cortex-a53", "arm,armv8";
104 enable-method = "psci";
105 cpu-idle-states = <&CPU_SLEEP_0>;
141 compatible = "arm,psci-0.2";
145 gic: interrupt-controller@ffb70000 {
146 compatible = "arm,cortex-a15-gic";
147 #interrupt-cells = <3>;
148 #address-cells = <0>;
149 interrupt-controller;
150 reg = <0x0 0xffb71000 0 0x1000>,
151 <0x0 0xffb72000 0 0x1000>;
154 ddrpctl: syscon@ff610000 {
155 compatible = "rockchip,rk3368-ddrpctl", "syscon";
156 reg = <0x0 0xff610000 0x0 0x400>;
159 pmu: syscon@ff730000 {
160 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
161 reg = <0x0 0xff730000 0x0 0x1000>;
164 pmugrf: syscon@ff738000 {
165 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
166 reg = <0x0 0xff738000 0x0 0x1000>;
169 sgrf: syscon@ff740000 {
170 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
171 reg = <0x0 0xff740000 0x0 0x1000>;
175 cru: syscon@ff760000 {
176 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
177 reg = <0x0 0xff760000 0x0 0x1000>;
180 grf: syscon@ff770000 {
181 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
182 reg = <0x0 0xff770000 0x0 0x1000>;
185 msch: syscon@ffac0000 {
186 compatible = "rockchip,rk3368-msch", "rockchip,msch", "syscon";
187 reg = <0x0 0xffac0000 0x0 0x3000>;
191 compatible = "arm,armv8-pmuv3";
192 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
202 cpu_axi_bus: cpu_axi_bus {
203 compatible = "rockchip,cpu_axi_bus";
204 #address-cells = <2>;
209 #address-cells = <2>;
214 reg = <0x0 0xffa80000 0x0 0x20>;
217 reg = <0x0 0xffa80080 0x0 0x20>;
220 reg = <0x0 0xffa80280 0x0 0x20>;
223 reg = <0x0 0xffa90000 0x0 0x20>;
226 reg = <0x0 0xffaa0000 0x0 0x20>;
229 reg = <0x0 0xffaa0080 0x0 0x20>;
232 reg = <0x0 0xffab0000 0x0 0x20>;
233 rockchip,priority = <2 2>;
236 reg = <0x0 0xffad0000 0x0 0x20>;
239 reg = <0x0 0xffad0080 0x0 0x20>;
242 reg = <0x0 0xffad0100 0x0 0x20>;
245 reg = <0x0 0xffad0180 0x0 0x20>;
246 rockchip,priority = <2 2>;
249 reg = <0x0 0xffad0200 0x0 0x20>;
250 rockchip,priority = <2 2>;
253 reg = <0x0 0xffad0280 0x0 0x20>;
256 reg = <0x0 0xffad0300 0x0 0x20>;
257 rockchip,priority = <2 2>;
260 reg = <0x0 0xffad0380 0x0 0x20>;
263 reg = <0x0 0xffad0400 0x0 0x20>;
266 reg = <0x0 0xffae0000 0x0 0x20>;
269 reg = <0x0 0xffae0100 0x0 0x20>;
272 reg = <0x0 0xffae0180 0x0 0x20>;
275 reg = <0x0 0xffaf0000 0x0 0x20>;
280 #address-cells = <2>;
285 reg = <0x0 0xffac0000 0x0 0x3c>;
286 rockchip,read-latency = <0x34>;
292 compatible = "rockchip,rk3368-efuse-256";
293 reg = <0x0 0xffb00000 0x0 0x8>;
297 compatible = "arm,armv8-timer";
298 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
299 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
300 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
301 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
302 clock-frequency = <24000000>;
306 compatible = "rockchip,timer";
307 reg = <0x0 0xff810000 0x0 0x20>;
308 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
309 rockchip,broadcast = <1>;
313 compatible = "rockchip,timer";
314 reg = <0x0 0xff810020 0x0 0x20>;
315 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
316 rockchip,percpu = <0>;
319 sram: sram@ff8c0000 {
320 compatible = "mmio-sram";
321 reg = <0x0 0xff8c0000 0x0 0xf000>; /* 60K (reserved 4K for mailbox)*/
325 watchdog: wdt@ff800000 {
326 compatible = "rockchip,watch dog";
327 reg = <0x0 0xff800000 0x0 0x100>;
328 clocks = <&pclk_alive_pre>;
329 clock-names = "pclk_wdt";
330 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
332 rockchip,timeout = <60>;
333 rockchip,atboot = <1>;
334 rockchip,debug = <0>;
339 #address-cells = <2>;
341 compatible = "arm,amba-bus";
342 interrupt-parent = <&gic>;
345 pdma0: pdma@ff600000 {
346 compatible = "arm,pl330", "arm,primecell";
347 reg = <0x0 0xff600000 0x0 0x4000>;
348 clocks = <&clk_gates12 11>;
349 clock-names = "apb_pclk";
350 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
356 pdma1: pdma@ff250000 {
357 compatible = "arm,pl330", "arm,primecell";
358 reg = <0x0 0xff250000 0x0 0x4000>;
359 clocks = <&clk_gates19 3>;
360 clock-names = "apb_pclk";
361 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
367 reset: reset@ff760300{
368 compatible = "rockchip,reset";
369 reg = <0x0 0xff760300 0x0 0x38>;
370 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
374 nandc0: nandc@ff400000 {
375 compatible = "rockchip,rk-nandc";
376 reg = <0x0 0xff400000 0x0 0x4000>;
377 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&clk_nandc0>, <&clk_gates20 9>, <&clk_gates20 11>;
380 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
383 nandc0reg: nandc0@ff400000 {
384 compatible = "rockchip,rk-nandc";
385 reg = <0x0 0xff400000 0x0 0x4000>;
388 emmc: rksdmmc@ff0f0000 {
389 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
390 reg = <0x0 0xff0f0000 0x0 0x4000>;
391 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
392 #address-cells = <1>;
394 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
395 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
396 rockchip,grf = <&grf>;
398 fifo-depth = <0x100>;
400 tune_regsbase = <0x418>;
403 sdmmc: rksdmmc@ff0c0000 {
404 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
405 reg = <0x0 0xff0c0000 0x0 0x4000>;
406 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
407 #address-cells = <1>;
409 pinctrl-names = "default", "idle", "udbg";
410 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
411 pinctrl-1 = <&sdmmc_gpio>;
412 pinctrl-2 = <&uart2_xfer &cpu_jtag &mcu_jtag &sdmmc_dectn>;
413 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
414 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
415 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
416 rockchip,grf = <&grf>;
418 fifo-depth = <0x100>;
420 tune_regsbase = <0x400>;
423 sdio: rksdmmc@ff0d0000 {
424 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
425 reg = <0x0 0xff0d0000 0x0 0x4000>;
426 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
427 #address-cells = <1>;
429 pinctrl-names = "default","idle";
430 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
431 pinctrl-1 = <&sdio0_gpio>;
432 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
433 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
434 rockchip,grf = <&grf>;
436 fifo-depth = <0x100>;
438 tune_regsbase = <0x408>;
442 compatible = "rockchip,rockchip-spi";
443 reg = <0x0 0xff110000 0x0 0x1000>;
444 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
445 #address-cells = <1>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
449 rockchip,spi-src-clk = <0>;
451 clocks =<&clk_spi0>, <&clk_gates19 4>;
452 clock-names = "spi", "pclk_spi0";
453 //dmas = <&pdma1 11>, <&pdma1 12>;
455 //dma-names = "tx", "rx";
460 compatible = "rockchip,rockchip-spi";
461 reg = <0x0 0xff120000 0x0 0x1000>;
462 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
463 #address-cells = <1>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0 &spi1_cs1>;
467 rockchip,spi-src-clk = <1>;
469 clocks = <&clk_spi1>, <&clk_gates19 5>;
470 clock-names = "spi", "pclk_spi1";
471 //dmas = <&pdma1 13>, <&pdma1 14>;
473 //dma-names = "tx", "rx";
478 compatible = "rockchip,rockchip-spi";
479 reg = <0x0 0xff130000 0x0 0x1000>;
480 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
481 #address-cells = <1>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
485 rockchip,spi-src-clk = <2>;
487 clocks = <&clk_spi2>, <&clk_gates19 6>;
488 clock-names = "spi", "pclk_spi2";
489 //dmas = <&pdma1 15>, <&pdma1 16>;
491 //dma-names = "tx", "rx";
495 uart_bt: serial@ff180000 {
496 compatible = "rockchip,serial";
497 reg = <0x0 0xff180000 0x0 0x100>;
498 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
499 clock-frequency = <24000000>;
500 clocks = <&clk_uart0>, <&clk_gates19 7>;
501 clock-names = "sclk_uart", "pclk_uart";
504 //dmas = <&pdma1 1>, <&pdma1 2>;
506 pinctrl-names = "default";
507 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
511 uart_bb: serial@ff190000 {
512 compatible = "rockchip,serial";
513 reg = <0x0 0xff190000 0x0 0x100>;
514 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
515 clock-frequency = <24000000>;
516 clocks = <&clk_uart1>, <&clk_gates19 8>;
517 clock-names = "sclk_uart", "pclk_uart";
520 //dmas = <&pdma1 3>, <&pdma1 4>;
522 pinctrl-names = "default";
523 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
527 uart_dbg: serial@ff690000 {
528 compatible = "rockchip,serial";
529 reg = <0x0 0xff690000 0x0 0x100>;
530 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
531 clock-frequency = <24000000>;
532 clocks = <&clk_uart2>, <&clk_gates13 5>;
533 clock-names = "sclk_uart", "pclk_uart";
536 //dmas = <&pdma0 4>, <&pdma0 5>;
538 //pinctrl-names = "default";
539 //pinctrl-0 = <&uart2_xfer>;
543 uart_gps: serial@ff1b0000 {
544 compatible = "rockchip,serial";
545 reg = <0x0 0xff1b0000 0x0 0x100>;
546 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
547 clock-frequency = <24000000>;
548 clocks = <&clk_uart3>, <&clk_gates19 9>;
549 clock-names = "sclk_uart", "pclk_uart";
550 current-speed = <115200>;
553 //dmas = <&pdma1 7>, <&pdma1 8>;
555 pinctrl-names = "default";
556 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
560 uart_exp: serial@ff1c0000 {
561 compatible = "rockchip,serial";
562 reg = <0x0 0xff1c0000 0x0 0x100>;
563 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
564 clock-frequency = <24000000>;
565 clocks = <&clk_uart4>, <&clk_gates19 10>;
566 clock-names = "sclk_uart", "pclk_uart";
569 //dmas = <&pdma1 9>, <&pdma1 10>;
571 pinctrl-names = "default";
572 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
576 mbox: mbox@ff6b0000 {
577 compatible = "rockchip,rk3368-mailbox";
578 reg = <0x0 0xff6b0000 0x0 0x1000>,
579 <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
580 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&clk_gates12 1>;
585 clock-names = "pclk_mailbox";
589 mbox_scpi: mbox-scpi {
590 compatible = "rockchip,mbox-scpi";
591 mboxes = <&mbox 0 &mbox 1>;
595 compatible = "rockchip,rk3368-ddr";
597 rockchip,ddrpctl = <&ddrpctl>;
598 rockchip,grf = <&grf>;
599 rockchip,msch = <&msch>;
602 rockchip_clocks_init: clocks-init{
603 compatible = "rockchip,clocks-init";
604 rockchip,clocks-init-parent =
605 <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
606 <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
607 <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
608 <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
609 rockchip,clocks-init-rate =
610 <&clk_gpll 576000000>, <&clk_core_b 792000000>,
611 <&clk_core_l 600000000>, <&clk_cpll 400000000>,
612 /*<&clk_npll 500000000>,*/ <&aclk_bus 300000000>,
613 <&hclk_bus 150000000>, <&pclk_bus 75000000>,
614 <&clk_crypto 150000000>, <&aclk_peri 300000000>,
615 <&hclk_peri 150000000>, <&pclk_peri 75000000>,
616 <&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>,
617 <&clk_cs 300000000>, <&clkin_trace 300000000>,
618 <&aclk_cci 600000000>, <&clk_mac 125000000>,
619 <&aclk_vio0 400000000>, <&hclk_vio 100000000>,
620 <&aclk_rga_pre 400000000>, <&clk_rga 400000000>,
621 <&clk_isp 400000000>, <&clk_edp 200000000>,
622 <&clk_gpu_core 400000000>, <&aclk_gpu_mem 400000000>,
623 <&aclk_gpu_cfg 400000000>, <&aclk_vepu 400000000>,
624 <&aclk_vdpu 400000000>, <&clk_hevc_core 300000000>,
625 <&clk_hevc_cabac 300000000>;
627 rockchip,clocks-uboot-has-init =
632 rockchip_clocks_enable: clocks-enable {
633 compatible = "rockchip,clocks-enable";
651 <&clk_gates12 12>,/*aclk_strc_sys*/
652 <&clk_gates12 6>,/*aclk_intmem1*/
653 <&clk_gates12 5>,/*aclk_intmem0*/
654 <&clk_gates12 4>,/*aclk_intmem*/
655 <&clk_gates13 9>,/*aclk_gic400*/
656 <&clk_gates12 9>,/*hclk_rom*/
659 <&clk_gates22 12>,/*pclk_timer0*/
660 <&clk_gates22 9>,/*pclk_alive_niu*/
661 <&clk_gates22 8>,/*pclk_grf*/
664 <&clk_gates23 5>,/*pclk_pmugrf*/
665 <&clk_gates23 3>,/*pclk_sgrf*/
666 <&clk_gates23 2>,/*pclk_pmu_noc*/
667 <&clk_gates23 1>,/*pclk_intmem1*/
668 <&clk_gates23 0>,/*pclk_pmu*/
671 <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
672 <&clk_gates20 8>,/*aclk_peri_niu*/
673 <&clk_gates21 4>,/*aclk_peri_mmu*/
674 <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
675 <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
676 <&clk_gates19 1>,/*pclk_peri_axi_matrix*/
678 <&clk_gates24 0>, /* g_clk_timer0 */
679 <&clk_gates24 1>, /* g_clk_timer1 */
683 <&clk_gates7 0>;/*clk_jtag*/
688 compatible = "rockchip,rk30-i2c";
689 reg = <0x0 0xff650000 0x0 0x1000>;
690 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
691 #address-cells = <1>;
693 pinctrl-names = "default", "gpio", "sleep";
694 pinctrl-0 = <&i2c0_xfer>;
695 pinctrl-1 = <&i2c0_gpio>;
696 pinctrl-2 = <&i2c0_sleep>;
697 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
698 clocks = <&clk_gates12 2>;
699 rockchip,check-idle = <1>;
705 compatible = "rockchip,rk30-i2c";
706 reg = <0x0 0xff660000 0x0 0x1000>;
707 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
708 #address-cells = <1>;
710 pinctrl-names = "default", "gpio", "sleep";
711 pinctrl-0 = <&i2c1_xfer>;
712 pinctrl-1 = <&i2c1_gpio>;
713 pinctrl-2 = <&i2c1_sleep>;
714 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
715 clocks = <&clk_gates12 3>;
716 rockchip,check-idle = <1>;
722 compatible = "rockchip,rk30-i2c";
723 reg = <0x0 0xff140000 0x0 0x1000>;
724 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
725 #address-cells = <1>;
727 pinctrl-names = "default", "gpio", "sleep";
728 pinctrl-0 = <&i2c2_xfer>;
729 pinctrl-1 = <&i2c2_gpio>;
730 pinctrl-2 = <&i2c2_sleep>;
731 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
732 clocks = <&clk_gates19 11>;
733 rockchip,check-idle = <1>;
739 compatible = "rockchip,rk30-i2c";
740 reg = <0x0 0xff150000 0x0 0x1000>;
741 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
742 #address-cells = <1>;
744 pinctrl-names = "default", "gpio", "sleep";
745 pinctrl-0 = <&i2c3_xfer>;
746 pinctrl-1 = <&i2c3_gpio>;
747 pinctrl-2 = <&i2c3_sleep>;
748 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
749 clocks = <&clk_gates19 12>;
750 rockchip,check-idle = <1>;
756 compatible = "rockchip,rk30-i2c";
757 reg = <0x0 0xff160000 0x0 0x1000>;
758 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
759 #address-cells = <1>;
761 pinctrl-names = "default", "gpio", "sleep";
762 pinctrl-0 = <&i2c4_xfer>;
763 pinctrl-1 = <&i2c4_gpio>;
764 pinctrl-2 = <&i2c4_sleep>;
765 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
766 clocks = <&clk_gates19 13>;
767 rockchip,check-idle = <1>;
773 compatible = "rockchip,rk30-i2c";
774 reg = <0x0 0xff170000 0x0 0x1000>;
775 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
776 #address-cells = <1>;
778 pinctrl-names = "default", "gpio", "sleep";
779 pinctrl-0 = <&i2c5_xfer>;
780 pinctrl-1 = <&i2c5_gpio>;
781 pinctrl-2 = <&i2c5_sleep>;
782 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
783 clocks = <&clk_gates19 14>;
784 rockchip,check-idle = <1>;
789 compatible = "rockchip,rk-fb";
790 rockchip,disp-mode = <NO_DUAL>;
794 rk_screen: rk_screen {
795 compatible = "rockchip,screen";
798 dsihost0: mipi@ff960000{
799 compatible = "rockchip,rk3368-dsi";
801 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
802 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
803 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
804 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>, <&pd_mipidsi>;
805 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host", "pd_mipi_dsi";
809 lvds: lvds@ff968000 {
810 compatible = "rockchip,rk3368-lvds";
811 rockchip,grf = <&grf>;
812 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
813 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
814 clocks = <&clk_gates22 10>, <&clk_gates17 3>, <&pd_lvds>;
815 clock-names = "pclk_lvds", "pclk_lvds_ctl", "pd_lvds";
820 compatible = "rockchip,rk32-edp";
821 reg = <0x0 0xff970000 0x0 0x4000>;
822 rockchip,grf = <&grf>;
823 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
825 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
826 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
827 reset-names = "edp_24m", "edp_apb";
830 hdmi: hdmi@ff980000 {
831 compatible = "rockchip,rk3368-hdmi";
832 reg = <0x0 0xff980000 0x0 0x20000>;
833 rockchip,grf = <&grf>;
834 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
835 pinctrl-names = "default", "gpio";
836 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
837 pinctrl-1 = <&i2c5_gpio>;
838 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
839 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
843 hdmi_hdcp2: hdmi_hdcp2@ff978000 {
844 compatible = "rockchip,rk3368-hdmi-hdcp2";
845 reg = <0x0 0xff978000 0x0 0x2000>;
846 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
847 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
848 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
852 lcdc: lcdc@ff930000 {
853 compatible = "rockchip,rk3368-lcdc";
854 rockchip,grf = <&grf>;
855 rockchip,pmugrf = <&pmugrf>;
856 rockchip,cru = <&cru>;
857 rockchip,prop = <PRMRY>;
858 rockchip,pwr18 = <0>;
859 rockchip,iommu-enabled = <1>;
860 reg = <0x0 0xff930000 0x0 0x10000>;
861 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
862 /*pinctrl-names = "default", "gpio";
863 *pinctrl-0 = <&lcdc_lcdc>;
864 *pinctrl-1 = <&lcdc_gpio>;
867 clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>, <&pd_vop>;
868 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll", "pd_lcdc";
872 compatible = "rockchip,saradc";
873 reg = <0x0 0xff100000 0x0 0x100>;
874 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
875 #io-channel-cells = <1>;
877 rockchip,adc-vref = <1800>;
878 clock-frequency = <1000000>;
879 clocks = <&clk_saradc>, <&clk_gates19 15>;
880 clock-names = "saradc", "pclk_saradc";
885 compatible = "rockchip,rga2";
886 reg = <0x0 0xff920000 0x0 0x1000>;
887 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
888 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
889 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
892 i2s0: i2s0@ff898000 {
893 compatible = "rockchip-i2s";
894 reg = <0x0 0xff898000 0x0 0x1000>;
896 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
897 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
898 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
899 dmas = <&pdma0 0>, <&pdma0 1>;
901 dma-names = "tx", "rx";
902 pinctrl-names = "default", "sleep";
903 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
904 pinctrl-1 = <&i2s_gpio>;
907 i2s1: i2s1@ff890000 {
908 compatible = "rockchip-i2s";
909 reg = <0x0 0xff890000 0x0 0x1000>;
911 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
912 clock-names = "i2s_clk", "i2s_hclk";
913 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
914 dmas = <&pdma0 6>, <&pdma0 7>;
916 dma-names = "tx", "rx";
919 spdif: spdif@ff880000 {
920 compatible = "rockchip-spdif";
921 reg = <0x0 0xff880000 0x0 0x1000>;
922 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
923 clock-names = "spdif_mclk", "spdif_hclk";
924 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
928 pinctrl-names = "default";
929 pinctrl-0 = <&spdif_tx>;
933 compatible = "rockchip,rk-pwm";
934 reg = <0x0 0xff680000 0x0 0x10>;
936 pinctrl-names = "default";
937 pinctrl-0 = <&pwm0_pin>;
938 clocks = <&clk_gates13 6>;
939 clock-names = "pclk_pwm";
944 compatible = "rockchip,rk-pwm";
945 reg = <0x0 0xff680010 0x0 0x10>;
947 pinctrl-names = "default";
948 pinctrl-0 = <&pwm1_pin>;
949 clocks = <&clk_gates13 6>;
950 clock-names = "pclk_pwm";
955 compatible = "rockchip,rk-pwm";
956 reg = <0x0 0xff680020 0x0 0x10>;
958 //pinctrl-names = "default";
959 //pinctrl-0 = <&pwm1_pin>;
960 clocks = <&clk_gates13 6>;
961 clock-names = "pclk_pwm";
966 compatible = "rockchip,rk-pwm";
967 reg = <0x0 0xff680030 0x0 0x10>;
969 pinctrl-names = "default";
970 pinctrl-0 = <&pwm3_pin>;
971 clocks = <&clk_gates13 6>;
972 clock-names = "pclk_pwm";
976 remotectl: pwm@ff680030 {
977 compatible = "rockchip,remotectl-pwm";
978 reg = <0x0 0xff680030 0x0 0x50>;
980 pinctrl-names = "default";
981 pinctrl-0 = <&pwm3_pin>;
982 clocks = <&clk_gates13 6>;
983 clock-names = "pclk_pwm";
988 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
992 voppwm: pwm@ff9301a0 {
993 compatible = "rockchip,vop-pwm";
994 reg = <0x0 0xff9301a0 0x0 0x10>;
996 pinctrl-names = "default";
997 pinctrl-0 = <&vop_pwm_pin>;
998 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
999 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
1000 status = "disabled";
1004 compatible = "rockchip,rk3368-pvtm";
1005 rockchip,grf = <&grf>;
1006 rockchip,pmugrf = <&pmugrf>;
1007 rockchip,pvtm-clk-out = <1>;
1011 compatible = "rockchip,rk3368-cpufreq";
1012 rockchip,grf = <&grf>;
1018 regulator_name = "vdd_arm";
1019 suspend_volt = <1000>; //mV
1021 clk_core_b_dvfs_table: clk_core_b {
1022 operating-points = <
1030 temp-limit-enable = <1>;
1032 min_temp_limit = <216000>;
1033 normal-temp-limit = <
1034 /*delta-temp delta-freq*/
1040 performance-temp-limit = <
1044 lkg_adjust_volt_en = <1>;
1046 def_table_lkg = <25>;
1047 min_adjust_freq = <216000>;
1048 lkg_adjust_volt_table = <
1049 /*lkg(mA) volt(uV)*/
1053 clk_core_l_dvfs_table: clk_core_l {
1054 operating-points = <
1062 temp-limit-enable = <1>;
1064 min_temp_limit = <216000>;
1065 normal-temp-limit = <
1066 /*delta-temp delta-freq*/
1072 performance-temp-limit = <
1076 lkg_adjust_volt_en = <1>;
1078 def_table_lkg = <25>;
1079 min_adjust_freq = <216000>;
1080 lkg_adjust_volt_table = <
1081 /*lkg(mA) volt(uV)*/
1088 vd_logic: vd_logic {
1089 regulator_name = "vdd_logic";
1090 suspend_volt = <1000>; //mV
1092 clk_ddr_dvfs_table: clk_ddr {
1093 operating-points = <
1100 /* bandwidth freq */
1109 status = "disabled";
1114 clk_gpu_dvfs_table: clk_gpu {
1115 operating-points = <
1135 compatible = "rockchip,ion";
1136 #address-cells = <1>;
1139 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1140 compatible = "rockchip,ion-heap";
1141 rockchip,ion_heap = <4>;
1142 reg = <0x00000000 0x00000000>; /* 0MB */
1144 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1145 compatible = "rockchip,ion-heap";
1146 rockchip,ion_heap = <0>;
1151 compatible = "rockchip,vpu_sub";
1152 iommu_enabled = <1>;
1153 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1154 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1155 interrupt-names = "irq_enc", "irq_dec";
1157 name = "vpu_service";
1160 hevc: hevc_service {
1161 compatible = "rockchip,hevc_sub";
1162 iommu_enabled = <1>;
1163 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1164 interrupt-names = "irq_dec";
1166 name = "hevc_service";
1169 vpu_combo: vpu_combo@ff9a0000 {
1170 compatible = "rockchip,vpu_combo";
1171 reg = <0x0 0xff9a0000 0x0 0x800>;
1172 rockchip,grf = <&grf>;
1174 rockchip,sub = <&vpu>, <&hevc>;
1175 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1176 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1178 mode_ctrl = <0x418>;
1184 compatible = "rockchip,iep";
1185 iommu_enabled = <1>;
1186 reg = <0x0 0xff900000 0x0 0x800>;
1187 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1188 clocks = <&clk_gates16 2>, <&clk_gates16 3>;
1189 clock-names = "aclk_iep", "hclk_iep";
1193 gmac: eth@ff290000 {
1194 compatible = "rockchip,rk3368-gmac";
1195 reg = <0x0 0xff290000 0x0 0x10000>;
1196 rockchip,grf = <&grf>;
1197 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
1198 interrupt-names = "macirq";
1200 clocks = <&clk_mac>, <&clk_gates7 4>,
1201 <&clk_gates7 5>, <&clk_gates7 6>,
1202 <&clk_gates7 7>, <&clk_gates20 13>,
1204 clock-names = "clk_mac", "mac_clk_rx",
1205 "mac_clk_tx", "clk_mac_ref",
1206 "clk_mac_refout", "aclk_mac",
1210 pinctrl-names = "default";
1211 pinctrl-0 = <&rgmii_pins>;
1212 status = "disabled";
1216 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1217 reg = <0x0 0xffa30000 0x0 0x10000>;
1218 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1219 interrupt-names = "GPU";
1224 compatible = "rockchip,iep_mmu";
1225 reg = <0x0 0xff900800 0x0 0x100>;
1226 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1227 interrupt-names = "iep_mmu";
1232 compatible = "rockchip,vip_mmu";
1233 reg = <0x0 0xff950800 0x0 0x100>;
1234 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1235 interrupt-names = "vip_mmu";
1240 compatible = "rockchip,vopb_mmu";
1241 reg = <0x0 0xff930300 0x0 0x100>;
1242 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1243 interrupt-names = "vop_mmu";
1247 dbgname = "isp_mmu";
1248 compatible = "rockchip,isp_mmu";
1249 reg = <0x0 0xff914000 0x0 0x100>,
1250 <0x0 0xff915000 0x0 0x100>;
1251 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1252 interrupt-names = "isp_mmu";
1256 dbgname = "hdcp_mmu";
1257 compatible = "rockchip,hdcp_mmu";
1258 reg = <0x0 0xff940000 0x0 0x100>;
1259 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1260 interrupt-names = "hdcp_mmu";
1265 compatible = "rockchip,hevc_mmu";
1266 reg = <0x0 0xff9a0440 0x0 0x40>, /*need to fix*/
1267 <0x0 0xff9a0480 0x0 0x40>;
1268 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1269 interrupt-names = "hevc_mmu";
1274 compatible = "rockchip,vpu_mmu";
1275 reg = <0x0 0xff9a0800 0x0 0x100>; /*need to fix*/
1276 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /*need to fix*/
1277 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1278 interrupt-names = "vepu_mmu", "vdpu_mmu";
1281 rockchip_suspend: rockchip_suspend {
1282 rockchip,ctrbits = <
1285 | RKPM_SLP_PMU_PLLS_PWRDN
1286 /*| RKPM_SLP_PMU_PMUALIVE_32K
1287 | RKPM_SLP_SFT_PLLS_DEEP
1288 | RKPM_SLP_PMU_DIS_OSC */
1289 | RKPM_SLP_SFT_PD_NBSCUS
1295 compatible = "rockchip,isp";
1296 reg = <0x0 0xff910000 0x0 0x10000>;
1297 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&clk_gates16 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>, <&pd_isp>, <&clk_gates16 9>;
1299 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx", "pd_isp", "clk_vio0_noc";
1300 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1301 pinctrl-0 = <&cif_clkout>;
1302 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1303 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1304 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1305 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1306 pinctrl-5 = <&cif_clkout>;
1307 pinctrl-6 = <&cif_clkout &isp_prelight>;
1308 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1309 pinctrl-8 = <&isp_flash_trigger>;
1310 rockchip,isp,mipiphy = <2>;
1311 rockchip,isp,cifphy = <1>;
1312 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1313 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1314 rockchip,grf = <&grf>;
1315 rockchip,cru = <&cru>;
1316 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1317 rockchip,isp,iommu_enable = <1>;
1322 compatible = "rockchip,cif";
1323 reg = <0x0 0xff950000 0x0 0x10000>;
1324 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1325 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1326 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1327 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1328 pinctrl-names = "cif_pin_all";
1329 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1330 rockchip,grf = <&grf>;
1331 rockchip,cru = <&cru>;
1337 #include "rk3368-thermal.dtsi"
1341 tsadc: tsadc@ff280000 {
1342 compatible = "rockchip,rk3368-tsadc";
1343 reg = <0x0 0xff280000 0x0 0x100>;
1344 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1345 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1346 rockchip,grf = <&grf>;
1347 rockchip,cru = <&cru>;
1348 rockchip,pmu = <&pmu>;
1349 clock-names = "tsadc", "apb_pclk";
1350 clock-frequency = <32000>;
1351 resets = <&reset RK3368_SRST_TSADC_P>;
1352 reset-names = "tsadc-apb";
1353 //pinctrl-names = "default";
1354 //pinctrl-0 = <&tsadc_int>;
1355 #thermal-sensor-cells = <1>;
1356 hw-shut-temp = <120000>;
1357 status = "disabled";
1361 compatible = "rockchip,rk3368-tsp";
1362 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1363 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1364 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1365 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1366 interrupt-names = "irq_tsp";
1367 // pinctrl-names = "default";
1368 // pinctrl-0 = <&isp_hsadc>;
1372 crypto: crypto@FF8A0000{
1373 compatible = "rockchip,rk3368-crypto";
1374 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1375 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1376 interrupt-names = "irq_crypto";
1377 clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1378 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1382 dwc_control_usb: dwc-control-usb {
1383 compatible = "rockchip,rk3368-dwc-control-usb";
1384 rockchip,grf = <&grf>;
1385 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1386 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1387 interrupt-names = "otg_id", "otg_bvalid",
1388 "otg_linestate", "host0_linestate";
1389 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1390 clock-names = "hclk_usb_peri", "usbphy_480m";
1391 //resets = <&reset RK3128_RST_USBPOR>;
1392 //reset-names = "usbphy_por";
1394 compatible = "inno,phy";
1395 regbase = &dwc_control_usb;
1396 rk_usb,bvalid = <0x4bc 23 1>;
1397 rk_usb,iddig = <0x4bc 26 1>;
1398 rk_usb,vdmsrcen = <0x718 12 1>;
1399 rk_usb,vdpsrcen = <0x718 11 1>;
1400 rk_usb,rdmpden = <0x718 10 1>;
1401 rk_usb,idpsrcen = <0x718 9 1>;
1402 rk_usb,idmsinken = <0x718 8 1>;
1403 rk_usb,idpsinken = <0x718 7 1>;
1404 rk_usb,dpattach = <0x4b8 31 1>;
1405 rk_usb,cpdet = <0x4b8 30 1>;
1406 rk_usb,dcpattach = <0x4b8 29 1>;
1411 compatible = "rockchip,rk3368-usb-phy";
1412 rockchip,grf = <&grf>;
1413 #address-cells = <1>;
1427 usb0: usb@ff580000 {
1428 compatible = "rockchip,rk3368_usb20_otg";
1429 reg = <0x0 0xff580000 0x0 0x40000>;
1430 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1431 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1432 clock-names = "clk_usbphy0", "hclk_otg";
1433 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1434 <&reset RK3368_SRST_USBOTGC0>;
1435 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1436 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1437 rockchip,usb-mode = <0>;
1440 usb_ehci: usb@ff500000 {
1441 compatible = "generic-ehci";
1442 reg = <0x0 0xff500000 0x0 0x20000>;
1443 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1444 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1445 clock-names = "clk_usbphy0", "hclk_ehci";
1448 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1449 // <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1450 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1453 usb_ohci: usb@ff520000 {
1454 compatible = "generic-ohci";
1455 reg = <0x0 0xff520000 0x0 0x20000>;
1456 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1457 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1458 clock-names = "clk_usbphy0", "hclk_ohci";
1461 usb_ehci1: usb@ff5c0000 {
1462 compatible = "rockchip,rk3288_rk_ehci1_host";
1463 reg = <0x0 0xff5c0000 0x0 0x40000>;
1464 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1466 clocks = <&ehci1phy_480m>, <&clk_gates7 8>,
1467 <&ehci1phy_12m>, <&usbphy_480m>,
1468 <&otgphy1_480m>, <&otgphy2_480m>;
1469 clock-names = "ehci1phy_480m", "hclk_ehci1",
1470 "ehci1phy_12m", "usbphy_480m",
1471 "ehci1_usbphy1", "ehci1_usbphy2";
1472 resets = <&reset RK3368_SRST_EHCI1>, <&reset RK3368_SRST_EHCI1_AUX>,
1473 <&reset RK3368_SRST_EHCI1PHY>;
1474 reset-names = "ehci1_ahb", "ehci1_aux", "ehci1_phy";
1476 status = "disabled";
1480 compatible = "rockchip,rk3368-pinctrl";
1481 rockchip,grf = <&grf>;
1482 rockchip,pmugrf = <&pmugrf>;
1483 #address-cells = <2>;
1487 gpio0: gpio0@ff750000 {
1488 compatible = "rockchip,gpio-bank";
1489 reg = <0x0 0xff750000 0x0 0x100>;
1490 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1491 clocks = <&clk_gates23 4>;
1496 interrupt-controller;
1497 #interrupt-cells = <2>;
1500 gpio1: gpio1@ff780000 {
1501 compatible = "rockchip,gpio-bank";
1502 reg = <0x0 0xff780000 0x0 0x100>;
1503 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1504 clocks = <&clk_gates22 1>;
1509 interrupt-controller;
1510 #interrupt-cells = <2>;
1513 gpio2: gpio2@ff790000 {
1514 compatible = "rockchip,gpio-bank";
1515 reg = <0x0 0xff790000 0x0 0x100>;
1516 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1517 clocks = <&clk_gates22 2>;
1522 interrupt-controller;
1523 #interrupt-cells = <2>;
1526 gpio3: gpio3@ff7a0000 {
1527 compatible = "rockchip,gpio-bank";
1528 reg = <0x0 0xff7a0000 0x0 0x100>;
1529 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1530 clocks = <&clk_gates22 3>;
1535 interrupt-controller;
1536 #interrupt-cells = <2>;
1539 pcfg_pull_up: pcfg-pull-up {
1543 pcfg_pull_down: pcfg-pull-down {
1547 pcfg_pull_none: pcfg-pull-none {
1551 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1552 drive-strength = <8>;
1555 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1556 drive-strength = <12>;
1559 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1561 drive-strength = <8>;
1564 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1565 drive-strength = <4>;
1568 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1570 drive-strength = <4>;
1573 pcfg_output_high: pcfg-output-high {
1577 pcfg_output_low: pcfg-output-low {
1581 pcfg_input_high: pcfg-input-high {
1587 i2c0_xfer: i2c0-xfer {
1588 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1589 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1591 i2c0_gpio: i2c0-gpio {
1592 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1593 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1595 i2c0_sleep: i2c0-sleep {
1596 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_input_high>,
1597 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_input_high>;
1602 i2c1_xfer: i2c1-xfer {
1603 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1604 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1606 i2c1_gpio: i2c1-gpio {
1607 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1608 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1610 i2c1_sleep: i2c1-sleep {
1611 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_input_high>,
1612 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_input_high>;
1617 i2c2_xfer: i2c2-xfer {
1618 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1619 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1621 i2c2_gpio: i2c2-gpio {
1622 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1623 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1625 i2c2_sleep: i2c2-sleep {
1626 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_input_high>,
1627 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_input_high>;
1632 i2c3_xfer: i2c3-xfer {
1633 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1634 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1636 i2c3_gpio: i2c3-gpio {
1637 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1638 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1640 i2c3_sleep: i2c3-sleep {
1641 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_input_high>,
1642 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_input_high>;
1647 i2c4_xfer: i2c4-xfer {
1648 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1649 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1651 i2c4_gpio: i2c4-gpio {
1652 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1653 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1655 i2c4_sleep: i2c4-sleep {
1656 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_input_high>,
1657 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_input_high>;
1662 i2c5_xfer: i2c5-xfer {
1663 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1664 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1666 i2c5_gpio: i2c5-gpio {
1667 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1668 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1670 i2c5_sleep: i2c5-sleep {
1671 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_input_high>,
1672 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_input_high>;
1677 uart0_xfer: uart0-xfer {
1678 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1679 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1682 uart0_cts: uart0-cts {
1683 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1686 uart0_rts: uart0-rts {
1687 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1690 uart0_rts_gpio: uart0-rts-gpio {
1691 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1696 uart1_xfer: uart1-xfer {
1697 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1698 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1701 uart1_cts: uart1-cts {
1702 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1705 uart1_rts: uart1-rts {
1706 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1711 uart2_xfer: uart2-xfer {
1712 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1713 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1718 uart3_xfer: uart3-xfer {
1719 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1720 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1723 uart3_cts: uart3-cts {
1724 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1727 uart3_rts: uart3-rts {
1728 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1733 uart4_xfer: uart4-xfer {
1734 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1735 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1738 uart4_cts: uart4-cts {
1739 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1742 uart4_rts: uart4-rts {
1743 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1748 spi0_clk: spi0-clk {
1749 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1751 spi0_cs0: spi0-cs0 {
1752 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1755 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1758 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1760 spi0_cs1: spi0-cs1 {
1761 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1766 spi1_clk: spi1-clk {
1767 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1769 spi1_cs0: spi1-cs0 {
1770 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1773 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1776 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1778 spi1_cs1: spi1-cs1 {
1779 rockchip,pins = <3 GPIO_D4 RK_FUNC_2 &pcfg_pull_up>;
1784 spi2_clk: spi2-clk {
1785 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1787 spi2_cs0: spi2-cs0 {
1788 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1791 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1794 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1799 i2s_mclk: i2s-mclk {
1800 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1804 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1807 i2s_lrckrx:i2s-lrckrx {
1808 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1811 i2s_lrcktx:i2s-lrcktx {
1812 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1816 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1820 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1824 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1828 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1832 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1835 i2s_gpio: i2s-gpio {
1836 rockchip,pins = <2 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,
1837 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1838 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1839 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1840 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1841 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1842 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1843 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1844 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1849 spdif_tx: spdif-tx {
1850 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1855 sdmmc_clk: sdmmc-clk {
1856 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1859 sdmmc_cmd: sdmmc-cmd {
1860 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1863 sdmmc_dectn: sdmmc-dectn {
1864 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1867 sdmmc_bus1: sdmmc-bus1 {
1868 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1871 sdmmc_bus4: sdmmc-bus4 {
1872 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1873 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1874 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1875 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1878 sdmmc_gpio: sdmmc-gpio {
1879 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1880 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1881 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1882 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1883 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1884 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1885 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1890 sdio0_bus1: sdio0-bus1 {
1891 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1894 sdio0_bus4: sdio0-bus4 {
1895 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1896 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1897 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1898 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1901 sdio0_cmd: sdio0-cmd {
1902 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1905 sdio0_clk: sdio0-clk {
1906 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1909 sdio0_dectn: sdio0-dectn {
1910 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1913 sdio0_wrprt: sdio0-wrprt {
1914 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1917 sdio0_pwren: sdio0-pwren {
1918 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1921 sdio0_bkpwr: sdio0-bkpwr {
1922 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1925 sdio0_int: sdio0-int {
1926 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1929 sdio0_gpio: sdio0-gpio {
1930 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1931 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1932 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1933 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1934 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1935 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1936 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1937 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1938 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1939 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1940 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1945 emmc_clk: emmc-clk {
1946 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1949 emmc_cmd: emmc-cmd {
1950 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1953 emmc_pwren: emmc-pwren {
1954 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1957 emmc_rstnout: emmc_rstnout {
1958 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1961 emmc_bus1: emmc-bus1 {
1962 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1965 emmc_bus4: emmc-bus4 {
1966 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1967 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1968 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1969 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1974 pwm0_pin: pwm0-pin {
1975 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1978 vop_pwm_pin:vop-pwm {
1979 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1984 pwm1_pin: pwm1-pin {
1985 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1990 pwm3_pin: pwm3-pin {
1991 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1996 lcdc_lcdc: lcdc-lcdc {
1998 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1999 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
2000 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
2001 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
2002 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
2003 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
2004 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
2005 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
2006 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
2007 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
2008 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
2009 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
2010 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
2011 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
2012 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
2013 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
2014 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
2015 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
2018 lcdc_gpio: lcdc-gpio {
2020 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
2021 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
2022 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
2023 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
2024 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
2025 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
2026 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
2027 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
2028 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
2029 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
2030 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
2031 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
2032 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
2033 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
2034 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
2035 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
2036 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
2037 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
2042 cif_clkout: cif-clkout {
2043 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2046 isp_dvp_d2d9: isp-dvp-d2d9 {
2047 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2048 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2049 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2050 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2051 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2052 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2053 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2054 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2055 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
2056 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
2057 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
2058 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2061 isp_dvp_d0d1: isp-dvp-d0d1 {
2062 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2063 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
2066 isp_dvp_d10d11:isp_d10d11 {
2067 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2068 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2071 isp_dvp_d0d7: isp-dvp-d0d7 {
2072 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2073 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
2074 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2075 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2076 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2077 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2078 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2079 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
2082 isp_shutter: isp-shutter {
2083 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2084 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2087 isp_flash_trigger: isp-flash-trigger {
2088 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2091 isp_prelight: isp-prelight {
2092 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2095 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2096 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
2102 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
2106 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
2110 gps_rfclk: gps-rfclk {
2111 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
2116 rgmii_pins: rgmii-pins {
2117 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2118 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2119 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2120 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2121 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2122 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
2123 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
2124 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
2125 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2126 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2127 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2128 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
2129 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
2130 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
2131 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
2134 rmii_pins: rmii-pins {
2135 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2136 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2137 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2138 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2139 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2140 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2141 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2142 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2143 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
2144 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
2149 tsadc_int: tsadc-int {
2150 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
2152 tsadc_gpio: tsadc-gpio {
2153 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
2158 hdmi_cec: hdmi-cec {
2159 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
2164 hdmii2c_xfer: hdmii2c-xfer {
2165 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
2166 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
2171 cpu_jtag: cpu-jtag {
2172 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_up>,
2173 <2 GPIO_B0 RK_FUNC_2 &pcfg_pull_up>;
2178 mcu_jtag: mcu-jtag {
2179 rockchip,pins = <2 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>,
2180 <2 GPIO_B1 RK_FUNC_2 &pcfg_pull_up>;
2186 compatible = "rockchip,rk3368-reboot";
2187 rockchip,cru = <&cru>;
2188 rockchip,pmugrf = <&pmugrf>;