1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include <dt-bindings/suspend/rockchip-rk3368.h>
3 #include <dt-bindings/pinctrl/rockchip.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/sensor-dev.h>
6 #include <dt-bindings/clock/rk_system_status.h>
8 #include "rk3368-clocks.dtsi"
11 compatible = "rockchip,rk3368";
13 rockchip,sram = <&sram>;
14 interrupt-parent = <&gic>;
41 entry-method = "arm,psci";
42 CPU_SLEEP_0: cpu-sleep-0 {
43 compatible = "arm,idle-state";
44 arm,psci-suspend-param = <0x1010000>;
45 entry-latency-us = <0x3fffffff>;
46 exit-latency-us = <0x40000000>;
47 min-residency-us = <0xffffffff>;
53 compatible = "arm,cortex-a53", "arm,armv8";
55 enable-method = "psci";
56 cpu-idle-states = <&CPU_SLEEP_0>;
60 compatible = "arm,cortex-a53", "arm,armv8";
62 enable-method = "psci";
63 cpu-idle-states = <&CPU_SLEEP_0>;
67 compatible = "arm,cortex-a53", "arm,armv8";
69 enable-method = "psci";
70 cpu-idle-states = <&CPU_SLEEP_0>;
74 compatible = "arm,cortex-a53", "arm,armv8";
76 enable-method = "psci";
77 cpu-idle-states = <&CPU_SLEEP_0>;
81 compatible = "arm,cortex-a53", "arm,armv8";
83 enable-method = "psci";
84 cpu-idle-states = <&CPU_SLEEP_0>;
88 compatible = "arm,cortex-a53", "arm,armv8";
90 enable-method = "psci";
91 cpu-idle-states = <&CPU_SLEEP_0>;
95 compatible = "arm,cortex-a53", "arm,armv8";
97 enable-method = "psci";
98 cpu-idle-states = <&CPU_SLEEP_0>;
102 compatible = "arm,cortex-a53", "arm,armv8";
104 enable-method = "psci";
105 cpu-idle-states = <&CPU_SLEEP_0>;
141 compatible = "arm,psci-0.2";
145 gic: interrupt-controller@ffb70000 {
146 compatible = "arm,cortex-a15-gic";
147 #interrupt-cells = <3>;
148 #address-cells = <0>;
149 interrupt-controller;
150 reg = <0x0 0xffb71000 0 0x1000>,
151 <0x0 0xffb72000 0 0x1000>;
154 ddrpctl: syscon@ff610000 {
155 compatible = "rockchip,rk3368-ddrpctl", "syscon";
156 reg = <0x0 0xff610000 0x0 0x400>;
159 pmu: syscon@ff730000 {
160 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
161 reg = <0x0 0xff730000 0x0 0x1000>;
164 pmugrf: syscon@ff738000 {
165 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
166 reg = <0x0 0xff738000 0x0 0x1000>;
169 sgrf: syscon@ff740000 {
170 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
171 reg = <0x0 0xff740000 0x0 0x1000>;
175 cru: syscon@ff760000 {
176 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
177 reg = <0x0 0xff760000 0x0 0x1000>;
180 grf: syscon@ff770000 {
181 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
182 reg = <0x0 0xff770000 0x0 0x1000>;
185 msch: syscon@ffac0000 {
186 compatible = "rockchip,rk3368-msch", "rockchip,msch", "syscon";
187 reg = <0x0 0xffac0000 0x0 0x3000>;
191 compatible = "arm,armv8-pmuv3";
192 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
202 cpu_axi_bus: cpu_axi_bus {
203 compatible = "rockchip,cpu_axi_bus";
204 #address-cells = <2>;
209 #address-cells = <2>;
214 reg = <0x0 0xffa80000 0x0 0x20>;
217 reg = <0x0 0xffa80080 0x0 0x20>;
220 reg = <0x0 0xffa80280 0x0 0x20>;
223 reg = <0x0 0xffa90000 0x0 0x20>;
226 reg = <0x0 0xffaa0000 0x0 0x20>;
229 reg = <0x0 0xffaa0080 0x0 0x20>;
232 reg = <0x0 0xffab0000 0x0 0x20>;
233 rockchip,priority = <2 2>;
236 reg = <0x0 0xffad0000 0x0 0x20>;
239 reg = <0x0 0xffad0080 0x0 0x20>;
242 reg = <0x0 0xffad0100 0x0 0x20>;
245 reg = <0x0 0xffad0180 0x0 0x20>;
246 rockchip,priority = <2 2>;
249 reg = <0x0 0xffad0200 0x0 0x20>;
250 rockchip,priority = <2 2>;
253 reg = <0x0 0xffad0280 0x0 0x20>;
256 reg = <0x0 0xffad0300 0x0 0x20>;
257 rockchip,priority = <2 2>;
260 reg = <0x0 0xffad0380 0x0 0x20>;
263 reg = <0x0 0xffad0400 0x0 0x20>;
266 reg = <0x0 0xffae0000 0x0 0x20>;
269 reg = <0x0 0xffae0100 0x0 0x20>;
272 reg = <0x0 0xffae0180 0x0 0x20>;
275 reg = <0x0 0xffaf0000 0x0 0x20>;
280 #address-cells = <2>;
285 reg = <0x0 0xffac0000 0x0 0x3c>;
286 rockchip,read-latency = <0x34>;
292 compatible = "rockchip,rk3368-efuse-256";
293 reg = <0x0 0xffb00000 0x0 0x8>;
297 compatible = "arm,armv8-timer";
298 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
299 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
300 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
301 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
302 clock-frequency = <24000000>;
306 compatible = "rockchip,timer";
307 reg = <0x0 0xff810000 0x0 0x20>;
308 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
309 rockchip,broadcast = <1>;
313 compatible = "rockchip,timer";
314 reg = <0x0 0xff810020 0x0 0x20>;
315 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
316 rockchip,percpu = <0>;
319 sram: sram@ff8c0000 {
320 compatible = "mmio-sram";
321 reg = <0x0 0xff8c0000 0x0 0xf000>; /* 60K (reserved 4K for mailbox)*/
325 watchdog: wdt@ff800000 {
326 compatible = "rockchip,watch dog";
327 reg = <0x0 0xff800000 0x0 0x100>;
328 clocks = <&pclk_alive_pre>;
329 clock-names = "pclk_wdt";
330 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
332 rockchip,timeout = <60>;
333 rockchip,atboot = <1>;
334 rockchip,debug = <0>;
339 #address-cells = <2>;
341 compatible = "arm,amba-bus";
342 interrupt-parent = <&gic>;
345 pdma0: pdma@ff600000 {
346 compatible = "arm,pl330", "arm,primecell";
347 reg = <0x0 0xff600000 0x0 0x4000>;
348 clocks = <&clk_gates12 11>;
349 clock-names = "apb_pclk";
350 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
356 pdma1: pdma@ff250000 {
357 compatible = "arm,pl330", "arm,primecell";
358 reg = <0x0 0xff250000 0x0 0x4000>;
359 clocks = <&clk_gates19 3>;
360 clock-names = "apb_pclk";
361 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
367 reset: reset@ff760300{
368 compatible = "rockchip,reset";
369 reg = <0x0 0xff760300 0x0 0x38>;
370 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
374 nandc0: nandc@ff400000 {
375 compatible = "rockchip,rk-nandc";
376 reg = <0x0 0xff400000 0x0 0x4000>;
377 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&clk_nandc0>, <&clk_gates20 9>, <&clk_gates20 11>;
380 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
383 nandc0reg: nandc0@ff400000 {
384 compatible = "rockchip,rk-nandc";
385 reg = <0x0 0xff400000 0x0 0x4000>;
388 emmc: rksdmmc@ff0f0000 {
389 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
390 reg = <0x0 0xff0f0000 0x0 0x4000>;
391 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
392 #address-cells = <1>;
394 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
395 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
396 rockchip,grf = <&grf>;
398 fifo-depth = <0x100>;
402 sdmmc: rksdmmc@ff0c0000 {
403 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
404 reg = <0x0 0xff0c0000 0x0 0x4000>;
405 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
406 #address-cells = <1>;
408 pinctrl-names = "default", "idle", "udbg";
409 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
410 pinctrl-1 = <&sdmmc_gpio>;
411 pinctrl-2 = <&uart2_xfer &cpu_jtag &mcu_jtag &sdmmc_dectn>;
412 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
413 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
414 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
415 rockchip,grf = <&grf>;
417 fifo-depth = <0x100>;
421 sdio: rksdmmc@ff0d0000 {
422 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
423 reg = <0x0 0xff0d0000 0x0 0x4000>;
424 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
425 #address-cells = <1>;
427 pinctrl-names = "default","idle";
428 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
429 pinctrl-1 = <&sdio0_gpio>;
430 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
431 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
432 rockchip,grf = <&grf>;
434 fifo-depth = <0x100>;
439 compatible = "rockchip,rockchip-spi";
440 reg = <0x0 0xff110000 0x0 0x1000>;
441 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
442 #address-cells = <1>;
444 pinctrl-names = "default";
445 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
446 rockchip,spi-src-clk = <0>;
448 clocks =<&clk_spi0>, <&clk_gates19 4>;
449 clock-names = "spi", "pclk_spi0";
450 //dmas = <&pdma1 11>, <&pdma1 12>;
452 //dma-names = "tx", "rx";
457 compatible = "rockchip,rockchip-spi";
458 reg = <0x0 0xff120000 0x0 0x1000>;
459 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
460 #address-cells = <1>;
462 pinctrl-names = "default";
463 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0 &spi1_cs1>;
464 rockchip,spi-src-clk = <1>;
466 clocks = <&clk_spi1>, <&clk_gates19 5>;
467 clock-names = "spi", "pclk_spi1";
468 //dmas = <&pdma1 13>, <&pdma1 14>;
470 //dma-names = "tx", "rx";
475 compatible = "rockchip,rockchip-spi";
476 reg = <0x0 0xff130000 0x0 0x1000>;
477 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
478 #address-cells = <1>;
480 pinctrl-names = "default";
481 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
482 rockchip,spi-src-clk = <2>;
484 clocks = <&clk_spi2>, <&clk_gates19 6>;
485 clock-names = "spi", "pclk_spi2";
486 //dmas = <&pdma1 15>, <&pdma1 16>;
488 //dma-names = "tx", "rx";
492 uart_bt: serial@ff180000 {
493 compatible = "rockchip,serial";
494 reg = <0x0 0xff180000 0x0 0x100>;
495 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
496 clock-frequency = <24000000>;
497 clocks = <&clk_uart0>, <&clk_gates19 7>;
498 clock-names = "sclk_uart", "pclk_uart";
501 //dmas = <&pdma1 1>, <&pdma1 2>;
503 pinctrl-names = "default";
504 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
508 uart_bb: serial@ff190000 {
509 compatible = "rockchip,serial";
510 reg = <0x0 0xff190000 0x0 0x100>;
511 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
512 clock-frequency = <24000000>;
513 clocks = <&clk_uart1>, <&clk_gates19 8>;
514 clock-names = "sclk_uart", "pclk_uart";
517 //dmas = <&pdma1 3>, <&pdma1 4>;
519 pinctrl-names = "default";
520 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
524 uart_dbg: serial@ff690000 {
525 compatible = "rockchip,serial";
526 reg = <0x0 0xff690000 0x0 0x100>;
527 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
528 clock-frequency = <24000000>;
529 clocks = <&clk_uart2>, <&clk_gates13 5>;
530 clock-names = "sclk_uart", "pclk_uart";
533 //dmas = <&pdma0 4>, <&pdma0 5>;
535 //pinctrl-names = "default";
536 //pinctrl-0 = <&uart2_xfer>;
540 uart_gps: serial@ff1b0000 {
541 compatible = "rockchip,serial";
542 reg = <0x0 0xff1b0000 0x0 0x100>;
543 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
544 clock-frequency = <24000000>;
545 clocks = <&clk_uart3>, <&clk_gates19 9>;
546 clock-names = "sclk_uart", "pclk_uart";
547 current-speed = <115200>;
550 //dmas = <&pdma1 7>, <&pdma1 8>;
552 pinctrl-names = "default";
553 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
557 uart_exp: serial@ff1c0000 {
558 compatible = "rockchip,serial";
559 reg = <0x0 0xff1c0000 0x0 0x100>;
560 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
561 clock-frequency = <24000000>;
562 clocks = <&clk_uart4>, <&clk_gates19 10>;
563 clock-names = "sclk_uart", "pclk_uart";
566 //dmas = <&pdma1 9>, <&pdma1 10>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
573 mbox: mbox@ff6b0000 {
574 compatible = "rockchip,rk3368-mailbox";
575 reg = <0x0 0xff6b0000 0x0 0x1000>,
576 <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
577 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&clk_gates12 1>;
582 clock-names = "pclk_mailbox";
586 mbox_scpi: mbox-scpi {
587 compatible = "rockchip,mbox-scpi";
588 mboxes = <&mbox 0 &mbox 1>;
592 compatible = "rockchip,rk3368-ddr";
594 rockchip,ddrpctl = <&ddrpctl>;
595 rockchip,grf = <&grf>;
596 rockchip,msch = <&msch>;
599 rockchip_clocks_init: clocks-init{
600 compatible = "rockchip,clocks-init";
601 rockchip,clocks-init-parent =
602 <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
603 <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
604 <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
605 <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
606 rockchip,clocks-init-rate =
607 <&clk_gpll 576000000>, <&clk_core_b 792000000>,
608 <&clk_core_l 600000000>, <&clk_cpll 400000000>,
609 /*<&clk_npll 500000000>,*/ <&aclk_bus 300000000>,
610 <&hclk_bus 150000000>, <&pclk_bus 75000000>,
611 <&clk_crypto 150000000>, <&aclk_peri 300000000>,
612 <&hclk_peri 150000000>, <&pclk_peri 75000000>,
613 <&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>,
614 <&clk_cs 300000000>, <&clkin_trace 300000000>,
615 <&aclk_cci 600000000>, <&clk_mac 125000000>,
616 <&aclk_vio0 400000000>, <&hclk_vio 100000000>,
617 <&aclk_rga_pre 400000000>, <&clk_rga 400000000>,
618 <&clk_isp 400000000>, <&clk_edp 200000000>,
619 <&clk_gpu_core 400000000>, <&aclk_gpu_mem 400000000>,
620 <&aclk_gpu_cfg 400000000>, <&aclk_vepu 400000000>,
621 <&aclk_vdpu 400000000>, <&clk_hevc_core 300000000>,
622 <&clk_hevc_cabac 300000000>;
624 rockchip,clocks-uboot-has-init =
629 rockchip_clocks_enable: clocks-enable {
630 compatible = "rockchip,clocks-enable";
648 <&clk_gates12 12>,/*aclk_strc_sys*/
649 <&clk_gates12 6>,/*aclk_intmem1*/
650 <&clk_gates12 5>,/*aclk_intmem0*/
651 <&clk_gates12 4>,/*aclk_intmem*/
652 <&clk_gates13 9>,/*aclk_gic400*/
653 <&clk_gates12 9>,/*hclk_rom*/
656 <&clk_gates22 12>,/*pclk_timer0*/
657 <&clk_gates22 9>,/*pclk_alive_niu*/
658 <&clk_gates22 8>,/*pclk_grf*/
661 <&clk_gates23 5>,/*pclk_pmugrf*/
662 <&clk_gates23 3>,/*pclk_sgrf*/
663 <&clk_gates23 2>,/*pclk_pmu_noc*/
664 <&clk_gates23 1>,/*pclk_intmem1*/
665 <&clk_gates23 0>,/*pclk_pmu*/
668 <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
669 <&clk_gates20 8>,/*aclk_peri_niu*/
670 <&clk_gates21 4>,/*aclk_peri_mmu*/
671 <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
672 <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
673 <&clk_gates19 1>,/*pclk_peri_axi_matrix*/
675 <&clk_gates24 0>, /* g_clk_timer0 */
676 <&clk_gates24 1>, /* g_clk_timer1 */
680 <&clk_gates7 0>;/*clk_jtag*/
685 compatible = "rockchip,rk30-i2c";
686 reg = <0x0 0xff650000 0x0 0x1000>;
687 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
688 #address-cells = <1>;
690 pinctrl-names = "default", "gpio", "sleep";
691 pinctrl-0 = <&i2c0_xfer>;
692 pinctrl-1 = <&i2c0_gpio>;
693 pinctrl-2 = <&i2c0_sleep>;
694 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
695 clocks = <&clk_gates12 2>;
696 rockchip,check-idle = <1>;
702 compatible = "rockchip,rk30-i2c";
703 reg = <0x0 0xff660000 0x0 0x1000>;
704 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
705 #address-cells = <1>;
707 pinctrl-names = "default", "gpio", "sleep";
708 pinctrl-0 = <&i2c1_xfer>;
709 pinctrl-1 = <&i2c1_gpio>;
710 pinctrl-2 = <&i2c1_sleep>;
711 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
712 clocks = <&clk_gates12 3>;
713 rockchip,check-idle = <1>;
719 compatible = "rockchip,rk30-i2c";
720 reg = <0x0 0xff140000 0x0 0x1000>;
721 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
722 #address-cells = <1>;
724 pinctrl-names = "default", "gpio", "sleep";
725 pinctrl-0 = <&i2c2_xfer>;
726 pinctrl-1 = <&i2c2_gpio>;
727 pinctrl-2 = <&i2c2_sleep>;
728 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
729 clocks = <&clk_gates19 11>;
730 rockchip,check-idle = <1>;
736 compatible = "rockchip,rk30-i2c";
737 reg = <0x0 0xff150000 0x0 0x1000>;
738 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
739 #address-cells = <1>;
741 pinctrl-names = "default", "gpio", "sleep";
742 pinctrl-0 = <&i2c3_xfer>;
743 pinctrl-1 = <&i2c3_gpio>;
744 pinctrl-2 = <&i2c3_sleep>;
745 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
746 clocks = <&clk_gates19 12>;
747 rockchip,check-idle = <1>;
753 compatible = "rockchip,rk30-i2c";
754 reg = <0x0 0xff160000 0x0 0x1000>;
755 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
756 #address-cells = <1>;
758 pinctrl-names = "default", "gpio", "sleep";
759 pinctrl-0 = <&i2c4_xfer>;
760 pinctrl-1 = <&i2c4_gpio>;
761 pinctrl-2 = <&i2c4_sleep>;
762 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
763 clocks = <&clk_gates19 13>;
764 rockchip,check-idle = <1>;
770 compatible = "rockchip,rk30-i2c";
771 reg = <0x0 0xff170000 0x0 0x1000>;
772 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
773 #address-cells = <1>;
775 pinctrl-names = "default", "gpio", "sleep";
776 pinctrl-0 = <&i2c5_xfer>;
777 pinctrl-1 = <&i2c5_gpio>;
778 pinctrl-2 = <&i2c5_sleep>;
779 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
780 clocks = <&clk_gates19 14>;
781 rockchip,check-idle = <1>;
786 compatible = "rockchip,rk-fb";
787 rockchip,disp-mode = <NO_DUAL>;
791 rk_screen: rk_screen {
792 compatible = "rockchip,screen";
795 dsihost0: mipi@ff960000{
796 compatible = "rockchip,rk3368-dsi";
798 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
799 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
800 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>, <&pd_mipidsi>;
802 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host", "pd_mipi_dsi";
806 lvds: lvds@ff968000 {
807 compatible = "rockchip,rk3368-lvds";
808 rockchip,grf = <&grf>;
809 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
810 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
811 clocks = <&clk_gates22 10>, <&clk_gates17 3>, <&pd_lvds>;
812 clock-names = "pclk_lvds", "pclk_lvds_ctl", "pd_lvds";
817 compatible = "rockchip,rk32-edp";
818 reg = <0x0 0xff970000 0x0 0x4000>;
819 rockchip,grf = <&grf>;
820 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
822 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
823 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
824 reset-names = "edp_24m", "edp_apb";
827 hdmi: hdmi@ff980000 {
828 compatible = "rockchip,rk3368-hdmi";
829 reg = <0x0 0xff980000 0x0 0x20000>;
830 rockchip,grf = <&grf>;
831 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
832 pinctrl-names = "default", "gpio";
833 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
834 pinctrl-1 = <&i2c5_gpio>;
835 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
836 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
840 hdmi_hdcp2: hdmi_hdcp2@ff978000 {
841 compatible = "rockchip,rk3368-hdmi-hdcp2";
842 reg = <0x0 0xff978000 0x0 0x2000>;
843 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
845 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
849 lcdc: lcdc@ff930000 {
850 compatible = "rockchip,rk3368-lcdc";
851 rockchip,grf = <&grf>;
852 rockchip,pmugrf = <&pmugrf>;
853 rockchip,cru = <&cru>;
854 rockchip,prop = <PRMRY>;
855 rockchip,pwr18 = <0>;
856 rockchip,iommu-enabled = <1>;
857 reg = <0x0 0xff930000 0x0 0x10000>;
858 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
859 /*pinctrl-names = "default", "gpio";
860 *pinctrl-0 = <&lcdc_lcdc>;
861 *pinctrl-1 = <&lcdc_gpio>;
864 clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>, <&pd_vop>;
865 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll", "pd_lcdc";
869 compatible = "rockchip,saradc";
870 reg = <0x0 0xff100000 0x0 0x100>;
871 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
872 #io-channel-cells = <1>;
874 rockchip,adc-vref = <1800>;
875 clock-frequency = <1000000>;
876 clocks = <&clk_saradc>, <&clk_gates19 15>;
877 clock-names = "saradc", "pclk_saradc";
882 compatible = "rockchip,rk3368-rga2";
883 reg = <0x0 0xff920000 0x0 0x1000>;
884 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
886 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
889 i2s0: i2s0@ff898000 {
890 compatible = "rockchip-i2s";
891 reg = <0x0 0xff898000 0x0 0x1000>;
893 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
894 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
895 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
896 dmas = <&pdma0 0>, <&pdma0 1>;
898 dma-names = "tx", "rx";
899 pinctrl-names = "default", "sleep";
900 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
901 pinctrl-1 = <&i2s_gpio>;
904 i2s1: i2s1@ff890000 {
905 compatible = "rockchip-i2s";
906 reg = <0x0 0xff890000 0x0 0x1000>;
908 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
909 clock-names = "i2s_clk", "i2s_hclk";
910 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
911 dmas = <&pdma0 6>, <&pdma0 7>;
913 dma-names = "tx", "rx";
916 spdif: spdif@ff880000 {
917 compatible = "rockchip-spdif";
918 reg = <0x0 0xff880000 0x0 0x1000>;
919 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
920 clock-names = "spdif_mclk", "spdif_hclk";
921 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
925 pinctrl-names = "default";
926 pinctrl-0 = <&spdif_tx>;
930 compatible = "rockchip,rk-pwm";
931 reg = <0x0 0xff680000 0x0 0x10>;
933 pinctrl-names = "default";
934 pinctrl-0 = <&pwm0_pin>;
935 clocks = <&clk_gates13 6>;
936 clock-names = "pclk_pwm";
941 compatible = "rockchip,rk-pwm";
942 reg = <0x0 0xff680010 0x0 0x10>;
944 pinctrl-names = "default";
945 pinctrl-0 = <&pwm1_pin>;
946 clocks = <&clk_gates13 6>;
947 clock-names = "pclk_pwm";
952 compatible = "rockchip,rk-pwm";
953 reg = <0x0 0xff680020 0x0 0x10>;
955 //pinctrl-names = "default";
956 //pinctrl-0 = <&pwm1_pin>;
957 clocks = <&clk_gates13 6>;
958 clock-names = "pclk_pwm";
963 compatible = "rockchip,rk-pwm";
964 reg = <0x0 0xff680030 0x0 0x10>;
966 pinctrl-names = "default";
967 pinctrl-0 = <&pwm3_pin>;
968 clocks = <&clk_gates13 6>;
969 clock-names = "pclk_pwm";
973 remotectl: pwm@ff680030 {
974 compatible = "rockchip,remotectl-pwm";
975 reg = <0x0 0xff680030 0x0 0x50>;
977 pinctrl-names = "default";
978 pinctrl-0 = <&pwm3_pin>;
979 clocks = <&clk_gates13 6>;
980 clock-names = "pclk_pwm";
985 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
989 voppwm: pwm@ff9301a0 {
990 compatible = "rockchip,vop-pwm";
991 reg = <0x0 0xff9301a0 0x0 0x10>;
993 pinctrl-names = "default";
994 pinctrl-0 = <&vop_pwm_pin>;
995 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
996 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
1001 compatible = "rockchip,rk3368-pvtm";
1002 rockchip,grf = <&grf>;
1003 rockchip,pmugrf = <&pmugrf>;
1004 rockchip,pvtm-clk-out = <1>;
1008 compatible = "rockchip,rk3368-cpufreq";
1009 rockchip,grf = <&grf>;
1015 regulator_name = "vdd_arm";
1016 suspend_volt = <1000>; //mV
1018 clk_core_b_dvfs_table: clk_core_b {
1019 operating-points = <
1027 temp-limit-enable = <1>;
1029 min_temp_limit = <216>;
1030 normal-temp-limit = <
1031 /*delta-temp delta-freq*/
1037 performance-temp-limit = <
1042 clk_core_l_dvfs_table: clk_core_l {
1043 operating-points = <
1051 temp-limit-enable = <1>;
1053 min_temp_limit = <216>;
1054 normal-temp-limit = <
1055 /*delta-temp delta-freq*/
1061 performance-temp-limit = <
1069 vd_logic: vd_logic {
1070 regulator_name = "vdd_logic";
1071 suspend_volt = <1000>; //mV
1073 clk_ddr_dvfs_table: clk_ddr {
1074 operating-points = <
1081 /* bandwidth freq */
1090 status = "disabled";
1095 clk_gpu_dvfs_table: clk_gpu {
1096 operating-points = <
1116 compatible = "rockchip,ion";
1117 #address-cells = <1>;
1120 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1121 compatible = "rockchip,ion-heap";
1122 rockchip,ion_heap = <4>;
1123 reg = <0x00000000 0x00000000>; /* 0MB */
1125 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1126 compatible = "rockchip,ion-heap";
1127 rockchip,ion_heap = <0>;
1132 compatible = "rockchip,vpu_sub";
1133 iommu_enabled = <1>;
1134 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1135 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1136 interrupt-names = "irq_enc", "irq_dec";
1138 name = "vpu_service";
1141 hevc: hevc_service {
1142 compatible = "rockchip,hevc_sub";
1143 iommu_enabled = <1>;
1144 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1145 interrupt-names = "irq_dec";
1147 name = "hevc_service";
1150 vpu_combo: vpu_combo@ff9a0000 {
1151 compatible = "rockchip,vpu_combo";
1152 reg = <0x0 0xff9a0000 0x0 0x800>;
1153 rockchip,grf = <&grf>;
1155 rockchip,sub = <&vpu>, <&hevc>;
1156 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1157 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1159 mode_ctrl = <0x418>;
1165 compatible = "rockchip,iep";
1166 iommu_enabled = <1>;
1167 reg = <0x0 0xff900000 0x0 0x800>;
1168 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1169 clocks = <&clk_gates16 2>, <&clk_gates16 3>;
1170 clock-names = "aclk_iep", "hclk_iep";
1174 gmac: eth@ff290000 {
1175 compatible = "rockchip,rk3368-gmac";
1176 reg = <0x0 0xff290000 0x0 0x10000>;
1177 rockchip,grf = <&grf>;
1178 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
1179 interrupt-names = "macirq";
1181 clocks = <&clk_mac>, <&clk_gates7 4>,
1182 <&clk_gates7 5>, <&clk_gates7 6>,
1183 <&clk_gates7 7>, <&clk_gates20 13>,
1185 clock-names = "clk_mac", "mac_clk_rx",
1186 "mac_clk_tx", "clk_mac_ref",
1187 "clk_mac_refout", "aclk_mac",
1191 pinctrl-names = "default";
1192 pinctrl-0 = <&rgmii_pins>;
1193 status = "disabled";
1197 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1198 reg = <0x0 0xffa30000 0x0 0x10000>;
1199 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1200 interrupt-names = "GPU";
1205 compatible = "rockchip,iep_mmu";
1206 reg = <0x0 0xff900800 0x0 0x100>;
1207 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1208 interrupt-names = "iep_mmu";
1213 compatible = "rockchip,vip_mmu";
1214 reg = <0x0 0xff950800 0x0 0x100>;
1215 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1216 interrupt-names = "vip_mmu";
1221 compatible = "rockchip,vopb_mmu";
1222 reg = <0x0 0xff930300 0x0 0x100>;
1223 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1224 interrupt-names = "vop_mmu";
1228 dbgname = "isp_mmu";
1229 compatible = "rockchip,isp_mmu";
1230 reg = <0x0 0xff914000 0x0 0x100>,
1231 <0x0 0xff915000 0x0 0x100>;
1232 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1233 interrupt-names = "isp_mmu";
1237 dbgname = "hdcp_mmu";
1238 compatible = "rockchip,hdcp_mmu";
1239 reg = <0x0 0xff940000 0x0 0x100>;
1240 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1241 interrupt-names = "hdcp_mmu";
1246 compatible = "rockchip,hevc_mmu";
1247 reg = <0x0 0xff9a0440 0x0 0x40>, /*need to fix*/
1248 <0x0 0xff9a0480 0x0 0x40>;
1249 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1250 interrupt-names = "hevc_mmu";
1255 compatible = "rockchip,vpu_mmu";
1256 reg = <0x0 0xff9a0800 0x0 0x100>; /*need to fix*/
1257 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /*need to fix*/
1258 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1259 interrupt-names = "vepu_mmu", "vdpu_mmu";
1262 rockchip_suspend: rockchip_suspend {
1263 rockchip,ctrbits = <
1266 | RKPM_SLP_PMU_PLLS_PWRDN
1267 /*| RKPM_SLP_PMU_PMUALIVE_32K
1268 | RKPM_SLP_SFT_PLLS_DEEP
1269 | RKPM_SLP_PMU_DIS_OSC */
1270 | RKPM_SLP_SFT_PD_NBSCUS
1276 compatible = "rockchip,isp";
1277 reg = <0x0 0xff910000 0x0 0x10000>;
1278 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1279 clocks = <&clk_gates16 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>, <&pd_isp>, <&clk_gates16 9>;
1280 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx", "pd_isp", "clk_vio0_noc";
1281 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1282 pinctrl-0 = <&cif_clkout>;
1283 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1284 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1285 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1286 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1287 pinctrl-5 = <&cif_clkout>;
1288 pinctrl-6 = <&cif_clkout &isp_prelight>;
1289 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1290 pinctrl-8 = <&isp_flash_trigger>;
1291 rockchip,isp,mipiphy = <2>;
1292 rockchip,isp,cifphy = <1>;
1293 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1294 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1295 rockchip,grf = <&grf>;
1296 rockchip,cru = <&cru>;
1297 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1298 rockchip,isp,iommu_enable = <1>;
1303 compatible = "rockchip,cif";
1304 reg = <0x0 0xff950000 0x0 0x10000>;
1305 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1306 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1307 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1308 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1309 pinctrl-names = "cif_pin_all";
1310 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1311 rockchip,grf = <&grf>;
1312 rockchip,cru = <&cru>;
1318 #include "rk3368-thermal.dtsi"
1322 tsadc: tsadc@ff280000 {
1323 compatible = "rockchip,rk3368-tsadc";
1324 reg = <0x0 0xff280000 0x0 0x100>;
1325 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1326 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1327 rockchip,grf = <&grf>;
1328 rockchip,cru = <&cru>;
1329 rockchip,pmu = <&pmu>;
1330 clock-names = "tsadc", "apb_pclk";
1331 clock-frequency = <32000>;
1332 resets = <&reset RK3368_SRST_TSADC_P>;
1333 reset-names = "tsadc-apb";
1334 //pinctrl-names = "default";
1335 //pinctrl-0 = <&tsadc_int>;
1336 #thermal-sensor-cells = <1>;
1337 hw-shut-temp = <120000>;
1338 status = "disabled";
1342 compatible = "rockchip,rk3368-tsp";
1343 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1344 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1345 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1346 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1347 interrupt-names = "irq_tsp";
1348 // pinctrl-names = "default";
1349 // pinctrl-0 = <&isp_hsadc>;
1353 crypto: crypto@FF8A0000{
1354 compatible = "rockchip,rk3368-crypto";
1355 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1356 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1357 interrupt-names = "irq_crypto";
1358 clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1359 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1363 dwc_control_usb: dwc-control-usb {
1364 compatible = "rockchip,rk3368-dwc-control-usb";
1365 rockchip,grf = <&grf>;
1366 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1368 interrupt-names = "otg_id", "otg_bvalid",
1369 "otg_linestate", "host0_linestate";
1370 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1371 clock-names = "hclk_usb_peri", "usbphy_480m";
1372 //resets = <&reset RK3128_RST_USBPOR>;
1373 //reset-names = "usbphy_por";
1375 compatible = "inno,phy";
1376 regbase = &dwc_control_usb;
1377 rk_usb,bvalid = <0x4bc 23 1>;
1378 rk_usb,iddig = <0x4bc 26 1>;
1379 rk_usb,vdmsrcen = <0x718 12 1>;
1380 rk_usb,vdpsrcen = <0x718 11 1>;
1381 rk_usb,rdmpden = <0x718 10 1>;
1382 rk_usb,idpsrcen = <0x718 9 1>;
1383 rk_usb,idmsinken = <0x718 8 1>;
1384 rk_usb,idpsinken = <0x718 7 1>;
1385 rk_usb,dpattach = <0x4b8 31 1>;
1386 rk_usb,cpdet = <0x4b8 30 1>;
1387 rk_usb,dcpattach = <0x4b8 29 1>;
1392 compatible = "rockchip,rk3368-usb-phy";
1393 rockchip,grf = <&grf>;
1394 #address-cells = <1>;
1408 usb0: usb@ff580000 {
1409 compatible = "rockchip,rk3368_usb20_otg";
1410 reg = <0x0 0xff580000 0x0 0x40000>;
1411 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1412 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1413 clock-names = "clk_usbphy0", "hclk_otg";
1414 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1415 <&reset RK3368_SRST_USBOTGC0>;
1416 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1417 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1418 rockchip,usb-mode = <0>;
1421 usb_ehci: usb@ff500000 {
1422 compatible = "generic-ehci";
1423 reg = <0x0 0xff500000 0x0 0x20000>;
1424 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1425 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1426 clock-names = "clk_usbphy0", "hclk_ehci";
1429 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1430 // <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1431 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1434 usb_ohci: usb@ff520000 {
1435 compatible = "generic-ohci";
1436 reg = <0x0 0xff520000 0x0 0x20000>;
1437 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1438 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1439 clock-names = "clk_usbphy0", "hclk_ohci";
1442 usb_ehci1: usb@ff5c0000 {
1443 compatible = "rockchip,rk3288_rk_ehci1_host";
1444 reg = <0x0 0xff5c0000 0x0 0x40000>;
1445 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1447 clocks = <&ehci1phy_480m>, <&clk_gates7 8>,
1448 <&ehci1phy_12m>, <&usbphy_480m>,
1449 <&otgphy1_480m>, <&otgphy2_480m>;
1450 clock-names = "ehci1phy_480m", "hclk_ehci1",
1451 "ehci1phy_12m", "usbphy_480m",
1452 "ehci1_usbphy1", "ehci1_usbphy2";
1453 resets = <&reset RK3368_SRST_EHCI1>, <&reset RK3368_SRST_EHCI1_AUX>,
1454 <&reset RK3368_SRST_EHCI1PHY>;
1455 reset-names = "ehci1_ahb", "ehci1_aux", "ehci1_phy";
1457 status = "disabled";
1461 compatible = "rockchip,rk3368-pinctrl";
1462 rockchip,grf = <&grf>;
1463 rockchip,pmugrf = <&pmugrf>;
1464 #address-cells = <2>;
1468 gpio0: gpio0@ff750000 {
1469 compatible = "rockchip,gpio-bank";
1470 reg = <0x0 0xff750000 0x0 0x100>;
1471 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1472 clocks = <&clk_gates23 4>;
1477 interrupt-controller;
1478 #interrupt-cells = <2>;
1481 gpio1: gpio1@ff780000 {
1482 compatible = "rockchip,gpio-bank";
1483 reg = <0x0 0xff780000 0x0 0x100>;
1484 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1485 clocks = <&clk_gates22 1>;
1490 interrupt-controller;
1491 #interrupt-cells = <2>;
1494 gpio2: gpio2@ff790000 {
1495 compatible = "rockchip,gpio-bank";
1496 reg = <0x0 0xff790000 0x0 0x100>;
1497 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1498 clocks = <&clk_gates22 2>;
1503 interrupt-controller;
1504 #interrupt-cells = <2>;
1507 gpio3: gpio3@ff7a0000 {
1508 compatible = "rockchip,gpio-bank";
1509 reg = <0x0 0xff7a0000 0x0 0x100>;
1510 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1511 clocks = <&clk_gates22 3>;
1516 interrupt-controller;
1517 #interrupt-cells = <2>;
1520 pcfg_pull_up: pcfg-pull-up {
1524 pcfg_pull_down: pcfg-pull-down {
1528 pcfg_pull_none: pcfg-pull-none {
1532 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1533 drive-strength = <8>;
1536 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1537 drive-strength = <12>;
1540 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1542 drive-strength = <8>;
1545 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1546 drive-strength = <4>;
1549 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1551 drive-strength = <4>;
1554 pcfg_output_high: pcfg-output-high {
1558 pcfg_output_low: pcfg-output-low {
1562 pcfg_input_high: pcfg-input-high {
1568 i2c0_xfer: i2c0-xfer {
1569 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1570 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1572 i2c0_gpio: i2c0-gpio {
1573 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1574 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1576 i2c0_sleep: i2c0-sleep {
1577 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_input_high>,
1578 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_input_high>;
1583 i2c1_xfer: i2c1-xfer {
1584 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1585 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1587 i2c1_gpio: i2c1-gpio {
1588 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1589 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1591 i2c1_sleep: i2c1-sleep {
1592 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_input_high>,
1593 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_input_high>;
1598 i2c2_xfer: i2c2-xfer {
1599 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1600 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1602 i2c2_gpio: i2c2-gpio {
1603 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1604 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1606 i2c2_sleep: i2c2-sleep {
1607 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_input_high>,
1608 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_input_high>;
1613 i2c3_xfer: i2c3-xfer {
1614 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1615 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1617 i2c3_gpio: i2c3-gpio {
1618 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1619 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1621 i2c3_sleep: i2c3-sleep {
1622 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_input_high>,
1623 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_input_high>;
1628 i2c4_xfer: i2c4-xfer {
1629 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1630 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1632 i2c4_gpio: i2c4-gpio {
1633 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1634 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1636 i2c4_sleep: i2c4-sleep {
1637 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_input_high>,
1638 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_input_high>;
1643 i2c5_xfer: i2c5-xfer {
1644 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1645 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1647 i2c5_gpio: i2c5-gpio {
1648 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1649 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1651 i2c5_sleep: i2c5-sleep {
1652 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_input_high>,
1653 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_input_high>;
1658 uart0_xfer: uart0-xfer {
1659 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1660 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1663 uart0_cts: uart0-cts {
1664 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1667 uart0_rts: uart0-rts {
1668 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1671 uart0_rts_gpio: uart0-rts-gpio {
1672 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1677 uart1_xfer: uart1-xfer {
1678 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1679 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1682 uart1_cts: uart1-cts {
1683 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1686 uart1_rts: uart1-rts {
1687 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1692 uart2_xfer: uart2-xfer {
1693 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1694 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1699 uart3_xfer: uart3-xfer {
1700 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1701 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1704 uart3_cts: uart3-cts {
1705 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1708 uart3_rts: uart3-rts {
1709 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1714 uart4_xfer: uart4-xfer {
1715 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1716 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1719 uart4_cts: uart4-cts {
1720 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1723 uart4_rts: uart4-rts {
1724 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1729 spi0_clk: spi0-clk {
1730 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1732 spi0_cs0: spi0-cs0 {
1733 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1736 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1739 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1741 spi0_cs1: spi0-cs1 {
1742 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1747 spi1_clk: spi1-clk {
1748 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1750 spi1_cs0: spi1-cs0 {
1751 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1754 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1757 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1759 spi1_cs1: spi1-cs1 {
1760 rockchip,pins = <3 GPIO_D4 RK_FUNC_2 &pcfg_pull_up>;
1765 spi2_clk: spi2-clk {
1766 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1768 spi2_cs0: spi2-cs0 {
1769 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1772 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1775 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1780 i2s_mclk: i2s-mclk {
1781 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1785 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1788 i2s_lrckrx:i2s-lrckrx {
1789 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1792 i2s_lrcktx:i2s-lrcktx {
1793 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1797 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1801 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1805 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1809 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1813 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1816 i2s_gpio: i2s-gpio {
1817 rockchip,pins = <2 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,
1818 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1819 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1820 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1821 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1822 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1823 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1824 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1825 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1830 spdif_tx: spdif-tx {
1831 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1836 sdmmc_clk: sdmmc-clk {
1837 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1840 sdmmc_cmd: sdmmc-cmd {
1841 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1844 sdmmc_dectn: sdmmc-dectn {
1845 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1848 sdmmc_bus1: sdmmc-bus1 {
1849 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1852 sdmmc_bus4: sdmmc-bus4 {
1853 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1854 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1855 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1856 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1859 sdmmc_gpio: sdmmc-gpio {
1860 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1861 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1862 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1863 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1864 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1865 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1866 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1871 sdio0_bus1: sdio0-bus1 {
1872 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1875 sdio0_bus4: sdio0-bus4 {
1876 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1877 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1878 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1879 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1882 sdio0_cmd: sdio0-cmd {
1883 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1886 sdio0_clk: sdio0-clk {
1887 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1890 sdio0_dectn: sdio0-dectn {
1891 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1894 sdio0_wrprt: sdio0-wrprt {
1895 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1898 sdio0_pwren: sdio0-pwren {
1899 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1902 sdio0_bkpwr: sdio0-bkpwr {
1903 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1906 sdio0_int: sdio0-int {
1907 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1910 sdio0_gpio: sdio0-gpio {
1911 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1912 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1913 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1914 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1915 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1916 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1917 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1918 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1919 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1920 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1921 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1926 emmc_clk: emmc-clk {
1927 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1930 emmc_cmd: emmc-cmd {
1931 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1934 emmc_pwren: emmc-pwren {
1935 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1938 emmc_rstnout: emmc_rstnout {
1939 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1942 emmc_bus1: emmc-bus1 {
1943 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1946 emmc_bus4: emmc-bus4 {
1947 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1948 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1949 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1950 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1955 pwm0_pin: pwm0-pin {
1956 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1959 vop_pwm_pin:vop-pwm {
1960 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1965 pwm1_pin: pwm1-pin {
1966 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1971 pwm3_pin: pwm3-pin {
1972 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1977 lcdc_lcdc: lcdc-lcdc {
1979 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1980 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1981 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1982 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1983 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1984 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1985 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1986 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1987 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1988 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1989 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1990 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1991 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1992 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1993 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1994 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1995 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1996 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1999 lcdc_gpio: lcdc-gpio {
2001 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
2002 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
2003 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
2004 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
2005 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
2006 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
2007 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
2008 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
2009 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
2010 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
2011 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
2012 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
2013 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
2014 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
2015 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
2016 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
2017 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
2018 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
2023 cif_clkout: cif-clkout {
2024 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2027 isp_dvp_d2d9: isp-dvp-d2d9 {
2028 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2029 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2030 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2031 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2032 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2033 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2034 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2035 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2036 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
2037 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
2038 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
2039 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2042 isp_dvp_d0d1: isp-dvp-d0d1 {
2043 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2044 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
2047 isp_dvp_d10d11:isp_d10d11 {
2048 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2049 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2052 isp_dvp_d0d7: isp-dvp-d0d7 {
2053 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2054 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
2055 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2056 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2057 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2058 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2059 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2060 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
2063 isp_shutter: isp-shutter {
2064 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2065 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2068 isp_flash_trigger: isp-flash-trigger {
2069 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2072 isp_prelight: isp-prelight {
2073 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2076 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2077 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
2083 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
2087 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
2091 gps_rfclk: gps-rfclk {
2092 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
2097 rgmii_pins: rgmii-pins {
2098 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2099 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2100 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2101 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2102 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2103 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
2104 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
2105 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
2106 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2107 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2108 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2109 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
2110 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
2111 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
2112 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
2115 rmii_pins: rmii-pins {
2116 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2117 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2118 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2119 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2120 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2121 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2122 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2123 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2124 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
2125 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
2130 tsadc_int: tsadc-int {
2131 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
2133 tsadc_gpio: tsadc-gpio {
2134 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
2139 hdmi_cec: hdmi-cec {
2140 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
2145 hdmii2c_xfer: hdmii2c-xfer {
2146 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
2147 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
2152 cpu_jtag: cpu-jtag {
2153 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_up>,
2154 <2 GPIO_B0 RK_FUNC_2 &pcfg_pull_up>;
2159 mcu_jtag: mcu-jtag {
2160 rockchip,pins = <2 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>,
2161 <2 GPIO_B1 RK_FUNC_2 &pcfg_pull_up>;
2167 compatible = "rockchip,rk3368-reboot";
2168 rockchip,cru = <&cru>;
2169 rockchip,pmugrf = <&pmugrf>;