arch/arm64/boot/dts/rk3368.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-rk3368.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/sensor-dev.h>
   6 #include <dt-bindings/clock/rk_system_status.h>
   7
   8 #include "rk3368-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk3368";
  12
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &uart_bt;
  20                 serial1 = &uart_bb;
  21                 serial2 = &uart_dbg;
  22                 serial3 = &uart_gps;
  23                 serial4 = &uart_exp;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &spi0;
  31                 spi1 = &spi1;
  32                 spi2 = &spi2;
  33                 lcdc = &lcdc;
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 idle-states {
  41                         entry-method = "arm,psci";
  42                         CPU_SLEEP_0: cpu-sleep-0 {
  43                                 compatible = "arm,idle-state";
  44                                 arm,psci-suspend-param = <0x1010000>;
  45                                 entry-latency-us = <0x3fffffff>;
  46                                 exit-latency-us = <0x40000000>;
  47                                 min-residency-us = <0xffffffff>;
  48                         };
  49                 };
  50
  51                 little0: cpu@0 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53", "arm,armv8";
  54                         reg = <0x0 0x0>;
  55                         enable-method = "psci";
  56                         cpu-idle-states = <&CPU_SLEEP_0>;
  57                 };
  58                 little1: cpu@1 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53", "arm,armv8";
  61                         reg = <0x0 0x1>;
  62                         enable-method = "psci";
  63                         cpu-idle-states = <&CPU_SLEEP_0>;
  64                 };
  65                 little2: cpu@2 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53", "arm,armv8";
  68                         reg = <0x0 0x2>;
  69                         enable-method = "psci";
  70                         cpu-idle-states = <&CPU_SLEEP_0>;
  71                 };
  72                 little3: cpu@3 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53", "arm,armv8";
  75                         reg = <0x0 0x3>;
  76                         enable-method = "psci";
  77                         cpu-idle-states = <&CPU_SLEEP_0>;
  78                 };
  79                 big0: cpu@100 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53", "arm,armv8";
  82                         reg = <0x0 0x100>;
  83                         enable-method = "psci";
  84                         cpu-idle-states = <&CPU_SLEEP_0>;
  85                 };
  86                 big1: cpu@101 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53", "arm,armv8";
  89                         reg = <0x0 0x101>;
  90                         enable-method = "psci";
  91                         cpu-idle-states = <&CPU_SLEEP_0>;
  92                 };
  93                 big2: cpu@102 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53", "arm,armv8";
  96                         reg = <0x0 0x102>;
  97                         enable-method = "psci";
  98                         cpu-idle-states = <&CPU_SLEEP_0>;
  99                 };
 100                 big3: cpu@103 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a53", "arm,armv8";
 103                         reg = <0x0 0x103>;
 104                         enable-method = "psci";
 105                         cpu-idle-states = <&CPU_SLEEP_0>;
 106                 };
 107
 108                 cpu-map {
 109                         cluster0 {
 110                                 core0 {
 111                                         cpu = <&big0>;
 112                                 };
 113                                 core1 {
 114                                         cpu = <&big1>;
 115                                 };
 116                                 core2 {
 117                                         cpu = <&big2>;
 118                                 };
 119                                 core3 {
 120                                         cpu = <&big3>;
 121                                 };
 122                         };
 123                         cluster1 {
 124                                 core0 {
 125                                         cpu = <&little0>;
 126                                 };
 127                                 core1 {
 128                                         cpu = <&little1>;
 129                                 };
 130                                 core2 {
 131                                         cpu = <&little2>;
 132                                 };
 133                                 core3 {
 134                                         cpu = <&little3>;
 135                                 };
 136                         };
 137                 };
 138         };
 139
 140         psci {
 141                 compatible = "arm,psci-0.2";
 142                 method = "smc";
 143         };
 144
 145         gic: interrupt-controller@ffb70000 {
 146                 compatible = "arm,cortex-a15-gic";
 147                 #interrupt-cells = <3>;
 148                 #address-cells = <0>;
 149                 interrupt-controller;
 150                 reg = <0x0 0xffb71000 0 0x1000>,
 151                       <0x0 0xffb72000 0 0x1000>;
 152         };
 153
 154         ddrpctl: syscon@ff610000 {
 155                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 156                 reg = <0x0 0xff610000 0x0 0x400>;
 157         };
 158
 159         pmu: syscon@ff730000 {
 160                 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
 161                 reg = <0x0 0xff730000 0x0 0x1000>;
 162         };
 163
 164         pmugrf: syscon@ff738000 {
 165                 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
 166                 reg = <0x0 0xff738000 0x0 0x1000>;
 167         };
 168
 169         sgrf: syscon@ff740000 {
 170                 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
 171                 reg = <0x0 0xff740000 0x0 0x1000>;
 172
 173         };
 174
 175         cru: syscon@ff760000 {
 176                 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
 177                 reg = <0x0 0xff760000 0x0 0x1000>;
 178         };
 179
 180         grf: syscon@ff770000 {
 181                 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
 182                 reg = <0x0 0xff770000 0x0 0x1000>;
 183         };
 184
 185         msch: syscon@ffac0000 {
 186                 compatible = "rockchip,rk3368-msch", "rockchip,msch", "syscon";
 187                 reg = <0x0 0xffac0000 0x0 0x3000>;
 188         };
 189
 190         arm-pmu {
 191                 compatible = "arm,armv8-pmuv3";
 192                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 200         };
 201
 202         cpu_axi_bus: cpu_axi_bus {
 203                 compatible = "rockchip,cpu_axi_bus";
 204                 #address-cells = <2>;
 205                 #size-cells = <2>;
 206                 ranges;
 207
 208                 qos {
 209                         #address-cells = <2>;
 210                         #size-cells = <2>;
 211                         ranges;
 212
 213                         dmac {
 214                                 reg = <0x0 0xffa80000 0x0 0x20>;
 215                         };
 216                         crypto {
 217                                 reg = <0x0 0xffa80080 0x0 0x20>;
 218                         };
 219                         tsp {
 220                                 reg = <0x0 0xffa80280 0x0 0x20>;
 221                         };
 222                         bus_cpup {
 223                                 reg = <0x0 0xffa90000 0x0 0x20>;
 224                         };
 225                         cci_r {
 226                                 reg = <0x0 0xffaa0000 0x0 0x20>;
 227                         };
 228                         cci_w {
 229                                 reg = <0x0 0xffaa0080 0x0 0x20>;
 230                         };
 231                         peri {
 232                                 reg = <0x0 0xffab0000 0x0 0x20>;
 233                                 rockchip,priority = <2 2>;
 234                         };
 235                         iep {
 236                                 reg = <0x0 0xffad0000 0x0 0x20>;
 237                         };
 238                         isp_r0 {
 239                                 reg = <0x0 0xffad0080 0x0 0x20>;
 240                         };
 241                         isp_r1 {
 242                                 reg = <0x0 0xffad0100 0x0 0x20>;
 243                         };
 244                         isp_w0 {
 245                                 reg = <0x0 0xffad0180 0x0 0x20>;
 246                                 rockchip,priority = <2 2>;
 247                         };
 248                         isp_w1 {
 249                                 reg = <0x0 0xffad0200 0x0 0x20>;
 250                                 rockchip,priority = <2 2>;
 251                         };
 252                         vip {
 253                                 reg = <0x0 0xffad0280 0x0 0x20>;
 254                         };
 255                         vop {
 256                                 reg = <0x0 0xffad0300 0x0 0x20>;
 257                                 rockchip,priority = <2 2>;
 258                         };
 259                         rga_r {
 260                                 reg = <0x0 0xffad0380 0x0 0x20>;
 261                         };
 262                         rga_w {
 263                                 reg = <0x0 0xffad0400 0x0 0x20>;
 264                         };
 265                         hevc_r {
 266                                 reg = <0x0 0xffae0000 0x0 0x20>;
 267                         };
 268                         vpu_r {
 269                                 reg = <0x0 0xffae0100 0x0 0x20>;
 270                         };
 271                         vpu_w {
 272                                 reg = <0x0 0xffae0180 0x0 0x20>;
 273                         };
 274                         gpu {
 275                                 reg = <0x0 0xffaf0000 0x0 0x20>;
 276                         };
 277                 };
 278
 279                 msch {
 280                         #address-cells = <2>;
 281                         #size-cells = <2>;
 282                         ranges;
 283
 284                         msch {
 285                                 reg = <0x0 0xffac0000 0x0 0x3c>;
 286                                 rockchip,read-latency = <0x34>;
 287                         };
 288                 };
 289         };
 290
 291         efuse_256@ffb00000 {
 292                 compatible = "rockchip,rk3368-efuse-256";
 293                 reg = <0x0 0xffb00000 0x0 0x8>;
 294         };
 295
 296         timer {
 297                 compatible = "arm,armv8-timer";
 298                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 299                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 300                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 301                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 302                 clock-frequency = <24000000>;
 303         };
 304
 305         timer@ff810000 {
 306                 compatible = "rockchip,timer";
 307                 reg = <0x0 0xff810000 0x0 0x20>;
 308                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 309                 rockchip,broadcast = <1>;
 310         };
 311
 312         timer@ff810020 {
 313                 compatible = "rockchip,timer";
 314                 reg = <0x0 0xff810020 0x0 0x20>;
 315                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 316                 rockchip,percpu = <0>;
 317         };
 318
 319         sram: sram@ff8c0000 {
 320                 compatible = "mmio-sram";
 321                 reg = <0x0 0xff8c0000 0x0 0xf000>; /* 60K (reserved 4K for mailbox)*/
 322                 map-exec;
 323         };
 324
 325         watchdog: wdt@ff800000 {
 326                 compatible = "rockchip,watch dog";
 327                 reg = <0x0 0xff800000 0x0 0x100>;
 328                 clocks = <&pclk_alive_pre>;
 329                 clock-names = "pclk_wdt";
 330                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 331                 rockchip,irq = <1>;
 332                 rockchip,timeout = <60>;
 333                 rockchip,atboot = <1>;
 334                 rockchip,debug = <0>;
 335                 status = "disabled";
 336         };
 337
 338         amba {
 339                 #address-cells = <2>;
 340                 #size-cells = <2>;
 341                 compatible = "arm,amba-bus";
 342                 interrupt-parent = <&gic>;
 343                 ranges;
 344
 345                 pdma0: pdma@ff600000 {
 346                         compatible = "arm,pl330", "arm,primecell";
 347                         reg = <0x0 0xff600000 0x0 0x4000>;
 348                         clocks = <&clk_gates12 11>;
 349                         clock-names = "apb_pclk";
 350                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 351                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 352                         #dma-cells = <1>;
 353
 354                 };
 355
 356                 pdma1: pdma@ff250000 {
 357                         compatible = "arm,pl330", "arm,primecell";
 358                         reg = <0x0 0xff250000 0x0 0x4000>;
 359                         clocks = <&clk_gates19 3>;
 360                         clock-names = "apb_pclk";
 361                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 362                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 363                         #dma-cells = <1>;
 364                 };
 365         };
 366
 367         reset: reset@ff760300{
 368                 compatible = "rockchip,reset";
 369                 reg = <0x0 0xff760300 0x0 0x38>;
 370                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 371                 #reset-cells = <1>;
 372         };
 373
 374         nandc0: nandc@ff400000 {
 375                 compatible = "rockchip,rk-nandc";
 376                 reg = <0x0 0xff400000 0x0 0x4000>;
 377                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 378                 nandc_id = <0>;
 379                 clocks = <&clk_nandc0>, <&clk_gates20 9>, <&clk_gates20 11>;
 380                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 381         };
 382
 383         nandc0reg: nandc0@ff400000 {
 384                 compatible = "rockchip,rk-nandc";
 385                 reg = <0x0 0xff400000 0x0 0x4000>;
 386         };
 387
 388         emmc: rksdmmc@ff0f0000 {
 389                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 390                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 391                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
 395                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 396                 rockchip,grf = <&grf>;
 397                 rockchip,cru = <&cru>;
 398                 num-slots = <1>;
 399                 fifo-depth = <0x100>;
 400                 bus-width = <8>;
 401                 tune_regsbase = <0x418>;
 402                 cru_regsbase = <0x320>;
 403                 cru_reset_offset = <3>;
 404         };
 405
 406         sdmmc: rksdmmc@ff0c0000 {
 407                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 408                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 409                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 410                 #address-cells = <1>;
 411                 #size-cells = <0>;
 412                 pinctrl-names = "default", "idle", "udbg";
 413                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 414                 pinctrl-1 = <&sdmmc_gpio>;
 415                 pinctrl-2 = <&uart2_xfer &cpu_jtag &mcu_jtag &sdmmc_dectn>;
 416                 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 417                 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
 418                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 419                 rockchip,grf = <&grf>;
 420                 rockchip,cru = <&cru>;
 421                 num-slots = <1>;
 422                 fifo-depth = <0x100>;
 423                 bus-width = <4>;
 424                 tune_regsbase = <0x400>;
 425                 cru_regsbase = <0x320>;
 426                 cru_reset_offset = <0>;
 427         };
 428
 429         sdio: rksdmmc@ff0d0000 {
 430                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 431                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 432                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 433                 #address-cells = <1>;
 434                 #size-cells = <0>;
 435                 pinctrl-names = "default","idle";
 436                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
 437                 pinctrl-1 = <&sdio0_gpio>;
 438                 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
 439                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 440                 rockchip,grf = <&grf>;
 441                 rockchip,cru = <&cru>;
 442                 num-slots = <1>;
 443                 fifo-depth = <0x100>;
 444                 bus-width = <4>;
 445                 tune_regsbase = <0x408>;
 446                 cru_regsbase = <0x320>;
 447                 cru_reset_offset = <1>;
 448         };
 449
 450         spi0: spi@ff110000 {
 451                 compatible = "rockchip,rockchip-spi";
 452                 reg = <0x0 0xff110000 0x0 0x1000>;
 453                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 454                 #address-cells = <1>;
 455                 #size-cells = <0>;
 456                 pinctrl-names = "default";
 457                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 458                 rockchip,spi-src-clk = <0>;
 459                 num-cs = <2>;
 460                 clocks =<&clk_spi0>, <&clk_gates19 4>;
 461                 clock-names = "spi", "pclk_spi0";
 462                 //dmas = <&pdma1 11>, <&pdma1 12>;
 463                 //#dma-cells = <2>;
 464                 //dma-names = "tx", "rx";
 465                 status = "disabled";
 466         };
 467
 468         spi1: spi@ff120000 {
 469                 compatible = "rockchip,rockchip-spi";
 470                 reg = <0x0 0xff120000 0x0 0x1000>;
 471                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 472                 #address-cells = <1>;
 473                 #size-cells = <0>;
 474                 pinctrl-names = "default";
 475                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0 &spi1_cs1>;
 476                 rockchip,spi-src-clk = <1>;
 477                 num-cs = <2>;
 478                 clocks = <&clk_spi1>, <&clk_gates19 5>;
 479                 clock-names = "spi", "pclk_spi1";
 480                 //dmas = <&pdma1 13>, <&pdma1 14>;
 481                 //#dma-cells = <2>;
 482                 //dma-names = "tx", "rx";
 483                 status = "disabled";
 484         };
 485
 486         spi2: spi@ff130000 {
 487                 compatible = "rockchip,rockchip-spi";
 488                 reg = <0x0 0xff130000 0x0 0x1000>;
 489                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 490                 #address-cells = <1>;
 491                 #size-cells = <0>;
 492                 pinctrl-names = "default";
 493                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 494                 rockchip,spi-src-clk = <2>;
 495                 num-cs = <1>;
 496                 clocks = <&clk_spi2>, <&clk_gates19 6>;
 497                 clock-names = "spi", "pclk_spi2";
 498                 //dmas = <&pdma1 15>, <&pdma1 16>;
 499                 //#dma-cells = <2>;
 500                 //dma-names = "tx", "rx";
 501                 status = "disabled";
 502         };
 503
 504         uart_bt: serial@ff180000 {
 505                 compatible = "rockchip,serial";
 506                 reg = <0x0 0xff180000 0x0 0x100>;
 507                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 508                 clock-frequency = <24000000>;
 509                 clocks = <&clk_uart0>, <&clk_gates19 7>;
 510                 clock-names = "sclk_uart", "pclk_uart";
 511                 reg-shift = <2>;
 512                 reg-io-width = <4>;
 513                 //dmas = <&pdma1 1>, <&pdma1 2>;
 514                 //#dma-cells = <2>;
 515                 pinctrl-names = "default";
 516                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 517                 status = "disabled";
 518         };
 519
 520         uart_bb: serial@ff190000 {
 521                 compatible = "rockchip,serial";
 522                 reg = <0x0 0xff190000 0x0 0x100>;
 523                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 524                 clock-frequency = <24000000>;
 525                 clocks = <&clk_uart1>, <&clk_gates19 8>;
 526                 clock-names = "sclk_uart", "pclk_uart";
 527                 reg-shift = <2>;
 528                 reg-io-width = <4>;
 529                 //dmas = <&pdma1 3>, <&pdma1 4>;
 530                 //#dma-cells = <2>;
 531                 pinctrl-names = "default";
 532                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 533                 status = "disabled";
 534         };
 535
 536         uart_dbg: serial@ff690000 {
 537                 compatible = "rockchip,serial";
 538                 reg = <0x0 0xff690000 0x0 0x100>;
 539                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 540                 clock-frequency = <24000000>;
 541                 clocks = <&clk_uart2>, <&clk_gates13 5>;
 542                 clock-names = "sclk_uart", "pclk_uart";
 543                 reg-shift = <2>;
 544                 reg-io-width = <4>;
 545                 //dmas = <&pdma0 4>, <&pdma0 5>;
 546                 //#dma-cells = <2>;
 547                 //pinctrl-names = "default";
 548                 //pinctrl-0 = <&uart2_xfer>;
 549                 status = "disabled";
 550         };
 551
 552         uart_gps: serial@ff1b0000 {
 553                 compatible = "rockchip,serial";
 554                 reg = <0x0 0xff1b0000 0x0 0x100>;
 555                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 556                 clock-frequency = <24000000>;
 557                 clocks = <&clk_uart3>, <&clk_gates19 9>;
 558                 clock-names = "sclk_uart", "pclk_uart";
 559                 current-speed = <115200>;
 560                 reg-shift = <2>;
 561                 reg-io-width = <4>;
 562                 //dmas = <&pdma1 7>, <&pdma1 8>;
 563                 //#dma-cells = <2>;
 564                 pinctrl-names = "default";
 565                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 566                 status = "disabled";
 567         };
 568
 569         uart_exp: serial@ff1c0000 {
 570                 compatible = "rockchip,serial";
 571                 reg = <0x0 0xff1c0000 0x0 0x100>;
 572                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 573                 clock-frequency = <24000000>;
 574                 clocks = <&clk_uart4>, <&clk_gates19 10>;
 575                 clock-names = "sclk_uart", "pclk_uart";
 576                 reg-shift = <2>;
 577                 reg-io-width = <4>;
 578                 //dmas = <&pdma1 9>, <&pdma1 10>;
 579                 //#dma-cells = <2>;
 580                 pinctrl-names = "default";
 581                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 582                 status = "disabled";
 583         };
 584
 585         mbox: mbox@ff6b0000 {
 586                 compatible = "rockchip,rk3368-mailbox";
 587                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 588                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 589                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 590                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 591                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 592                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 593                 clocks = <&clk_gates12 1>;
 594                 clock-names = "pclk_mailbox";
 595                 #mbox-cells = <1>;
 596         };
 597
 598         mbox_scpi: mbox-scpi {
 599                 compatible = "rockchip,mbox-scpi";
 600                 mboxes = <&mbox 0 &mbox 1 &mbox 2>;
 601                 chan-nums = <3>;
 602         };
 603
 604         ddr {
 605                 compatible = "rockchip,rk3368-ddr";
 606                 status = "okay";
 607                 rockchip,ddrpctl = <&ddrpctl>;
 608                 rockchip,grf = <&grf>;
 609                 rockchip,msch = <&msch>;
 610         };
 611
 612         rockchip_clocks_init: clocks-init{
 613                 compatible = "rockchip,clocks-init";
 614                 rockchip,clocks-init-parent =
 615                         <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
 616                         <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
 617                         <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
 618                         <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
 619                 rockchip,clocks-init-rate =
 620                         <&clk_gpll 576000000>,          <&clk_core_b 792000000>,
 621                         <&clk_core_l 600000000>,        <&clk_cpll 400000000>,
 622                         /*<&clk_npll 500000000>,*/      <&aclk_bus 300000000>,
 623                         <&hclk_bus 150000000>,          <&pclk_bus 75000000>,
 624                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 625                         <&hclk_peri 150000000>,         <&pclk_peri 75000000>,
 626                         <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
 627                         <&clk_cs 300000000>,            <&clkin_trace 300000000>,
 628                         <&aclk_cci 600000000>,          <&clk_mac 125000000>,
 629                         <&aclk_vio0 400000000>,         <&hclk_vio 100000000>,
 630                         <&aclk_rga_pre 400000000>,      <&clk_rga 400000000>,
 631                         <&clk_isp 400000000>,           <&clk_edp 200000000>,
 632                         <&clk_gpu_core 400000000>,      <&aclk_gpu_mem 400000000>,
 633                         <&aclk_gpu_cfg 400000000>,      <&aclk_vepu 400000000>,
 634                         <&aclk_vdpu 400000000>,         <&clk_hevc_core 300000000>,
 635                         <&clk_hevc_cabac 300000000>;
 636 /*
 637                 rockchip,clocks-uboot-has-init =
 638                         <&aclk_vio0>;
 639 */
 640         };
 641
 642         rockchip_clocks_enable: clocks-enable {
 643                 compatible = "rockchip,clocks-enable";
 644                 clocks =
 645                         /*PLL*/
 646                         <&clk_apllb>,
 647                         <&clk_aplll>,
 648                         <&clk_dpll>,
 649                         <&clk_gpll>,
 650                         <&clk_cpll>,
 651
 652                         /*PD_CORE*/
 653                         <&clk_cs>,
 654                         <&clkin_trace>,
 655                         <&aclk_cci>,
 656
 657                         /*PD_BUS*/
 658                         <&aclk_bus>,
 659                         <&hclk_bus>,
 660                         <&pclk_bus>,
 661                         <&clk_gates12 12>,/*aclk_strc_sys*/
 662                         <&clk_gates12 6>,/*aclk_intmem1*/
 663                         <&clk_gates12 5>,/*aclk_intmem0*/
 664                         <&clk_gates12 4>,/*aclk_intmem*/
 665                         <&clk_gates13 9>,/*aclk_gic400*/
 666                         <&clk_gates12 9>,/*hclk_rom*/
 667
 668                         /*PD_ALIVE*/
 669                         <&clk_gates22 12>,/*pclk_timer0*/
 670                         <&clk_gates22 9>,/*pclk_alive_niu*/
 671                         <&clk_gates22 8>,/*pclk_grf*/
 672
 673                         /*PD_PMU*/
 674                         <&clk_gates23 5>,/*pclk_pmugrf*/
 675                         <&clk_gates23 3>,/*pclk_sgrf*/
 676                         <&clk_gates23 2>,/*pclk_pmu_noc*/
 677                         <&clk_gates23 1>,/*pclk_intmem1*/
 678                         <&clk_gates23 0>,/*pclk_pmu*/
 679
 680                         /*PD_PERI*/
 681                         <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
 682                         <&clk_gates20 8>,/*aclk_peri_niu*/
 683                         <&clk_gates21 4>,/*aclk_peri_mmu*/
 684                         <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
 685                         <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
 686                         <&clk_gates19 1>,/*pclk_peri_axi_matrix*/
 687
 688                         <&clk_gates24 0>, /* g_clk_timer0 */
 689                         <&clk_gates24 1>, /* g_clk_timer1 */
 690
 691                         <&fclk_mcu>,
 692                         <&stclk_mcu>,
 693                         <&clk_gates7 0>;/*clk_jtag*/
 694         };
 695
 696         /* I2C_PMU */
 697         i2c0: i2c@ff650000 {
 698                 compatible = "rockchip,rk30-i2c";
 699                 reg = <0x0 0xff650000 0x0 0x1000>;
 700                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 701                 #address-cells = <1>;
 702                 #size-cells = <0>;
 703                 pinctrl-names = "default", "gpio", "sleep";
 704                 pinctrl-0 = <&i2c0_xfer>;
 705                 pinctrl-1 = <&i2c0_gpio>;
 706                 pinctrl-2 = <&i2c0_sleep>;
 707                 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
 708                 clocks = <&clk_gates12 2>;
 709                 rockchip,check-idle = <1>;
 710                 status = "disabled";
 711         };
 712
 713         /* I2C_AUDIO */
 714         i2c1: i2c@ff660000 {
 715                 compatible = "rockchip,rk30-i2c";
 716                 reg = <0x0 0xff660000 0x0 0x1000>;
 717                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 718                 #address-cells = <1>;
 719                 #size-cells = <0>;
 720                 pinctrl-names = "default", "gpio", "sleep";
 721                 pinctrl-0 = <&i2c1_xfer>;
 722                 pinctrl-1 = <&i2c1_gpio>;
 723                 pinctrl-2 = <&i2c1_sleep>;
 724                 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
 725                 clocks = <&clk_gates12 3>;
 726                 rockchip,check-idle = <1>;
 727                 status = "disabled";
 728         };
 729
 730         /* I2C_SENSOR */
 731         i2c2: i2c@ff140000 {
 732                 compatible = "rockchip,rk30-i2c";
 733                 reg = <0x0 0xff140000 0x0 0x1000>;
 734                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 735                 #address-cells = <1>;
 736                 #size-cells = <0>;
 737                 pinctrl-names = "default", "gpio", "sleep";
 738                 pinctrl-0 = <&i2c2_xfer>;
 739                 pinctrl-1 = <&i2c2_gpio>;
 740                 pinctrl-2 = <&i2c2_sleep>;
 741                 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 742                 clocks = <&clk_gates19 11>;
 743                 rockchip,check-idle = <1>;
 744                 status = "disabled";
 745         };
 746
 747         /* I2C_CAM */
 748         i2c3: i2c@ff150000 {
 749                 compatible = "rockchip,rk30-i2c";
 750                 reg = <0x0 0xff150000 0x0 0x1000>;
 751                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 752                 #address-cells = <1>;
 753                 #size-cells = <0>;
 754                 pinctrl-names = "default", "gpio", "sleep";
 755                 pinctrl-0 = <&i2c3_xfer>;
 756                 pinctrl-1 = <&i2c3_gpio>;
 757                 pinctrl-2 = <&i2c3_sleep>;
 758                 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
 759                 clocks = <&clk_gates19 12>;
 760                 rockchip,check-idle = <1>;
 761                 status = "disabled";
 762         };
 763
 764         /* I2C_TP */
 765         i2c4: i2c@ff160000 {
 766                 compatible = "rockchip,rk30-i2c";
 767                 reg = <0x0 0xff160000 0x0 0x1000>;
 768                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 769                 #address-cells = <1>;
 770                 #size-cells = <0>;
 771                 pinctrl-names = "default", "gpio", "sleep";
 772                 pinctrl-0 = <&i2c4_xfer>;
 773                 pinctrl-1 = <&i2c4_gpio>;
 774                 pinctrl-2 = <&i2c4_sleep>;
 775                 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
 776                 clocks = <&clk_gates19 13>;
 777                 rockchip,check-idle = <1>;
 778                 status = "disabled";
 779         };
 780
 781         /* I2C_HDMI */
 782         i2c5: i2c@ff170000 {
 783                 compatible = "rockchip,rk30-i2c";
 784                 reg = <0x0 0xff170000 0x0 0x1000>;
 785                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 786                 #address-cells = <1>;
 787                 #size-cells = <0>;
 788                 pinctrl-names = "default", "gpio", "sleep";
 789                 pinctrl-0 = <&i2c5_xfer>;
 790                 pinctrl-1 = <&i2c5_gpio>;
 791                 pinctrl-2 = <&i2c5_sleep>;
 792                 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
 793                 clocks = <&clk_gates19 14>;
 794                 rockchip,check-idle = <1>;
 795                 status = "disabled";
 796         };
 797
 798         fb: fb {
 799                 compatible = "rockchip,rk-fb";
 800                 rockchip,disp-mode = <NO_DUAL>;
 801         };
 802
 803
 804         rk_screen: rk_screen {
 805                 compatible = "rockchip,screen";
 806         };
 807
 808         dsihost0: mipi@ff960000{
 809                 compatible = "rockchip,rk3368-dsi";
 810                 rockchip,prop = <0>;
 811                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 812                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 813                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 814                 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>, <&pd_mipidsi>;
 815                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host", "pd_mipi_dsi";
 816                 status = "disabled";
 817         };
 818
 819         lvds: lvds@ff968000 {
 820                 compatible = "rockchip,rk3368-lvds";
 821                 rockchip,grf = <&grf>;
 822                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 823                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 824                 clocks = <&clk_gates22 10>, <&clk_gates17 3>, <&pd_lvds>;
 825                 clock-names = "pclk_lvds", "pclk_lvds_ctl", "pd_lvds";
 826                 status = "disabled";
 827         };
 828
 829         edp: edp@ff970000 {
 830                 compatible = "rockchip,rk32-edp";
 831                 reg = <0x0 0xff970000 0x0 0x4000>;
 832                 rockchip,grf = <&grf>;
 833                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 834                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
 835                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 836                 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
 837                 reset-names = "edp_24m", "edp_apb";
 838         };
 839
 840         hdmi: hdmi@ff980000 {
 841                 compatible = "rockchip,rk3368-hdmi";
 842                 reg = <0x0 0xff980000 0x0 0x20000>;
 843                 rockchip,grf = <&grf>;
 844                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 845                 pinctrl-names = "default", "gpio";
 846                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 847                 pinctrl-1 = <&i2c5_gpio>;
 848                 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
 849                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 850                 status = "disabled";
 851         };
 852
 853         hdmi_hdcp2: hdmi_hdcp2@ff978000 {
 854                 compatible = "rockchip,rk3368-hdmi-hdcp2";
 855                 reg = <0x0 0xff978000 0x0 0x2000>;
 856                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 857                 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
 858                 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
 859                 status = "disabled";
 860         };
 861
 862         lcdc: lcdc@ff930000 {
 863                  compatible = "rockchip,rk3368-lcdc";
 864                  rockchip,grf = <&grf>;
 865                  rockchip,pmugrf = <&pmugrf>;
 866                  rockchip,cru = <&cru>;
 867                  rockchip,prop = <PRMRY>;
 868                  rockchip,pwr18 = <0>;
 869                  rockchip,iommu-enabled = <1>;
 870                  reg = <0x0 0xff930000 0x0 0x10000>;
 871                  interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 872                 /*pinctrl-names = "default", "gpio";
 873                  *pinctrl-0 = <&lcdc_lcdc>;
 874                  *pinctrl-1 = <&lcdc_gpio>;
 875                  */
 876                  status = "disabled";
 877                  clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>, <&pd_vop>;
 878                  clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll", "pd_lcdc";
 879         };
 880
 881         adc: adc@ff100000 {
 882                 compatible = "rockchip,saradc";
 883                 reg = <0x0 0xff100000 0x0 0x100>;
 884                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 885                 #io-channel-cells = <1>;
 886                 io-channel-ranges;
 887                 rockchip,adc-vref = <1800>;
 888                 clock-frequency = <1000000>;
 889                 clocks = <&clk_saradc>, <&clk_gates19 15>;
 890                 clock-names = "saradc", "pclk_saradc";
 891                 status = "disabled";
 892         };
 893
 894         rga@ff920000 {
 895                 compatible = "rockchip,rga2";
 896                 dev_mode = <1>;
 897                 reg = <0x0 0xff920000 0x0 0x1000>;
 898                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 899                 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
 900                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 901         };
 902
 903         i2s0: i2s0@ff898000 {
 904                 compatible = "rockchip-i2s";
 905                 reg = <0x0 0xff898000 0x0 0x1000>;
 906                 i2s-id = <0>;
 907                 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 908                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 909                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 910                 dmas = <&pdma0 0>, <&pdma0 1>;
 911                 #dma-cells = <2>;
 912                 dma-names = "tx", "rx";
 913                 pinctrl-names = "default", "sleep";
 914                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 915                 pinctrl-1 = <&i2s_gpio>;
 916         };
 917
 918         i2s1: i2s1@ff890000 {
 919                 compatible = "rockchip-i2s";
 920                 reg = <0x0 0xff890000 0x0 0x1000>;
 921                 i2s-id = <1>;
 922                 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
 923                 clock-names = "i2s_clk", "i2s_hclk";
 924                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 925                 dmas = <&pdma0 6>, <&pdma0 7>;
 926                 #dma-cells = <2>;
 927                 dma-names = "tx", "rx";
 928         };
 929
 930         spdif: spdif@ff880000 {
 931                 compatible = "rockchip-spdif";
 932                 reg = <0x0 0xff880000 0x0 0x1000>;
 933                 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
 934                 clock-names = "spdif_mclk", "spdif_hclk";
 935                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 936                 dmas = <&pdma0 3>;
 937                 #dma-cells = <1>;
 938                 dma-names = "tx";
 939                 pinctrl-names = "default";
 940                 pinctrl-0 = <&spdif_tx>;
 941         };
 942
 943         pwm0: pwm@ff680000 {
 944                 compatible = "rockchip,rk-pwm";
 945                 reg = <0x0 0xff680000 0x0 0x10>;
 946                 #pwm-cells = <2>;
 947                 pinctrl-names = "default";
 948                 pinctrl-0 = <&pwm0_pin>;
 949                 clocks = <&clk_gates13 6>;
 950                 clock-names = "pclk_pwm";
 951                 status = "disabled";
 952         };
 953
 954         pwm1: pwm@ff680010 {
 955                 compatible = "rockchip,rk-pwm";
 956                 reg = <0x0 0xff680010 0x0 0x10>;
 957                 #pwm-cells = <2>;
 958                 pinctrl-names = "default";
 959                 pinctrl-0 = <&pwm1_pin>;
 960                 clocks = <&clk_gates13 6>;
 961                 clock-names = "pclk_pwm";
 962                 status = "disabled";
 963         };
 964
 965         pwm2: pwm@ff680020 {
 966                 compatible = "rockchip,rk-pwm";
 967                 reg = <0x0 0xff680020 0x0 0x10>;
 968                 #pwm-cells = <2>;
 969                 //pinctrl-names = "default";
 970                 //pinctrl-0 = <&pwm1_pin>;
 971                 clocks = <&clk_gates13 6>;
 972                 clock-names = "pclk_pwm";
 973                 status = "disabled";
 974         };
 975
 976         pwm3: pwm@ff680030 {
 977                 compatible = "rockchip,rk-pwm";
 978                 reg = <0x0 0xff680030 0x0 0x10>;
 979                 #pwm-cells = <2>;
 980                 pinctrl-names = "default";
 981                 pinctrl-0 = <&pwm3_pin>;
 982                 clocks = <&clk_gates13 6>;
 983                 clock-names = "pclk_pwm";
 984                 status = "disabled";
 985         };
 986
 987         remotectl: pwm@ff680030 {
 988                 compatible = "rockchip,remotectl-pwm";
 989                 reg = <0x0 0xff680030 0x0 0x50>;
 990                 #pwm-cells = <2>;
 991                 pinctrl-names = "default";
 992                 pinctrl-0 = <&pwm3_pin>;
 993                 clocks = <&clk_gates13 6>;
 994                 clock-names = "pclk_pwm";
 995                 dmas = <&pdma0 2>;
 996                 #dma-cells = <2>;
 997                 dma-names = "rx";
 998                 remote_pwm_id = <3>;
 999                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1000                 status = "disabled";
1001         };
1002
1003         voppwm: pwm@ff9301a0 {
1004                 compatible = "rockchip,vop-pwm";
1005                 reg = <0x0 0xff9301a0 0x0 0x10>;
1006                 #pwm-cells = <2>;
1007                 pinctrl-names = "default";
1008                 pinctrl-0 = <&vop_pwm_pin>;
1009                 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
1010                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
1011                 status = "disabled";
1012         };
1013
1014         pvtm {
1015                 compatible = "rockchip,rk3368-pvtm";
1016                 rockchip,grf = <&grf>;
1017                 rockchip,pmugrf = <&pmugrf>;
1018                 rockchip,pvtm-clk-out = <1>;
1019         };
1020
1021         cpufreq {
1022                 compatible = "rockchip,rk3368-cpufreq";
1023                 rockchip,grf = <&grf>;
1024         };
1025
1026         dvfs {
1027
1028                 vd_arm: vd_arm {
1029                         regulator_name = "vdd_arm";
1030                         suspend_volt = <1000>; //mV
1031                         pd_core {
1032                                 clk_core_b_dvfs_table: clk_core_b {
1033                                         operating-points = <
1034                                                 /* KHz    uV */
1035                                                 312000 1200000
1036                                                 504000 1200000
1037                                                 816000 1200000
1038                                                 1008000 1200000
1039                                                 >;
1040                                         status = "okay";
1041                                         cluster = <0>;
1042                                         temp-limit-enable = <1>;
1043                                         target-temp = <80>;
1044                                         min_temp_limit = <216000>;
1045                                         normal-temp-limit = <
1046                                         /*delta-temp    delta-freq*/
1047                                                 3       96000
1048                                                 6       144000
1049                                                 9       192000
1050                                                 15      384000
1051                                                 >;
1052                                         performance-temp-limit = <
1053                                                 /*temp    freq*/
1054                                                 100     816000
1055                                                 >;
1056                                         lkg_adjust_volt_en = <1>;
1057                                         channel = <0>;
1058                                         def_table_lkg = <25>;
1059                                         min_adjust_freq = <216000>;
1060                                         lkg_adjust_volt_table = <
1061                                                 /*lkg(mA)  volt(uV)*/
1062                                                 0         25000
1063                                                 >;
1064                                         pvtm_min_temp = <25>;
1065                                 };
1066                                 clk_core_l_dvfs_table: clk_core_l {
1067                                         operating-points = <
1068                                                 /* KHz    uV */
1069                                                 312000 1200000
1070                                                 504000 1200000
1071                                                 816000 1200000
1072                                                 1008000 1200000
1073                                                 >;
1074                                         status = "okay";
1075                                         cluster = <1>;
1076                                         temp-limit-enable = <1>;
1077                                         target-temp = <80>;
1078                                         min_temp_limit = <216000>;
1079                                         normal-temp-limit = <
1080                                         /*delta-temp    delta-freq*/
1081                                                 3       96000
1082                                                 6       144000
1083                                                 9       192000
1084                                                 15      384000
1085                                                 >;
1086                                         performance-temp-limit = <
1087                                                 /*temp    freq*/
1088                                                 100     816000
1089                                                 >;
1090                                         lkg_adjust_volt_en = <1>;
1091                                         channel = <0>;
1092                                         def_table_lkg = <25>;
1093                                         min_adjust_freq = <216000>;
1094                                         lkg_adjust_volt_table = <
1095                                                 /*lkg(mA)  volt(uV)*/
1096                                                 0         25000
1097                                                 >;
1098                                         pvtm_min_temp = <25>;
1099                                 };
1100                         };
1101                 };
1102
1103                 vd_logic: vd_logic {
1104                         regulator_name = "vdd_logic";
1105                         suspend_volt = <1000>; //mV
1106                         pd_ddr {
1107                                 clk_ddr_dvfs_table: clk_ddr {
1108                                         operating-points = <
1109                                                 /* KHz    uV */
1110                                                 200000 1200000
1111                                                 300000 1200000
1112                                                 400000 1200000
1113                                                 >;
1114                                         bd-freq-table = <
1115                                                 /* bandwidth   freq */
1116                                                 2700           792000
1117                                                 2600           600000
1118                                                 2280           456000
1119                                                 1560           396000
1120                                                 1020           324000
1121                                                 720            240000
1122                                                 >;
1123                                         channel = <2>;
1124                                         status = "disabled";
1125                                 };
1126                         };
1127
1128                         pd_gpu {
1129                                 clk_gpu_dvfs_table: clk_gpu {
1130                                         operating-points = <
1131                                                 /* KHz    uV */
1132                                                 200000 1200000
1133                                                 300000 1200000
1134                                                 400000 1200000
1135                                                 >;
1136                                         channel = <1>;
1137                                         status = "okay";
1138                                         regu-mode-table = <
1139                                                 /*freq     mode*/
1140                                                 200000     4
1141                                                 0          3
1142                                         >;
1143                                         regu-mode-en = <0>;
1144                                 };
1145                         };
1146                 };
1147         };
1148
1149         ion {
1150                 compatible = "rockchip,ion";
1151                 #address-cells = <1>;
1152                 #size-cells = <0>;
1153
1154                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1155                         compatible = "rockchip,ion-heap";
1156                         rockchip,ion_heap = <4>;
1157                         reg = <0x00000000 0x00000000>; /* 0MB */
1158                 };
1159                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1160                         compatible = "rockchip,ion-heap";
1161                         rockchip,ion_heap = <0>;
1162                 };
1163         };
1164
1165         vpu: vpu_service {
1166                 compatible = "rockchip,vpu_sub";
1167                 iommu_enabled = <1>;
1168                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1169                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1170                 interrupt-names = "irq_enc", "irq_dec";
1171                 dev_mode = <0>;
1172                 name = "vpu_service";
1173         };
1174
1175         hevc: hevc_service {
1176                 compatible = "rockchip,hevc_sub";
1177                 iommu_enabled = <1>;
1178                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1179                 interrupt-names = "irq_dec";
1180                 dev_mode = <1>;
1181                 name = "hevc_service";
1182         };
1183
1184         vpu_combo: vpu_combo@ff9a0000 {
1185                 compatible = "rockchip,vpu_combo";
1186                 reg = <0x0 0xff9a0000 0x0 0x800>;
1187                 rockchip,grf = <&grf>;
1188                 subcnt = <2>;
1189                 rockchip,sub = <&vpu>, <&hevc>;
1190                 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1191                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1192                 resets = <&reset RK3368_SRST_VIDEO_H>, <&reset RK3368_SRST_VIDEO_A>,
1193                         <&reset RK3368_SRST_VIDEO>;
1194                 reset-names = "video_h", "video_a", "video";
1195                 mode_bit = <12>;
1196                 mode_ctrl = <0x418>;
1197                 name = "vpu_combo";
1198                 status = "okay";
1199         };
1200
1201         iep: iep@ff900000 {
1202                 compatible = "rockchip,iep";
1203                 iommu_enabled = <1>;
1204                 reg = <0x0 0xff900000 0x0 0x800>;
1205                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1206                 clocks = <&clk_gates16 2>, <&clk_gates16 3>;
1207                 clock-names = "aclk_iep", "hclk_iep";
1208                 status = "okay";
1209         };
1210
1211         gmac: eth@ff290000 {
1212                 compatible = "rockchip,rk3368-gmac";
1213                 reg = <0x0 0xff290000 0x0 0x10000>;
1214                 rockchip,grf = <&grf>;
1215                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1216                 interrupt-names = "macirq";
1217
1218                 clocks = <&clk_mac>, <&clk_gates7 4>,
1219                          <&clk_gates7 5>, <&clk_gates7 6>,
1220                          <&clk_gates7 7>, <&clk_gates20 13>,
1221                          <&clk_gates20 14>;
1222                 clock-names = "clk_mac", "mac_clk_rx",
1223                               "mac_clk_tx", "clk_mac_ref",
1224                               "clk_mac_refout", "aclk_mac",
1225                               "pclk_mac";
1226
1227                 phy-mode = "rgmii";
1228                 pinctrl-names = "default";
1229                 pinctrl-0 = <&rgmii_pins>;
1230                 status = "disabled";
1231         };
1232
1233         gpu {
1234                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1235                 reg = <0x0 0xffa30000 0x0 0x10000>;
1236                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1237                 interrupt-names = "GPU";
1238         };
1239
1240         iep_mmu {
1241                 dbgname = "iep";
1242                 compatible = "rockchip,iep_mmu";
1243                 reg = <0x0 0xff900800 0x0 0x100>;
1244                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1245                 interrupt-names = "iep_mmu";
1246         };
1247
1248         vip_mmu {
1249                 dbgname = "vip";
1250                 compatible = "rockchip,vip_mmu";
1251                 reg = <0x0 0xff950800 0x0 0x100>;
1252                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1253                 interrupt-names = "vip_mmu";
1254         };
1255
1256         vop_mmu {
1257                 dbgname = "vop";
1258                 compatible = "rockchip,vopb_mmu";
1259                 reg = <0x0 0xff930300 0x0 0x100>;
1260                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1261                 interrupt-names = "vop_mmu";
1262         };
1263
1264         isp_mmu {
1265                 dbgname = "isp_mmu";
1266                 compatible = "rockchip,isp_mmu";
1267                 reg = <0x0 0xff914000 0x0 0x100>,
1268                 <0x0 0xff915000 0x0 0x100>;
1269                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1270                 interrupt-names = "isp_mmu";
1271         };
1272
1273         hdcp_mmu {
1274                 dbgname = "hdcp_mmu";
1275                 compatible = "rockchip,hdcp_mmu";
1276                 reg = <0x0 0xff940000 0x0 0x100>;
1277                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1278                 interrupt-names = "hdcp_mmu";
1279         };
1280
1281         hevc_mmu {
1282                 dbgname = "hevc";
1283                 compatible = "rockchip,hevc_mmu";
1284                 reg = <0x0 0xff9a0440 0x0 0x40>,                      /*need to fix*/
1285                           <0x0 0xff9a0480 0x0 0x40>;
1286                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;        /*need to fix*/
1287                 interrupt-names = "hevc_mmu";
1288         };
1289
1290         vpu_mmu {
1291                 dbgname = "vpu";
1292                 compatible = "rockchip,vpu_mmu";
1293                 reg = <0x0 0xff9a0800 0x0 0x100>;                    /*need to fix*/
1294                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,        /*need to fix*/
1295                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1296                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1297         };
1298
1299         rockchip_suspend: rockchip_suspend {
1300                 rockchip,ctrbits = <
1301                         (0
1302                         | RKPM_SLP_ARMOFF
1303                         | RKPM_SLP_PMU_PLLS_PWRDN
1304                         /*| RKPM_SLP_PMU_PMUALIVE_32K
1305                         | RKPM_SLP_SFT_PLLS_DEEP
1306                         | RKPM_SLP_PMU_DIS_OSC */
1307                         | RKPM_SLP_SFT_PD_NBSCUS
1308                         )
1309                         >;
1310         };
1311
1312         isp: isp@ff910000{
1313                 compatible = "rockchip,isp";
1314                 reg = <0x0 0xff910000 0x0 0x10000>;
1315                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1316                 clocks = <&clk_gates16 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>, <&pd_isp>, <&clk_gates16 9>;
1317                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx", "pd_isp", "clk_vio0_noc";
1318                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1319                 pinctrl-0 = <&cif_clkout>;
1320                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1321                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1322                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1323                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1324                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
1325                 pinctrl-6 = <&cif_clkout>;
1326                 pinctrl-7 = <&cif_clkout &isp_prelight>;
1327                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
1328                 pinctrl-9 = <&isp_flash_trigger>;
1329                 rockchip,isp,mipiphy = <2>;
1330                 rockchip,isp,cifphy = <1>;
1331                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1332                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1333                 rockchip,grf = <&grf>;
1334                 rockchip,cru = <&cru>;
1335                 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1336                 rockchip,isp,iommu_enable = <1>;
1337                 status = "okay";
1338         };
1339
1340         cif: cif@ff950000 {
1341                 compatible = "rockchip,cif";
1342                 reg = <0x0 0xff950000 0x0 0x10000>;
1343                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1344                 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1345                 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1346                 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1347                 pinctrl-names = "cif_pin_all";
1348                 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1349                 rockchip,grf = <&grf>;
1350                 rockchip,cru = <&cru>;
1351                 status = "okay";
1352         };
1353
1354 /*
1355         thermal-zones {
1356                 #include "rk3368-thermal.dtsi"
1357         };
1358 */
1359
1360         tsadc: tsadc@ff280000 {
1361                 compatible = "rockchip,rk3368-tsadc";
1362                 reg = <0x0 0xff280000 0x0 0x100>;
1363                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1364                 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1365                 rockchip,grf = <&grf>;
1366                 rockchip,cru = <&cru>;
1367                 rockchip,pmu = <&pmu>;
1368                 clock-names = "tsadc", "apb_pclk";
1369                 clock-frequency = <32000>;
1370                 resets = <&reset RK3368_SRST_TSADC_P>;
1371                 reset-names = "tsadc-apb";
1372                 //pinctrl-names = "default";
1373                 //pinctrl-0 = <&tsadc_int>;
1374                 #thermal-sensor-cells = <1>;
1375                 hw-shut-temp = <120000>;
1376                 status = "disabled";
1377         };
1378
1379         tsp: tsp@FF8B0000 {
1380                 compatible = "rockchip,rk3368-tsp";
1381                 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1382                 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1383                 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1384                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1385                 interrupt-names = "irq_tsp";
1386                 // pinctrl-names = "default";
1387                 // pinctrl-0 = <&isp_hsadc>;
1388                 status = "okay";
1389         };
1390
1391         crypto: crypto@FF8A0000{
1392                 compatible = "rockchip,rk3368-crypto";
1393                 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1394                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1395                 interrupt-names = "irq_crypto";
1396                         clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1397                 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1398                 status = "okay";
1399         };
1400
1401         dwc_control_usb: dwc-control-usb {
1402                 compatible = "rockchip,rk3368-dwc-control-usb";
1403                 rockchip,grf = <&grf>;
1404                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1405                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1406                 interrupt-names = "otg_id", "otg_bvalid",
1407                                   "otg_linestate", "host0_linestate";
1408                 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1409                 clock-names = "hclk_usb_peri", "usbphy_480m";
1410                 //resets = <&reset RK3128_RST_USBPOR>;
1411                 //reset-names = "usbphy_por";
1412                 usb_bc{
1413                         compatible = "inno,phy";
1414                         regbase = &dwc_control_usb;
1415                         rk_usb,bvalid     = <0x4bc 23 1>;
1416                         rk_usb,iddig      = <0x4bc 26 1>;
1417                         rk_usb,vdmsrcen   = <0x718 12 1>;
1418                         rk_usb,vdpsrcen   = <0x718 11 1>;
1419                         rk_usb,rdmpden    = <0x718 10 1>;
1420                         rk_usb,idpsrcen   = <0x718  9 1>;
1421                         rk_usb,idmsinken  = <0x718  8 1>;
1422                         rk_usb,idpsinken  = <0x718  7 1>;
1423                         rk_usb,dpattach   = <0x4b8 31 1>;
1424                         rk_usb,cpdet      = <0x4b8 30 1>;
1425                         rk_usb,dcpattach  = <0x4b8 29 1>;
1426                 };
1427         };
1428
1429         usbphy: phy {
1430                 compatible = "rockchip,rk3368-usb-phy";
1431                 rockchip,grf = <&grf>;
1432                 #address-cells = <1>;
1433                 #size-cells = <0>;
1434
1435                 usbphy0: usb-phy0 {
1436                         #phy-cells = <0>;
1437                         reg = <0x700>;
1438                 };
1439
1440                 usbphy1: usb-phy1 {
1441                         #phy-cells = <0>;
1442                         reg = <0x728>;
1443                 };
1444         };
1445
1446         usb0: usb@ff580000 {
1447                 compatible = "rockchip,rk3368_usb20_otg";
1448                 reg = <0x0 0xff580000 0x0 0x40000>;
1449                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1450                 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1451                 clock-names = "clk_usbphy0", "hclk_otg";
1452                 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1453                                 <&reset RK3368_SRST_USBOTGC0>;
1454                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1455                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1456                 rockchip,usb-mode = <0>;
1457         };
1458
1459         usb_ehci: usb@ff500000 {
1460                 compatible = "generic-ehci";
1461                 reg = <0x0 0xff500000 0x0 0x20000>;
1462                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1463                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1464                 clock-names = "clk_usbphy0", "hclk_ehci";
1465                 phys = <&usbphy1>;
1466                 phy-names = "usb";
1467                 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1468                 //              <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1469                 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1470         };
1471
1472         usb_ohci: usb@ff520000 {
1473                 compatible = "generic-ohci";
1474                 reg = <0x0 0xff520000 0x0 0x20000>;
1475                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1476                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1477                 clock-names =  "clk_usbphy0", "hclk_ohci";
1478         };
1479
1480         usb_ehci1: usb@ff5c0000 {
1481                 compatible = "rockchip,rk3288_rk_ehci1_host";
1482                 reg = <0x0 0xff5c0000 0x0 0x40000>;
1483                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1484 /*
1485                 clocks = <&ehci1phy_480m>, <&clk_gates7 8>,
1486                          <&ehci1phy_12m>, <&usbphy_480m>,
1487                          <&otgphy1_480m>, <&otgphy2_480m>;
1488                 clock-names = "ehci1phy_480m", "hclk_ehci1",
1489                               "ehci1phy_12m", "usbphy_480m",
1490                               "ehci1_usbphy1", "ehci1_usbphy2";
1491                 resets = <&reset RK3368_SRST_EHCI1>, <&reset RK3368_SRST_EHCI1_AUX>,
1492                                 <&reset RK3368_SRST_EHCI1PHY>;
1493                 reset-names = "ehci1_ahb", "ehci1_aux", "ehci1_phy";
1494 */
1495                 status = "disabled";
1496         };
1497
1498         pinctrl: pinctrl {
1499                 compatible = "rockchip,rk3368-pinctrl";
1500                 rockchip,grf = <&grf>;
1501                 rockchip,pmugrf = <&pmugrf>;
1502                 #address-cells = <2>;
1503                 #size-cells = <2>;
1504                 ranges;
1505
1506                 gpio0: gpio0@ff750000 {
1507                         compatible = "rockchip,gpio-bank";
1508                         reg =   <0x0 0xff750000 0x0 0x100>;
1509                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1510                         clocks = <&clk_gates23 4>;
1511
1512                         gpio-controller;
1513                         #gpio-cells = <2>;
1514
1515                         interrupt-controller;
1516                         #interrupt-cells = <2>;
1517                 };
1518
1519                 gpio1: gpio1@ff780000 {
1520                         compatible = "rockchip,gpio-bank";
1521                         reg = <0x0 0xff780000 0x0 0x100>;
1522                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1523                         clocks = <&clk_gates22 1>;
1524
1525                         gpio-controller;
1526                         #gpio-cells = <2>;
1527
1528                         interrupt-controller;
1529                         #interrupt-cells = <2>;
1530                 };
1531
1532                 gpio2: gpio2@ff790000 {
1533                         compatible = "rockchip,gpio-bank";
1534                         reg = <0x0 0xff790000 0x0 0x100>;
1535                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1536                         clocks = <&clk_gates22 2>;
1537
1538                         gpio-controller;
1539                         #gpio-cells = <2>;
1540
1541                         interrupt-controller;
1542                         #interrupt-cells = <2>;
1543                 };
1544
1545                 gpio3: gpio3@ff7a0000 {
1546                         compatible = "rockchip,gpio-bank";
1547                         reg = <0x0 0xff7a0000 0x0 0x100>;
1548                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1549                         clocks = <&clk_gates22 3>;
1550
1551                         gpio-controller;
1552                         #gpio-cells = <2>;
1553
1554                         interrupt-controller;
1555                         #interrupt-cells = <2>;
1556                 };
1557
1558                 pcfg_pull_up: pcfg-pull-up {
1559                         bias-pull-up;
1560                 };
1561
1562                 pcfg_pull_down: pcfg-pull-down {
1563                         bias-pull-down;
1564                 };
1565
1566                 pcfg_pull_none: pcfg-pull-none {
1567                         bias-disable;
1568                 };
1569
1570                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1571                         drive-strength = <8>;
1572                 };
1573
1574                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1575                         drive-strength = <12>;
1576                 };
1577
1578                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1579                         bias-pull-up;
1580                         drive-strength = <8>;
1581                 };
1582
1583                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1584                         drive-strength = <4>;
1585                 };
1586
1587                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1588                         bias-pull-up;
1589                         drive-strength = <4>;
1590                 };
1591
1592                 pcfg_output_high: pcfg-output-high {
1593                         output-high;
1594                 };
1595
1596                 pcfg_output_low: pcfg-output-low {
1597                         output-low;
1598                 };
1599
1600                 pcfg_input_high: pcfg-input-high {
1601                         bias-pull-up;
1602                         input-enable;
1603                 };
1604
1605                 i2c0 {
1606                         i2c0_xfer: i2c0-xfer {
1607                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1608                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1609                         };
1610                         i2c0_gpio: i2c0-gpio {
1611                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1612                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1613                         };
1614                         i2c0_sleep: i2c0-sleep {
1615                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_input_high>,
1616                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_input_high>;
1617                         };
1618                 };
1619
1620                 i2c1 {
1621                         i2c1_xfer: i2c1-xfer {
1622                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1623                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1624                         };
1625                         i2c1_gpio: i2c1-gpio {
1626                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1627                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1628                         };
1629                         i2c1_sleep: i2c1-sleep {
1630                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_input_high>,
1631                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_input_high>;
1632                         };
1633                 };
1634
1635                 i2c2 {
1636                         i2c2_xfer: i2c2-xfer {
1637                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1638                                                 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1639                         };
1640                         i2c2_gpio: i2c2-gpio {
1641                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1642                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1643                         };
1644                         i2c2_sleep: i2c2-sleep {
1645                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_input_high>,
1646                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_input_high>;
1647                         };
1648                 };
1649
1650                 i2c3 {
1651                         i2c3_xfer: i2c3-xfer {
1652                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1653                                                 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1654                         };
1655                         i2c3_gpio: i2c3-gpio {
1656                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1657                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1658                         };
1659                         i2c3_sleep: i2c3-sleep {
1660                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_input_high>,
1661                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_input_high>;
1662                         };
1663                 };
1664
1665                 i2c4 {
1666                         i2c4_xfer: i2c4-xfer {
1667                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1668                                                 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1669                         };
1670                         i2c4_gpio: i2c4-gpio {
1671                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1672                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1673                         };
1674                         i2c4_sleep: i2c4-sleep {
1675                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_input_high>,
1676                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_input_high>;
1677                         };
1678                 };
1679
1680                 i2c5 {
1681                         i2c5_xfer: i2c5-xfer {
1682                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1683                                                 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1684                         };
1685                         i2c5_gpio: i2c5-gpio {
1686                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1687                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1688                         };
1689                         i2c5_sleep: i2c5-sleep {
1690                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_input_high>,
1691                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_input_high>;
1692                         };
1693                 };
1694
1695                 uart0 {
1696                         uart0_xfer: uart0-xfer {
1697                                 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1698                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1699                         };
1700
1701                         uart0_cts: uart0-cts {
1702                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1703                         };
1704
1705                         uart0_rts: uart0-rts {
1706                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1707                         };
1708
1709                         uart0_rts_gpio: uart0-rts-gpio {
1710                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1711                         };
1712                 };
1713
1714                 uart1 {
1715                         uart1_xfer: uart1-xfer {
1716                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1717                                                 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1718                         };
1719
1720                         uart1_cts: uart1-cts {
1721                                 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1722                         };
1723
1724                         uart1_rts: uart1-rts {
1725                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1726                         };
1727                 };
1728
1729                 uart2 {
1730                         uart2_xfer: uart2-xfer {
1731                                 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1732                                                 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1733                         };
1734                 };
1735
1736                 uart3 {
1737                         uart3_xfer: uart3-xfer {
1738                                 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1739                                                 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1740                         };
1741
1742                         uart3_cts: uart3-cts {
1743                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1744                         };
1745
1746                         uart3_rts: uart3-rts {
1747                                 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1748                         };
1749                 };
1750
1751                 uart4 {
1752                         uart4_xfer: uart4-xfer {
1753                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1754                                                 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1755                         };
1756
1757                         uart4_cts: uart4-cts {
1758                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1759                         };
1760
1761                         uart4_rts: uart4-rts {
1762                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1763                         };
1764                 };
1765
1766                 spi0 {
1767                         spi0_clk: spi0-clk {
1768                                 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1769                         };
1770                         spi0_cs0: spi0-cs0 {
1771                                 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1772                         };
1773                         spi0_tx: spi0-tx {
1774                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1775                         };
1776                         spi0_rx: spi0-rx {
1777                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1778                         };
1779                         spi0_cs1: spi0-cs1 {
1780                                 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1781                         };
1782                 };
1783
1784                 spi1 {
1785                         spi1_clk: spi1-clk {
1786                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1787                         };
1788                         spi1_cs0: spi1-cs0 {
1789                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1790                         };
1791                         spi1_rx: spi1-rx {
1792                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1793                         };
1794                         spi1_tx: spi1-tx {
1795                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1796                         };
1797                         spi1_cs1: spi1-cs1 {
1798                                 rockchip,pins = <3 GPIO_D4 RK_FUNC_2 &pcfg_pull_up>;
1799                         };
1800                 };
1801
1802                 spi2 {
1803                         spi2_clk: spi2-clk {
1804                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1805                         };
1806                         spi2_cs0: spi2-cs0 {
1807                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1808                         };
1809                         spi2_rx: spi2-rx {
1810                                 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1811                         };
1812                         spi2_tx: spi2-tx {
1813                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1814                         };
1815                 };
1816
1817                 i2s {
1818                         i2s_mclk: i2s-mclk {
1819                                 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1820                         };
1821
1822                         i2s_sclk:i2s-sclk {
1823                                 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1824                         };
1825
1826                         i2s_lrckrx:i2s-lrckrx {
1827                                 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1828                         };
1829
1830                         i2s_lrcktx:i2s-lrcktx {
1831                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1832                         };
1833
1834                         i2s_sdi:i2s-sdi {
1835                                 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1836                         };
1837
1838                         i2s_sdo0:i2s-sdo0 {
1839                                 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1840                         };
1841
1842                         i2s_sdo1:i2s-sdo1 {
1843                                 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1844                         };
1845
1846                         i2s_sdo2:i2s-sdo2 {
1847                                 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1848                         };
1849
1850                         i2s_sdo3:i2s-sdo3 {
1851                                 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1852                         };
1853
1854                         i2s_gpio: i2s-gpio {
1855                                 rockchip,pins = <2 GPIO_C4  RK_FUNC_GPIO &pcfg_pull_none>,
1856                                                 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1857                                                 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1858                                                 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1859                                                 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1860                                                 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1861                                                 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1862                                                 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1863                                                 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1864                         };
1865                 };
1866
1867                 spdif {
1868                         spdif_tx: spdif-tx {
1869                                 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1870                         };
1871                 };
1872
1873                 sdmmc {
1874                         sdmmc_clk: sdmmc-clk {
1875                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1876                         };
1877
1878                         sdmmc_cmd: sdmmc-cmd {
1879                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1880                         };
1881
1882                         sdmmc_dectn: sdmmc-dectn {
1883                                 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1884                         };
1885
1886                         sdmmc_bus1: sdmmc-bus1 {
1887                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1888                         };
1889
1890                         sdmmc_bus4: sdmmc-bus4 {
1891                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1892                                                 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1893                                                 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1894                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1895                         };
1896
1897                         sdmmc_gpio: sdmmc-gpio {
1898                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1899                                                 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1900                                                 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1901                                                 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1902                                                 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1903                                                 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1904                                                 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1905                         };
1906                 };
1907
1908                 sdio0 {
1909                         sdio0_bus1: sdio0-bus1 {
1910                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1911                         };
1912
1913                         sdio0_bus4: sdio0-bus4 {
1914                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1915                                                 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1916                                                 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1917                                                 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1918                         };
1919
1920                         sdio0_cmd: sdio0-cmd {
1921                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1922                         };
1923
1924                         sdio0_clk: sdio0-clk {
1925                                 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1926                         };
1927
1928                         sdio0_dectn: sdio0-dectn {
1929                                 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1930                         };
1931
1932                         sdio0_wrprt: sdio0-wrprt {
1933                                 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1934                         };
1935
1936                         sdio0_pwren: sdio0-pwren {
1937                                 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1938                         };
1939
1940                         sdio0_bkpwr: sdio0-bkpwr {
1941                                 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1942                         };
1943
1944                         sdio0_int: sdio0-int {
1945                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1946                         };
1947
1948                         sdio0_gpio: sdio0-gpio {
1949                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1950                                                 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1951                                                 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1952                                                 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1953                                                 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1954                                                 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1955                                                 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1956                                                 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1957                                                 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1958                                                 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1959                                                 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1960                         };
1961                 };
1962
1963                 emmc {
1964                         emmc_clk: emmc-clk {
1965                                 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1966                         };
1967
1968                         emmc_cmd: emmc-cmd {
1969                                 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1970                         };
1971
1972                         emmc_pwren: emmc-pwren {
1973                                 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1974                         };
1975
1976                         emmc_rstnout: emmc_rstnout {
1977                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1978                         };
1979
1980                         emmc_bus1: emmc-bus1 {
1981                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1982                         };
1983
1984                         emmc_bus4: emmc-bus4 {
1985                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1986                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1987                                                 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1988                                                 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1989                         };
1990                 };
1991
1992                 pwm0 {
1993                         pwm0_pin: pwm0-pin {
1994                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1995                         };
1996
1997                         vop_pwm_pin:vop-pwm {
1998                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1999                         };
2000                 };
2001
2002                 pwm1 {
2003                         pwm1_pin: pwm1-pin {
2004                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
2005                         };
2006                 };
2007
2008                 pwm3 {
2009                         pwm3_pin: pwm3-pin {
2010                                 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
2011                         };
2012                 };
2013
2014                 lcdc {
2015                         lcdc_lcdc: lcdc-lcdc {
2016                                 rockchip,pins =
2017                                                 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
2018                                                 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
2019                                                 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
2020                                                 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
2021                                                 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
2022                                                 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
2023                                                 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
2024                                                 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
2025                                                 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
2026                                                 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
2027                                                 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
2028                                                 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
2029                                                 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
2030                                                 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
2031                                                 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
2032                                                 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
2033                                                 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
2034                                                 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
2035                         };
2036
2037                         lcdc_gpio: lcdc-gpio {
2038                                 rockchip,pins =
2039                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
2040                                                 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
2041                                                 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
2042                                                 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
2043                                                 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
2044                                                 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
2045                                                 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
2046                                                 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
2047                                                 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
2048                                                 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
2049                                                 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
2050                                                 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
2051                                                 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
2052                                                 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
2053                                                 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
2054                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
2055                                                 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
2056                                                 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
2057                         };
2058                 };
2059
2060                 isp {
2061                         cif_clkout: cif-clkout {
2062                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2063                         };
2064
2065                         isp_dvp_d2d9: isp-dvp-d2d9 {
2066                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2067                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2068                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2069                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2070                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2071                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2072                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2073                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2074                                                 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
2075                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
2076                                                 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
2077                                                 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2078                         };
2079
2080                         isp_dvp_d0d1: isp-dvp-d0d1 {
2081                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2082                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
2083                         };
2084
2085                         isp_dvp_d10d11:isp_d10d11       {
2086                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2087                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2088                         };
2089
2090                         isp_dvp_d0d7: isp-dvp-d0d7 {
2091                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2092                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
2093                                                 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2094                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2095                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2096                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2097                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2098                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
2099                         };
2100
2101                         isp_dvp_d4d11: isp-dvp-d4d11 {
2102                                 rockchip,pins =
2103                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2104                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2105                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2106                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2107                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2108                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2109                                                 <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2110                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2111                         };
2112
2113                         isp_shutter: isp-shutter {
2114                                 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2115                                                 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2116                         };
2117
2118                         isp_flash_trigger: isp-flash-trigger {
2119                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2120                         };
2121
2122                         isp_prelight: isp-prelight {
2123                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2124                         };
2125
2126                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2127                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
2128                         };
2129                 };
2130
2131                 gps {
2132                         gps_mag: gps-mag {
2133                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
2134                         };
2135
2136                         gps_sig: gps-sig {
2137                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
2138
2139                         };
2140
2141                         gps_rfclk: gps-rfclk {
2142                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
2143                         };
2144                 };
2145
2146                 gmac {
2147                         rgmii_pins: rgmii-pins {
2148                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2149                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2150                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2151                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2152                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2153                                                 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
2154                                                 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
2155                                                 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
2156                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2157                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2158                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2159                                                 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
2160                                                 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
2161                                                 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
2162                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
2163                         };
2164
2165                         rmii_pins: rmii-pins {
2166                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2167                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2168                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2169                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2170                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2171                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2172                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2173                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2174                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
2175                                                 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
2176                         };
2177                 };
2178
2179                 tsadc_pin {
2180                         tsadc_int: tsadc-int {
2181                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
2182                         };
2183                         tsadc_gpio: tsadc-gpio {
2184                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
2185                         };
2186                 };
2187
2188                 hdmi_pin {
2189                         hdmi_cec: hdmi-cec {
2190                                 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
2191                         };
2192                 };
2193
2194                 hdmi_i2c {
2195                         hdmii2c_xfer: hdmii2c-xfer {
2196                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
2197                                                 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
2198                         };
2199                 };
2200
2201                 cpu_jtag {
2202                         cpu_jtag: cpu-jtag {
2203                                 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_up>,
2204                                                 <2 GPIO_B0 RK_FUNC_2 &pcfg_pull_up>;
2205                         };
2206                 };
2207
2208                 mcu_jtag {
2209                         mcu_jtag: mcu-jtag {
2210                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>,
2211                                                 <2 GPIO_B1 RK_FUNC_2 &pcfg_pull_up>;
2212                         };
2213                 };
2214         };
2215
2216         reboot {
2217                 compatible = "rockchip,rk3368-reboot";
2218                 rockchip,cru = <&cru>;
2219                 rockchip,pmugrf = <&pmugrf>;
2220         };
2221 };