arch/arm64/boot/dts/rk3368.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/sensor-dev.h>
   6 #include <dt-bindings/clock/rk_system_status.h>
   7
   8 #include "rk3368-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk3368";
  12
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &uart_bt;
  20                 serial1 = &uart_bb;
  21                 serial2 = &uart_dbg;
  22                 serial3 = &uart_gps;
  23                 serial4 = &uart_exp;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &spi0;
  31                 spi1 = &spi1;
  32                 spi2 = &spi2;
  33                 lcdc = &lcdc;
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a53","arm,armv8";
  43                         reg = <0x0 0x0>;
  44                 };
  45         };
  46
  47         gic: interrupt-controller@ffb70000 {
  48                 compatible = "arm,cortex-a15-gic";
  49                 #interrupt-cells = <3>;
  50                 #address-cells = <0>;
  51                 interrupt-controller;
  52                 reg = <0x0 0xffb71000 0 0x1000>,
  53                       <0x0 0xffb72000 0 0x1000>;
  54         };
  55
  56         pmu_grf: syscon@ff738000 {
  57                 compatible = "rockchip,rk3388-pmu-grf", "syscon";
  58                 reg = <0x0 0xff738000 0x0 0x100>;
  59         };
  60
  61         sgrf: syscon@ff740000 {
  62                 compatible = "rockchip,rk3388-sgrf", "syscon";
  63                 reg = <0x0 0xff740000 0x0 0x1000>;
  64
  65         };
  66
  67         grf: syscon@ff770000 {
  68                 compatible = "rockchip,rk3388-grf", "syscon";
  69                 reg = <0x0 0xff770000 0x0 0x1000>;
  70         };
  71
  72         arm-pmu {
  73                 compatible = "arm,armv8-pmuv3";
  74                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
  75                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
  76                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
  77                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
  78                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
  79                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
  82         };
  83
  84         cpu_axi_bus: cpu_axi_bus {
  85                 compatible = "rockchip,cpu_axi_bus";
  86                 #address-cells = <2>;
  87                 #size-cells = <2>;
  88                 ranges;
  89
  90                 qos {
  91                         #address-cells = <2>;
  92                         #size-cells = <2>;
  93                         ranges;
  94
  95                         /* service cpup */
  96                         bus_cpup {
  97                                 reg = <0x0 0xffa80000 0x0 0x20>;
  98                         };
  99                         /* service dmac */
 100                         bus_dmac {
 101                                 reg = <0x0 0xffa90000 0x0 0x20>;
 102                         };
 103                         crypto {
 104                                 reg = <0x0 0xffa90080 0x0 0x20>;
 105                         };
 106                         mcu {
 107                                 reg = <0x0 0xffa90100 0x0 0x20>;
 108                         };
 109                         tsp {
 110                                 reg = <0x0 0xffa90280 0x0 0x20>;
 111                         };
 112                         /* service cci */
 113                         cci_r {
 114                                 reg = <0x0 0xffaa0000 0x0 0x20>;
 115                         };
 116                         cci_w {
 117                                 reg = <0x0 0xffaa0080 0x0 0x20>;
 118                         };
 119                         /* service peri */
 120                         peri {
 121                                 reg = <0x0 0xffab0000 0x0 0x20>;
 122                         };
 123                         /* service vio */
 124                         vio0_iep {
 125                                 reg = <0x0 0xffad0000 0x0 0x20>;
 126                         };
 127                         vio0_isp_r0 {
 128                                 reg = <0x0 0xffad0080 0x0 0x20>;
 129                         };
 130                         vio0_isp_r1 {
 131                                 reg = <0x0 0xffad0100 0x0 0x20>;
 132                         };
 133                         vio0_isp_w0 {
 134                                 reg = <0x0 0xffad0180 0x0 0x20>;
 135                         };
 136                         vio0_isp_w1 {
 137                                 reg = <0x0 0xffad0200 0x0 0x20>;
 138                         };
 139                         vio_vip {
 140                                 reg = <0x0 0xffad0280 0x0 0x20>;
 141                         };
 142                         vio1_vop {
 143                                 reg = <0x0 0xffad0300 0x0 0x20>;
 144                         };
 145                         vio1_rga_r {
 146                                 reg = <0x0 0xffad0380 0x0 0x20>;
 147                         };
 148                         vio1_rga_w {
 149                                 reg = <0x0 0xffad0400 0x0 0x20>;
 150                         };
 151                         /* service video */
 152                         video {
 153                                 reg = <0x0 0xffae0000 0x0 0x20>;
 154                         };
 155                         hevc_r {
 156                                 reg = <0x0 0xffae0000 0x0 0x20>;
 157                                 rockchip,priority = <2 2>;
 158                         };
 159                         hevc_w {
 160                                 reg = <0x0 0xffae0080 0x0 0x20>;
 161                                 rockchip,priority = <2 2>;
 162                         };
 163                         vpu_r {
 164                                 reg = <0x0 0xffae0100 0x0 0x20>;
 165                         };
 166                         vpu_w {
 167                                 reg = <0x0 0xffae0180 0x0 0x20>;
 168                                 rockchip,priority = <2 2>;
 169                         };
 170                 };
 171
 172                 msch {
 173                         #address-cells = <2>;
 174                         #size-cells = <2>;
 175                         ranges;
 176
 177                         msch {
 178                                 reg = <0x0 0xffac0000 0x0 0x3c>;
 179                                 rockchip,read-latency = <0x34>;
 180                         };
 181                 };
 182         };
 183
 184         timer {
 185                 compatible = "arm,armv8-timer";
 186                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 187                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 188                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 189                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 190                 clock-frequency = <24000000>;
 191         };
 192
 193         timer@ff810000 {
 194                 compatible = "rockchip,timer";
 195                 reg = <0x0 0xff810000 0x0 0x20>;
 196                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 197                 rockchip,broadcast = <1>;
 198         };
 199
 200         sram: sram@ff8c0000 {
 201                 compatible = "mmio-sram";
 202                 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
 203                 map-exec;
 204         };
 205
 206         watchdog: wdt@ff800000 {
 207                 compatible = "rockchip,watch dog";
 208                 reg = <0x0 0xff800000 0x0 0x100>;
 209                 clocks = <&pclk_alive_pre>;
 210                 clock-names = "pclk_wdt";
 211                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 212                 rockchip,irq = <1>;
 213                 rockchip,timeout = <60>;
 214                 rockchip,atboot = <1>;
 215                 rockchip,debug = <0>;
 216                 status = "disabled";
 217         };
 218
 219         amba {
 220                 #address-cells = <2>;
 221                 #size-cells = <2>;
 222                 compatible = "arm,amba-bus";
 223                 interrupt-parent = <&gic>;
 224                 ranges;
 225
 226                 pdma0: pdma@ffb20000 {
 227                         compatible = "arm,pl330", "arm,primecell";
 228                         reg = <0x0 0xffb20000 0x0 0x4000>;
 229                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 230                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 231                         #dma-cells = <1>;
 232                 };
 233
 234                 pdma1: pdma@ff250000 {
 235                         compatible = "arm,pl330", "arm,primecell";
 236                         reg = <0x0 0xff250000 0x0 0x4000>;
 237                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 238                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 239                         #dma-cells = <1>;
 240                 };
 241         };
 242
 243         reset: reset@ff760300{
 244                 compatible = "rockchip,reset";
 245                 reg = <0x0 0xff760300 0x0 0x38>;
 246                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 247                 #reset-cells = <1>;
 248         };
 249
 250         nandc0: nandc@ff400000 {
 251                 compatible = "rockchip,rk-nandc";
 252                 reg = <0x0 0xff400000 0x0 0x4000>;
 253                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 254                 nandc_id = <0>;
 255                 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
 256                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 257         };
 258
 259         nandc0reg: nandc0@ff400000 {
 260                 compatible = "rockchip,rk-nandc";
 261                 reg = <0x0 0xff400000 0x0 0x4000>;
 262         };
 263
 264         emmc: rksdmmc@ff0f0000 {
 265                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 266                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 267                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 268                 #address-cells = <1>;
 269                 #size-cells = <0>;
 270                 clocks = <&clk_emmc>, <&clk_gates21 2>;
 271                 clock-names = "clk_mmc", "hclk_mmc";
 272                 num-slots = <1>;
 273                 fifo-depth = <0x100>;
 274                 bus-width = <8>;
 275         };
 276
 277         sdmmc: rksdmmc@ff0c0000 {
 278                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 279                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 280                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 281                 #address-cells = <1>;
 282                 #size-cells = <0>;
 283                 pinctrl-names = "default", "idle";
 284                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 285                 pinctrl-1 = <&sdmmc_gpio>;
 286                 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 287                 clocks = <&clk_sdmmc0>, <&clk_gates21 0>;
 288                 clock-names = "clk_mmc", "hclk_mmc";
 289                 num-slots = <1>;
 290                 fifo-depth = <0x100>;
 291                 bus-width = <4>;
 292         };
 293
 294         sdio: rksdmmc@ff0d0000 {
 295                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 296                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 297                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 298                 #address-cells = <1>;
 299                 #size-cells = <0>;
 300                 pinctrl-names = "default","idle";
 301                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
 302                 pinctrl-1 = <&sdio0_gpio>;
 303                 clocks = <&clk_sdio0>, <&clk_gates21 1>;
 304                 clock-names = "clk_mmc", "hclk_mmc";
 305                 num-slots = <1>;
 306                 fifo-depth = <0x100>;
 307                 bus-width = <4>;
 308         };
 309
 310         spi0: spi@ff110000 {
 311                 compatible = "rockchip,rockchip-spi";
 312                 reg = <0x0 0xff110000 0x0 0x1000>;
 313                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316                 pinctrl-names = "default";
 317                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 318                 rockchip,spi-src-clk = <0>;
 319                 num-cs = <2>;
 320                 clocks =<&clk_spi0>, <&clk_gates19 4>;
 321                 clock-names = "spi", "pclk_spi0";
 322                 //dmas = <&pdma1 11>, <&pdma1 12>;
 323                 //#dma-cells = <2>;
 324                 //dma-names = "tx", "rx";
 325                 status = "disabled";
 326         };
 327
 328         spi1: spi@ff120000 {
 329                 compatible = "rockchip,rockchip-spi";
 330                 reg = <0x0 0xff120000 0x0 0x1000>;
 331                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 332                 #address-cells = <1>;
 333                 #size-cells = <0>;
 334                 pinctrl-names = "default";
 335                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 336                 rockchip,spi-src-clk = <1>;
 337                 num-cs = <1>;
 338                 clocks = <&clk_spi1>, <&clk_gates19 5>;
 339                 clock-names = "spi", "pclk_spi1";
 340                 //dmas = <&pdma1 13>, <&pdma1 14>;
 341                 //#dma-cells = <2>;
 342                 //dma-names = "tx", "rx";
 343                 status = "disabled";
 344         };
 345
 346         spi2: spi@ff130000 {
 347                 compatible = "rockchip,rockchip-spi";
 348                 reg = <0x0 0xff130000 0x0 0x1000>;
 349                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 350                 #address-cells = <1>;
 351                 #size-cells = <0>;
 352                 pinctrl-names = "default";
 353                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 354                 rockchip,spi-src-clk = <2>;
 355                 num-cs = <1>;
 356                 clocks = <&clk_spi2>, <&clk_gates19 6>;
 357                 clock-names = "spi", "pclk_spi2";
 358                 //dmas = <&pdma1 15>, <&pdma1 16>;
 359                 //#dma-cells = <2>;
 360                 //dma-names = "tx", "rx";
 361                 status = "disabled";
 362         };
 363
 364         uart_bt: serial@ff180000 {
 365                 compatible = "rockchip,serial";
 366                 reg = <0x0 0xff180000 0x0 0x100>;
 367                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 368                 clock-frequency = <24000000>;
 369                 clocks = <&clk_uart0>, <&clk_gates19 7>;
 370                 clock-names = "sclk_uart", "pclk_uart";
 371                 reg-shift = <2>;
 372                 reg-io-width = <4>;
 373                 //dmas = <&pdma1 1>, <&pdma1 2>;
 374                 //#dma-cells = <2>;
 375                 pinctrl-names = "default";
 376                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 377                 status = "disabled";
 378         };
 379
 380         uart_bb: serial@ff190000 {
 381                 compatible = "rockchip,serial";
 382                 reg = <0x0 0xff190000 0x0 0x100>;
 383                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 384                 clock-frequency = <24000000>;
 385                 clocks = <&clk_uart1>, <&clk_gates19 8>;
 386                 clock-names = "sclk_uart", "pclk_uart";
 387                 reg-shift = <2>;
 388                 reg-io-width = <4>;
 389                 //dmas = <&pdma1 3>, <&pdma1 4>;
 390                 //#dma-cells = <2>;
 391                 pinctrl-names = "default";
 392                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 393                 status = "disabled";
 394         };
 395
 396         uart_dbg: serial@ff690000 {
 397                 compatible = "rockchip,serial";
 398                 reg = <0x0 0xff690000 0x0 0x100>;
 399                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 400                 clock-frequency = <24000000>;
 401                 clocks = <&clk_uart2>, <&clk_gates13 5>;
 402                 clock-names = "sclk_uart", "pclk_uart";
 403                 reg-shift = <2>;
 404                 reg-io-width = <4>;
 405                 //dmas = <&pdma0 4>, <&pdma0 5>;
 406                 //#dma-cells = <2>;
 407                 pinctrl-names = "default";
 408                 pinctrl-0 = <&uart2_xfer>;
 409                 //status = "disabled";
 410         };
 411
 412         uart_gps: serial@ff1b0000 {
 413                 compatible = "rockchip,serial";
 414                 reg = <0x0 0xff1b0000 0x0 0x100>;
 415                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 416                 clock-frequency = <24000000>;
 417                 clocks = <&clk_uart3>, <&clk_gates19 9>;
 418                 clock-names = "sclk_uart", "pclk_uart";
 419                 current-speed = <115200>;
 420                 reg-shift = <2>;
 421                 reg-io-width = <4>;
 422                 //dmas = <&pdma1 7>, <&pdma1 8>;
 423                 //#dma-cells = <2>;
 424                 pinctrl-names = "default";
 425                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 426                 status = "disabled";
 427         };
 428
 429         uart_exp: serial@ff1c0000 {
 430                 compatible = "rockchip,serial";
 431                 reg = <0x0 0xff1c0000 0x0 0x100>;
 432                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 433                 clock-frequency = <24000000>;
 434                 clocks = <&clk_uart4>, <&clk_gates19 10>;
 435                 clock-names = "sclk_uart", "pclk_uart";
 436                 reg-shift = <2>;
 437                 reg-io-width = <4>;
 438                 //dmas = <&pdma1 9>, <&pdma1 10>;
 439                 //#dma-cells = <2>;
 440                 pinctrl-names = "default";
 441                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 442                 status = "disabled";
 443         };
 444
 445         rockchip_clocks_init: clocks-init{
 446                 compatible = "rockchip,clocks-init";
 447                 rockchip,clocks-init-parent =
 448                         <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
 449                         <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
 450                         <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
 451                         <&clk_cs &clk_gpll>;
 452                 rockchip,clocks-init-rate =
 453                         <&clk_core_b 792000000>,        <&clk_core_l 600000000>,
 454                         <&clk_gpll 576000000>,          <&clk_cpll 400000000>,
 455                         /*<&clk_npll 500000000>,*/      <&aclk_bus 300000000>,
 456                         <&hclk_bus 150000000>,          <&pclk_bus 75000000>,
 457                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 458                         <&hclk_peri 150000000>,         <&pclk_peri 75000000>,
 459                         <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
 460                         <&clk_cs 300000000>,            <&clkin_trace 300000000>,
 461                         <&aclk_cci 600000000>,          <&clk_mac 50000000>,
 462                         <&aclk_vio0 400000000>,         <&hclk_vio 100000000>,
 463                         <&aclk_rga_pre 400000000>,      <&clk_rga 400000000>,
 464                         <&clk_isp 400000000>,           <&clk_edp 200000000>,
 465                         <&clk_gpu_core 400000000>,      <&aclk_gpu_mem 400000000>,
 466                         <&aclk_gpu_cfg 400000000>,      <&aclk_vepu 400000000>,
 467                         <&aclk_vdpu 400000000>,         <&clk_hevc_core 300000000>,
 468                         <&clk_hevc_cabac 300000000>;
 469 /*
 470                 rockchip,clocks-uboot-has-init =
 471                         <&aclk_vio0>;
 472 */
 473         };
 474
 475         rockchip_clocks_enable: clocks-enable {
 476                 compatible = "rockchip,clocks-enable";
 477                 clocks =
 478                         /*PLL*/
 479                         <&clk_apllb>,
 480                         <&clk_aplll>,
 481                         <&clk_dpll>,
 482                         <&clk_gpll>,
 483                         <&clk_cpll>,
 484
 485                         /*PD_CORE*/
 486                         <&clk_cs>,
 487                         <&clkin_trace>,
 488
 489                         /*PD_BUS*/
 490                         <&aclk_bus>,
 491                         <&hclk_bus>,
 492                         <&pclk_bus>,
 493                         <&clk_gates12 12>,/*aclk_strc_sys*/
 494                         <&clk_gates12 6>,/*aclk_intmem1*/
 495                         <&clk_gates12 5>,/*aclk_intmem0*/
 496                         <&clk_gates12 4>,/*aclk_intmem*/
 497                         <&clk_gates13 9>,/*aclk_gic400*/
 498
 499                         /*PD_ALIVE*/
 500                         <&clk_gates22 13>,/*pclk_timer1*/
 501                         <&clk_gates22 12>,/*pclk_timer0*/
 502                         <&clk_gates22 9>,/*pclk_alive_niu*/
 503                         <&clk_gates22 8>,/*pclk_grf*/
 504
 505                         /*PD_PMU*/
 506                         <&clk_gates23 5>,/*pclk_pmugrf*/
 507                         <&clk_gates23 3>,/*pclk_sgrf*/
 508                         <&clk_gates23 2>,/*pclk_pmu_noc*/
 509                         <&clk_gates23 1>,/*pclk_intmem1*/
 510                         <&clk_gates23 0>,/*pclk_pmu*/
 511
 512                         /*PD_PERI*/
 513                         <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
 514                         <&clk_gates20 8>,/*aclk_peri_niu*/
 515                         <&clk_gates21 4>,/*aclk_peri_mmu*/
 516                         <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
 517                         <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
 518                         <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
 519         };
 520
 521         i2c0: i2c@ff650000 {
 522                 compatible = "rockchip,rk30-i2c";
 523                 reg = <0x0 0xff650000 0x0 0x1000>;
 524                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 525                 #address-cells = <1>;
 526                 #size-cells = <0>;
 527                 pinctrl-names = "default", "gpio";
 528                 pinctrl-0 = <&i2c0_xfer>;
 529                 pinctrl-1 = <&i2c0_gpio>;
 530                 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
 531                 clocks = <&clk_gates12 2>;
 532                 rockchip,check-idle = <1>;
 533                 status = "disabled";
 534         };
 535
 536         i2c1: i2c@ff140000 {
 537                 compatible = "rockchip,rk30-i2c";
 538                 reg = <0x0 0xff140000 0x0 0x1000>;
 539                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 540                 #address-cells = <1>;
 541                 #size-cells = <0>;
 542                 pinctrl-names = "default", "gpio";
 543                 pinctrl-0 = <&i2c1_xfer>;
 544                 pinctrl-1 = <&i2c1_gpio>;
 545                 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
 546                 clocks = <&clk_gates19 11>;
 547                 rockchip,check-idle = <1>;
 548                 status = "disabled";
 549         };
 550
 551         i2c2: i2c@ff660000 {
 552                 compatible = "rockchip,rk30-i2c";
 553                 reg = <0x0 0xff660000 0x0 0x1000>;
 554                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 555                 #address-cells = <1>;
 556                 #size-cells = <0>;
 557                 pinctrl-names = "default", "gpio";
 558                 pinctrl-0 = <&i2c2_xfer>;
 559                 pinctrl-1 = <&i2c2_gpio>;
 560                 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 561                 clocks = <&clk_gates12 3>;
 562                 rockchip,check-idle = <1>;
 563                 status = "disabled";
 564         };
 565
 566         i2c3: i2c@ff150000 {
 567                 compatible = "rockchip,rk30-i2c";
 568                 reg = <0x0 0xff150000 0x0 0x1000>;
 569                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 570                 #address-cells = <1>;
 571                 #size-cells = <0>;
 572                 pinctrl-names = "default", "gpio";
 573                 pinctrl-0 = <&i2c3_xfer>;
 574                 pinctrl-1 = <&i2c3_gpio>;
 575                 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
 576                 clocks = <&clk_gates19 12>;
 577                 rockchip,check-idle = <1>;
 578                 status = "disabled";
 579         };
 580
 581         i2c4: i2c@ff160000 {
 582                 compatible = "rockchip,rk30-i2c";
 583                 reg = <0x0 0xff160000 0x0 0x1000>;
 584                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 585                 #address-cells = <1>;
 586                 #size-cells = <0>;
 587                 pinctrl-names = "default", "gpio";
 588                 pinctrl-0 = <&i2c4_xfer>;
 589                 pinctrl-1 = <&i2c4_gpio>;
 590                 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
 591                 clocks = <&clk_gates19 13>;
 592                 rockchip,check-idle = <1>;
 593                 status = "disabled";
 594         };
 595
 596         i2c5: i2c@ff170000 {
 597                 compatible = "rockchip,rk30-i2c";
 598                 reg = <0x0 0xff170000 0x0 0x1000>;
 599                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 600                 #address-cells = <1>;
 601                 #size-cells = <0>;
 602                 pinctrl-names = "default", "gpio";
 603                 pinctrl-0 = <&i2c5_xfer>;
 604                 pinctrl-1 = <&i2c5_gpio>;
 605                 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
 606                 clocks = <&clk_gates19 14>;
 607                 rockchip,check-idle = <1>;
 608                 status = "disabled";
 609         };
 610
 611         fb: fb {
 612                 compatible = "rockchip,rk-fb";
 613                 rockchip,disp-mode = <NO_DUAL>;
 614         };
 615
 616
 617         rk_screen: rk_screen {
 618                 compatible = "rockchip,screen";
 619         };
 620
 621         dsihost0: mipi@ff960000{
 622                 compatible = "rockchip,rk33x-dsi";
 623                 rockchip,prop = <0>;
 624                 reg = <0xff960000 0x4000>, <0xff968000 0x4000>;
 625                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 626                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 627                 clocks = <&clk_gates4 14>, <&clk_gates17 3>, <&clk_gates22 10>;
 628                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi_host", "pclk_mipi_dsi_phy";
 629                 status = "okay";
 630         };
 631
 632         lvds: lvds@ff968000 {
 633                 compatible = "rockchip,rk3368-lvds";
 634                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600b0 0x0 0x01>;
 635                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 636                 clocks = <&clk_gates22 10>, <&clk_gates17 3>;
 637                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 638                 status = "disabled";
 639         };
 640
 641         edp: edp@ff970000 {
 642                 compatible = "rockchip,rk32-edp";
 643                 reg = <0x0 0xff970000 0x0 0x4000>;
 644                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 645                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
 646                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 647         };
 648
 649         hdmi: hdmi@ff980000 {
 650                 compatible = "rockchip,rk3368-hdmi";
 651                 reg = <0x0 0xff980000 0x0 0x20000>;
 652                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 653                 pinctrl-names = "default", "gpio";
 654                 pinctrl-0 = <&i2c5_xfer &hdmi_cec>;
 655                 pinctrl-1 = <&i2c5_gpio>;
 656                 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
 657                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 658                 status = "disabled";
 659         };
 660
 661         hdmi_hdcp2: hdmi_hdcp2@ff978000 {
 662                 compatible = "rockchip,rk3368-hdmi-hdcp2";
 663                 reg = <0x0 0xff978000 0x0 0x2000>;
 664                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 665                 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
 666                 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
 667                 status = "disabled";
 668         };
 669
 670         lcdc: lcdc@ff930000 {
 671                  compatible = "rockchip,rk3368-lcdc";
 672                  rockchip,prop = <PRMRY>;
 673                  rockchip,pwr18 = <0>;
 674                  rockchip,iommu-enabled = <0>;
 675                  reg = <0x0 0xff930000 0x0 0x10000>;
 676                  interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 677                  pinctrl-names = "default", "gpio";
 678                  pinctrl-0 = <&lcdc_lcdc>;
 679                  pinctrl-1 = <&lcdc_gpio>;
 680                  status = "disabled";
 681                  clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
 682                  clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
 683         };
 684
 685         adc: adc@ff100000 {
 686                 compatible = "rockchip,saradc";
 687                 reg = <0x0 0xff100000 0x0 0x100>;
 688                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 689                 #io-channel-cells = <1>;
 690                 io-channel-ranges;
 691                 rockchip,adc-vref = <1800>;
 692                 clock-frequency = <1000000>;
 693                 clocks = <&clk_saradc>, <&clk_gates19 15>;
 694                 clock-names = "saradc", "pclk_saradc";
 695                 status = "disabled";
 696         };
 697
 698         rga@ff920000 {
 699                 compatible = "rockchip,rk3368-rga2";
 700                 reg = <0x0 0xff920000 0x0 0x1000>;
 701                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 702                 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
 703                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 704         };
 705
 706         i2s0: i2s0@ff898000 {
 707                 compatible = "rockchip-i2s";
 708                 reg = <0x0 0xff898000 0x0 0x1000>;
 709                 i2s-id = <0>;
 710                 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 711                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 712                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 713                 dmas = <&pdma0 0>, <&pdma0 1>;
 714                 #dma-cells = <2>;
 715                 dma-names = "tx", "rx";
 716                 pinctrl-names = "default", "sleep";
 717                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 718                 pinctrl-1 = <&i2s_gpio>;
 719         };
 720
 721         i2s1: i2s1@ff890000 {
 722                 compatible = "rockchip-i2s";
 723                 reg = <0x0 0xff890000 0x0 0x1000>;
 724                 i2s-id = <1>;
 725                 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
 726                 clock-names = "i2s_clk", "i2s_hclk";
 727                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 728                 dmas = <&pdma0 6>, <&pdma0 7>;
 729                 #dma-cells = <2>;
 730                 dma-names = "tx", "rx";
 731         };
 732
 733         spdif: spdif@ff880000 {
 734                 compatible = "rockchip-spdif";
 735                 reg = <0x0 0xff880000 0x0 0x1000>;
 736                 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
 737                 clock-names = "spdif_mclk", "spdif_hclk";
 738                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 739                 dmas = <&pdma0 3>;
 740                 #dma-cells = <1>;
 741                 dma-names = "tx";
 742                 pinctrl-names = "default";
 743                 pinctrl-0 = <&spdif_tx>;
 744         };
 745
 746         pwm0: pwm@ff680000 {
 747                 compatible = "rockchip,rk-pwm";
 748                 reg = <0x0 0xff680000 0x0 0x10>;
 749                 #pwm-cells = <2>;
 750                 pinctrl-names = "default";
 751                 pinctrl-0 = <&pwm0_pin>;
 752                 clocks = <&clk_gates13 6>;
 753                 clock-names = "pclk_pwm";
 754                 status = "disabled";
 755         };
 756
 757         pwm1: pwm@ff680010 {
 758                 compatible = "rockchip,rk-pwm";
 759                 reg = <0x0 0xff680010 0x0 0x10>;
 760                 #pwm-cells = <2>;
 761                 pinctrl-names = "default";
 762                 pinctrl-0 = <&pwm1_pin>;
 763                 clocks = <&clk_gates13 6>;
 764                 clock-names = "pclk_pwm";
 765                 status = "disabled";
 766         };
 767
 768         pwm2: pwm@ff680020 {
 769                 compatible = "rockchip,rk-pwm";
 770                 reg = <0x0 0xff680020 0x0 0x10>;
 771                 #pwm-cells = <2>;
 772                 //pinctrl-names = "default";
 773                 //pinctrl-0 = <&pwm1_pin>;
 774                 clocks = <&clk_gates13 6>;
 775                 clock-names = "pclk_pwm";
 776                 status = "disabled";
 777         };
 778
 779         pwm3: pwm@ff680030 {
 780                 compatible = "rockchip,rk-pwm";
 781                 reg = <0x0 0xff680030 0x0 0x10>;
 782                 #pwm-cells = <2>;
 783                 pinctrl-names = "default";
 784                 pinctrl-0 = <&pwm3_pin>;
 785                 clocks = <&clk_gates13 6>;
 786                 clock-names = "pclk_pwm";
 787                 status = "disabled";
 788         };
 789
 790         dvfs {
 791
 792                 vd_arm: vd_arm {
 793                         regulator_name = "vdd_arm";
 794                         suspend_volt = <1000>; //mV
 795                         pd_core {
 796                                 clk_core_dvfs_table: clk_core {
 797                                         operating-points = <
 798                                                 /* KHz    uV */
 799                                                 312000 1100000
 800                                                 504000 1100000
 801                                                 816000 1100000
 802                                                 1008000 1100000
 803                                                 >;
 804                                         channel = <0>;
 805                                         temp-limit-enable = <0>;
 806                                         target-temp = <80>;
 807                                         normal-temp-limit = <
 808                                         /*delta-temp    delta-freq*/
 809                                                 3       96000
 810                                                 6       144000
 811                                                 9       192000
 812                                                 15      384000
 813                                                 >;
 814                                         performance-temp-limit = <
 815                                                 /*temp    freq*/
 816                                                 100     816000
 817                                                 >;
 818                                         status = "okay";
 819                                         regu-mode-table = <
 820                                                 /*freq     mode*/
 821                                                 1008000    4
 822                                                 0          3
 823                                         >;
 824                                         regu-mode-en = <0>;
 825                                 };
 826                         };
 827                 };
 828
 829                 vd_logic: vd_logic {
 830                         regulator_name = "vdd_logic";
 831                         suspend_volt = <1000>; //mV
 832                         pd_ddr {
 833                                 clk_ddr_dvfs_table: clk_ddr {
 834                                         operating-points = <
 835                                                 /* KHz    uV */
 836                                                 200000 1200000
 837                                                 300000 1200000
 838                                                 400000 1200000
 839                                                 >;
 840                                         channel = <2>;
 841                                         status = "disabled";
 842                                 };
 843                         };
 844
 845                         pd_vio {
 846                                 aclk_vio1_dvfs_table: aclk_vio1 {
 847                                         operating-points = <
 848                                                 /* KHz    uV */
 849                                                 100000 1100000
 850                                                 500000 1100000
 851                                                 >;
 852                                         status = "okay";
 853                                 };
 854                         };
 855                 };
 856
 857                 vd_gpu: vd_gpu {
 858                         regulator_name = "vdd_gpu";
 859                         suspend_volt = <1000>; //mV
 860                         pd_gpu {
 861                                 clk_gpu_dvfs_table: clk_gpu {
 862                                         operating-points = <
 863                                                 /* KHz    uV */
 864                                                 200000 1200000
 865                                                 300000 1200000
 866                                                 400000 1200000
 867                                                 >;
 868                                         channel = <1>;
 869                                         status = "okay";
 870                                         regu-mode-table = <
 871                                                 /*freq     mode*/
 872                                                 200000     4
 873                                                 0          3
 874                                         >;
 875                                         regu-mode-en = <0>;
 876                                 };
 877                         };
 878                 };
 879         };
 880
 881         ion {
 882                 compatible = "rockchip,ion";
 883                 #address-cells = <1>;
 884                 #size-cells = <0>;
 885
 886                 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
 887                         compatible = "rockchip,ion-heap";
 888                         rockchip,ion_heap = <1>;
 889                         reg = <0x0 0x00000000 0x0 0x08000000>; /* 512MB */
 890                 };
 891                 rockchip,ion-heap@3 { /* VMALLOC HEAP */
 892                         compatible = "rockchip,ion-heap";
 893                         rockchip,ion_heap = <3>;
 894                 };
 895         };
 896
 897         vpu: vpu_service@ff9a0000 {
 898                 compatible = "vpu_service";
 899                 iommu_enabled = <0>;
 900                 reg = <0x0 0xff9a0000 0x0 0x800>;
 901                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 902                 interrupt-names = "irq_enc", "irq_dec";
 903                 /*
 904                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
 905                 clock-names = "aclk_vcodec", "hclk_vcodec";
 906                 */
 907                 name = "vpu_service";
 908                 /* status = "disabled"; */
 909         };
 910
 911         iep: iep@ff900000 {
 912                 compatible = "rockchip,iep";
 913                 iommu_enabled = <0>;
 914                 reg = <0x0 0xff900000 0x0 0x800>;
 915                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 916                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
 917                 clock-names = "aclk_iep", "hclk_iep";
 918                 status = "okay";
 919         };
 920
 921         gmac: eth@ff290000 {
 922                 compatible = "rockchip,rk3368-gmac";
 923                 reg = <0x0 0xff290000 0x0 0x10000>;
 924                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
 925                 interrupt-names = "macirq";
 926
 927                 clocks = <&clk_mac>, <&clk_gates5 0>,
 928                          <&clk_gates5 1>, <&clk_gates5 2>,
 929                          <&clk_gates5 3>, <&clk_gates8 0>,
 930                          <&clk_gates8 1>;
 931                 clock-names = "clk_mac", "mac_clk_rx",
 932                               "mac_clk_tx", "clk_mac_ref",
 933                               "clk_mac_refout", "aclk_mac",
 934                               "pclk_mac";
 935
 936                 phy-mode = "rgmii";
 937                 pinctrl-names = "default";
 938                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
 939         };
 940
 941         gpu {
 942                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
 943                 reg = <0x0 0xffa30000 0x0 0x10000>;
 944                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 945                 interrupt-names = "GPU";
 946         };
 947
 948         iep_mmu {
 949                 dbgname = "iep";
 950                 compatible = "rockchip,iep_mmu";
 951                 reg = <0x0 0xff900800 0x0 0x100>;
 952                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 953                 interrupt-names = "iep_mmu";
 954         };
 955
 956         vip_mmu {
 957                 dbgname = "vip";
 958                 compatible = "rockchip,vip_mmu";
 959                 reg = <0x0 0xff950800 0x0 0x100>;
 960                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 961                 interrupt-names = "vip_mmu";
 962         };
 963
 964         vop_mmu {
 965                 dbgname = "vop";
 966                 compatible = "rockchip,vop_mmu";
 967                 reg = <0x0 0xff930300 0x0 0x100>;
 968                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 969                 interrupt-names = "vop_mmu";
 970         };
 971
 972         isp_mmu {
 973                 dbgname = "isp_mmu";
 974                 compatible = "rockchip,isp_mmu";
 975                 reg = <0x0 0xff914000 0x0 0x100>,
 976                 <0x0 0xff915000 0x0 0x100>;
 977                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 978                 interrupt-names = "isp_mmu";
 979         };
 980
 981         hdcp_mmu {
 982                 dbgname = "hdcp_mmu";
 983                 compatible = "rockchip,hdcp_mmu";
 984                 reg = <0x0 0xff940000 0x0 0x100>;
 985                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 986                 interrupt-names = "hdcp_mmu";
 987         };
 988
 989         hevc_mmu {
 990                 dbgname = "hevc";
 991                 compatible = "rockchip,hevc_mmu";
 992                 reg = <0x0 0xff9c0440 0x0 0x40>,                      /*need to fix*/
 993                           <0x0 0xff9c0480 0x0 0x40>;
 994                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;        /*need to fix*/
 995                 interrupt-names = "hevc_mmu";
 996         };
 997
 998         vpu_mmu {
 999                 dbgname = "vpu";
1000                 compatible = "rockchip,vpu_mmu";
1001                 reg = <0x0 0xff9a0800 0x0 0x100>;                    /*need to fix*/
1002                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;       /*need to fix*/
1003                 interrupt-names = "vpu_mmu";
1004         };
1005
1006         rockchip_suspend {
1007                 rockchip,ctrbits = <
1008                         (0
1009                          |RKPM_CTR_PWR_DMNS
1010                          |RKPM_CTR_GTCLKS
1011                          |RKPM_CTR_PLLS
1012                          |RKPM_CTR_GPIOS
1013                         /*
1014                          |RKPM_CTR_SYSCLK_DIV
1015                          |RKPM_CTR_IDLEAUTO_MD
1016                          |RKPM_CTR_ARMOFF_LPMD
1017                         */
1018                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1019                         )
1020                         >;
1021                 rockchip,pmic-suspend_gpios = <
1022                                  /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1023                         >;
1024                 rockchip,pmic-resume_gpios = <
1025                                 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1026                         >;
1027         };
1028
1029         isp: isp@ff910000{
1030                 compatible = "rockchip,isp";
1031                 reg = <0x0 0xff910000 0x0 0x10000>;
1032                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1033                 clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
1034                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
1035                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1036                 pinctrl-0 = <&cif_clkout>;
1037                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1038                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1039                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1040                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1041                 pinctrl-5 = <&cif_clkout>;
1042                 pinctrl-6 = <&cif_clkout &isp_prelight>;
1043                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1044                 pinctrl-8 = <&isp_flash_trigger>;
1045                 rockchip,isp,mipiphy = <2>;
1046                 rockchip,isp,cifphy = <1>;
1047                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1048                 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1049                 rockchip,isp,iommu_enable = <1>;
1050                 status = "okay";
1051         };
1052
1053         tsadc: tsadc@ff280000 {
1054                 compatible = "rockchip,tsadc";
1055                 reg = <0x0 0xff280000 0x0 0x100>;
1056                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1057                 #io-channel-cells = <1>;
1058                 io-channel-ranges;
1059                 clock-frequency = <10000>;
1060                 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1061                 clock-names = "tsadc", "pclk_tsadc";
1062                 pinctrl-names = "default", "tsadc_int";
1063                 pinctrl-0 = <&tsadc_gpio>;
1064                 pinctrl-1 = <&tsadc_int>;
1065                 tsadc-ht-temp = <120>;
1066                 tsadc-ht-reset-cru = <1>;
1067                 tsadc-ht-pull-gpio = <0>;
1068                 status = "disabled";
1069         };
1070
1071         tsp: tsp@FF8B0000 {
1072                 compatible = "rockchip,rk3368-tsp";
1073                 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1074                 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1075                 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1076                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1077                 interrupt-names = "irq_tsp";
1078                 // pinctrl-names = "default";
1079                 // pinctrl-0 = <&isp_hsadc>;
1080                 status = "okay";
1081         };
1082
1083         crypto: crypto@FF8A0000{
1084                 compatible = "rockchip,rk3368-crypto";
1085                 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1086                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1087                 interrupt-names = "irq_crypto";
1088                         clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1089                 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1090                 status = "okay";
1091         };
1092
1093         pinctrl: pinctrl {
1094                 compatible = "rockchip,rk3368-pinctrl";
1095                 rockchip,grf = <&grf>;
1096                 rockchip,pmu = <&pmu_grf>;
1097                 #address-cells = <2>;
1098                 #size-cells = <2>;
1099                 ranges;
1100
1101                 gpio0: gpio0@ff750000 {
1102                         compatible = "rockchip,gpio-bank";
1103                         reg =   <0x0 0xff750000 0x0 0x100>;
1104                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1105                         clocks = <&clk_gates23 4>;
1106
1107                         gpio-controller;
1108                         #gpio-cells = <2>;
1109
1110                         interrupt-controller;
1111                         #interrupt-cells = <2>;
1112                 };
1113
1114                 gpio1: gpio1@ff780000 {
1115                         compatible = "rockchip,gpio-bank";
1116                         reg = <0x0 0xff780000 0x0 0x100>;
1117                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1118                         clocks = <&clk_gates22 1>;
1119
1120                         gpio-controller;
1121                         #gpio-cells = <2>;
1122
1123                         interrupt-controller;
1124                         #interrupt-cells = <2>;
1125                 };
1126
1127                 gpio2: gpio2@ff790000 {
1128                         compatible = "rockchip,gpio-bank";
1129                         reg = <0x0 0xff790000 0x0 0x100>;
1130                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1131                         clocks = <&clk_gates22 2>;
1132
1133                         gpio-controller;
1134                         #gpio-cells = <2>;
1135
1136                         interrupt-controller;
1137                         #interrupt-cells = <2>;
1138                 };
1139
1140                 gpio3: gpio3@ff7a0000 {
1141                         compatible = "rockchip,gpio-bank";
1142                         reg = <0x0 0xff7a0000 0x0 0x100>;
1143                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1144                         clocks = <&clk_gates22 3>;
1145
1146                         gpio-controller;
1147                         #gpio-cells = <2>;
1148
1149                         interrupt-controller;
1150                         #interrupt-cells = <2>;
1151                 };
1152
1153                 pcfg_pull_up: pcfg-pull-up {
1154                         bias-pull-up;
1155                 };
1156
1157                 pcfg_pull_down: pcfg-pull-down {
1158                         bias-pull-down;
1159                 };
1160
1161                 pcfg_pull_none: pcfg-pull-none {
1162                         bias-disable;
1163                 };
1164
1165                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1166                         drive-strength = <8>;
1167                 };
1168
1169                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1170                         bias-pull-up;
1171                         drive-strength = <8>;
1172                 };
1173
1174                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1175                         drive-strength = <4>;
1176                 };
1177
1178                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1179                         bias-pull-up;
1180                         drive-strength = <4>;
1181                 };
1182
1183                 pcfg_output_high: pcfg-output-high {
1184                         output-high;
1185                 };
1186
1187                 pcfg_output_low: pcfg-output-low {
1188                         output-low;
1189                 };
1190
1191                 i2c0 {
1192                         i2c0_xfer: i2c0-xfer {
1193                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1194                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1195                         };
1196                         i2c0_gpio: i2c0-gpio {
1197                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1198                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1199                         };
1200                 };
1201
1202                 i2c1 {
1203                         i2c1_xfer: i2c1-xfer {
1204                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1205                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1206                         };
1207                         i2c1_gpio: i2c1-gpio {
1208                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1209                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1210                         };
1211                 };
1212
1213                 i2c2 {
1214                         i2c2_xfer: i2c2-xfer {
1215                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1216                                                 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1217                         };
1218                         i2c2_gpio: i2c2-gpio {
1219                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1220                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1221             };
1222                 };
1223
1224                 i2c3 {
1225                         i2c3_xfer: i2c3-xfer {
1226                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1227                                                 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1228                         };
1229                         i2c3_gpio: i2c3-gpio {
1230                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1231                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1232                         };
1233                 };
1234
1235                 i2c4 {
1236                         i2c4_xfer: i2c4-xfer {
1237                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1238                                                 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1239                         };
1240                         i2c4_gpio: i2c4-gpio {
1241                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1242                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1243                         };
1244                 };
1245
1246                 i2c5 {
1247                         i2c5_xfer: i2c5-xfer {
1248                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1249                                                 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1250                         };
1251                         i2c5_gpio: i2c5-gpio {
1252                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1253                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1254                         };
1255                 };
1256
1257                 uart0 {
1258                         uart0_xfer: uart0-xfer {
1259                                 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1260                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1261                         };
1262
1263                         uart0_cts: uart0-cts {
1264                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1265                         };
1266
1267                         uart0_rts: uart0-rts {
1268                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1269                         };
1270
1271                         uart0_rts_gpio: uart0-rts-gpio {
1272                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1273                         };
1274                 };
1275
1276                 uart1 {
1277                         uart1_xfer: uart1-xfer {
1278                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1279                                                 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1280                         };
1281
1282                         uart1_cts: uart1-cts {
1283                                 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1284                         };
1285
1286                         uart1_rts: uart1-rts {
1287                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1288                         };
1289                 };
1290
1291                 uart2 {
1292                         uart2_xfer: uart2-xfer {
1293                                 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1294                                                 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1295                         };
1296                 };
1297
1298                 uart3 {
1299                         uart3_xfer: uart3-xfer {
1300                                 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1301                                                 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1302                         };
1303
1304                         uart3_cts: uart3-cts {
1305                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1306                         };
1307
1308                         uart3_rts: uart3-rts {
1309                                 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1310                         };
1311                 };
1312
1313                 uart4 {
1314                         uart4_xfer: uart4-xfer {
1315                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1316                                                 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1317                         };
1318
1319                         uart4_cts: uart4-cts {
1320                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1321                         };
1322
1323                         uart4_rts: uart4-rts {
1324                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1325                         };
1326                 };
1327
1328                 spi0 {
1329                         spi0_clk: spi0-clk {
1330                                 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1331                         };
1332                         spi0_cs0: spi0-cs0 {
1333                                 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1334                         };
1335                         spi0_tx: spi0-tx {
1336                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1337                         };
1338                         spi0_rx: spi0-rx {
1339                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1340                         };
1341                         spi0_cs1: spi0-cs1 {
1342                                 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1343                         };
1344                 };
1345
1346                 spi1 {
1347                         spi1_clk: spi1-clk {
1348                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1349                         };
1350                         spi1_cs0: spi1-cs0 {
1351                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1352                         };
1353                         spi1_rx: spi1-rx {
1354                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1355                         };
1356                         spi1_tx: spi1-tx {
1357                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1358                         };
1359                 };
1360
1361                 spi2 {
1362                         spi2_clk: spi2-clk {
1363                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1364                         };
1365                         spi2_cs0: spi2-cs0 {
1366                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1367                         };
1368                         spi2_rx: spi2-rx {
1369                                 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1370                         };
1371                         spi2_tx: spi2-tx {
1372                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1373                         };
1374                 };
1375
1376                 i2s {
1377                         i2s_mclk: i2s-mclk {
1378                                 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1379                         };
1380
1381                         i2s_sclk:i2s-sclk {
1382                                 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1383                         };
1384
1385                         i2s_lrckrx:i2s-lrckrx {
1386                                 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1387                         };
1388
1389                         i2s_lrcktx:i2s-lrcktx {
1390                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1391                         };
1392
1393                         i2s_sdi:i2s-sdi {
1394                                 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1395                         };
1396
1397                         i2s_sdo0:i2s-sdo0 {
1398                                 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1399                         };
1400
1401                         i2s_sdo1:i2s-sdo1 {
1402                                 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1403                         };
1404
1405                         i2s_sdo2:i2s-sdo2 {
1406                                 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1407                         };
1408
1409                         i2s_sdo3:i2s-sdo3 {
1410                                 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1411                         };
1412
1413                         i2s_gpio: i2s-gpio {
1414                                 rockchip,pins = <2 GPIO_C4  RK_FUNC_GPIO &pcfg_pull_none>,
1415                                                 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1416                                                 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1417                                                 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1418                                                 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1419                                                 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1420                                                 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1421                                                 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1422                                                 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1423                         };
1424                 };
1425
1426                 spdif {
1427                         spdif_tx: spdif-tx {
1428                                 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1429                         };
1430                 };
1431
1432                 sdmmc {
1433                         sdmmc_clk: sdmmc-clk {
1434                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1435                         };
1436
1437                         sdmmc_cmd: sdmmc-cmd {
1438                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1439                         };
1440
1441                         sdmmc_dectn: sdmmc-dectn {
1442                                 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1443                         };
1444
1445                         sdmmc_bus1: sdmmc-bus1 {
1446                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1447                         };
1448
1449                         sdmmc_bus4: sdmmc-bus4 {
1450                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1451                                                 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1452                                                 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1453                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1454                         };
1455
1456                         sdmmc_gpio: sdmmc-gpio {
1457                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1458                                                 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1459                                                 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1460                                                 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1461                                                 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1462                                                 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1463                                                 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1464                         };
1465                 };
1466
1467                 sdio0 {
1468                         sdio0_bus1: sdio0-bus1 {
1469                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1470                         };
1471
1472                         sdio0_bus4: sdio0-bus4 {
1473                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1474                                                 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1475                                                 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1476                                                 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1477                         };
1478
1479                         sdio0_cmd: sdio0-cmd {
1480                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1481                         };
1482
1483                         sdio0_clk: sdio0-clk {
1484                                 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1485                         };
1486
1487                         sdio0_dectn: sdio0-dectn {
1488                                 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1489                         };
1490
1491                         sdio0_wrprt: sdio0-wrprt {
1492                                 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1493                         };
1494
1495                         sdio0_pwren: sdio0-pwren {
1496                                 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1497                         };
1498
1499                         sdio0_bkpwr: sdio0-bkpwr {
1500                                 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1501                         };
1502
1503                         sdio0_int: sdio0-int {
1504                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1505                         };
1506
1507                         sdio0_gpio: sdio0-gpio {
1508                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1509                                                 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1510                                                 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1511                                                 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1512                                                 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1513                                                 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1514                                                 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1515                                                 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1516                                                 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1517                                                 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1518                                                 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1519                         };
1520                 };
1521
1522                 emmc {
1523                         emmc_clk: emmc-clk {
1524                                 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1525                         };
1526
1527                         emmc_cmd: emmc-cmd {
1528                                 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1529                         };
1530
1531                         emmc_pwren: emmc-pwren {
1532                                 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1533                         };
1534
1535                         emmc_rstnout: emmc_rstnout {
1536                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1537                         };
1538
1539                         emmc_bus1: emmc-bus1 {
1540                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1541                         };
1542
1543                         emmc_bus4: emmc-bus4 {
1544                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1545                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1546                                                 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1547                                                 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1548                         };
1549                 };
1550
1551                 pwm0 {
1552                         pwm0_pin: pwm0-pin {
1553                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1554                         };
1555
1556                         vop_pwm_pin:vop-pwm {
1557                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1558                         };
1559                 };
1560
1561                 pwm1 {
1562                         pwm1_pin: pwm1-pin {
1563                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1564                         };
1565                 };
1566
1567                 pwm3 {
1568                         pwm3_pin: pwm3-pin {
1569                                 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1570                         };
1571                 };
1572
1573                 lcdc {
1574                         lcdc_lcdc: lcdc-lcdc {
1575                                 rockchip,pins = <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1576                                                 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1577                                                 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1578                                                 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1579                         };
1580
1581                         lcdc_gpio: lcdc-gpio {
1582                                 rockchip,pins = <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1583                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1584                                                 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1585                                                 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1586                         };
1587                 };
1588
1589                 isp {
1590                         cif_clkout: cif-clkout {
1591                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1592                         };
1593
1594                         isp_dvp_d2d9: isp-dvp-d2d9 {
1595                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1596                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1597                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1598                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1599                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1600                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1601                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1602                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1603                                                 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1604                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1605                                                 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1606                                                 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1607                         };
1608
1609                         isp_dvp_d0d1: isp-dvp-d0d1 {
1610                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1611                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1612                         };
1613
1614                         isp_dvp_d10d11:isp_d10d11       {
1615                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1616                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1617                         };
1618
1619                         isp_dvp_d0d7: isp-dvp-d0d7 {
1620                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1621                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1622                                                 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1623                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1624                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1625                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1626                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1627                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1628                         };
1629
1630                         isp_shutter: isp-shutter {
1631                                 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1632                                                 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1633                         };
1634
1635                         isp_flash_trigger: isp-flash-trigger {
1636                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1637                         };
1638
1639                         isp_prelight: isp-prelight {
1640                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1641                         };
1642
1643                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1644                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1645                         };
1646                 };
1647
1648                 gps {
1649                         gps_mag: gps-mag {
1650                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1651                         };
1652
1653                         gps_sig: gps-sig {
1654                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1655
1656                         };
1657
1658                         gps_rfclk: gps-rfclk {
1659                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1660                         };
1661                 };
1662
1663                 gmac {
1664                         mac_clk: mac-clk {
1665                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1666                         };
1667
1668                         mac_txpins: mac-txpins {
1669                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//TXD0
1670                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//TXD1
1671                                                 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//TXD2
1672                                                 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//TXD3
1673                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//TXEN
1674                                                 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>;//TXCLK
1675                         };
1676
1677                         mac_rxpins: mac-rxpins {
1678                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1679                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1680                                                 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1681                                                 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1682                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1683                                                 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//RXER
1684                                                 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1685                                                 <3 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;//COL
1686                         };
1687
1688                         mac_crs: mac-crs {
1689                                 rockchip,pins = <3 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>; //CRS
1690                         };
1691
1692                         mac_mdpins: mac-mdpins {
1693                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1694                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;//MDC
1695                         };
1696                 };
1697
1698                 tsadc_pin {
1699                         tsadc_int: tsadc-int {
1700                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
1701                         };
1702                         tsadc_gpio: tsadc-gpio {
1703                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
1704                         };
1705                 };
1706
1707                 hdmi_pin {
1708                         hdmi_cec: hdmi-cec {
1709                                 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1710                         };
1711                 };
1712         };
1713 };