1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include <dt-bindings/suspend/rockchip-pm.h>
3 #include <dt-bindings/pinctrl/rockchip.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/sensor-dev.h>
6 #include <dt-bindings/clock/rk_system_status.h>
8 #include "rk3368-clocks.dtsi"
11 compatible = "rockchip,rk3368";
13 rockchip,sram = <&sram>;
14 interrupt-parent = <&gic>;
41 entry-method = "arm,psci";
42 CPU_SLEEP_0: cpu-sleep-0 {
43 compatible = "arm,idle-state";
44 arm,psci-suspend-param = <0x1010000>;
45 entry-latency-us = <0x3fffffff>;
46 exit-latency-us = <0x40000000>;
47 min-residency-us = <0xffffffff>;
53 compatible = "arm,cortex-a53", "arm,armv8";
55 enable-method = "psci";
56 cpu-idle-states = <&CPU_SLEEP_0>;
60 compatible = "arm,cortex-a53", "arm,armv8";
62 enable-method = "psci";
63 cpu-idle-states = <&CPU_SLEEP_0>;
67 compatible = "arm,cortex-a53", "arm,armv8";
69 enable-method = "psci";
70 cpu-idle-states = <&CPU_SLEEP_0>;
74 compatible = "arm,cortex-a53", "arm,armv8";
76 enable-method = "psci";
77 cpu-idle-states = <&CPU_SLEEP_0>;
81 compatible = "arm,cortex-a53", "arm,armv8";
83 enable-method = "psci";
84 cpu-idle-states = <&CPU_SLEEP_0>;
88 compatible = "arm,cortex-a53", "arm,armv8";
90 enable-method = "psci";
91 cpu-idle-states = <&CPU_SLEEP_0>;
95 compatible = "arm,cortex-a53", "arm,armv8";
97 enable-method = "psci";
98 cpu-idle-states = <&CPU_SLEEP_0>;
102 compatible = "arm,cortex-a53", "arm,armv8";
104 enable-method = "psci";
105 cpu-idle-states = <&CPU_SLEEP_0>;
141 compatible = "arm,psci-0.2";
145 gic: interrupt-controller@ffb70000 {
146 compatible = "arm,cortex-a15-gic";
147 #interrupt-cells = <3>;
148 #address-cells = <0>;
149 interrupt-controller;
150 reg = <0x0 0xffb71000 0 0x1000>,
151 <0x0 0xffb72000 0 0x1000>;
154 ddrpctl: syscon@ff610000 {
155 compatible = "rockchip,rk3368-ddrpctl", "syscon";
156 reg = <0x0 0xff610000 0x0 0x400>;
159 pmu: syscon@ff730000 {
160 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
161 reg = <0x0 0xff730000 0x0 0x1000>;
164 pmugrf: syscon@ff738000 {
165 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
166 reg = <0x0 0xff738000 0x0 0x1000>;
169 sgrf: syscon@ff740000 {
170 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
171 reg = <0x0 0xff740000 0x0 0x1000>;
175 cru: syscon@ff760000 {
176 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
177 reg = <0x0 0xff760000 0x0 0x1000>;
180 grf: syscon@ff770000 {
181 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
182 reg = <0x0 0xff770000 0x0 0x1000>;
185 msch: syscon@ffac0000 {
186 compatible = "rockchip,rk3368-msch", "rockchip,msch", "syscon";
187 reg = <0x0 0xffac0000 0x0 0x3000>;
191 compatible = "arm,armv8-pmuv3";
192 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
202 cpu_axi_bus: cpu_axi_bus {
203 compatible = "rockchip,cpu_axi_bus";
204 #address-cells = <2>;
209 #address-cells = <2>;
214 reg = <0x0 0xffa80000 0x0 0x20>;
217 reg = <0x0 0xffa80080 0x0 0x20>;
220 reg = <0x0 0xffa80280 0x0 0x20>;
223 reg = <0x0 0xffa90000 0x0 0x20>;
226 reg = <0x0 0xffaa0000 0x0 0x20>;
229 reg = <0x0 0xffaa0080 0x0 0x20>;
232 reg = <0x0 0xffab0000 0x0 0x20>;
233 rockchip,priority = <2 2>;
236 reg = <0x0 0xffad0000 0x0 0x20>;
239 reg = <0x0 0xffad0080 0x0 0x20>;
242 reg = <0x0 0xffad0100 0x0 0x20>;
245 reg = <0x0 0xffad0180 0x0 0x20>;
246 rockchip,priority = <2 2>;
249 reg = <0x0 0xffad0200 0x0 0x20>;
250 rockchip,priority = <2 2>;
253 reg = <0x0 0xffad0280 0x0 0x20>;
256 reg = <0x0 0xffad0300 0x0 0x20>;
257 rockchip,priority = <2 2>;
260 reg = <0x0 0xffad0380 0x0 0x20>;
263 reg = <0x0 0xffad0400 0x0 0x20>;
266 reg = <0x0 0xffae0000 0x0 0x20>;
269 reg = <0x0 0xffae0100 0x0 0x20>;
272 reg = <0x0 0xffae0180 0x0 0x20>;
275 reg = <0x0 0xffaf0000 0x0 0x20>;
280 #address-cells = <2>;
285 reg = <0x0 0xffac0000 0x0 0x3c>;
286 rockchip,read-latency = <0x34>;
292 compatible = "arm,armv8-timer";
293 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
294 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
295 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
296 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
297 clock-frequency = <24000000>;
301 compatible = "rockchip,timer";
302 reg = <0x0 0xff810000 0x0 0x20>;
303 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
304 rockchip,broadcast = <1>;
307 sram: sram@ff8c0000 {
308 compatible = "mmio-sram";
309 reg = <0x0 0xff8c0000 0x0 0xf000>; /* 60K (reserved 4K for mailbox)*/
313 watchdog: wdt@ff800000 {
314 compatible = "rockchip,watch dog";
315 reg = <0x0 0xff800000 0x0 0x100>;
316 clocks = <&pclk_alive_pre>;
317 clock-names = "pclk_wdt";
318 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
320 rockchip,timeout = <60>;
321 rockchip,atboot = <1>;
322 rockchip,debug = <0>;
327 #address-cells = <2>;
329 compatible = "arm,amba-bus";
330 interrupt-parent = <&gic>;
333 pdma0: pdma@ff600000 {
334 compatible = "arm,pl330", "arm,primecell";
335 reg = <0x0 0xff600000 0x0 0x4000>;
336 clocks = <&clk_gates12 11>;
337 clock-names = "apb_pclk";
338 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
344 pdma1: pdma@ff250000 {
345 compatible = "arm,pl330", "arm,primecell";
346 reg = <0x0 0xff250000 0x0 0x4000>;
347 clocks = <&clk_gates19 3>;
348 clock-names = "apb_pclk";
349 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
355 reset: reset@ff760300{
356 compatible = "rockchip,reset";
357 reg = <0x0 0xff760300 0x0 0x38>;
358 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
362 nandc0: nandc@ff400000 {
363 compatible = "rockchip,rk-nandc";
364 reg = <0x0 0xff400000 0x0 0x4000>;
365 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&clk_nandc0>, <&clk_gates20 9>, <&clk_gates20 11>;
368 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
371 nandc0reg: nandc0@ff400000 {
372 compatible = "rockchip,rk-nandc";
373 reg = <0x0 0xff400000 0x0 0x4000>;
376 emmc: rksdmmc@ff0f0000 {
377 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
378 reg = <0x0 0xff0f0000 0x0 0x4000>;
379 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
380 #address-cells = <1>;
382 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
383 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
384 rockchip,grf = <&grf>;
386 fifo-depth = <0x100>;
390 sdmmc: rksdmmc@ff0c0000 {
391 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
392 reg = <0x0 0xff0c0000 0x0 0x4000>;
393 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
394 #address-cells = <1>;
396 pinctrl-names = "default", "idle", "udbg";
397 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
398 pinctrl-1 = <&sdmmc_gpio>;
399 pinctrl-2 = <&uart2_xfer &cpu_jtag &mcu_jtag &sdmmc_dectn>;
400 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
401 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
402 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
403 rockchip,grf = <&grf>;
405 fifo-depth = <0x100>;
409 sdio: rksdmmc@ff0d0000 {
410 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
411 reg = <0x0 0xff0d0000 0x0 0x4000>;
412 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
413 #address-cells = <1>;
415 pinctrl-names = "default","idle";
416 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
417 pinctrl-1 = <&sdio0_gpio>;
418 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
419 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
420 rockchip,grf = <&grf>;
422 fifo-depth = <0x100>;
427 compatible = "rockchip,rockchip-spi";
428 reg = <0x0 0xff110000 0x0 0x1000>;
429 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
430 #address-cells = <1>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
434 rockchip,spi-src-clk = <0>;
436 clocks =<&clk_spi0>, <&clk_gates19 4>;
437 clock-names = "spi", "pclk_spi0";
438 //dmas = <&pdma1 11>, <&pdma1 12>;
440 //dma-names = "tx", "rx";
445 compatible = "rockchip,rockchip-spi";
446 reg = <0x0 0xff120000 0x0 0x1000>;
447 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
448 #address-cells = <1>;
450 pinctrl-names = "default";
451 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0 &spi1_cs1>;
452 rockchip,spi-src-clk = <1>;
454 clocks = <&clk_spi1>, <&clk_gates19 5>;
455 clock-names = "spi", "pclk_spi1";
456 //dmas = <&pdma1 13>, <&pdma1 14>;
458 //dma-names = "tx", "rx";
463 compatible = "rockchip,rockchip-spi";
464 reg = <0x0 0xff130000 0x0 0x1000>;
465 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
466 #address-cells = <1>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
470 rockchip,spi-src-clk = <2>;
472 clocks = <&clk_spi2>, <&clk_gates19 6>;
473 clock-names = "spi", "pclk_spi2";
474 //dmas = <&pdma1 15>, <&pdma1 16>;
476 //dma-names = "tx", "rx";
480 uart_bt: serial@ff180000 {
481 compatible = "rockchip,serial";
482 reg = <0x0 0xff180000 0x0 0x100>;
483 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
484 clock-frequency = <24000000>;
485 clocks = <&clk_uart0>, <&clk_gates19 7>;
486 clock-names = "sclk_uart", "pclk_uart";
489 //dmas = <&pdma1 1>, <&pdma1 2>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
496 uart_bb: serial@ff190000 {
497 compatible = "rockchip,serial";
498 reg = <0x0 0xff190000 0x0 0x100>;
499 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
500 clock-frequency = <24000000>;
501 clocks = <&clk_uart1>, <&clk_gates19 8>;
502 clock-names = "sclk_uart", "pclk_uart";
505 //dmas = <&pdma1 3>, <&pdma1 4>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
512 uart_dbg: serial@ff690000 {
513 compatible = "rockchip,serial";
514 reg = <0x0 0xff690000 0x0 0x100>;
515 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
516 clock-frequency = <24000000>;
517 clocks = <&clk_uart2>, <&clk_gates13 5>;
518 clock-names = "sclk_uart", "pclk_uart";
521 //dmas = <&pdma0 4>, <&pdma0 5>;
523 //pinctrl-names = "default";
524 //pinctrl-0 = <&uart2_xfer>;
528 uart_gps: serial@ff1b0000 {
529 compatible = "rockchip,serial";
530 reg = <0x0 0xff1b0000 0x0 0x100>;
531 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
532 clock-frequency = <24000000>;
533 clocks = <&clk_uart3>, <&clk_gates19 9>;
534 clock-names = "sclk_uart", "pclk_uart";
535 current-speed = <115200>;
538 //dmas = <&pdma1 7>, <&pdma1 8>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
545 uart_exp: serial@ff1c0000 {
546 compatible = "rockchip,serial";
547 reg = <0x0 0xff1c0000 0x0 0x100>;
548 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
549 clock-frequency = <24000000>;
550 clocks = <&clk_uart4>, <&clk_gates19 10>;
551 clock-names = "sclk_uart", "pclk_uart";
554 //dmas = <&pdma1 9>, <&pdma1 10>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
561 mbox: mbox@ff6b0000 {
562 compatible = "rockchip,rk3368-mailbox";
563 reg = <0x0 0xff6b0000 0x0 0x1000>,
564 <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
565 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&clk_gates12 1>;
570 clock-names = "pclk_mailbox";
574 mbox_scpi: mbox-scpi {
575 compatible = "rockchip,mbox-scpi";
576 mboxes = <&mbox 0 &mbox 1>;
580 compatible = "rockchip,rk3368-ddr";
582 rockchip,ddrpctl = <&ddrpctl>;
583 rockchip,grf = <&grf>;
584 rockchip,msch = <&msch>;
587 rockchip_clocks_init: clocks-init{
588 compatible = "rockchip,clocks-init";
589 rockchip,clocks-init-parent =
590 <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
591 <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
592 <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
593 <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
594 rockchip,clocks-init-rate =
595 <&clk_gpll 576000000>, <&clk_core_b 792000000>,
596 <&clk_core_l 600000000>, <&clk_cpll 400000000>,
597 /*<&clk_npll 500000000>,*/ <&aclk_bus 300000000>,
598 <&hclk_bus 150000000>, <&pclk_bus 75000000>,
599 <&clk_crypto 150000000>, <&aclk_peri 300000000>,
600 <&hclk_peri 150000000>, <&pclk_peri 75000000>,
601 <&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>,
602 <&clk_cs 300000000>, <&clkin_trace 300000000>,
603 <&aclk_cci 600000000>, <&clk_mac 125000000>,
604 <&aclk_vio0 400000000>, <&hclk_vio 100000000>,
605 <&aclk_rga_pre 400000000>, <&clk_rga 400000000>,
606 <&clk_isp 400000000>, <&clk_edp 200000000>,
607 <&clk_gpu_core 400000000>, <&aclk_gpu_mem 400000000>,
608 <&aclk_gpu_cfg 400000000>, <&aclk_vepu 400000000>,
609 <&aclk_vdpu 400000000>, <&clk_hevc_core 300000000>,
610 <&clk_hevc_cabac 300000000>;
612 rockchip,clocks-uboot-has-init =
617 rockchip_clocks_enable: clocks-enable {
618 compatible = "rockchip,clocks-enable";
636 <&clk_gates12 12>,/*aclk_strc_sys*/
637 <&clk_gates12 6>,/*aclk_intmem1*/
638 <&clk_gates12 5>,/*aclk_intmem0*/
639 <&clk_gates12 4>,/*aclk_intmem*/
640 <&clk_gates13 9>,/*aclk_gic400*/
641 <&clk_gates12 9>,/*hclk_rom*/
644 <&clk_gates22 13>,/*pclk_timer1*/
645 <&clk_gates22 12>,/*pclk_timer0*/
646 <&clk_gates22 9>,/*pclk_alive_niu*/
647 <&clk_gates22 8>,/*pclk_grf*/
650 <&clk_gates23 5>,/*pclk_pmugrf*/
651 <&clk_gates23 3>,/*pclk_sgrf*/
652 <&clk_gates23 2>,/*pclk_pmu_noc*/
653 <&clk_gates23 1>,/*pclk_intmem1*/
654 <&clk_gates23 0>,/*pclk_pmu*/
657 <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
658 <&clk_gates20 8>,/*aclk_peri_niu*/
659 <&clk_gates21 4>,/*aclk_peri_mmu*/
660 <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
661 <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
662 <&clk_gates19 1>,/*pclk_peri_axi_matrix*/
666 <&clk_gates7 0>;/*clk_jtag*/
671 compatible = "rockchip,rk30-i2c";
672 reg = <0x0 0xff650000 0x0 0x1000>;
673 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
674 #address-cells = <1>;
676 pinctrl-names = "default", "gpio", "sleep";
677 pinctrl-0 = <&i2c0_xfer>;
678 pinctrl-1 = <&i2c0_gpio>;
679 pinctrl-2 = <&i2c0_sleep>;
680 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
681 clocks = <&clk_gates12 2>;
682 rockchip,check-idle = <1>;
688 compatible = "rockchip,rk30-i2c";
689 reg = <0x0 0xff660000 0x0 0x1000>;
690 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
691 #address-cells = <1>;
693 pinctrl-names = "default", "gpio", "sleep";
694 pinctrl-0 = <&i2c1_xfer>;
695 pinctrl-1 = <&i2c1_gpio>;
696 pinctrl-2 = <&i2c1_sleep>;
697 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
698 clocks = <&clk_gates12 3>;
699 rockchip,check-idle = <1>;
705 compatible = "rockchip,rk30-i2c";
706 reg = <0x0 0xff140000 0x0 0x1000>;
707 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
708 #address-cells = <1>;
710 pinctrl-names = "default", "gpio", "sleep";
711 pinctrl-0 = <&i2c2_xfer>;
712 pinctrl-1 = <&i2c2_gpio>;
713 pinctrl-2 = <&i2c2_sleep>;
714 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
715 clocks = <&clk_gates19 11>;
716 rockchip,check-idle = <1>;
722 compatible = "rockchip,rk30-i2c";
723 reg = <0x0 0xff150000 0x0 0x1000>;
724 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
725 #address-cells = <1>;
727 pinctrl-names = "default", "gpio", "sleep";
728 pinctrl-0 = <&i2c3_xfer>;
729 pinctrl-1 = <&i2c3_gpio>;
730 pinctrl-2 = <&i2c3_sleep>;
731 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
732 clocks = <&clk_gates19 12>;
733 rockchip,check-idle = <1>;
739 compatible = "rockchip,rk30-i2c";
740 reg = <0x0 0xff160000 0x0 0x1000>;
741 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
742 #address-cells = <1>;
744 pinctrl-names = "default", "gpio", "sleep";
745 pinctrl-0 = <&i2c4_xfer>;
746 pinctrl-1 = <&i2c4_gpio>;
747 pinctrl-2 = <&i2c4_sleep>;
748 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
749 clocks = <&clk_gates19 13>;
750 rockchip,check-idle = <1>;
756 compatible = "rockchip,rk30-i2c";
757 reg = <0x0 0xff170000 0x0 0x1000>;
758 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
759 #address-cells = <1>;
761 pinctrl-names = "default", "gpio", "sleep";
762 pinctrl-0 = <&i2c5_xfer>;
763 pinctrl-1 = <&i2c5_gpio>;
764 pinctrl-2 = <&i2c5_sleep>;
765 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
766 clocks = <&clk_gates19 14>;
767 rockchip,check-idle = <1>;
772 compatible = "rockchip,rk-fb";
773 rockchip,disp-mode = <NO_DUAL>;
777 rk_screen: rk_screen {
778 compatible = "rockchip,screen";
781 dsihost0: mipi@ff960000{
782 compatible = "rockchip,rk3368-dsi";
784 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
785 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
786 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>, <&pd_mipidsi>;
788 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host", "pd_mipi_dsi";
792 lvds: lvds@ff968000 {
793 compatible = "rockchip,rk3368-lvds";
794 rockchip,grf = <&grf>;
795 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
796 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
797 clocks = <&clk_gates22 10>, <&clk_gates17 3>, <&pd_lvds>;
798 clock-names = "pclk_lvds", "pclk_lvds_ctl", "pd_lvds";
803 compatible = "rockchip,rk32-edp";
804 reg = <0x0 0xff970000 0x0 0x4000>;
805 rockchip,grf = <&grf>;
806 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
808 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
809 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
810 reset-names = "edp_24m", "edp_apb";
813 hdmi: hdmi@ff980000 {
814 compatible = "rockchip,rk3368-hdmi";
815 reg = <0x0 0xff980000 0x0 0x20000>;
816 rockchip,grf = <&grf>;
817 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
818 pinctrl-names = "default", "gpio";
819 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
820 pinctrl-1 = <&i2c5_gpio>;
821 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
822 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
826 hdmi_hdcp2: hdmi_hdcp2@ff978000 {
827 compatible = "rockchip,rk3368-hdmi-hdcp2";
828 reg = <0x0 0xff978000 0x0 0x2000>;
829 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
830 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
831 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
835 lcdc: lcdc@ff930000 {
836 compatible = "rockchip,rk3368-lcdc";
837 rockchip,grf = <&grf>;
838 rockchip,pmugrf = <&pmugrf>;
839 rockchip,cru = <&cru>;
840 rockchip,prop = <PRMRY>;
841 rockchip,pwr18 = <0>;
842 rockchip,iommu-enabled = <1>;
843 reg = <0x0 0xff930000 0x0 0x10000>;
844 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
845 /*pinctrl-names = "default", "gpio";
846 *pinctrl-0 = <&lcdc_lcdc>;
847 *pinctrl-1 = <&lcdc_gpio>;
850 clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>, <&pd_vop>;
851 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll", "pd_lcdc";
855 compatible = "rockchip,saradc";
856 reg = <0x0 0xff100000 0x0 0x100>;
857 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
858 #io-channel-cells = <1>;
860 rockchip,adc-vref = <1800>;
861 clock-frequency = <1000000>;
862 clocks = <&clk_saradc>, <&clk_gates19 15>;
863 clock-names = "saradc", "pclk_saradc";
868 compatible = "rockchip,rk3368-rga2";
869 reg = <0x0 0xff920000 0x0 0x1000>;
870 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
872 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
875 i2s0: i2s0@ff898000 {
876 compatible = "rockchip-i2s";
877 reg = <0x0 0xff898000 0x0 0x1000>;
879 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
880 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
881 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
882 dmas = <&pdma0 0>, <&pdma0 1>;
884 dma-names = "tx", "rx";
885 pinctrl-names = "default", "sleep";
886 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
887 pinctrl-1 = <&i2s_gpio>;
890 i2s1: i2s1@ff890000 {
891 compatible = "rockchip-i2s";
892 reg = <0x0 0xff890000 0x0 0x1000>;
894 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
895 clock-names = "i2s_clk", "i2s_hclk";
896 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
897 dmas = <&pdma0 6>, <&pdma0 7>;
899 dma-names = "tx", "rx";
902 spdif: spdif@ff880000 {
903 compatible = "rockchip-spdif";
904 reg = <0x0 0xff880000 0x0 0x1000>;
905 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
906 clock-names = "spdif_mclk", "spdif_hclk";
907 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
911 pinctrl-names = "default";
912 pinctrl-0 = <&spdif_tx>;
916 compatible = "rockchip,rk-pwm";
917 reg = <0x0 0xff680000 0x0 0x10>;
919 pinctrl-names = "default";
920 pinctrl-0 = <&pwm0_pin>;
921 clocks = <&clk_gates13 6>;
922 clock-names = "pclk_pwm";
927 compatible = "rockchip,rk-pwm";
928 reg = <0x0 0xff680010 0x0 0x10>;
930 pinctrl-names = "default";
931 pinctrl-0 = <&pwm1_pin>;
932 clocks = <&clk_gates13 6>;
933 clock-names = "pclk_pwm";
938 compatible = "rockchip,rk-pwm";
939 reg = <0x0 0xff680020 0x0 0x10>;
941 //pinctrl-names = "default";
942 //pinctrl-0 = <&pwm1_pin>;
943 clocks = <&clk_gates13 6>;
944 clock-names = "pclk_pwm";
949 compatible = "rockchip,rk-pwm";
950 reg = <0x0 0xff680030 0x0 0x10>;
952 pinctrl-names = "default";
953 pinctrl-0 = <&pwm3_pin>;
954 clocks = <&clk_gates13 6>;
955 clock-names = "pclk_pwm";
959 remotectl: pwm@ff680030 {
960 compatible = "rockchip,remotectl-pwm";
961 reg = <0x0 0xff680030 0x0 0x50>;
963 pinctrl-names = "default";
964 pinctrl-0 = <&pwm3_pin>;
965 clocks = <&clk_gates13 6>;
966 clock-names = "pclk_pwm";
971 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
975 voppwm: pwm@ff9301a0 {
976 compatible = "rockchip,vop-pwm";
977 reg = <0x0 0xff9301a0 0x0 0x10>;
979 pinctrl-names = "default";
980 pinctrl-0 = <&vop_pwm_pin>;
981 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
982 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
987 compatible = "rockchip,rk3368-pvtm";
988 rockchip,grf = <&grf>;
989 rockchip,pmugrf = <&pmugrf>;
990 rockchip,pvtm-clk-out = <1>;
994 compatible = "rockchip,rk3368-cpufreq";
995 rockchip,grf = <&grf>;
1001 regulator_name = "vdd_arm";
1002 suspend_volt = <1000>; //mV
1004 clk_core_b_dvfs_table: clk_core_b {
1005 operating-points = <
1013 temp-limit-enable = <1>;
1015 min_temp_limit = <216>;
1016 normal-temp-limit = <
1017 /*delta-temp delta-freq*/
1023 performance-temp-limit = <
1028 clk_core_l_dvfs_table: clk_core_l {
1029 operating-points = <
1037 temp-limit-enable = <1>;
1039 min_temp_limit = <216>;
1040 normal-temp-limit = <
1041 /*delta-temp delta-freq*/
1047 performance-temp-limit = <
1055 vd_logic: vd_logic {
1056 regulator_name = "vdd_logic";
1057 suspend_volt = <1000>; //mV
1059 clk_ddr_dvfs_table: clk_ddr {
1060 operating-points = <
1067 status = "disabled";
1072 clk_gpu_dvfs_table: clk_gpu {
1073 operating-points = <
1093 compatible = "rockchip,ion";
1094 #address-cells = <1>;
1097 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1098 compatible = "rockchip,ion-heap";
1099 rockchip,ion_heap = <4>;
1100 reg = <0x00000000 0x00000000>; /* 0MB */
1102 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1103 compatible = "rockchip,ion-heap";
1104 rockchip,ion_heap = <0>;
1109 compatible = "rockchip,vpu_sub";
1110 iommu_enabled = <1>;
1111 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1113 interrupt-names = "irq_enc", "irq_dec";
1115 name = "vpu_service";
1118 hevc: hevc_service {
1119 compatible = "rockchip,hevc_sub";
1120 iommu_enabled = <1>;
1121 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1122 interrupt-names = "irq_dec";
1124 name = "hevc_service";
1127 vpu_combo: vpu_combo@ff9a0000 {
1128 compatible = "rockchip,vpu_combo";
1129 reg = <0x0 0xff9a0000 0x0 0x800>;
1130 rockchip,grf = <&grf>;
1132 rockchip,sub = <&vpu>, <&hevc>;
1133 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1134 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1136 mode_ctrl = <0x418>;
1142 compatible = "rockchip,iep";
1143 iommu_enabled = <1>;
1144 reg = <0x0 0xff900000 0x0 0x800>;
1145 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1146 clocks = <&clk_gates16 2>, <&clk_gates16 3>;
1147 clock-names = "aclk_iep", "hclk_iep";
1151 gmac: eth@ff290000 {
1152 compatible = "rockchip,rk3368-gmac";
1153 reg = <0x0 0xff290000 0x0 0x10000>;
1154 rockchip,grf = <&grf>;
1155 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
1156 interrupt-names = "macirq";
1158 clocks = <&clk_mac>, <&clk_gates7 4>,
1159 <&clk_gates7 5>, <&clk_gates7 6>,
1160 <&clk_gates7 7>, <&clk_gates20 13>,
1162 clock-names = "clk_mac", "mac_clk_rx",
1163 "mac_clk_tx", "clk_mac_ref",
1164 "clk_mac_refout", "aclk_mac",
1168 pinctrl-names = "default";
1169 pinctrl-0 = <&rgmii_pins>;
1170 status = "disabled";
1174 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1175 reg = <0x0 0xffa30000 0x0 0x10000>;
1176 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1177 interrupt-names = "GPU";
1182 compatible = "rockchip,iep_mmu";
1183 reg = <0x0 0xff900800 0x0 0x100>;
1184 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1185 interrupt-names = "iep_mmu";
1190 compatible = "rockchip,vip_mmu";
1191 reg = <0x0 0xff950800 0x0 0x100>;
1192 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1193 interrupt-names = "vip_mmu";
1198 compatible = "rockchip,vopb_mmu";
1199 reg = <0x0 0xff930300 0x0 0x100>;
1200 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1201 interrupt-names = "vop_mmu";
1205 dbgname = "isp_mmu";
1206 compatible = "rockchip,isp_mmu";
1207 reg = <0x0 0xff914000 0x0 0x100>,
1208 <0x0 0xff915000 0x0 0x100>;
1209 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1210 interrupt-names = "isp_mmu";
1214 dbgname = "hdcp_mmu";
1215 compatible = "rockchip,hdcp_mmu";
1216 reg = <0x0 0xff940000 0x0 0x100>;
1217 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1218 interrupt-names = "hdcp_mmu";
1223 compatible = "rockchip,hevc_mmu";
1224 reg = <0x0 0xff9a0440 0x0 0x40>, /*need to fix*/
1225 <0x0 0xff9a0480 0x0 0x40>;
1226 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1227 interrupt-names = "hevc_mmu";
1232 compatible = "rockchip,vpu_mmu";
1233 reg = <0x0 0xff9a0800 0x0 0x100>; /*need to fix*/
1234 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /*need to fix*/
1235 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1236 interrupt-names = "vepu_mmu", "vdpu_mmu";
1240 rockchip,ctrbits = <
1247 |RKPM_CTR_SYSCLK_DIV
1248 |RKPM_CTR_IDLEAUTO_MD
1249 |RKPM_CTR_ARMOFF_LPMD
1251 |RKPM_CTR_ARMOFF_LOGDP_LPMD
1254 rockchip,pmic-suspend_gpios = <
1255 /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1257 rockchip,pmic-resume_gpios = <
1258 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1263 compatible = "rockchip,isp";
1264 reg = <0x0 0xff910000 0x0 0x10000>;
1265 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1266 clocks = <&clk_gates16 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>, <&pd_isp>;
1267 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx", "pd_isp";
1268 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1269 pinctrl-0 = <&cif_clkout>;
1270 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1271 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1272 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1273 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1274 pinctrl-5 = <&cif_clkout>;
1275 pinctrl-6 = <&cif_clkout &isp_prelight>;
1276 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1277 pinctrl-8 = <&isp_flash_trigger>;
1278 rockchip,isp,mipiphy = <2>;
1279 rockchip,isp,cifphy = <1>;
1280 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1281 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1282 rockchip,grf = <&grf>;
1283 rockchip,cru = <&cru>;
1284 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1285 rockchip,isp,iommu_enable = <1>;
1290 compatible = "rockchip,cif";
1291 reg = <0x0 0xff950000 0x0 0x10000>;
1292 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1293 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1294 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1295 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1296 pinctrl-names = "cif_pin_all";
1297 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1298 rockchip,grf = <&grf>;
1299 rockchip,cru = <&cru>;
1305 #include "rk3368-thermal.dtsi"
1309 tsadc: tsadc@ff280000 {
1310 compatible = "rockchip,rk3368-tsadc";
1311 reg = <0x0 0xff280000 0x0 0x100>;
1312 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1313 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1314 rockchip,grf = <&grf>;
1315 rockchip,cru = <&cru>;
1316 rockchip,pmu = <&pmu>;
1317 clock-names = "tsadc", "apb_pclk";
1318 clock-frequency = <32000>;
1319 resets = <&reset RK3368_SRST_TSADC_P>;
1320 reset-names = "tsadc-apb";
1321 //pinctrl-names = "default";
1322 //pinctrl-0 = <&tsadc_int>;
1323 #thermal-sensor-cells = <1>;
1324 hw-shut-temp = <120000>;
1325 status = "disabled";
1329 compatible = "rockchip,rk3368-tsp";
1330 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1331 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1332 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1333 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1334 interrupt-names = "irq_tsp";
1335 // pinctrl-names = "default";
1336 // pinctrl-0 = <&isp_hsadc>;
1340 crypto: crypto@FF8A0000{
1341 compatible = "rockchip,rk3368-crypto";
1342 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1343 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1344 interrupt-names = "irq_crypto";
1345 clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1346 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1350 dwc_control_usb: dwc-control-usb {
1351 compatible = "rockchip,rk3368-dwc-control-usb";
1352 rockchip,grf = <&grf>;
1353 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1355 interrupt-names = "otg_id", "otg_bvalid",
1356 "otg_linestate", "host0_linestate";
1357 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1358 clock-names = "hclk_usb_peri", "usbphy_480m";
1359 //resets = <&reset RK3128_RST_USBPOR>;
1360 //reset-names = "usbphy_por";
1362 compatible = "inno,phy";
1363 regbase = &dwc_control_usb;
1364 rk_usb,bvalid = <0x4bc 23 1>;
1365 rk_usb,iddig = <0x4bc 26 1>;
1366 rk_usb,vdmsrcen = <0x718 12 1>;
1367 rk_usb,vdpsrcen = <0x718 11 1>;
1368 rk_usb,rdmpden = <0x718 10 1>;
1369 rk_usb,idpsrcen = <0x718 9 1>;
1370 rk_usb,idmsinken = <0x718 8 1>;
1371 rk_usb,idpsinken = <0x718 7 1>;
1372 rk_usb,dpattach = <0x4b8 31 1>;
1373 rk_usb,cpdet = <0x4b8 30 1>;
1374 rk_usb,dcpattach = <0x4b8 29 1>;
1378 usb0: usb@ff580000 {
1379 compatible = "rockchip,rk3368_usb20_otg";
1380 reg = <0x0 0xff580000 0x0 0x40000>;
1381 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1382 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1383 clock-names = "clk_usbphy0", "hclk_otg";
1384 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1385 <&reset RK3368_SRST_USBOTGC0>;
1386 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1387 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1388 rockchip,usb-mode = <0>;
1391 usb_ehci: usb@ff500000 {
1392 compatible = "generic-ehci";
1393 reg = <0x0 0xff500000 0x0 0x20000>;
1394 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1395 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1396 clock-names = "clk_usbphy0", "hclk_ehci";
1397 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1398 // <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1399 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1402 usb_ohci: usb@ff520000 {
1403 compatible = "generic-ohci";
1404 reg = <0x0 0xff520000 0x0 0x20000>;
1405 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1406 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1407 clock-names = "clk_usbphy0", "hclk_ohci";
1410 usb_hsic: usb@ff5c0000 {
1411 compatible = "rockchip,rk3288_rk_hsic_host";
1412 reg = <0x0 0xff5c0000 0x0 0x40000>;
1413 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1415 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1416 <&hsicphy_12m>, <&usbphy_480m>,
1417 <&otgphy1_480m>, <&otgphy2_480m>;
1418 clock-names = "hsicphy_480m", "hclk_hsic",
1419 "hsicphy_12m", "usbphy_480m",
1420 "hsic_usbphy1", "hsic_usbphy2";
1421 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1422 <&reset RK3288_SOFT_RST_HSICPHY>;
1423 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1425 status = "disabled";
1429 compatible = "rockchip,rk3368-pinctrl";
1430 rockchip,grf = <&grf>;
1431 rockchip,pmugrf = <&pmugrf>;
1432 #address-cells = <2>;
1436 gpio0: gpio0@ff750000 {
1437 compatible = "rockchip,gpio-bank";
1438 reg = <0x0 0xff750000 0x0 0x100>;
1439 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1440 clocks = <&clk_gates23 4>;
1445 interrupt-controller;
1446 #interrupt-cells = <2>;
1449 gpio1: gpio1@ff780000 {
1450 compatible = "rockchip,gpio-bank";
1451 reg = <0x0 0xff780000 0x0 0x100>;
1452 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1453 clocks = <&clk_gates22 1>;
1458 interrupt-controller;
1459 #interrupt-cells = <2>;
1462 gpio2: gpio2@ff790000 {
1463 compatible = "rockchip,gpio-bank";
1464 reg = <0x0 0xff790000 0x0 0x100>;
1465 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1466 clocks = <&clk_gates22 2>;
1471 interrupt-controller;
1472 #interrupt-cells = <2>;
1475 gpio3: gpio3@ff7a0000 {
1476 compatible = "rockchip,gpio-bank";
1477 reg = <0x0 0xff7a0000 0x0 0x100>;
1478 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1479 clocks = <&clk_gates22 3>;
1484 interrupt-controller;
1485 #interrupt-cells = <2>;
1488 pcfg_pull_up: pcfg-pull-up {
1492 pcfg_pull_down: pcfg-pull-down {
1496 pcfg_pull_none: pcfg-pull-none {
1500 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1501 drive-strength = <8>;
1504 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1505 drive-strength = <12>;
1508 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1510 drive-strength = <8>;
1513 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1514 drive-strength = <4>;
1517 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1519 drive-strength = <4>;
1522 pcfg_output_high: pcfg-output-high {
1526 pcfg_output_low: pcfg-output-low {
1530 pcfg_input_high: pcfg-input-high {
1536 i2c0_xfer: i2c0-xfer {
1537 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1538 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1540 i2c0_gpio: i2c0-gpio {
1541 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1542 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1544 i2c0_sleep: i2c0-sleep {
1545 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_input_high>,
1546 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_input_high>;
1551 i2c1_xfer: i2c1-xfer {
1552 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1553 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1555 i2c1_gpio: i2c1-gpio {
1556 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1557 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1559 i2c1_sleep: i2c1-sleep {
1560 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_input_high>,
1561 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_input_high>;
1566 i2c2_xfer: i2c2-xfer {
1567 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1568 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1570 i2c2_gpio: i2c2-gpio {
1571 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1572 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1574 i2c2_sleep: i2c2-sleep {
1575 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_input_high>,
1576 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_input_high>;
1581 i2c3_xfer: i2c3-xfer {
1582 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1583 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1585 i2c3_gpio: i2c3-gpio {
1586 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1587 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1589 i2c3_sleep: i2c3-sleep {
1590 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_input_high>,
1591 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_input_high>;
1596 i2c4_xfer: i2c4-xfer {
1597 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1598 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1600 i2c4_gpio: i2c4-gpio {
1601 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1602 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1604 i2c4_sleep: i2c4-sleep {
1605 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_input_high>,
1606 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_input_high>;
1611 i2c5_xfer: i2c5-xfer {
1612 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1613 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1615 i2c5_gpio: i2c5-gpio {
1616 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1617 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1619 i2c5_sleep: i2c5-sleep {
1620 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_input_high>,
1621 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_input_high>;
1626 uart0_xfer: uart0-xfer {
1627 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1628 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1631 uart0_cts: uart0-cts {
1632 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1635 uart0_rts: uart0-rts {
1636 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1639 uart0_rts_gpio: uart0-rts-gpio {
1640 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1645 uart1_xfer: uart1-xfer {
1646 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1647 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1650 uart1_cts: uart1-cts {
1651 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1654 uart1_rts: uart1-rts {
1655 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1660 uart2_xfer: uart2-xfer {
1661 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1662 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1667 uart3_xfer: uart3-xfer {
1668 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1669 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1672 uart3_cts: uart3-cts {
1673 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1676 uart3_rts: uart3-rts {
1677 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1682 uart4_xfer: uart4-xfer {
1683 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1684 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1687 uart4_cts: uart4-cts {
1688 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1691 uart4_rts: uart4-rts {
1692 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1697 spi0_clk: spi0-clk {
1698 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1700 spi0_cs0: spi0-cs0 {
1701 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1704 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1707 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1709 spi0_cs1: spi0-cs1 {
1710 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1715 spi1_clk: spi1-clk {
1716 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1718 spi1_cs0: spi1-cs0 {
1719 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1722 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1725 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1727 spi1_cs1: spi1-cs1 {
1728 rockchip,pins = <3 GPIO_D4 RK_FUNC_2 &pcfg_pull_up>;
1733 spi2_clk: spi2-clk {
1734 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1736 spi2_cs0: spi2-cs0 {
1737 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1740 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1743 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1748 i2s_mclk: i2s-mclk {
1749 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1753 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1756 i2s_lrckrx:i2s-lrckrx {
1757 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1760 i2s_lrcktx:i2s-lrcktx {
1761 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1765 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1769 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1773 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1777 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1781 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1784 i2s_gpio: i2s-gpio {
1785 rockchip,pins = <2 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,
1786 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1787 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1788 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1789 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1790 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1791 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1792 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1793 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1798 spdif_tx: spdif-tx {
1799 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1804 sdmmc_clk: sdmmc-clk {
1805 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1808 sdmmc_cmd: sdmmc-cmd {
1809 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1812 sdmmc_dectn: sdmmc-dectn {
1813 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1816 sdmmc_bus1: sdmmc-bus1 {
1817 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1820 sdmmc_bus4: sdmmc-bus4 {
1821 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1822 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1823 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1824 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1827 sdmmc_gpio: sdmmc-gpio {
1828 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1829 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1830 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1831 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1832 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1833 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1834 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1839 sdio0_bus1: sdio0-bus1 {
1840 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1843 sdio0_bus4: sdio0-bus4 {
1844 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1845 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1846 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1847 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1850 sdio0_cmd: sdio0-cmd {
1851 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1854 sdio0_clk: sdio0-clk {
1855 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1858 sdio0_dectn: sdio0-dectn {
1859 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1862 sdio0_wrprt: sdio0-wrprt {
1863 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1866 sdio0_pwren: sdio0-pwren {
1867 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1870 sdio0_bkpwr: sdio0-bkpwr {
1871 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1874 sdio0_int: sdio0-int {
1875 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1878 sdio0_gpio: sdio0-gpio {
1879 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1880 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1881 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1882 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1883 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1884 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1885 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1886 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1887 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1888 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1889 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1894 emmc_clk: emmc-clk {
1895 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1898 emmc_cmd: emmc-cmd {
1899 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1902 emmc_pwren: emmc-pwren {
1903 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1906 emmc_rstnout: emmc_rstnout {
1907 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1910 emmc_bus1: emmc-bus1 {
1911 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1914 emmc_bus4: emmc-bus4 {
1915 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1916 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1917 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1918 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1923 pwm0_pin: pwm0-pin {
1924 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1927 vop_pwm_pin:vop-pwm {
1928 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1933 pwm1_pin: pwm1-pin {
1934 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1939 pwm3_pin: pwm3-pin {
1940 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1945 lcdc_lcdc: lcdc-lcdc {
1947 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1948 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1949 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1950 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1951 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1952 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1953 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1954 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1955 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1956 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1957 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1958 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1959 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1960 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1961 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1962 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1963 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1964 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1967 lcdc_gpio: lcdc-gpio {
1969 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1970 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1971 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1972 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1973 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1974 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1975 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1976 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1977 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1978 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1979 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1980 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1981 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1982 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1983 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1984 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1985 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1986 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1991 cif_clkout: cif-clkout {
1992 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1995 isp_dvp_d2d9: isp-dvp-d2d9 {
1996 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1997 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1998 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1999 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2000 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2001 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2002 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2003 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2004 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
2005 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
2006 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
2007 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2010 isp_dvp_d0d1: isp-dvp-d0d1 {
2011 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2012 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
2015 isp_dvp_d10d11:isp_d10d11 {
2016 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2017 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2020 isp_dvp_d0d7: isp-dvp-d0d7 {
2021 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2022 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
2023 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2024 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2025 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2026 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2027 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2028 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
2031 isp_shutter: isp-shutter {
2032 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2033 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2036 isp_flash_trigger: isp-flash-trigger {
2037 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2040 isp_prelight: isp-prelight {
2041 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2044 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2045 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
2051 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
2055 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
2059 gps_rfclk: gps-rfclk {
2060 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
2065 rgmii_pins: rgmii-pins {
2066 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2067 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2068 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2069 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2070 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2071 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
2072 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
2073 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
2074 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2075 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2076 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2077 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
2078 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
2079 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
2080 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
2083 rmii_pins: rmii-pins {
2084 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2085 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2086 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2087 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2088 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2089 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2090 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2091 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2092 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
2093 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
2098 tsadc_int: tsadc-int {
2099 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
2101 tsadc_gpio: tsadc-gpio {
2102 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
2107 hdmi_cec: hdmi-cec {
2108 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
2113 hdmii2c_xfer: hdmii2c-xfer {
2114 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
2115 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
2120 cpu_jtag: cpu-jtag {
2121 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_up>,
2122 <2 GPIO_B0 RK_FUNC_2 &pcfg_pull_up>;
2127 mcu_jtag: mcu-jtag {
2128 rockchip,pins = <2 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>,
2129 <2 GPIO_B1 RK_FUNC_2 &pcfg_pull_up>;
2135 compatible = "rockchip,rk3368-reboot";
2136 rockchip,cru = <&cru>;
2137 rockchip,pmugrf = <&pmugrf>;