arch/arm64/boot/dts/rk3368.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/sensor-dev.h>
   6 #include <dt-bindings/clock/rk_system_status.h>
   7
   8 #include "rk3368-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk3368";
  12
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &uart_bt;
  20                 serial1 = &uart_bb;
  21                 serial2 = &uart_dbg;
  22                 serial3 = &uart_gps;
  23                 serial4 = &uart_exp;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &spi0;
  31                 spi1 = &spi1;
  32                 spi2 = &spi2;
  33                 lcdc = &lcdc;
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 idle-states {
  41                         entry-method = "arm,psci";
  42                         CPU_SLEEP_0: cpu-sleep-0 {
  43                                 compatible = "arm,idle-state";
  44                                 arm,psci-suspend-param = <0x1010000>;
  45                                 entry-latency-us = <0x3fffffff>;
  46                                 exit-latency-us = <0x40000000>;
  47                                 min-residency-us = <0xffffffff>;
  48                         };
  49                 };
  50
  51                 little0: cpu@0 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53", "arm,armv8";
  54                         reg = <0x0 0x0>;
  55                         enable-method = "psci";
  56                         cpu-idle-states = <&CPU_SLEEP_0>;
  57                 };
  58                 little1: cpu@1 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53", "arm,armv8";
  61                         reg = <0x0 0x1>;
  62                         enable-method = "psci";
  63                         cpu-idle-states = <&CPU_SLEEP_0>;
  64                 };
  65                 little2: cpu@2 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53", "arm,armv8";
  68                         reg = <0x0 0x2>;
  69                         enable-method = "psci";
  70                         cpu-idle-states = <&CPU_SLEEP_0>;
  71                 };
  72                 little3: cpu@3 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53", "arm,armv8";
  75                         reg = <0x0 0x3>;
  76                         enable-method = "psci";
  77                         cpu-idle-states = <&CPU_SLEEP_0>;
  78                 };
  79                 big0: cpu@100 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53", "arm,armv8";
  82                         reg = <0x0 0x100>;
  83                         enable-method = "psci";
  84                         cpu-idle-states = <&CPU_SLEEP_0>;
  85                 };
  86                 big1: cpu@101 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53", "arm,armv8";
  89                         reg = <0x0 0x101>;
  90                         enable-method = "psci";
  91                         cpu-idle-states = <&CPU_SLEEP_0>;
  92                 };
  93                 big2: cpu@102 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53", "arm,armv8";
  96                         reg = <0x0 0x102>;
  97                         enable-method = "psci";
  98                         cpu-idle-states = <&CPU_SLEEP_0>;
  99                 };
 100                 big3: cpu@103 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a53", "arm,armv8";
 103                         reg = <0x0 0x103>;
 104                         enable-method = "psci";
 105                         cpu-idle-states = <&CPU_SLEEP_0>;
 106                 };
 107
 108                 cpu-map {
 109                         cluster0 {
 110                                 core0 {
 111                                         cpu = <&big0>;
 112                                 };
 113                                 core1 {
 114                                         cpu = <&big1>;
 115                                 };
 116                                 core2 {
 117                                         cpu = <&big2>;
 118                                 };
 119                                 core3 {
 120                                         cpu = <&big3>;
 121                                 };
 122                         };
 123                         cluster1 {
 124                                 core0 {
 125                                         cpu = <&little0>;
 126                                 };
 127                                 core1 {
 128                                         cpu = <&little1>;
 129                                 };
 130                                 core2 {
 131                                         cpu = <&little2>;
 132                                 };
 133                                 core3 {
 134                                         cpu = <&little3>;
 135                                 };
 136                         };
 137                 };
 138         };
 139
 140         psci {
 141                 compatible = "arm,psci-0.2";
 142                 method = "smc";
 143         };
 144
 145         gic: interrupt-controller@ffb70000 {
 146                 compatible = "arm,cortex-a15-gic";
 147                 #interrupt-cells = <3>;
 148                 #address-cells = <0>;
 149                 interrupt-controller;
 150                 reg = <0x0 0xffb71000 0 0x1000>,
 151                       <0x0 0xffb72000 0 0x1000>;
 152         };
 153
 154         ddrpctl: syscon@ff610000 {
 155                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 156                 reg = <0x0 0xff610000 0x0 0x400>;
 157         };
 158
 159         pmu: syscon@ff730000 {
 160                 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
 161                 reg = <0x0 0xff730000 0x0 0x1000>;
 162         };
 163
 164         pmugrf: syscon@ff738000 {
 165                 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
 166                 reg = <0x0 0xff738000 0x0 0x1000>;
 167         };
 168
 169         sgrf: syscon@ff740000 {
 170                 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
 171                 reg = <0x0 0xff740000 0x0 0x1000>;
 172
 173         };
 174
 175         cru: syscon@ff760000 {
 176                 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
 177                 reg = <0x0 0xff760000 0x0 0x1000>;
 178         };
 179
 180         grf: syscon@ff770000 {
 181                 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
 182                 reg = <0x0 0xff770000 0x0 0x1000>;
 183         };
 184
 185         msch: syscon@ffac0000 {
 186                 compatible = "rockchip,rk3368-msch", "rockchip,msch", "syscon";
 187                 reg = <0x0 0xffac0000 0x0 0x3000>;
 188         };
 189
 190         arm-pmu {
 191                 compatible = "arm,armv8-pmuv3";
 192                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 200         };
 201
 202         cpu_axi_bus: cpu_axi_bus {
 203                 compatible = "rockchip,cpu_axi_bus";
 204                 #address-cells = <2>;
 205                 #size-cells = <2>;
 206                 ranges;
 207
 208                 qos {
 209                         #address-cells = <2>;
 210                         #size-cells = <2>;
 211                         ranges;
 212
 213                         dmac {
 214                                 reg = <0x0 0xffa80000 0x0 0x20>;
 215                         };
 216                         crypto {
 217                                 reg = <0x0 0xffa80080 0x0 0x20>;
 218                         };
 219                         tsp {
 220                                 reg = <0x0 0xffa80280 0x0 0x20>;
 221                         };
 222                         bus_cpup {
 223                                 reg = <0x0 0xffa90000 0x0 0x20>;
 224                         };
 225                         cci_r {
 226                                 reg = <0x0 0xffaa0000 0x0 0x20>;
 227                         };
 228                         cci_w {
 229                                 reg = <0x0 0xffaa0080 0x0 0x20>;
 230                         };
 231                         peri {
 232                                 reg = <0x0 0xffab0000 0x0 0x20>;
 233                                 rockchip,priority = <2 2>;
 234                         };
 235                         iep {
 236                                 reg = <0x0 0xffad0000 0x0 0x20>;
 237                         };
 238                         isp_r0 {
 239                                 reg = <0x0 0xffad0080 0x0 0x20>;
 240                         };
 241                         isp_r1 {
 242                                 reg = <0x0 0xffad0100 0x0 0x20>;
 243                         };
 244                         isp_w0 {
 245                                 reg = <0x0 0xffad0180 0x0 0x20>;
 246                                 rockchip,priority = <2 2>;
 247                         };
 248                         isp_w1 {
 249                                 reg = <0x0 0xffad0200 0x0 0x20>;
 250                                 rockchip,priority = <2 2>;
 251                         };
 252                         vip {
 253                                 reg = <0x0 0xffad0280 0x0 0x20>;
 254                         };
 255                         vop {
 256                                 reg = <0x0 0xffad0300 0x0 0x20>;
 257                                 rockchip,priority = <2 2>;
 258                         };
 259                         rga_r {
 260                                 reg = <0x0 0xffad0380 0x0 0x20>;
 261                         };
 262                         rga_w {
 263                                 reg = <0x0 0xffad0400 0x0 0x20>;
 264                         };
 265                         hevc_r {
 266                                 reg = <0x0 0xffae0000 0x0 0x20>;
 267                         };
 268                         vpu_r {
 269                                 reg = <0x0 0xffae0100 0x0 0x20>;
 270                         };
 271                         vpu_w {
 272                                 reg = <0x0 0xffae0180 0x0 0x20>;
 273                         };
 274                         gpu {
 275                                 reg = <0x0 0xffaf0000 0x0 0x20>;
 276                         };
 277                 };
 278
 279                 msch {
 280                         #address-cells = <2>;
 281                         #size-cells = <2>;
 282                         ranges;
 283
 284                         msch {
 285                                 reg = <0x0 0xffac0000 0x0 0x3c>;
 286                                 rockchip,read-latency = <0x34>;
 287                         };
 288                 };
 289         };
 290
 291         timer {
 292                 compatible = "arm,armv8-timer";
 293                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 294                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 295                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 296                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 297                 clock-frequency = <24000000>;
 298         };
 299
 300         timer@ff810000 {
 301                 compatible = "rockchip,timer";
 302                 reg = <0x0 0xff810000 0x0 0x20>;
 303                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 304                 rockchip,broadcast = <1>;
 305         };
 306
 307         sram: sram@ff8c0000 {
 308                 compatible = "mmio-sram";
 309                 reg = <0x0 0xff8c0000 0x0 0xf000>; /* 60K (reserved 4K for mailbox)*/
 310                 map-exec;
 311         };
 312
 313         watchdog: wdt@ff800000 {
 314                 compatible = "rockchip,watch dog";
 315                 reg = <0x0 0xff800000 0x0 0x100>;
 316                 clocks = <&pclk_alive_pre>;
 317                 clock-names = "pclk_wdt";
 318                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 319                 rockchip,irq = <1>;
 320                 rockchip,timeout = <60>;
 321                 rockchip,atboot = <1>;
 322                 rockchip,debug = <0>;
 323                 status = "disabled";
 324         };
 325
 326         amba {
 327                 #address-cells = <2>;
 328                 #size-cells = <2>;
 329                 compatible = "arm,amba-bus";
 330                 interrupt-parent = <&gic>;
 331                 ranges;
 332
 333                 pdma0: pdma@ff600000 {
 334                         compatible = "arm,pl330", "arm,primecell";
 335                         reg = <0x0 0xff600000 0x0 0x4000>;
 336                         clocks = <&clk_gates12 11>;
 337                         clock-names = "apb_pclk";
 338                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 339                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 340                         #dma-cells = <1>;
 341
 342                 };
 343
 344                 pdma1: pdma@ff250000 {
 345                         compatible = "arm,pl330", "arm,primecell";
 346                         reg = <0x0 0xff250000 0x0 0x4000>;
 347                         clocks = <&clk_gates19 3>;
 348                         clock-names = "apb_pclk";
 349                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 350                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 351                         #dma-cells = <1>;
 352                 };
 353         };
 354
 355         reset: reset@ff760300{
 356                 compatible = "rockchip,reset";
 357                 reg = <0x0 0xff760300 0x0 0x38>;
 358                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 359                 #reset-cells = <1>;
 360         };
 361
 362         nandc0: nandc@ff400000 {
 363                 compatible = "rockchip,rk-nandc";
 364                 reg = <0x0 0xff400000 0x0 0x4000>;
 365                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 366                 nandc_id = <0>;
 367                 clocks = <&clk_nandc0>, <&clk_gates20 9>, <&clk_gates20 11>;
 368                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 369         };
 370
 371         nandc0reg: nandc0@ff400000 {
 372                 compatible = "rockchip,rk-nandc";
 373                 reg = <0x0 0xff400000 0x0 0x4000>;
 374         };
 375
 376         emmc: rksdmmc@ff0f0000 {
 377                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 378                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 379                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 380                 #address-cells = <1>;
 381                 #size-cells = <0>;
 382                 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
 383                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 384                 rockchip,grf = <&grf>;
 385                 num-slots = <1>;
 386                 fifo-depth = <0x100>;
 387                 bus-width = <8>;
 388         };
 389
 390         sdmmc: rksdmmc@ff0c0000 {
 391                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 392                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 393                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 394                 #address-cells = <1>;
 395                 #size-cells = <0>;
 396                 pinctrl-names = "default", "idle", "udbg";
 397                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 398                 pinctrl-1 = <&sdmmc_gpio>;
 399                 pinctrl-2 = <&uart2_xfer &cpu_jtag &mcu_jtag &sdmmc_dectn>;
 400                 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 401                 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
 402                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 403                 rockchip,grf = <&grf>;
 404                 num-slots = <1>;
 405                 fifo-depth = <0x100>;
 406                 bus-width = <4>;
 407         };
 408
 409         sdio: rksdmmc@ff0d0000 {
 410                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 411                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 412                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 413                 #address-cells = <1>;
 414                 #size-cells = <0>;
 415                 pinctrl-names = "default","idle";
 416                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
 417                 pinctrl-1 = <&sdio0_gpio>;
 418                 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
 419                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 420                 rockchip,grf = <&grf>;
 421                 num-slots = <1>;
 422                 fifo-depth = <0x100>;
 423                 bus-width = <4>;
 424         };
 425
 426         spi0: spi@ff110000 {
 427                 compatible = "rockchip,rockchip-spi";
 428                 reg = <0x0 0xff110000 0x0 0x1000>;
 429                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 430                 #address-cells = <1>;
 431                 #size-cells = <0>;
 432                 pinctrl-names = "default";
 433                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 434                 rockchip,spi-src-clk = <0>;
 435                 num-cs = <2>;
 436                 clocks =<&clk_spi0>, <&clk_gates19 4>;
 437                 clock-names = "spi", "pclk_spi0";
 438                 //dmas = <&pdma1 11>, <&pdma1 12>;
 439                 //#dma-cells = <2>;
 440                 //dma-names = "tx", "rx";
 441                 status = "disabled";
 442         };
 443
 444         spi1: spi@ff120000 {
 445                 compatible = "rockchip,rockchip-spi";
 446                 reg = <0x0 0xff120000 0x0 0x1000>;
 447                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 448                 #address-cells = <1>;
 449                 #size-cells = <0>;
 450                 pinctrl-names = "default";
 451                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0 &spi1_cs1>;
 452                 rockchip,spi-src-clk = <1>;
 453                 num-cs = <2>;
 454                 clocks = <&clk_spi1>, <&clk_gates19 5>;
 455                 clock-names = "spi", "pclk_spi1";
 456                 //dmas = <&pdma1 13>, <&pdma1 14>;
 457                 //#dma-cells = <2>;
 458                 //dma-names = "tx", "rx";
 459                 status = "disabled";
 460         };
 461
 462         spi2: spi@ff130000 {
 463                 compatible = "rockchip,rockchip-spi";
 464                 reg = <0x0 0xff130000 0x0 0x1000>;
 465                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 466                 #address-cells = <1>;
 467                 #size-cells = <0>;
 468                 pinctrl-names = "default";
 469                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 470                 rockchip,spi-src-clk = <2>;
 471                 num-cs = <1>;
 472                 clocks = <&clk_spi2>, <&clk_gates19 6>;
 473                 clock-names = "spi", "pclk_spi2";
 474                 //dmas = <&pdma1 15>, <&pdma1 16>;
 475                 //#dma-cells = <2>;
 476                 //dma-names = "tx", "rx";
 477                 status = "disabled";
 478         };
 479
 480         uart_bt: serial@ff180000 {
 481                 compatible = "rockchip,serial";
 482                 reg = <0x0 0xff180000 0x0 0x100>;
 483                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 484                 clock-frequency = <24000000>;
 485                 clocks = <&clk_uart0>, <&clk_gates19 7>;
 486                 clock-names = "sclk_uart", "pclk_uart";
 487                 reg-shift = <2>;
 488                 reg-io-width = <4>;
 489                 //dmas = <&pdma1 1>, <&pdma1 2>;
 490                 //#dma-cells = <2>;
 491                 pinctrl-names = "default";
 492                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 493                 status = "disabled";
 494         };
 495
 496         uart_bb: serial@ff190000 {
 497                 compatible = "rockchip,serial";
 498                 reg = <0x0 0xff190000 0x0 0x100>;
 499                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 500                 clock-frequency = <24000000>;
 501                 clocks = <&clk_uart1>, <&clk_gates19 8>;
 502                 clock-names = "sclk_uart", "pclk_uart";
 503                 reg-shift = <2>;
 504                 reg-io-width = <4>;
 505                 //dmas = <&pdma1 3>, <&pdma1 4>;
 506                 //#dma-cells = <2>;
 507                 pinctrl-names = "default";
 508                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 509                 status = "disabled";
 510         };
 511
 512         uart_dbg: serial@ff690000 {
 513                 compatible = "rockchip,serial";
 514                 reg = <0x0 0xff690000 0x0 0x100>;
 515                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 516                 clock-frequency = <24000000>;
 517                 clocks = <&clk_uart2>, <&clk_gates13 5>;
 518                 clock-names = "sclk_uart", "pclk_uart";
 519                 reg-shift = <2>;
 520                 reg-io-width = <4>;
 521                 //dmas = <&pdma0 4>, <&pdma0 5>;
 522                 //#dma-cells = <2>;
 523                 //pinctrl-names = "default";
 524                 //pinctrl-0 = <&uart2_xfer>;
 525                 status = "disabled";
 526         };
 527
 528         uart_gps: serial@ff1b0000 {
 529                 compatible = "rockchip,serial";
 530                 reg = <0x0 0xff1b0000 0x0 0x100>;
 531                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 532                 clock-frequency = <24000000>;
 533                 clocks = <&clk_uart3>, <&clk_gates19 9>;
 534                 clock-names = "sclk_uart", "pclk_uart";
 535                 current-speed = <115200>;
 536                 reg-shift = <2>;
 537                 reg-io-width = <4>;
 538                 //dmas = <&pdma1 7>, <&pdma1 8>;
 539                 //#dma-cells = <2>;
 540                 pinctrl-names = "default";
 541                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 542                 status = "disabled";
 543         };
 544
 545         uart_exp: serial@ff1c0000 {
 546                 compatible = "rockchip,serial";
 547                 reg = <0x0 0xff1c0000 0x0 0x100>;
 548                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 549                 clock-frequency = <24000000>;
 550                 clocks = <&clk_uart4>, <&clk_gates19 10>;
 551                 clock-names = "sclk_uart", "pclk_uart";
 552                 reg-shift = <2>;
 553                 reg-io-width = <4>;
 554                 //dmas = <&pdma1 9>, <&pdma1 10>;
 555                 //#dma-cells = <2>;
 556                 pinctrl-names = "default";
 557                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 558                 status = "disabled";
 559         };
 560
 561         mbox: mbox@ff6b0000 {
 562                 compatible = "rockchip,rk3368-mailbox";
 563                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 564                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 565                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 566                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 567                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 568                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 569                 clocks = <&clk_gates12 1>;
 570                 clock-names = "pclk_mailbox";
 571                 #mbox-cells = <1>;
 572         };
 573
 574         mbox_scpi: mbox-scpi {
 575                 compatible = "rockchip,mbox-scpi";
 576                 mboxes = <&mbox 0 &mbox 1>;
 577         };
 578
 579         ddr {
 580                 compatible = "rockchip,rk3368-ddr";
 581                 status = "okay";
 582                 rockchip,ddrpctl = <&ddrpctl>;
 583                 rockchip,grf = <&grf>;
 584                 rockchip,msch = <&msch>;
 585         };
 586
 587         rockchip_clocks_init: clocks-init{
 588                 compatible = "rockchip,clocks-init";
 589                 rockchip,clocks-init-parent =
 590                         <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
 591                         <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
 592                         <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
 593                         <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
 594                 rockchip,clocks-init-rate =
 595                         <&clk_gpll 576000000>,          <&clk_core_b 792000000>,
 596                         <&clk_core_l 600000000>,        <&clk_cpll 400000000>,
 597                         /*<&clk_npll 500000000>,*/      <&aclk_bus 300000000>,
 598                         <&hclk_bus 150000000>,          <&pclk_bus 75000000>,
 599                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 600                         <&hclk_peri 150000000>,         <&pclk_peri 75000000>,
 601                         <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
 602                         <&clk_cs 300000000>,            <&clkin_trace 300000000>,
 603                         <&aclk_cci 600000000>,          <&clk_mac 125000000>,
 604                         <&aclk_vio0 400000000>,         <&hclk_vio 100000000>,
 605                         <&aclk_rga_pre 400000000>,      <&clk_rga 400000000>,
 606                         <&clk_isp 400000000>,           <&clk_edp 200000000>,
 607                         <&clk_gpu_core 400000000>,      <&aclk_gpu_mem 400000000>,
 608                         <&aclk_gpu_cfg 400000000>,      <&aclk_vepu 400000000>,
 609                         <&aclk_vdpu 400000000>,         <&clk_hevc_core 300000000>,
 610                         <&clk_hevc_cabac 300000000>;
 611 /*
 612                 rockchip,clocks-uboot-has-init =
 613                         <&aclk_vio0>;
 614 */
 615         };
 616
 617         rockchip_clocks_enable: clocks-enable {
 618                 compatible = "rockchip,clocks-enable";
 619                 clocks =
 620                         /*PLL*/
 621                         <&clk_apllb>,
 622                         <&clk_aplll>,
 623                         <&clk_dpll>,
 624                         <&clk_gpll>,
 625                         <&clk_cpll>,
 626
 627                         /*PD_CORE*/
 628                         <&clk_cs>,
 629                         <&clkin_trace>,
 630                         <&aclk_cci>,
 631
 632                         /*PD_BUS*/
 633                         <&aclk_bus>,
 634                         <&hclk_bus>,
 635                         <&pclk_bus>,
 636                         <&clk_gates12 12>,/*aclk_strc_sys*/
 637                         <&clk_gates12 6>,/*aclk_intmem1*/
 638                         <&clk_gates12 5>,/*aclk_intmem0*/
 639                         <&clk_gates12 4>,/*aclk_intmem*/
 640                         <&clk_gates13 9>,/*aclk_gic400*/
 641                         <&clk_gates12 9>,/*hclk_rom*/
 642
 643                         /*PD_ALIVE*/
 644                         <&clk_gates22 13>,/*pclk_timer1*/
 645                         <&clk_gates22 12>,/*pclk_timer0*/
 646                         <&clk_gates22 9>,/*pclk_alive_niu*/
 647                         <&clk_gates22 8>,/*pclk_grf*/
 648
 649                         /*PD_PMU*/
 650                         <&clk_gates23 5>,/*pclk_pmugrf*/
 651                         <&clk_gates23 3>,/*pclk_sgrf*/
 652                         <&clk_gates23 2>,/*pclk_pmu_noc*/
 653                         <&clk_gates23 1>,/*pclk_intmem1*/
 654                         <&clk_gates23 0>,/*pclk_pmu*/
 655
 656                         /*PD_PERI*/
 657                         <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
 658                         <&clk_gates20 8>,/*aclk_peri_niu*/
 659                         <&clk_gates21 4>,/*aclk_peri_mmu*/
 660                         <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
 661                         <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
 662                         <&clk_gates19 1>,/*pclk_peri_axi_matrix*/
 663
 664                         <&fclk_mcu>,
 665                         <&stclk_mcu>,
 666                         <&clk_gates7 0>;/*clk_jtag*/
 667         };
 668
 669         /* I2C_PMU */
 670         i2c0: i2c@ff650000 {
 671                 compatible = "rockchip,rk30-i2c";
 672                 reg = <0x0 0xff650000 0x0 0x1000>;
 673                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 674                 #address-cells = <1>;
 675                 #size-cells = <0>;
 676                 pinctrl-names = "default", "gpio", "sleep";
 677                 pinctrl-0 = <&i2c0_xfer>;
 678                 pinctrl-1 = <&i2c0_gpio>;
 679                 pinctrl-2 = <&i2c0_sleep>;
 680                 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
 681                 clocks = <&clk_gates12 2>;
 682                 rockchip,check-idle = <1>;
 683                 status = "disabled";
 684         };
 685
 686         /* I2C_AUDIO */
 687         i2c1: i2c@ff660000 {
 688                 compatible = "rockchip,rk30-i2c";
 689                 reg = <0x0 0xff660000 0x0 0x1000>;
 690                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 691                 #address-cells = <1>;
 692                 #size-cells = <0>;
 693                 pinctrl-names = "default", "gpio", "sleep";
 694                 pinctrl-0 = <&i2c1_xfer>;
 695                 pinctrl-1 = <&i2c1_gpio>;
 696                 pinctrl-2 = <&i2c1_sleep>;
 697                 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
 698                 clocks = <&clk_gates12 3>;
 699                 rockchip,check-idle = <1>;
 700                 status = "disabled";
 701         };
 702
 703         /* I2C_SENSOR */
 704         i2c2: i2c@ff140000 {
 705                 compatible = "rockchip,rk30-i2c";
 706                 reg = <0x0 0xff140000 0x0 0x1000>;
 707                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 708                 #address-cells = <1>;
 709                 #size-cells = <0>;
 710                 pinctrl-names = "default", "gpio", "sleep";
 711                 pinctrl-0 = <&i2c2_xfer>;
 712                 pinctrl-1 = <&i2c2_gpio>;
 713                 pinctrl-2 = <&i2c2_sleep>;
 714                 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 715                 clocks = <&clk_gates19 11>;
 716                 rockchip,check-idle = <1>;
 717                 status = "disabled";
 718         };
 719
 720         /* I2C_CAM */
 721         i2c3: i2c@ff150000 {
 722                 compatible = "rockchip,rk30-i2c";
 723                 reg = <0x0 0xff150000 0x0 0x1000>;
 724                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 725                 #address-cells = <1>;
 726                 #size-cells = <0>;
 727                 pinctrl-names = "default", "gpio", "sleep";
 728                 pinctrl-0 = <&i2c3_xfer>;
 729                 pinctrl-1 = <&i2c3_gpio>;
 730                 pinctrl-2 = <&i2c3_sleep>;
 731                 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
 732                 clocks = <&clk_gates19 12>;
 733                 rockchip,check-idle = <1>;
 734                 status = "disabled";
 735         };
 736
 737         /* I2C_TP */
 738         i2c4: i2c@ff160000 {
 739                 compatible = "rockchip,rk30-i2c";
 740                 reg = <0x0 0xff160000 0x0 0x1000>;
 741                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 742                 #address-cells = <1>;
 743                 #size-cells = <0>;
 744                 pinctrl-names = "default", "gpio", "sleep";
 745                 pinctrl-0 = <&i2c4_xfer>;
 746                 pinctrl-1 = <&i2c4_gpio>;
 747                 pinctrl-2 = <&i2c4_sleep>;
 748                 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
 749                 clocks = <&clk_gates19 13>;
 750                 rockchip,check-idle = <1>;
 751                 status = "disabled";
 752         };
 753
 754         /* I2C_HDMI */
 755         i2c5: i2c@ff170000 {
 756                 compatible = "rockchip,rk30-i2c";
 757                 reg = <0x0 0xff170000 0x0 0x1000>;
 758                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 759                 #address-cells = <1>;
 760                 #size-cells = <0>;
 761                 pinctrl-names = "default", "gpio", "sleep";
 762                 pinctrl-0 = <&i2c5_xfer>;
 763                 pinctrl-1 = <&i2c5_gpio>;
 764                 pinctrl-2 = <&i2c5_sleep>;
 765                 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
 766                 clocks = <&clk_gates19 14>;
 767                 rockchip,check-idle = <1>;
 768                 status = "disabled";
 769         };
 770
 771         fb: fb {
 772                 compatible = "rockchip,rk-fb";
 773                 rockchip,disp-mode = <NO_DUAL>;
 774         };
 775
 776
 777         rk_screen: rk_screen {
 778                 compatible = "rockchip,screen";
 779         };
 780
 781         dsihost0: mipi@ff960000{
 782                 compatible = "rockchip,rk3368-dsi";
 783                 rockchip,prop = <0>;
 784                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 785                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 786                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 787                 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>, <&pd_mipidsi>;
 788                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host", "pd_mipi_dsi";
 789                 status = "disabled";
 790         };
 791
 792         lvds: lvds@ff968000 {
 793                 compatible = "rockchip,rk3368-lvds";
 794                 rockchip,grf = <&grf>;
 795                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 796                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 797                 clocks = <&clk_gates22 10>, <&clk_gates17 3>, <&pd_lvds>;
 798                 clock-names = "pclk_lvds", "pclk_lvds_ctl", "pd_lvds";
 799                 status = "disabled";
 800         };
 801
 802         edp: edp@ff970000 {
 803                 compatible = "rockchip,rk32-edp";
 804                 reg = <0x0 0xff970000 0x0 0x4000>;
 805                 rockchip,grf = <&grf>;
 806                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 807                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
 808                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 809                 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
 810                 reset-names = "edp_24m", "edp_apb";
 811         };
 812
 813         hdmi: hdmi@ff980000 {
 814                 compatible = "rockchip,rk3368-hdmi";
 815                 reg = <0x0 0xff980000 0x0 0x20000>;
 816                 rockchip,grf = <&grf>;
 817                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 818                 pinctrl-names = "default", "gpio";
 819                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 820                 pinctrl-1 = <&i2c5_gpio>;
 821                 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
 822                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 823                 status = "disabled";
 824         };
 825
 826         hdmi_hdcp2: hdmi_hdcp2@ff978000 {
 827                 compatible = "rockchip,rk3368-hdmi-hdcp2";
 828                 reg = <0x0 0xff978000 0x0 0x2000>;
 829                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 830                 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
 831                 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
 832                 status = "disabled";
 833         };
 834
 835         lcdc: lcdc@ff930000 {
 836                  compatible = "rockchip,rk3368-lcdc";
 837                  rockchip,grf = <&grf>;
 838                  rockchip,pmugrf = <&pmugrf>;
 839                  rockchip,cru = <&cru>;
 840                  rockchip,prop = <PRMRY>;
 841                  rockchip,pwr18 = <0>;
 842                  rockchip,iommu-enabled = <1>;
 843                  reg = <0x0 0xff930000 0x0 0x10000>;
 844                  interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 845                 /*pinctrl-names = "default", "gpio";
 846                  *pinctrl-0 = <&lcdc_lcdc>;
 847                  *pinctrl-1 = <&lcdc_gpio>;
 848                  */
 849                  status = "disabled";
 850                  clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>, <&pd_vop>;
 851                  clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll", "pd_lcdc";
 852         };
 853
 854         adc: adc@ff100000 {
 855                 compatible = "rockchip,saradc";
 856                 reg = <0x0 0xff100000 0x0 0x100>;
 857                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 858                 #io-channel-cells = <1>;
 859                 io-channel-ranges;
 860                 rockchip,adc-vref = <1800>;
 861                 clock-frequency = <1000000>;
 862                 clocks = <&clk_saradc>, <&clk_gates19 15>;
 863                 clock-names = "saradc", "pclk_saradc";
 864                 status = "disabled";
 865         };
 866
 867         rga@ff920000 {
 868                 compatible = "rockchip,rk3368-rga2";
 869                 reg = <0x0 0xff920000 0x0 0x1000>;
 870                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 871                 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
 872                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 873         };
 874
 875         i2s0: i2s0@ff898000 {
 876                 compatible = "rockchip-i2s";
 877                 reg = <0x0 0xff898000 0x0 0x1000>;
 878                 i2s-id = <0>;
 879                 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 880                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 881                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 882                 dmas = <&pdma0 0>, <&pdma0 1>;
 883                 #dma-cells = <2>;
 884                 dma-names = "tx", "rx";
 885                 pinctrl-names = "default", "sleep";
 886                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 887                 pinctrl-1 = <&i2s_gpio>;
 888         };
 889
 890         i2s1: i2s1@ff890000 {
 891                 compatible = "rockchip-i2s";
 892                 reg = <0x0 0xff890000 0x0 0x1000>;
 893                 i2s-id = <1>;
 894                 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
 895                 clock-names = "i2s_clk", "i2s_hclk";
 896                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 897                 dmas = <&pdma0 6>, <&pdma0 7>;
 898                 #dma-cells = <2>;
 899                 dma-names = "tx", "rx";
 900         };
 901
 902         spdif: spdif@ff880000 {
 903                 compatible = "rockchip-spdif";
 904                 reg = <0x0 0xff880000 0x0 0x1000>;
 905                 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
 906                 clock-names = "spdif_mclk", "spdif_hclk";
 907                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 908                 dmas = <&pdma0 3>;
 909                 #dma-cells = <1>;
 910                 dma-names = "tx";
 911                 pinctrl-names = "default";
 912                 pinctrl-0 = <&spdif_tx>;
 913         };
 914
 915         pwm0: pwm@ff680000 {
 916                 compatible = "rockchip,rk-pwm";
 917                 reg = <0x0 0xff680000 0x0 0x10>;
 918                 #pwm-cells = <2>;
 919                 pinctrl-names = "default";
 920                 pinctrl-0 = <&pwm0_pin>;
 921                 clocks = <&clk_gates13 6>;
 922                 clock-names = "pclk_pwm";
 923                 status = "disabled";
 924         };
 925
 926         pwm1: pwm@ff680010 {
 927                 compatible = "rockchip,rk-pwm";
 928                 reg = <0x0 0xff680010 0x0 0x10>;
 929                 #pwm-cells = <2>;
 930                 pinctrl-names = "default";
 931                 pinctrl-0 = <&pwm1_pin>;
 932                 clocks = <&clk_gates13 6>;
 933                 clock-names = "pclk_pwm";
 934                 status = "disabled";
 935         };
 936
 937         pwm2: pwm@ff680020 {
 938                 compatible = "rockchip,rk-pwm";
 939                 reg = <0x0 0xff680020 0x0 0x10>;
 940                 #pwm-cells = <2>;
 941                 //pinctrl-names = "default";
 942                 //pinctrl-0 = <&pwm1_pin>;
 943                 clocks = <&clk_gates13 6>;
 944                 clock-names = "pclk_pwm";
 945                 status = "disabled";
 946         };
 947
 948         pwm3: pwm@ff680030 {
 949                 compatible = "rockchip,rk-pwm";
 950                 reg = <0x0 0xff680030 0x0 0x10>;
 951                 #pwm-cells = <2>;
 952                 pinctrl-names = "default";
 953                 pinctrl-0 = <&pwm3_pin>;
 954                 clocks = <&clk_gates13 6>;
 955                 clock-names = "pclk_pwm";
 956                 status = "disabled";
 957         };
 958
 959         remotectl: pwm@ff680030 {
 960                 compatible = "rockchip,remotectl-pwm";
 961                 reg = <0x0 0xff680030 0x0 0x50>;
 962                 #pwm-cells = <2>;
 963                 pinctrl-names = "default";
 964                 pinctrl-0 = <&pwm3_pin>;
 965                 clocks = <&clk_gates13 6>;
 966                 clock-names = "pclk_pwm";
 967                 dmas = <&pdma0 2>;
 968                 #dma-cells = <2>;
 969                 dma-names = "rx";
 970                 remote_pwm_id = <3>;
 971                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 972                 status = "disabled";
 973         };
 974
 975         voppwm: pwm@ff9301a0 {
 976                 compatible = "rockchip,vop-pwm";
 977                 reg = <0x0 0xff9301a0 0x0 0x10>;
 978                 #pwm-cells = <2>;
 979                 pinctrl-names = "default";
 980                 pinctrl-0 = <&vop_pwm_pin>;
 981                 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
 982                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 983                 status = "disabled";
 984         };
 985
 986         pvtm {
 987                 compatible = "rockchip,rk3368-pvtm";
 988                 rockchip,grf = <&grf>;
 989                 rockchip,pmugrf = <&pmugrf>;
 990                 rockchip,pvtm-clk-out = <1>;
 991         };
 992
 993         cpufreq {
 994                 compatible = "rockchip,rk3368-cpufreq";
 995                 rockchip,grf = <&grf>;
 996         };
 997
 998         dvfs {
 999
1000                 vd_arm: vd_arm {
1001                         regulator_name = "vdd_arm";
1002                         suspend_volt = <1000>; //mV
1003                         pd_core {
1004                                 clk_core_b_dvfs_table: clk_core_b {
1005                                         operating-points = <
1006                                                 /* KHz    uV */
1007                                                 312000 1200000
1008                                                 504000 1200000
1009                                                 816000 1200000
1010                                                 1008000 1200000
1011                                                 >;
1012                                         status = "okay";
1013                                         temp-limit-enable = <1>;
1014                                         target-temp = <80>;
1015                                         min_temp_limit = <216>;
1016                                         normal-temp-limit = <
1017                                         /*delta-temp    delta-freq*/
1018                                                 3       96000
1019                                                 6       144000
1020                                                 9       192000
1021                                                 15      384000
1022                                                 >;
1023                                         performance-temp-limit = <
1024                                                 /*temp    freq*/
1025                                                 100     816000
1026                                                 >;
1027                                 };
1028                                 clk_core_l_dvfs_table: clk_core_l {
1029                                         operating-points = <
1030                                                 /* KHz    uV */
1031                                                 312000 1200000
1032                                                 504000 1200000
1033                                                 816000 1200000
1034                                                 1008000 1200000
1035                                                 >;
1036                                         status = "okay";
1037                                         temp-limit-enable = <1>;
1038                                         target-temp = <80>;
1039                                         min_temp_limit = <216>;
1040                                         normal-temp-limit = <
1041                                         /*delta-temp    delta-freq*/
1042                                                 3       96000
1043                                                 6       144000
1044                                                 9       192000
1045                                                 15      384000
1046                                                 >;
1047                                         performance-temp-limit = <
1048                                                 /*temp    freq*/
1049                                                 100     816000
1050                                                 >;
1051                                 };
1052                         };
1053                 };
1054
1055                 vd_logic: vd_logic {
1056                         regulator_name = "vdd_logic";
1057                         suspend_volt = <1000>; //mV
1058                         pd_ddr {
1059                                 clk_ddr_dvfs_table: clk_ddr {
1060                                         operating-points = <
1061                                                 /* KHz    uV */
1062                                                 200000 1200000
1063                                                 300000 1200000
1064                                                 400000 1200000
1065                                                 >;
1066                                         channel = <2>;
1067                                         status = "disabled";
1068                                 };
1069                         };
1070
1071                         pd_gpu {
1072                                 clk_gpu_dvfs_table: clk_gpu {
1073                                         operating-points = <
1074                                                 /* KHz    uV */
1075                                                 200000 1200000
1076                                                 300000 1200000
1077                                                 400000 1200000
1078                                                 >;
1079                                         channel = <1>;
1080                                         status = "okay";
1081                                         regu-mode-table = <
1082                                                 /*freq     mode*/
1083                                                 200000     4
1084                                                 0          3
1085                                         >;
1086                                         regu-mode-en = <0>;
1087                                 };
1088                         };
1089                 };
1090         };
1091
1092         ion {
1093                 compatible = "rockchip,ion";
1094                 #address-cells = <1>;
1095                 #size-cells = <0>;
1096
1097                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1098                         compatible = "rockchip,ion-heap";
1099                         rockchip,ion_heap = <4>;
1100                         reg = <0x00000000 0x00000000>; /* 0MB */
1101                 };
1102                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1103                         compatible = "rockchip,ion-heap";
1104                         rockchip,ion_heap = <0>;
1105                 };
1106         };
1107
1108         vpu: vpu_service {
1109                 compatible = "rockchip,vpu_sub";
1110                 iommu_enabled = <1>;
1111                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1112                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1113                 interrupt-names = "irq_enc", "irq_dec";
1114                 dev_mode = <0>;
1115                 name = "vpu_service";
1116         };
1117
1118         hevc: hevc_service {
1119                 compatible = "rockchip,hevc_sub";
1120                 iommu_enabled = <1>;
1121                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1122                 interrupt-names = "irq_dec";
1123                 dev_mode = <1>;
1124                 name = "hevc_service";
1125         };
1126
1127         vpu_combo: vpu_combo@ff9a0000 {
1128                 compatible = "rockchip,vpu_combo";
1129                 reg = <0x0 0xff9a0000 0x0 0x800>;
1130                 rockchip,grf = <&grf>;
1131                 subcnt = <2>;
1132                 rockchip,sub = <&vpu>, <&hevc>;
1133                 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1134                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1135                 mode_bit = <12>;
1136                 mode_ctrl = <0x418>;
1137                 name = "vpu_combo";
1138                 status = "okay";
1139         };
1140
1141         iep: iep@ff900000 {
1142                 compatible = "rockchip,iep";
1143                 iommu_enabled = <1>;
1144                 reg = <0x0 0xff900000 0x0 0x800>;
1145                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1146                 clocks = <&clk_gates16 2>, <&clk_gates16 3>;
1147                 clock-names = "aclk_iep", "hclk_iep";
1148                 status = "okay";
1149         };
1150
1151         gmac: eth@ff290000 {
1152                 compatible = "rockchip,rk3368-gmac";
1153                 reg = <0x0 0xff290000 0x0 0x10000>;
1154                 rockchip,grf = <&grf>;
1155                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1156                 interrupt-names = "macirq";
1157
1158                 clocks = <&clk_mac>, <&clk_gates7 4>,
1159                          <&clk_gates7 5>, <&clk_gates7 6>,
1160                          <&clk_gates7 7>, <&clk_gates20 13>,
1161                          <&clk_gates20 14>;
1162                 clock-names = "clk_mac", "mac_clk_rx",
1163                               "mac_clk_tx", "clk_mac_ref",
1164                               "clk_mac_refout", "aclk_mac",
1165                               "pclk_mac";
1166
1167                 phy-mode = "rgmii";
1168                 pinctrl-names = "default";
1169                 pinctrl-0 = <&rgmii_pins>;
1170                 status = "disabled";
1171         };
1172
1173         gpu {
1174                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1175                 reg = <0x0 0xffa30000 0x0 0x10000>;
1176                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1177                 interrupt-names = "GPU";
1178         };
1179
1180         iep_mmu {
1181                 dbgname = "iep";
1182                 compatible = "rockchip,iep_mmu";
1183                 reg = <0x0 0xff900800 0x0 0x100>;
1184                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1185                 interrupt-names = "iep_mmu";
1186         };
1187
1188         vip_mmu {
1189                 dbgname = "vip";
1190                 compatible = "rockchip,vip_mmu";
1191                 reg = <0x0 0xff950800 0x0 0x100>;
1192                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1193                 interrupt-names = "vip_mmu";
1194         };
1195
1196         vop_mmu {
1197                 dbgname = "vop";
1198                 compatible = "rockchip,vopb_mmu";
1199                 reg = <0x0 0xff930300 0x0 0x100>;
1200                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1201                 interrupt-names = "vop_mmu";
1202         };
1203
1204         isp_mmu {
1205                 dbgname = "isp_mmu";
1206                 compatible = "rockchip,isp_mmu";
1207                 reg = <0x0 0xff914000 0x0 0x100>,
1208                 <0x0 0xff915000 0x0 0x100>;
1209                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1210                 interrupt-names = "isp_mmu";
1211         };
1212
1213         hdcp_mmu {
1214                 dbgname = "hdcp_mmu";
1215                 compatible = "rockchip,hdcp_mmu";
1216                 reg = <0x0 0xff940000 0x0 0x100>;
1217                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1218                 interrupt-names = "hdcp_mmu";
1219         };
1220
1221         hevc_mmu {
1222                 dbgname = "hevc";
1223                 compatible = "rockchip,hevc_mmu";
1224                 reg = <0x0 0xff9a0440 0x0 0x40>,                      /*need to fix*/
1225                           <0x0 0xff9a0480 0x0 0x40>;
1226                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;        /*need to fix*/
1227                 interrupt-names = "hevc_mmu";
1228         };
1229
1230         vpu_mmu {
1231                 dbgname = "vpu";
1232                 compatible = "rockchip,vpu_mmu";
1233                 reg = <0x0 0xff9a0800 0x0 0x100>;                    /*need to fix*/
1234                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,        /*need to fix*/
1235                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1236                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1237         };
1238
1239         rockchip_suspend {
1240                 rockchip,ctrbits = <
1241                         (0
1242                          |RKPM_CTR_PWR_DMNS
1243                          |RKPM_CTR_GTCLKS
1244                          |RKPM_CTR_PLLS
1245                          |RKPM_CTR_GPIOS
1246                         /*
1247                          |RKPM_CTR_SYSCLK_DIV
1248                          |RKPM_CTR_IDLEAUTO_MD
1249                          |RKPM_CTR_ARMOFF_LPMD
1250                         */
1251                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1252                         )
1253                         >;
1254                 rockchip,pmic-suspend_gpios = <
1255                                  /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1256                         >;
1257                 rockchip,pmic-resume_gpios = <
1258                                 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1259                         >;
1260         };
1261
1262         isp: isp@ff910000{
1263                 compatible = "rockchip,isp";
1264                 reg = <0x0 0xff910000 0x0 0x10000>;
1265                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1266                 clocks = <&clk_gates16 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>, <&pd_isp>;
1267                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx", "pd_isp";
1268                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1269                 pinctrl-0 = <&cif_clkout>;
1270                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1271                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1272                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1273                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1274                 pinctrl-5 = <&cif_clkout>;
1275                 pinctrl-6 = <&cif_clkout &isp_prelight>;
1276                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1277                 pinctrl-8 = <&isp_flash_trigger>;
1278                 rockchip,isp,mipiphy = <2>;
1279                 rockchip,isp,cifphy = <1>;
1280                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1281                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1282                 rockchip,grf = <&grf>;
1283                 rockchip,cru = <&cru>;
1284                 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1285                 rockchip,isp,iommu_enable = <1>;
1286                 status = "okay";
1287         };
1288
1289         cif: cif@ff950000 {
1290                 compatible = "rockchip,cif";
1291                 reg = <0x0 0xff950000 0x0 0x10000>;
1292                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1293                 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1294                 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1295                 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1296                 pinctrl-names = "cif_pin_all";
1297                 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1298                 rockchip,grf = <&grf>;
1299                 rockchip,cru = <&cru>;
1300                 status = "okay";
1301         };
1302
1303 /*
1304         thermal-zones {
1305                 #include "rk3368-thermal.dtsi"
1306         };
1307 */
1308
1309         tsadc: tsadc@ff280000 {
1310                 compatible = "rockchip,rk3368-tsadc";
1311                 reg = <0x0 0xff280000 0x0 0x100>;
1312                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1313                 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1314                 rockchip,grf = <&grf>;
1315                 rockchip,cru = <&cru>;
1316                 rockchip,pmu = <&pmu>;
1317                 clock-names = "tsadc", "apb_pclk";
1318                 clock-frequency = <32000>;
1319                 resets = <&reset RK3368_SRST_TSADC_P>;
1320                 reset-names = "tsadc-apb";
1321                 //pinctrl-names = "default";
1322                 //pinctrl-0 = <&tsadc_int>;
1323                 #thermal-sensor-cells = <1>;
1324                 hw-shut-temp = <120000>;
1325                 status = "disabled";
1326         };
1327
1328         tsp: tsp@FF8B0000 {
1329                 compatible = "rockchip,rk3368-tsp";
1330                 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1331                 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1332                 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1333                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1334                 interrupt-names = "irq_tsp";
1335                 // pinctrl-names = "default";
1336                 // pinctrl-0 = <&isp_hsadc>;
1337                 status = "okay";
1338         };
1339
1340         crypto: crypto@FF8A0000{
1341                 compatible = "rockchip,rk3368-crypto";
1342                 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1343                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1344                 interrupt-names = "irq_crypto";
1345                         clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1346                 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1347                 status = "okay";
1348         };
1349
1350         dwc_control_usb: dwc-control-usb {
1351                 compatible = "rockchip,rk3368-dwc-control-usb";
1352                 rockchip,grf = <&grf>;
1353                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1354                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1355                 interrupt-names = "otg_id", "otg_bvalid",
1356                                   "otg_linestate", "host0_linestate";
1357                 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1358                 clock-names = "hclk_usb_peri", "usbphy_480m";
1359                 //resets = <&reset RK3128_RST_USBPOR>;
1360                 //reset-names = "usbphy_por";
1361                 usb_bc{
1362                         compatible = "inno,phy";
1363                         regbase = &dwc_control_usb;
1364                         rk_usb,bvalid     = <0x4bc 23 1>;
1365                         rk_usb,iddig      = <0x4bc 26 1>;
1366                         rk_usb,vdmsrcen   = <0x718 12 1>;
1367                         rk_usb,vdpsrcen   = <0x718 11 1>;
1368                         rk_usb,rdmpden    = <0x718 10 1>;
1369                         rk_usb,idpsrcen   = <0x718  9 1>;
1370                         rk_usb,idmsinken  = <0x718  8 1>;
1371                         rk_usb,idpsinken  = <0x718  7 1>;
1372                         rk_usb,dpattach   = <0x4b8 31 1>;
1373                         rk_usb,cpdet      = <0x4b8 30 1>;
1374                         rk_usb,dcpattach  = <0x4b8 29 1>;
1375                 };
1376         };
1377
1378         usb0: usb@ff580000 {
1379                 compatible = "rockchip,rk3368_usb20_otg";
1380                 reg = <0x0 0xff580000 0x0 0x40000>;
1381                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1382                 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1383                 clock-names = "clk_usbphy0", "hclk_otg";
1384                 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1385                                 <&reset RK3368_SRST_USBOTGC0>;
1386                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1387                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1388                 rockchip,usb-mode = <0>;
1389         };
1390
1391         usb_ehci: usb@ff500000 {
1392                 compatible = "generic-ehci";
1393                 reg = <0x0 0xff500000 0x0 0x20000>;
1394                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1395                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1396                 clock-names = "clk_usbphy0", "hclk_ehci";
1397                 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1398                 //              <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1399                 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1400         };
1401
1402         usb_ohci: usb@ff520000 {
1403                 compatible = "generic-ohci";
1404                 reg = <0x0 0xff520000 0x0 0x20000>;
1405                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1406                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1407                 clock-names =  "clk_usbphy0", "hclk_ohci";
1408         };
1409
1410         usb_hsic: usb@ff5c0000 {
1411                 compatible = "rockchip,rk3288_rk_hsic_host";
1412                 reg = <0x0 0xff5c0000 0x0 0x40000>;
1413                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1414 /*
1415                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1416                          <&hsicphy_12m>, <&usbphy_480m>,
1417                          <&otgphy1_480m>, <&otgphy2_480m>;
1418                 clock-names = "hsicphy_480m", "hclk_hsic",
1419                               "hsicphy_12m", "usbphy_480m",
1420                               "hsic_usbphy1", "hsic_usbphy2";
1421                 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1422                                 <&reset RK3288_SOFT_RST_HSICPHY>;
1423                 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1424 */
1425                 status = "disabled";
1426         };
1427
1428         pinctrl: pinctrl {
1429                 compatible = "rockchip,rk3368-pinctrl";
1430                 rockchip,grf = <&grf>;
1431                 rockchip,pmugrf = <&pmugrf>;
1432                 #address-cells = <2>;
1433                 #size-cells = <2>;
1434                 ranges;
1435
1436                 gpio0: gpio0@ff750000 {
1437                         compatible = "rockchip,gpio-bank";
1438                         reg =   <0x0 0xff750000 0x0 0x100>;
1439                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1440                         clocks = <&clk_gates23 4>;
1441
1442                         gpio-controller;
1443                         #gpio-cells = <2>;
1444
1445                         interrupt-controller;
1446                         #interrupt-cells = <2>;
1447                 };
1448
1449                 gpio1: gpio1@ff780000 {
1450                         compatible = "rockchip,gpio-bank";
1451                         reg = <0x0 0xff780000 0x0 0x100>;
1452                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1453                         clocks = <&clk_gates22 1>;
1454
1455                         gpio-controller;
1456                         #gpio-cells = <2>;
1457
1458                         interrupt-controller;
1459                         #interrupt-cells = <2>;
1460                 };
1461
1462                 gpio2: gpio2@ff790000 {
1463                         compatible = "rockchip,gpio-bank";
1464                         reg = <0x0 0xff790000 0x0 0x100>;
1465                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1466                         clocks = <&clk_gates22 2>;
1467
1468                         gpio-controller;
1469                         #gpio-cells = <2>;
1470
1471                         interrupt-controller;
1472                         #interrupt-cells = <2>;
1473                 };
1474
1475                 gpio3: gpio3@ff7a0000 {
1476                         compatible = "rockchip,gpio-bank";
1477                         reg = <0x0 0xff7a0000 0x0 0x100>;
1478                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1479                         clocks = <&clk_gates22 3>;
1480
1481                         gpio-controller;
1482                         #gpio-cells = <2>;
1483
1484                         interrupt-controller;
1485                         #interrupt-cells = <2>;
1486                 };
1487
1488                 pcfg_pull_up: pcfg-pull-up {
1489                         bias-pull-up;
1490                 };
1491
1492                 pcfg_pull_down: pcfg-pull-down {
1493                         bias-pull-down;
1494                 };
1495
1496                 pcfg_pull_none: pcfg-pull-none {
1497                         bias-disable;
1498                 };
1499
1500                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1501                         drive-strength = <8>;
1502                 };
1503
1504                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1505                         drive-strength = <12>;
1506                 };
1507
1508                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1509                         bias-pull-up;
1510                         drive-strength = <8>;
1511                 };
1512
1513                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1514                         drive-strength = <4>;
1515                 };
1516
1517                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1518                         bias-pull-up;
1519                         drive-strength = <4>;
1520                 };
1521
1522                 pcfg_output_high: pcfg-output-high {
1523                         output-high;
1524                 };
1525
1526                 pcfg_output_low: pcfg-output-low {
1527                         output-low;
1528                 };
1529
1530                 pcfg_input_high: pcfg-input-high {
1531                         bias-pull-up;
1532                         input-enable;
1533                 };
1534
1535                 i2c0 {
1536                         i2c0_xfer: i2c0-xfer {
1537                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1538                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1539                         };
1540                         i2c0_gpio: i2c0-gpio {
1541                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1542                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1543                         };
1544                         i2c0_sleep: i2c0-sleep {
1545                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_input_high>,
1546                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_input_high>;
1547                         };
1548                 };
1549
1550                 i2c1 {
1551                         i2c1_xfer: i2c1-xfer {
1552                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1553                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1554                         };
1555                         i2c1_gpio: i2c1-gpio {
1556                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1557                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1558                         };
1559                         i2c1_sleep: i2c1-sleep {
1560                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_input_high>,
1561                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_input_high>;
1562                         };
1563                 };
1564
1565                 i2c2 {
1566                         i2c2_xfer: i2c2-xfer {
1567                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1568                                                 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1569                         };
1570                         i2c2_gpio: i2c2-gpio {
1571                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1572                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1573                         };
1574                         i2c2_sleep: i2c2-sleep {
1575                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_input_high>,
1576                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_input_high>;
1577                         };
1578                 };
1579
1580                 i2c3 {
1581                         i2c3_xfer: i2c3-xfer {
1582                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1583                                                 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1584                         };
1585                         i2c3_gpio: i2c3-gpio {
1586                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1587                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1588                         };
1589                         i2c3_sleep: i2c3-sleep {
1590                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_input_high>,
1591                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_input_high>;
1592                         };
1593                 };
1594
1595                 i2c4 {
1596                         i2c4_xfer: i2c4-xfer {
1597                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1598                                                 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1599                         };
1600                         i2c4_gpio: i2c4-gpio {
1601                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1602                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1603                         };
1604                         i2c4_sleep: i2c4-sleep {
1605                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_input_high>,
1606                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_input_high>;
1607                         };
1608                 };
1609
1610                 i2c5 {
1611                         i2c5_xfer: i2c5-xfer {
1612                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1613                                                 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1614                         };
1615                         i2c5_gpio: i2c5-gpio {
1616                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1617                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1618                         };
1619                         i2c5_sleep: i2c5-sleep {
1620                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_input_high>,
1621                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_input_high>;
1622                         };
1623                 };
1624
1625                 uart0 {
1626                         uart0_xfer: uart0-xfer {
1627                                 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1628                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1629                         };
1630
1631                         uart0_cts: uart0-cts {
1632                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1633                         };
1634
1635                         uart0_rts: uart0-rts {
1636                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1637                         };
1638
1639                         uart0_rts_gpio: uart0-rts-gpio {
1640                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1641                         };
1642                 };
1643
1644                 uart1 {
1645                         uart1_xfer: uart1-xfer {
1646                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1647                                                 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1648                         };
1649
1650                         uart1_cts: uart1-cts {
1651                                 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1652                         };
1653
1654                         uart1_rts: uart1-rts {
1655                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1656                         };
1657                 };
1658
1659                 uart2 {
1660                         uart2_xfer: uart2-xfer {
1661                                 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1662                                                 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1663                         };
1664                 };
1665
1666                 uart3 {
1667                         uart3_xfer: uart3-xfer {
1668                                 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1669                                                 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1670                         };
1671
1672                         uart3_cts: uart3-cts {
1673                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1674                         };
1675
1676                         uart3_rts: uart3-rts {
1677                                 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1678                         };
1679                 };
1680
1681                 uart4 {
1682                         uart4_xfer: uart4-xfer {
1683                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1684                                                 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1685                         };
1686
1687                         uart4_cts: uart4-cts {
1688                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1689                         };
1690
1691                         uart4_rts: uart4-rts {
1692                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1693                         };
1694                 };
1695
1696                 spi0 {
1697                         spi0_clk: spi0-clk {
1698                                 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1699                         };
1700                         spi0_cs0: spi0-cs0 {
1701                                 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1702                         };
1703                         spi0_tx: spi0-tx {
1704                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1705                         };
1706                         spi0_rx: spi0-rx {
1707                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1708                         };
1709                         spi0_cs1: spi0-cs1 {
1710                                 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1711                         };
1712                 };
1713
1714                 spi1 {
1715                         spi1_clk: spi1-clk {
1716                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1717                         };
1718                         spi1_cs0: spi1-cs0 {
1719                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1720                         };
1721                         spi1_rx: spi1-rx {
1722                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1723                         };
1724                         spi1_tx: spi1-tx {
1725                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1726                         };
1727                         spi1_cs1: spi1-cs1 {
1728                                 rockchip,pins = <3 GPIO_D4 RK_FUNC_2 &pcfg_pull_up>;
1729                         };
1730                 };
1731
1732                 spi2 {
1733                         spi2_clk: spi2-clk {
1734                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1735                         };
1736                         spi2_cs0: spi2-cs0 {
1737                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1738                         };
1739                         spi2_rx: spi2-rx {
1740                                 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1741                         };
1742                         spi2_tx: spi2-tx {
1743                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1744                         };
1745                 };
1746
1747                 i2s {
1748                         i2s_mclk: i2s-mclk {
1749                                 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1750                         };
1751
1752                         i2s_sclk:i2s-sclk {
1753                                 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1754                         };
1755
1756                         i2s_lrckrx:i2s-lrckrx {
1757                                 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1758                         };
1759
1760                         i2s_lrcktx:i2s-lrcktx {
1761                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1762                         };
1763
1764                         i2s_sdi:i2s-sdi {
1765                                 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1766                         };
1767
1768                         i2s_sdo0:i2s-sdo0 {
1769                                 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1770                         };
1771
1772                         i2s_sdo1:i2s-sdo1 {
1773                                 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1774                         };
1775
1776                         i2s_sdo2:i2s-sdo2 {
1777                                 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1778                         };
1779
1780                         i2s_sdo3:i2s-sdo3 {
1781                                 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1782                         };
1783
1784                         i2s_gpio: i2s-gpio {
1785                                 rockchip,pins = <2 GPIO_C4  RK_FUNC_GPIO &pcfg_pull_none>,
1786                                                 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1787                                                 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1788                                                 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1789                                                 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1790                                                 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1791                                                 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1792                                                 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1793                                                 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1794                         };
1795                 };
1796
1797                 spdif {
1798                         spdif_tx: spdif-tx {
1799                                 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1800                         };
1801                 };
1802
1803                 sdmmc {
1804                         sdmmc_clk: sdmmc-clk {
1805                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1806                         };
1807
1808                         sdmmc_cmd: sdmmc-cmd {
1809                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1810                         };
1811
1812                         sdmmc_dectn: sdmmc-dectn {
1813                                 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1814                         };
1815
1816                         sdmmc_bus1: sdmmc-bus1 {
1817                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1818                         };
1819
1820                         sdmmc_bus4: sdmmc-bus4 {
1821                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1822                                                 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1823                                                 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1824                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1825                         };
1826
1827                         sdmmc_gpio: sdmmc-gpio {
1828                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1829                                                 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1830                                                 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1831                                                 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1832                                                 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1833                                                 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1834                                                 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1835                         };
1836                 };
1837
1838                 sdio0 {
1839                         sdio0_bus1: sdio0-bus1 {
1840                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1841                         };
1842
1843                         sdio0_bus4: sdio0-bus4 {
1844                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1845                                                 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1846                                                 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1847                                                 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1848                         };
1849
1850                         sdio0_cmd: sdio0-cmd {
1851                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1852                         };
1853
1854                         sdio0_clk: sdio0-clk {
1855                                 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1856                         };
1857
1858                         sdio0_dectn: sdio0-dectn {
1859                                 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1860                         };
1861
1862                         sdio0_wrprt: sdio0-wrprt {
1863                                 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1864                         };
1865
1866                         sdio0_pwren: sdio0-pwren {
1867                                 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1868                         };
1869
1870                         sdio0_bkpwr: sdio0-bkpwr {
1871                                 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1872                         };
1873
1874                         sdio0_int: sdio0-int {
1875                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1876                         };
1877
1878                         sdio0_gpio: sdio0-gpio {
1879                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1880                                                 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1881                                                 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1882                                                 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1883                                                 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1884                                                 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1885                                                 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1886                                                 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1887                                                 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1888                                                 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1889                                                 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1890                         };
1891                 };
1892
1893                 emmc {
1894                         emmc_clk: emmc-clk {
1895                                 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1896                         };
1897
1898                         emmc_cmd: emmc-cmd {
1899                                 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1900                         };
1901
1902                         emmc_pwren: emmc-pwren {
1903                                 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1904                         };
1905
1906                         emmc_rstnout: emmc_rstnout {
1907                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1908                         };
1909
1910                         emmc_bus1: emmc-bus1 {
1911                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1912                         };
1913
1914                         emmc_bus4: emmc-bus4 {
1915                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1916                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1917                                                 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1918                                                 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1919                         };
1920                 };
1921
1922                 pwm0 {
1923                         pwm0_pin: pwm0-pin {
1924                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1925                         };
1926
1927                         vop_pwm_pin:vop-pwm {
1928                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1929                         };
1930                 };
1931
1932                 pwm1 {
1933                         pwm1_pin: pwm1-pin {
1934                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1935                         };
1936                 };
1937
1938                 pwm3 {
1939                         pwm3_pin: pwm3-pin {
1940                                 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1941                         };
1942                 };
1943
1944                 lcdc {
1945                         lcdc_lcdc: lcdc-lcdc {
1946                                 rockchip,pins =
1947                                                 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1948                                                 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1949                                                 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1950                                                 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1951                                                 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1952                                                 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1953                                                 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1954                                                 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1955                                                 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1956                                                 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1957                                                 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1958                                                 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1959                                                 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1960                                                 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1961                                                 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1962                                                 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1963                                                 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1964                                                 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1965                         };
1966
1967                         lcdc_gpio: lcdc-gpio {
1968                                 rockchip,pins =
1969                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1970                                                 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1971                                                 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1972                                                 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1973                                                 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1974                                                 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1975                                                 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1976                                                 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1977                                                 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1978                                                 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1979                                                 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1980                                                 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1981                                                 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1982                                                 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1983                                                 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1984                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1985                                                 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1986                                                 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1987                         };
1988                 };
1989
1990                 isp {
1991                         cif_clkout: cif-clkout {
1992                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1993                         };
1994
1995                         isp_dvp_d2d9: isp-dvp-d2d9 {
1996                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1997                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1998                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1999                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2000                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2001                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2002                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2003                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2004                                                 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
2005                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
2006                                                 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
2007                                                 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2008                         };
2009
2010                         isp_dvp_d0d1: isp-dvp-d0d1 {
2011                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2012                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
2013                         };
2014
2015                         isp_dvp_d10d11:isp_d10d11       {
2016                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2017                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2018                         };
2019
2020                         isp_dvp_d0d7: isp-dvp-d0d7 {
2021                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2022                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
2023                                                 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2024                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2025                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2026                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2027                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2028                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
2029                         };
2030
2031                         isp_shutter: isp-shutter {
2032                                 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2033                                                 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2034                         };
2035
2036                         isp_flash_trigger: isp-flash-trigger {
2037                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2038                         };
2039
2040                         isp_prelight: isp-prelight {
2041                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2042                         };
2043
2044                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2045                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
2046                         };
2047                 };
2048
2049                 gps {
2050                         gps_mag: gps-mag {
2051                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
2052                         };
2053
2054                         gps_sig: gps-sig {
2055                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
2056
2057                         };
2058
2059                         gps_rfclk: gps-rfclk {
2060                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
2061                         };
2062                 };
2063
2064                 gmac {
2065                         rgmii_pins: rgmii-pins {
2066                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2067                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2068                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2069                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2070                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2071                                                 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
2072                                                 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
2073                                                 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
2074                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2075                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2076                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2077                                                 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
2078                                                 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
2079                                                 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
2080                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
2081                         };
2082
2083                         rmii_pins: rmii-pins {
2084                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2085                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2086                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2087                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2088                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2089                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2090                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2091                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2092                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
2093                                                 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
2094                         };
2095                 };
2096
2097                 tsadc_pin {
2098                         tsadc_int: tsadc-int {
2099                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
2100                         };
2101                         tsadc_gpio: tsadc-gpio {
2102                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
2103                         };
2104                 };
2105
2106                 hdmi_pin {
2107                         hdmi_cec: hdmi-cec {
2108                                 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
2109                         };
2110                 };
2111
2112                 hdmi_i2c {
2113                         hdmii2c_xfer: hdmii2c-xfer {
2114                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
2115                                                 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
2116                         };
2117                 };
2118
2119                 cpu_jtag {
2120                         cpu_jtag: cpu-jtag {
2121                                 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_up>,
2122                                                 <2 GPIO_B0 RK_FUNC_2 &pcfg_pull_up>;
2123                         };
2124                 };
2125
2126                 mcu_jtag {
2127                         mcu_jtag: mcu-jtag {
2128                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>,
2129                                                 <2 GPIO_B1 RK_FUNC_2 &pcfg_pull_up>;
2130                         };
2131                 };
2132         };
2133
2134         reboot {
2135                 compatible = "rockchip,rk3368-reboot";
2136                 rockchip,cru = <&cru>;
2137                 rockchip,pmugrf = <&pmugrf>;
2138         };
2139 };