arch/arm64/boot/dts/rk3368.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-rk3368.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/sensor-dev.h>
   6 #include <dt-bindings/clock/rk_system_status.h>
   7
   8 #include "rk3368-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk3368";
  12
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &uart_bt;
  20                 serial1 = &uart_bb;
  21                 serial2 = &uart_dbg;
  22                 serial3 = &uart_gps;
  23                 serial4 = &uart_exp;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &spi0;
  31                 spi1 = &spi1;
  32                 spi2 = &spi2;
  33                 lcdc = &lcdc;
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 idle-states {
  41                         entry-method = "arm,psci";
  42                         CPU_SLEEP_0: cpu-sleep-0 {
  43                                 compatible = "arm,idle-state";
  44                                 arm,psci-suspend-param = <0x1010000>;
  45                                 entry-latency-us = <0x3fffffff>;
  46                                 exit-latency-us = <0x40000000>;
  47                                 min-residency-us = <0xffffffff>;
  48                         };
  49                 };
  50
  51                 little0: cpu@0 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53", "arm,armv8";
  54                         reg = <0x0 0x0>;
  55                         enable-method = "psci";
  56                         cpu-idle-states = <&CPU_SLEEP_0>;
  57                 };
  58                 little1: cpu@1 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53", "arm,armv8";
  61                         reg = <0x0 0x1>;
  62                         enable-method = "psci";
  63                         cpu-idle-states = <&CPU_SLEEP_0>;
  64                 };
  65                 little2: cpu@2 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53", "arm,armv8";
  68                         reg = <0x0 0x2>;
  69                         enable-method = "psci";
  70                         cpu-idle-states = <&CPU_SLEEP_0>;
  71                 };
  72                 little3: cpu@3 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53", "arm,armv8";
  75                         reg = <0x0 0x3>;
  76                         enable-method = "psci";
  77                         cpu-idle-states = <&CPU_SLEEP_0>;
  78                 };
  79                 big0: cpu@100 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53", "arm,armv8";
  82                         reg = <0x0 0x100>;
  83                         enable-method = "psci";
  84                         cpu-idle-states = <&CPU_SLEEP_0>;
  85                 };
  86                 big1: cpu@101 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53", "arm,armv8";
  89                         reg = <0x0 0x101>;
  90                         enable-method = "psci";
  91                         cpu-idle-states = <&CPU_SLEEP_0>;
  92                 };
  93                 big2: cpu@102 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53", "arm,armv8";
  96                         reg = <0x0 0x102>;
  97                         enable-method = "psci";
  98                         cpu-idle-states = <&CPU_SLEEP_0>;
  99                 };
 100                 big3: cpu@103 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a53", "arm,armv8";
 103                         reg = <0x0 0x103>;
 104                         enable-method = "psci";
 105                         cpu-idle-states = <&CPU_SLEEP_0>;
 106                 };
 107
 108                 cpu-map {
 109                         cluster0 {
 110                                 core0 {
 111                                         cpu = <&big0>;
 112                                 };
 113                                 core1 {
 114                                         cpu = <&big1>;
 115                                 };
 116                                 core2 {
 117                                         cpu = <&big2>;
 118                                 };
 119                                 core3 {
 120                                         cpu = <&big3>;
 121                                 };
 122                         };
 123                         cluster1 {
 124                                 core0 {
 125                                         cpu = <&little0>;
 126                                 };
 127                                 core1 {
 128                                         cpu = <&little1>;
 129                                 };
 130                                 core2 {
 131                                         cpu = <&little2>;
 132                                 };
 133                                 core3 {
 134                                         cpu = <&little3>;
 135                                 };
 136                         };
 137                 };
 138         };
 139
 140         psci {
 141                 compatible = "arm,psci-0.2";
 142                 method = "smc";
 143         };
 144
 145         gic: interrupt-controller@ffb70000 {
 146                 compatible = "arm,cortex-a15-gic";
 147                 #interrupt-cells = <3>;
 148                 #address-cells = <0>;
 149                 interrupt-controller;
 150                 reg = <0x0 0xffb71000 0 0x1000>,
 151                       <0x0 0xffb72000 0 0x1000>;
 152         };
 153
 154         ddrpctl: syscon@ff610000 {
 155                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 156                 reg = <0x0 0xff610000 0x0 0x400>;
 157         };
 158
 159         pmu: syscon@ff730000 {
 160                 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
 161                 reg = <0x0 0xff730000 0x0 0x1000>;
 162         };
 163
 164         pmugrf: syscon@ff738000 {
 165                 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
 166                 reg = <0x0 0xff738000 0x0 0x1000>;
 167         };
 168
 169         sgrf: syscon@ff740000 {
 170                 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
 171                 reg = <0x0 0xff740000 0x0 0x1000>;
 172
 173         };
 174
 175         cru: syscon@ff760000 {
 176                 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
 177                 reg = <0x0 0xff760000 0x0 0x1000>;
 178         };
 179
 180         grf: syscon@ff770000 {
 181                 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
 182                 reg = <0x0 0xff770000 0x0 0x1000>;
 183         };
 184
 185         msch: syscon@ffac0000 {
 186                 compatible = "rockchip,rk3368-msch", "rockchip,msch", "syscon";
 187                 reg = <0x0 0xffac0000 0x0 0x3000>;
 188         };
 189
 190         arm-pmu {
 191                 compatible = "arm,armv8-pmuv3";
 192                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 200         };
 201
 202         cpu_axi_bus: cpu_axi_bus {
 203                 compatible = "rockchip,cpu_axi_bus";
 204                 #address-cells = <2>;
 205                 #size-cells = <2>;
 206                 ranges;
 207
 208                 qos {
 209                         #address-cells = <2>;
 210                         #size-cells = <2>;
 211                         ranges;
 212
 213                         dmac {
 214                                 reg = <0x0 0xffa80000 0x0 0x20>;
 215                         };
 216                         crypto {
 217                                 reg = <0x0 0xffa80080 0x0 0x20>;
 218                         };
 219                         tsp {
 220                                 reg = <0x0 0xffa80280 0x0 0x20>;
 221                         };
 222                         bus_cpup {
 223                                 reg = <0x0 0xffa90000 0x0 0x20>;
 224                         };
 225                         cci_r {
 226                                 reg = <0x0 0xffaa0000 0x0 0x20>;
 227                         };
 228                         cci_w {
 229                                 reg = <0x0 0xffaa0080 0x0 0x20>;
 230                         };
 231                         peri {
 232                                 reg = <0x0 0xffab0000 0x0 0x20>;
 233                                 rockchip,priority = <2 2>;
 234                         };
 235                         iep {
 236                                 reg = <0x0 0xffad0000 0x0 0x20>;
 237                         };
 238                         isp_r0 {
 239                                 reg = <0x0 0xffad0080 0x0 0x20>;
 240                         };
 241                         isp_r1 {
 242                                 reg = <0x0 0xffad0100 0x0 0x20>;
 243                         };
 244                         isp_w0 {
 245                                 reg = <0x0 0xffad0180 0x0 0x20>;
 246                                 rockchip,priority = <2 2>;
 247                         };
 248                         isp_w1 {
 249                                 reg = <0x0 0xffad0200 0x0 0x20>;
 250                                 rockchip,priority = <2 2>;
 251                         };
 252                         vip {
 253                                 reg = <0x0 0xffad0280 0x0 0x20>;
 254                         };
 255                         vop {
 256                                 reg = <0x0 0xffad0300 0x0 0x20>;
 257                                 rockchip,priority = <2 2>;
 258                         };
 259                         rga_r {
 260                                 reg = <0x0 0xffad0380 0x0 0x20>;
 261                         };
 262                         rga_w {
 263                                 reg = <0x0 0xffad0400 0x0 0x20>;
 264                         };
 265                         hevc_r {
 266                                 reg = <0x0 0xffae0000 0x0 0x20>;
 267                         };
 268                         vpu_r {
 269                                 reg = <0x0 0xffae0100 0x0 0x20>;
 270                         };
 271                         vpu_w {
 272                                 reg = <0x0 0xffae0180 0x0 0x20>;
 273                         };
 274                         gpu {
 275                                 reg = <0x0 0xffaf0000 0x0 0x20>;
 276                         };
 277                 };
 278
 279                 msch {
 280                         #address-cells = <2>;
 281                         #size-cells = <2>;
 282                         ranges;
 283
 284                         msch {
 285                                 reg = <0x0 0xffac0000 0x0 0x3c>;
 286                                 rockchip,read-latency = <0x34>;
 287                         };
 288                 };
 289         };
 290
 291         efuse_256@ffb00000 {
 292                 compatible = "rockchip,rk3368-efuse-256";
 293                 reg = <0x0 0xffb00000 0x0 0x8>;
 294         };
 295
 296         timer {
 297                 compatible = "arm,armv8-timer";
 298                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 299                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 300                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 301                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 302                 clock-frequency = <24000000>;
 303         };
 304
 305         timer@ff810000 {
 306                 compatible = "rockchip,timer";
 307                 reg = <0x0 0xff810000 0x0 0x20>;
 308                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 309                 rockchip,broadcast = <1>;
 310         };
 311
 312         timer@ff810020 {
 313                 compatible = "rockchip,timer";
 314                 reg = <0x0 0xff810020 0x0 0x20>;
 315                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 316                 rockchip,percpu = <0>;
 317         };
 318
 319         sram: sram@ff8c0000 {
 320                 compatible = "mmio-sram";
 321                 reg = <0x0 0xff8c0000 0x0 0xf000>; /* 60K (reserved 4K for mailbox)*/
 322                 map-exec;
 323         };
 324
 325         watchdog: wdt@ff800000 {
 326                 compatible = "rockchip,watch dog";
 327                 reg = <0x0 0xff800000 0x0 0x100>;
 328                 clocks = <&pclk_alive_pre>;
 329                 clock-names = "pclk_wdt";
 330                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 331                 rockchip,irq = <1>;
 332                 rockchip,timeout = <60>;
 333                 rockchip,atboot = <1>;
 334                 rockchip,debug = <0>;
 335                 status = "disabled";
 336         };
 337
 338         amba {
 339                 #address-cells = <2>;
 340                 #size-cells = <2>;
 341                 compatible = "arm,amba-bus";
 342                 interrupt-parent = <&gic>;
 343                 ranges;
 344
 345                 pdma0: pdma@ff600000 {
 346                         compatible = "arm,pl330", "arm,primecell";
 347                         reg = <0x0 0xff600000 0x0 0x4000>;
 348                         clocks = <&clk_gates12 11>;
 349                         clock-names = "apb_pclk";
 350                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 351                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 352                         #dma-cells = <1>;
 353
 354                 };
 355
 356                 pdma1: pdma@ff250000 {
 357                         compatible = "arm,pl330", "arm,primecell";
 358                         reg = <0x0 0xff250000 0x0 0x4000>;
 359                         clocks = <&clk_gates19 3>;
 360                         clock-names = "apb_pclk";
 361                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 362                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 363                         #dma-cells = <1>;
 364                 };
 365         };
 366
 367         reset: reset@ff760300{
 368                 compatible = "rockchip,reset";
 369                 reg = <0x0 0xff760300 0x0 0x38>;
 370                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 371                 #reset-cells = <1>;
 372         };
 373
 374         nandc0: nandc@ff400000 {
 375                 compatible = "rockchip,rk-nandc";
 376                 reg = <0x0 0xff400000 0x0 0x4000>;
 377                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 378                 nandc_id = <0>;
 379                 clocks = <&clk_nandc0>, <&clk_gates20 9>, <&clk_gates20 11>;
 380                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 381         };
 382
 383         nandc0reg: nandc0@ff400000 {
 384                 compatible = "rockchip,rk-nandc";
 385                 reg = <0x0 0xff400000 0x0 0x4000>;
 386         };
 387
 388         emmc: rksdmmc@ff0f0000 {
 389                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 390                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 391                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
 395                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 396                 rockchip,grf = <&grf>;
 397                 rockchip,cru = <&cru>;
 398                 num-slots = <1>;
 399                 fifo-depth = <0x100>;
 400                 bus-width = <8>;
 401                 tune_regsbase = <0x418>;
 402                 cru_regsbase = <0x320>;
 403                 cru_reset_offset = <3>;
 404         };
 405
 406         sdmmc: rksdmmc@ff0c0000 {
 407                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 408                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 409                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 410                 #address-cells = <1>;
 411                 #size-cells = <0>;
 412                 pinctrl-names = "default", "idle", "udbg";
 413                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 414                 pinctrl-1 = <&sdmmc_gpio>;
 415                 pinctrl-2 = <&uart2_xfer &cpu_jtag &mcu_jtag &sdmmc_dectn>;
 416                 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 417                 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
 418                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 419                 rockchip,grf = <&grf>;
 420                 rockchip,cru = <&cru>;
 421                 num-slots = <1>;
 422                 fifo-depth = <0x100>;
 423                 bus-width = <4>;
 424                 tune_regsbase = <0x400>;
 425                 cru_regsbase = <0x320>;
 426                 cru_reset_offset = <0>;
 427         };
 428
 429         sdio: rksdmmc@ff0d0000 {
 430                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 431                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 432                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 433                 #address-cells = <1>;
 434                 #size-cells = <0>;
 435                 pinctrl-names = "default","idle";
 436                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
 437                 pinctrl-1 = <&sdio0_gpio>;
 438                 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
 439                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 440                 rockchip,grf = <&grf>;
 441                 rockchip,cru = <&cru>;
 442                 num-slots = <1>;
 443                 fifo-depth = <0x100>;
 444                 bus-width = <4>;
 445                 tune_regsbase = <0x408>;
 446                 cru_regsbase = <0x320>;
 447                 cru_reset_offset = <1>;
 448         };
 449
 450         spi0: spi@ff110000 {
 451                 compatible = "rockchip,rockchip-spi";
 452                 reg = <0x0 0xff110000 0x0 0x1000>;
 453                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 454                 #address-cells = <1>;
 455                 #size-cells = <0>;
 456                 pinctrl-names = "default";
 457                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 458                 rockchip,spi-src-clk = <0>;
 459                 num-cs = <2>;
 460                 clocks =<&clk_spi0>, <&clk_gates19 4>;
 461                 clock-names = "spi", "pclk_spi0";
 462                 //dmas = <&pdma1 11>, <&pdma1 12>;
 463                 //#dma-cells = <2>;
 464                 //dma-names = "tx", "rx";
 465                 status = "disabled";
 466         };
 467
 468         spi1: spi@ff120000 {
 469                 compatible = "rockchip,rockchip-spi";
 470                 reg = <0x0 0xff120000 0x0 0x1000>;
 471                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 472                 #address-cells = <1>;
 473                 #size-cells = <0>;
 474                 pinctrl-names = "default";
 475                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0 &spi1_cs1>;
 476                 rockchip,spi-src-clk = <1>;
 477                 num-cs = <2>;
 478                 clocks = <&clk_spi1>, <&clk_gates19 5>;
 479                 clock-names = "spi", "pclk_spi1";
 480                 //dmas = <&pdma1 13>, <&pdma1 14>;
 481                 //#dma-cells = <2>;
 482                 //dma-names = "tx", "rx";
 483                 status = "disabled";
 484         };
 485
 486         spi2: spi@ff130000 {
 487                 compatible = "rockchip,rockchip-spi";
 488                 reg = <0x0 0xff130000 0x0 0x1000>;
 489                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 490                 #address-cells = <1>;
 491                 #size-cells = <0>;
 492                 pinctrl-names = "default";
 493                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 494                 rockchip,spi-src-clk = <2>;
 495                 num-cs = <1>;
 496                 clocks = <&clk_spi2>, <&clk_gates19 6>;
 497                 clock-names = "spi", "pclk_spi2";
 498                 //dmas = <&pdma1 15>, <&pdma1 16>;
 499                 //#dma-cells = <2>;
 500                 //dma-names = "tx", "rx";
 501                 status = "disabled";
 502         };
 503
 504         uart_bt: serial@ff180000 {
 505                 compatible = "rockchip,serial";
 506                 reg = <0x0 0xff180000 0x0 0x100>;
 507                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 508                 clock-frequency = <24000000>;
 509                 clocks = <&clk_uart0>, <&clk_gates19 7>;
 510                 clock-names = "sclk_uart", "pclk_uart";
 511                 reg-shift = <2>;
 512                 reg-io-width = <4>;
 513                 //dmas = <&pdma1 1>, <&pdma1 2>;
 514                 //#dma-cells = <2>;
 515                 pinctrl-names = "default";
 516                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 517                 status = "disabled";
 518         };
 519
 520         uart_bb: serial@ff190000 {
 521                 compatible = "rockchip,serial";
 522                 reg = <0x0 0xff190000 0x0 0x100>;
 523                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 524                 clock-frequency = <24000000>;
 525                 clocks = <&clk_uart1>, <&clk_gates19 8>;
 526                 clock-names = "sclk_uart", "pclk_uart";
 527                 reg-shift = <2>;
 528                 reg-io-width = <4>;
 529                 //dmas = <&pdma1 3>, <&pdma1 4>;
 530                 //#dma-cells = <2>;
 531                 pinctrl-names = "default";
 532                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 533                 status = "disabled";
 534         };
 535
 536         uart_dbg: serial@ff690000 {
 537                 compatible = "rockchip,serial";
 538                 reg = <0x0 0xff690000 0x0 0x100>;
 539                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 540                 clock-frequency = <24000000>;
 541                 clocks = <&clk_uart2>, <&clk_gates13 5>;
 542                 clock-names = "sclk_uart", "pclk_uart";
 543                 reg-shift = <2>;
 544                 reg-io-width = <4>;
 545                 //dmas = <&pdma0 4>, <&pdma0 5>;
 546                 //#dma-cells = <2>;
 547                 //pinctrl-names = "default";
 548                 //pinctrl-0 = <&uart2_xfer>;
 549                 status = "disabled";
 550         };
 551
 552         uart_gps: serial@ff1b0000 {
 553                 compatible = "rockchip,serial";
 554                 reg = <0x0 0xff1b0000 0x0 0x100>;
 555                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 556                 clock-frequency = <24000000>;
 557                 clocks = <&clk_uart3>, <&clk_gates19 9>;
 558                 clock-names = "sclk_uart", "pclk_uart";
 559                 current-speed = <115200>;
 560                 reg-shift = <2>;
 561                 reg-io-width = <4>;
 562                 //dmas = <&pdma1 7>, <&pdma1 8>;
 563                 //#dma-cells = <2>;
 564                 pinctrl-names = "default";
 565                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 566                 status = "disabled";
 567         };
 568
 569         uart_exp: serial@ff1c0000 {
 570                 compatible = "rockchip,serial";
 571                 reg = <0x0 0xff1c0000 0x0 0x100>;
 572                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 573                 clock-frequency = <24000000>;
 574                 clocks = <&clk_uart4>, <&clk_gates19 10>;
 575                 clock-names = "sclk_uart", "pclk_uart";
 576                 reg-shift = <2>;
 577                 reg-io-width = <4>;
 578                 //dmas = <&pdma1 9>, <&pdma1 10>;
 579                 //#dma-cells = <2>;
 580                 pinctrl-names = "default";
 581                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 582                 status = "disabled";
 583         };
 584
 585         mbox: mbox@ff6b0000 {
 586                 compatible = "rockchip,rk3368-mailbox";
 587                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 588                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 589                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 590                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 591                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 592                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 593                 clocks = <&clk_gates12 1>;
 594                 clock-names = "pclk_mailbox";
 595                 #mbox-cells = <1>;
 596         };
 597
 598         mbox_scpi: mbox-scpi {
 599                 compatible = "rockchip,mbox-scpi";
 600                 mboxes = <&mbox 0 &mbox 1>;
 601         };
 602
 603         ddr {
 604                 compatible = "rockchip,rk3368-ddr";
 605                 status = "okay";
 606                 rockchip,ddrpctl = <&ddrpctl>;
 607                 rockchip,grf = <&grf>;
 608                 rockchip,msch = <&msch>;
 609         };
 610
 611         rockchip_clocks_init: clocks-init{
 612                 compatible = "rockchip,clocks-init";
 613                 rockchip,clocks-init-parent =
 614                         <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
 615                         <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
 616                         <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
 617                         <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
 618                 rockchip,clocks-init-rate =
 619                         <&clk_gpll 576000000>,          <&clk_core_b 792000000>,
 620                         <&clk_core_l 600000000>,        <&clk_cpll 400000000>,
 621                         /*<&clk_npll 500000000>,*/      <&aclk_bus 300000000>,
 622                         <&hclk_bus 150000000>,          <&pclk_bus 75000000>,
 623                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 624                         <&hclk_peri 150000000>,         <&pclk_peri 75000000>,
 625                         <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
 626                         <&clk_cs 300000000>,            <&clkin_trace 300000000>,
 627                         <&aclk_cci 600000000>,          <&clk_mac 125000000>,
 628                         <&aclk_vio0 400000000>,         <&hclk_vio 100000000>,
 629                         <&aclk_rga_pre 400000000>,      <&clk_rga 400000000>,
 630                         <&clk_isp 400000000>,           <&clk_edp 200000000>,
 631                         <&clk_gpu_core 400000000>,      <&aclk_gpu_mem 400000000>,
 632                         <&aclk_gpu_cfg 400000000>,      <&aclk_vepu 400000000>,
 633                         <&aclk_vdpu 400000000>,         <&clk_hevc_core 300000000>,
 634                         <&clk_hevc_cabac 300000000>;
 635 /*
 636                 rockchip,clocks-uboot-has-init =
 637                         <&aclk_vio0>;
 638 */
 639         };
 640
 641         rockchip_clocks_enable: clocks-enable {
 642                 compatible = "rockchip,clocks-enable";
 643                 clocks =
 644                         /*PLL*/
 645                         <&clk_apllb>,
 646                         <&clk_aplll>,
 647                         <&clk_dpll>,
 648                         <&clk_gpll>,
 649                         <&clk_cpll>,
 650
 651                         /*PD_CORE*/
 652                         <&clk_cs>,
 653                         <&clkin_trace>,
 654                         <&aclk_cci>,
 655
 656                         /*PD_BUS*/
 657                         <&aclk_bus>,
 658                         <&hclk_bus>,
 659                         <&pclk_bus>,
 660                         <&clk_gates12 12>,/*aclk_strc_sys*/
 661                         <&clk_gates12 6>,/*aclk_intmem1*/
 662                         <&clk_gates12 5>,/*aclk_intmem0*/
 663                         <&clk_gates12 4>,/*aclk_intmem*/
 664                         <&clk_gates13 9>,/*aclk_gic400*/
 665                         <&clk_gates12 9>,/*hclk_rom*/
 666
 667                         /*PD_ALIVE*/
 668                         <&clk_gates22 12>,/*pclk_timer0*/
 669                         <&clk_gates22 9>,/*pclk_alive_niu*/
 670                         <&clk_gates22 8>,/*pclk_grf*/
 671
 672                         /*PD_PMU*/
 673                         <&clk_gates23 5>,/*pclk_pmugrf*/
 674                         <&clk_gates23 3>,/*pclk_sgrf*/
 675                         <&clk_gates23 2>,/*pclk_pmu_noc*/
 676                         <&clk_gates23 1>,/*pclk_intmem1*/
 677                         <&clk_gates23 0>,/*pclk_pmu*/
 678
 679                         /*PD_PERI*/
 680                         <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
 681                         <&clk_gates20 8>,/*aclk_peri_niu*/
 682                         <&clk_gates21 4>,/*aclk_peri_mmu*/
 683                         <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
 684                         <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
 685                         <&clk_gates19 1>,/*pclk_peri_axi_matrix*/
 686
 687                         <&clk_gates24 0>, /* g_clk_timer0 */
 688                         <&clk_gates24 1>, /* g_clk_timer1 */
 689
 690                         <&fclk_mcu>,
 691                         <&stclk_mcu>,
 692                         <&clk_gates7 0>;/*clk_jtag*/
 693         };
 694
 695         /* I2C_PMU */
 696         i2c0: i2c@ff650000 {
 697                 compatible = "rockchip,rk30-i2c";
 698                 reg = <0x0 0xff650000 0x0 0x1000>;
 699                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 700                 #address-cells = <1>;
 701                 #size-cells = <0>;
 702                 pinctrl-names = "default", "gpio", "sleep";
 703                 pinctrl-0 = <&i2c0_xfer>;
 704                 pinctrl-1 = <&i2c0_gpio>;
 705                 pinctrl-2 = <&i2c0_sleep>;
 706                 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
 707                 clocks = <&clk_gates12 2>;
 708                 rockchip,check-idle = <1>;
 709                 status = "disabled";
 710         };
 711
 712         /* I2C_AUDIO */
 713         i2c1: i2c@ff660000 {
 714                 compatible = "rockchip,rk30-i2c";
 715                 reg = <0x0 0xff660000 0x0 0x1000>;
 716                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 717                 #address-cells = <1>;
 718                 #size-cells = <0>;
 719                 pinctrl-names = "default", "gpio", "sleep";
 720                 pinctrl-0 = <&i2c1_xfer>;
 721                 pinctrl-1 = <&i2c1_gpio>;
 722                 pinctrl-2 = <&i2c1_sleep>;
 723                 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
 724                 clocks = <&clk_gates12 3>;
 725                 rockchip,check-idle = <1>;
 726                 status = "disabled";
 727         };
 728
 729         /* I2C_SENSOR */
 730         i2c2: i2c@ff140000 {
 731                 compatible = "rockchip,rk30-i2c";
 732                 reg = <0x0 0xff140000 0x0 0x1000>;
 733                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 734                 #address-cells = <1>;
 735                 #size-cells = <0>;
 736                 pinctrl-names = "default", "gpio", "sleep";
 737                 pinctrl-0 = <&i2c2_xfer>;
 738                 pinctrl-1 = <&i2c2_gpio>;
 739                 pinctrl-2 = <&i2c2_sleep>;
 740                 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 741                 clocks = <&clk_gates19 11>;
 742                 rockchip,check-idle = <1>;
 743                 status = "disabled";
 744         };
 745
 746         /* I2C_CAM */
 747         i2c3: i2c@ff150000 {
 748                 compatible = "rockchip,rk30-i2c";
 749                 reg = <0x0 0xff150000 0x0 0x1000>;
 750                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 751                 #address-cells = <1>;
 752                 #size-cells = <0>;
 753                 pinctrl-names = "default", "gpio", "sleep";
 754                 pinctrl-0 = <&i2c3_xfer>;
 755                 pinctrl-1 = <&i2c3_gpio>;
 756                 pinctrl-2 = <&i2c3_sleep>;
 757                 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
 758                 clocks = <&clk_gates19 12>;
 759                 rockchip,check-idle = <1>;
 760                 status = "disabled";
 761         };
 762
 763         /* I2C_TP */
 764         i2c4: i2c@ff160000 {
 765                 compatible = "rockchip,rk30-i2c";
 766                 reg = <0x0 0xff160000 0x0 0x1000>;
 767                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 768                 #address-cells = <1>;
 769                 #size-cells = <0>;
 770                 pinctrl-names = "default", "gpio", "sleep";
 771                 pinctrl-0 = <&i2c4_xfer>;
 772                 pinctrl-1 = <&i2c4_gpio>;
 773                 pinctrl-2 = <&i2c4_sleep>;
 774                 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
 775                 clocks = <&clk_gates19 13>;
 776                 rockchip,check-idle = <1>;
 777                 status = "disabled";
 778         };
 779
 780         /* I2C_HDMI */
 781         i2c5: i2c@ff170000 {
 782                 compatible = "rockchip,rk30-i2c";
 783                 reg = <0x0 0xff170000 0x0 0x1000>;
 784                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 785                 #address-cells = <1>;
 786                 #size-cells = <0>;
 787                 pinctrl-names = "default", "gpio", "sleep";
 788                 pinctrl-0 = <&i2c5_xfer>;
 789                 pinctrl-1 = <&i2c5_gpio>;
 790                 pinctrl-2 = <&i2c5_sleep>;
 791                 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
 792                 clocks = <&clk_gates19 14>;
 793                 rockchip,check-idle = <1>;
 794                 status = "disabled";
 795         };
 796
 797         fb: fb {
 798                 compatible = "rockchip,rk-fb";
 799                 rockchip,disp-mode = <NO_DUAL>;
 800         };
 801
 802
 803         rk_screen: rk_screen {
 804                 compatible = "rockchip,screen";
 805         };
 806
 807         dsihost0: mipi@ff960000{
 808                 compatible = "rockchip,rk3368-dsi";
 809                 rockchip,prop = <0>;
 810                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 811                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 812                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 813                 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>, <&pd_mipidsi>;
 814                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host", "pd_mipi_dsi";
 815                 status = "disabled";
 816         };
 817
 818         lvds: lvds@ff968000 {
 819                 compatible = "rockchip,rk3368-lvds";
 820                 rockchip,grf = <&grf>;
 821                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 822                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 823                 clocks = <&clk_gates22 10>, <&clk_gates17 3>, <&pd_lvds>;
 824                 clock-names = "pclk_lvds", "pclk_lvds_ctl", "pd_lvds";
 825                 status = "disabled";
 826         };
 827
 828         edp: edp@ff970000 {
 829                 compatible = "rockchip,rk32-edp";
 830                 reg = <0x0 0xff970000 0x0 0x4000>;
 831                 rockchip,grf = <&grf>;
 832                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 833                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
 834                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 835                 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
 836                 reset-names = "edp_24m", "edp_apb";
 837         };
 838
 839         hdmi: hdmi@ff980000 {
 840                 compatible = "rockchip,rk3368-hdmi";
 841                 reg = <0x0 0xff980000 0x0 0x20000>;
 842                 rockchip,grf = <&grf>;
 843                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 844                 pinctrl-names = "default", "gpio";
 845                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 846                 pinctrl-1 = <&i2c5_gpio>;
 847                 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
 848                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 849                 status = "disabled";
 850         };
 851
 852         hdmi_hdcp2: hdmi_hdcp2@ff978000 {
 853                 compatible = "rockchip,rk3368-hdmi-hdcp2";
 854                 reg = <0x0 0xff978000 0x0 0x2000>;
 855                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 856                 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
 857                 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
 858                 status = "disabled";
 859         };
 860
 861         lcdc: lcdc@ff930000 {
 862                  compatible = "rockchip,rk3368-lcdc";
 863                  rockchip,grf = <&grf>;
 864                  rockchip,pmugrf = <&pmugrf>;
 865                  rockchip,cru = <&cru>;
 866                  rockchip,prop = <PRMRY>;
 867                  rockchip,pwr18 = <0>;
 868                  rockchip,iommu-enabled = <1>;
 869                  reg = <0x0 0xff930000 0x0 0x10000>;
 870                  interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 871                 /*pinctrl-names = "default", "gpio";
 872                  *pinctrl-0 = <&lcdc_lcdc>;
 873                  *pinctrl-1 = <&lcdc_gpio>;
 874                  */
 875                  status = "disabled";
 876                  clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>, <&pd_vop>;
 877                  clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll", "pd_lcdc";
 878         };
 879
 880         adc: adc@ff100000 {
 881                 compatible = "rockchip,saradc";
 882                 reg = <0x0 0xff100000 0x0 0x100>;
 883                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 884                 #io-channel-cells = <1>;
 885                 io-channel-ranges;
 886                 rockchip,adc-vref = <1800>;
 887                 clock-frequency = <1000000>;
 888                 clocks = <&clk_saradc>, <&clk_gates19 15>;
 889                 clock-names = "saradc", "pclk_saradc";
 890                 status = "disabled";
 891         };
 892
 893         rga@ff920000 {
 894                 compatible = "rockchip,rga2";
 895                 dev_mode = <1>;
 896                 reg = <0x0 0xff920000 0x0 0x1000>;
 897                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 898                 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
 899                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 900         };
 901
 902         i2s0: i2s0@ff898000 {
 903                 compatible = "rockchip-i2s";
 904                 reg = <0x0 0xff898000 0x0 0x1000>;
 905                 i2s-id = <0>;
 906                 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 907                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 908                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 909                 dmas = <&pdma0 0>, <&pdma0 1>;
 910                 #dma-cells = <2>;
 911                 dma-names = "tx", "rx";
 912                 pinctrl-names = "default", "sleep";
 913                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 914                 pinctrl-1 = <&i2s_gpio>;
 915         };
 916
 917         i2s1: i2s1@ff890000 {
 918                 compatible = "rockchip-i2s";
 919                 reg = <0x0 0xff890000 0x0 0x1000>;
 920                 i2s-id = <1>;
 921                 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
 922                 clock-names = "i2s_clk", "i2s_hclk";
 923                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 924                 dmas = <&pdma0 6>, <&pdma0 7>;
 925                 #dma-cells = <2>;
 926                 dma-names = "tx", "rx";
 927         };
 928
 929         spdif: spdif@ff880000 {
 930                 compatible = "rockchip-spdif";
 931                 reg = <0x0 0xff880000 0x0 0x1000>;
 932                 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
 933                 clock-names = "spdif_mclk", "spdif_hclk";
 934                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 935                 dmas = <&pdma0 3>;
 936                 #dma-cells = <1>;
 937                 dma-names = "tx";
 938                 pinctrl-names = "default";
 939                 pinctrl-0 = <&spdif_tx>;
 940         };
 941
 942         pwm0: pwm@ff680000 {
 943                 compatible = "rockchip,rk-pwm";
 944                 reg = <0x0 0xff680000 0x0 0x10>;
 945                 #pwm-cells = <2>;
 946                 pinctrl-names = "default";
 947                 pinctrl-0 = <&pwm0_pin>;
 948                 clocks = <&clk_gates13 6>;
 949                 clock-names = "pclk_pwm";
 950                 status = "disabled";
 951         };
 952
 953         pwm1: pwm@ff680010 {
 954                 compatible = "rockchip,rk-pwm";
 955                 reg = <0x0 0xff680010 0x0 0x10>;
 956                 #pwm-cells = <2>;
 957                 pinctrl-names = "default";
 958                 pinctrl-0 = <&pwm1_pin>;
 959                 clocks = <&clk_gates13 6>;
 960                 clock-names = "pclk_pwm";
 961                 status = "disabled";
 962         };
 963
 964         pwm2: pwm@ff680020 {
 965                 compatible = "rockchip,rk-pwm";
 966                 reg = <0x0 0xff680020 0x0 0x10>;
 967                 #pwm-cells = <2>;
 968                 //pinctrl-names = "default";
 969                 //pinctrl-0 = <&pwm1_pin>;
 970                 clocks = <&clk_gates13 6>;
 971                 clock-names = "pclk_pwm";
 972                 status = "disabled";
 973         };
 974
 975         pwm3: pwm@ff680030 {
 976                 compatible = "rockchip,rk-pwm";
 977                 reg = <0x0 0xff680030 0x0 0x10>;
 978                 #pwm-cells = <2>;
 979                 pinctrl-names = "default";
 980                 pinctrl-0 = <&pwm3_pin>;
 981                 clocks = <&clk_gates13 6>;
 982                 clock-names = "pclk_pwm";
 983                 status = "disabled";
 984         };
 985
 986         remotectl: pwm@ff680030 {
 987                 compatible = "rockchip,remotectl-pwm";
 988                 reg = <0x0 0xff680030 0x0 0x50>;
 989                 #pwm-cells = <2>;
 990                 pinctrl-names = "default";
 991                 pinctrl-0 = <&pwm3_pin>;
 992                 clocks = <&clk_gates13 6>;
 993                 clock-names = "pclk_pwm";
 994                 dmas = <&pdma0 2>;
 995                 #dma-cells = <2>;
 996                 dma-names = "rx";
 997                 remote_pwm_id = <3>;
 998                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 999                 status = "disabled";
1000         };
1001
1002         voppwm: pwm@ff9301a0 {
1003                 compatible = "rockchip,vop-pwm";
1004                 reg = <0x0 0xff9301a0 0x0 0x10>;
1005                 #pwm-cells = <2>;
1006                 pinctrl-names = "default";
1007                 pinctrl-0 = <&vop_pwm_pin>;
1008                 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
1009                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
1010                 status = "disabled";
1011         };
1012
1013         pvtm {
1014                 compatible = "rockchip,rk3368-pvtm";
1015                 rockchip,grf = <&grf>;
1016                 rockchip,pmugrf = <&pmugrf>;
1017                 rockchip,pvtm-clk-out = <1>;
1018         };
1019
1020         cpufreq {
1021                 compatible = "rockchip,rk3368-cpufreq";
1022                 rockchip,grf = <&grf>;
1023         };
1024
1025         dvfs {
1026
1027                 vd_arm: vd_arm {
1028                         regulator_name = "vdd_arm";
1029                         suspend_volt = <1000>; //mV
1030                         pd_core {
1031                                 clk_core_b_dvfs_table: clk_core_b {
1032                                         operating-points = <
1033                                                 /* KHz    uV */
1034                                                 312000 1200000
1035                                                 504000 1200000
1036                                                 816000 1200000
1037                                                 1008000 1200000
1038                                                 >;
1039                                         status = "okay";
1040                                         temp-limit-enable = <1>;
1041                                         target-temp = <80>;
1042                                         min_temp_limit = <216000>;
1043                                         normal-temp-limit = <
1044                                         /*delta-temp    delta-freq*/
1045                                                 3       96000
1046                                                 6       144000
1047                                                 9       192000
1048                                                 15      384000
1049                                                 >;
1050                                         performance-temp-limit = <
1051                                                 /*temp    freq*/
1052                                                 100     816000
1053                                                 >;
1054                                         lkg_adjust_volt_en = <1>;
1055                                         channel = <0>;
1056                                         def_table_lkg = <25>;
1057                                         min_adjust_freq = <216000>;
1058                                         lkg_adjust_volt_table = <
1059                                                 /*lkg(mA)  volt(uV)*/
1060                                                 0         25000
1061                                                 >;
1062                                 };
1063                                 clk_core_l_dvfs_table: clk_core_l {
1064                                         operating-points = <
1065                                                 /* KHz    uV */
1066                                                 312000 1200000
1067                                                 504000 1200000
1068                                                 816000 1200000
1069                                                 1008000 1200000
1070                                                 >;
1071                                         status = "okay";
1072                                         temp-limit-enable = <1>;
1073                                         target-temp = <80>;
1074                                         min_temp_limit = <216000>;
1075                                         normal-temp-limit = <
1076                                         /*delta-temp    delta-freq*/
1077                                                 3       96000
1078                                                 6       144000
1079                                                 9       192000
1080                                                 15      384000
1081                                                 >;
1082                                         performance-temp-limit = <
1083                                                 /*temp    freq*/
1084                                                 100     816000
1085                                                 >;
1086                                         lkg_adjust_volt_en = <1>;
1087                                         channel = <0>;
1088                                         def_table_lkg = <25>;
1089                                         min_adjust_freq = <216000>;
1090                                         lkg_adjust_volt_table = <
1091                                                 /*lkg(mA)  volt(uV)*/
1092                                                 0         25000
1093                                                 >;
1094                                 };
1095                         };
1096                 };
1097
1098                 vd_logic: vd_logic {
1099                         regulator_name = "vdd_logic";
1100                         suspend_volt = <1000>; //mV
1101                         pd_ddr {
1102                                 clk_ddr_dvfs_table: clk_ddr {
1103                                         operating-points = <
1104                                                 /* KHz    uV */
1105                                                 200000 1200000
1106                                                 300000 1200000
1107                                                 400000 1200000
1108                                                 >;
1109                                         bd-freq-table = <
1110                                                 /* bandwidth   freq */
1111                                                 2700           792000
1112                                                 2600           600000
1113                                                 2280           456000
1114                                                 1560           396000
1115                                                 1020           324000
1116                                                 720            240000
1117                                                 >;
1118                                         channel = <2>;
1119                                         status = "disabled";
1120                                 };
1121                         };
1122
1123                         pd_gpu {
1124                                 clk_gpu_dvfs_table: clk_gpu {
1125                                         operating-points = <
1126                                                 /* KHz    uV */
1127                                                 200000 1200000
1128                                                 300000 1200000
1129                                                 400000 1200000
1130                                                 >;
1131                                         channel = <1>;
1132                                         status = "okay";
1133                                         regu-mode-table = <
1134                                                 /*freq     mode*/
1135                                                 200000     4
1136                                                 0          3
1137                                         >;
1138                                         regu-mode-en = <0>;
1139                                 };
1140                         };
1141                 };
1142         };
1143
1144         ion {
1145                 compatible = "rockchip,ion";
1146                 #address-cells = <1>;
1147                 #size-cells = <0>;
1148
1149                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1150                         compatible = "rockchip,ion-heap";
1151                         rockchip,ion_heap = <4>;
1152                         reg = <0x00000000 0x00000000>; /* 0MB */
1153                 };
1154                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1155                         compatible = "rockchip,ion-heap";
1156                         rockchip,ion_heap = <0>;
1157                 };
1158         };
1159
1160         vpu: vpu_service {
1161                 compatible = "rockchip,vpu_sub";
1162                 iommu_enabled = <1>;
1163                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1164                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1165                 interrupt-names = "irq_enc", "irq_dec";
1166                 dev_mode = <0>;
1167                 name = "vpu_service";
1168         };
1169
1170         hevc: hevc_service {
1171                 compatible = "rockchip,hevc_sub";
1172                 iommu_enabled = <1>;
1173                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1174                 interrupt-names = "irq_dec";
1175                 dev_mode = <1>;
1176                 name = "hevc_service";
1177         };
1178
1179         vpu_combo: vpu_combo@ff9a0000 {
1180                 compatible = "rockchip,vpu_combo";
1181                 reg = <0x0 0xff9a0000 0x0 0x800>;
1182                 rockchip,grf = <&grf>;
1183                 subcnt = <2>;
1184                 rockchip,sub = <&vpu>, <&hevc>;
1185                 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1186                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1187                 resets = <&reset RK3368_SRST_VIDEO_H>, <&reset RK3368_SRST_VIDEO_A>,
1188                         <&reset RK3368_SRST_VIDEO>;
1189                 reset-names = "video_h", "video_a", "video";
1190                 mode_bit = <12>;
1191                 mode_ctrl = <0x418>;
1192                 name = "vpu_combo";
1193                 status = "okay";
1194         };
1195
1196         iep: iep@ff900000 {
1197                 compatible = "rockchip,iep";
1198                 iommu_enabled = <1>;
1199                 reg = <0x0 0xff900000 0x0 0x800>;
1200                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1201                 clocks = <&clk_gates16 2>, <&clk_gates16 3>;
1202                 clock-names = "aclk_iep", "hclk_iep";
1203                 status = "okay";
1204         };
1205
1206         gmac: eth@ff290000 {
1207                 compatible = "rockchip,rk3368-gmac";
1208                 reg = <0x0 0xff290000 0x0 0x10000>;
1209                 rockchip,grf = <&grf>;
1210                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1211                 interrupt-names = "macirq";
1212
1213                 clocks = <&clk_mac>, <&clk_gates7 4>,
1214                          <&clk_gates7 5>, <&clk_gates7 6>,
1215                          <&clk_gates7 7>, <&clk_gates20 13>,
1216                          <&clk_gates20 14>;
1217                 clock-names = "clk_mac", "mac_clk_rx",
1218                               "mac_clk_tx", "clk_mac_ref",
1219                               "clk_mac_refout", "aclk_mac",
1220                               "pclk_mac";
1221
1222                 phy-mode = "rgmii";
1223                 pinctrl-names = "default";
1224                 pinctrl-0 = <&rgmii_pins>;
1225                 status = "disabled";
1226         };
1227
1228         gpu {
1229                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1230                 reg = <0x0 0xffa30000 0x0 0x10000>;
1231                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1232                 interrupt-names = "GPU";
1233         };
1234
1235         iep_mmu {
1236                 dbgname = "iep";
1237                 compatible = "rockchip,iep_mmu";
1238                 reg = <0x0 0xff900800 0x0 0x100>;
1239                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1240                 interrupt-names = "iep_mmu";
1241         };
1242
1243         vip_mmu {
1244                 dbgname = "vip";
1245                 compatible = "rockchip,vip_mmu";
1246                 reg = <0x0 0xff950800 0x0 0x100>;
1247                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1248                 interrupt-names = "vip_mmu";
1249         };
1250
1251         vop_mmu {
1252                 dbgname = "vop";
1253                 compatible = "rockchip,vopb_mmu";
1254                 reg = <0x0 0xff930300 0x0 0x100>;
1255                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1256                 interrupt-names = "vop_mmu";
1257         };
1258
1259         isp_mmu {
1260                 dbgname = "isp_mmu";
1261                 compatible = "rockchip,isp_mmu";
1262                 reg = <0x0 0xff914000 0x0 0x100>,
1263                 <0x0 0xff915000 0x0 0x100>;
1264                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1265                 interrupt-names = "isp_mmu";
1266         };
1267
1268         hdcp_mmu {
1269                 dbgname = "hdcp_mmu";
1270                 compatible = "rockchip,hdcp_mmu";
1271                 reg = <0x0 0xff940000 0x0 0x100>;
1272                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1273                 interrupt-names = "hdcp_mmu";
1274         };
1275
1276         hevc_mmu {
1277                 dbgname = "hevc";
1278                 compatible = "rockchip,hevc_mmu";
1279                 reg = <0x0 0xff9a0440 0x0 0x40>,                      /*need to fix*/
1280                           <0x0 0xff9a0480 0x0 0x40>;
1281                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;        /*need to fix*/
1282                 interrupt-names = "hevc_mmu";
1283         };
1284
1285         vpu_mmu {
1286                 dbgname = "vpu";
1287                 compatible = "rockchip,vpu_mmu";
1288                 reg = <0x0 0xff9a0800 0x0 0x100>;                    /*need to fix*/
1289                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,        /*need to fix*/
1290                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1291                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1292         };
1293
1294         rockchip_suspend: rockchip_suspend {
1295                 rockchip,ctrbits = <
1296                         (0
1297                         | RKPM_SLP_ARMOFF
1298                         | RKPM_SLP_PMU_PLLS_PWRDN
1299                         /*| RKPM_SLP_PMU_PMUALIVE_32K
1300                         | RKPM_SLP_SFT_PLLS_DEEP
1301                         | RKPM_SLP_PMU_DIS_OSC */
1302                         | RKPM_SLP_SFT_PD_NBSCUS
1303                         )
1304                         >;
1305         };
1306
1307         isp: isp@ff910000{
1308                 compatible = "rockchip,isp";
1309                 reg = <0x0 0xff910000 0x0 0x10000>;
1310                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1311                 clocks = <&clk_gates16 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>, <&pd_isp>, <&clk_gates16 9>;
1312                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx", "pd_isp", "clk_vio0_noc";
1313                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1314                 pinctrl-0 = <&cif_clkout>;
1315                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1316                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1317                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1318                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1319                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
1320                 pinctrl-6 = <&cif_clkout>;
1321                 pinctrl-7 = <&cif_clkout &isp_prelight>;
1322                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
1323                 pinctrl-9 = <&isp_flash_trigger>;
1324                 rockchip,isp,mipiphy = <2>;
1325                 rockchip,isp,cifphy = <1>;
1326                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1327                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1328                 rockchip,grf = <&grf>;
1329                 rockchip,cru = <&cru>;
1330                 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1331                 rockchip,isp,iommu_enable = <1>;
1332                 status = "okay";
1333         };
1334
1335         cif: cif@ff950000 {
1336                 compatible = "rockchip,cif";
1337                 reg = <0x0 0xff950000 0x0 0x10000>;
1338                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1339                 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1340                 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1341                 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1342                 pinctrl-names = "cif_pin_all";
1343                 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1344                 rockchip,grf = <&grf>;
1345                 rockchip,cru = <&cru>;
1346                 status = "okay";
1347         };
1348
1349 /*
1350         thermal-zones {
1351                 #include "rk3368-thermal.dtsi"
1352         };
1353 */
1354
1355         tsadc: tsadc@ff280000 {
1356                 compatible = "rockchip,rk3368-tsadc";
1357                 reg = <0x0 0xff280000 0x0 0x100>;
1358                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1359                 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1360                 rockchip,grf = <&grf>;
1361                 rockchip,cru = <&cru>;
1362                 rockchip,pmu = <&pmu>;
1363                 clock-names = "tsadc", "apb_pclk";
1364                 clock-frequency = <32000>;
1365                 resets = <&reset RK3368_SRST_TSADC_P>;
1366                 reset-names = "tsadc-apb";
1367                 //pinctrl-names = "default";
1368                 //pinctrl-0 = <&tsadc_int>;
1369                 #thermal-sensor-cells = <1>;
1370                 hw-shut-temp = <120000>;
1371                 status = "disabled";
1372         };
1373
1374         tsp: tsp@FF8B0000 {
1375                 compatible = "rockchip,rk3368-tsp";
1376                 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1377                 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1378                 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1379                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1380                 interrupt-names = "irq_tsp";
1381                 // pinctrl-names = "default";
1382                 // pinctrl-0 = <&isp_hsadc>;
1383                 status = "okay";
1384         };
1385
1386         crypto: crypto@FF8A0000{
1387                 compatible = "rockchip,rk3368-crypto";
1388                 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1389                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1390                 interrupt-names = "irq_crypto";
1391                         clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1392                 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1393                 status = "okay";
1394         };
1395
1396         dwc_control_usb: dwc-control-usb {
1397                 compatible = "rockchip,rk3368-dwc-control-usb";
1398                 rockchip,grf = <&grf>;
1399                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1400                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1401                 interrupt-names = "otg_id", "otg_bvalid",
1402                                   "otg_linestate", "host0_linestate";
1403                 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1404                 clock-names = "hclk_usb_peri", "usbphy_480m";
1405                 //resets = <&reset RK3128_RST_USBPOR>;
1406                 //reset-names = "usbphy_por";
1407                 usb_bc{
1408                         compatible = "inno,phy";
1409                         regbase = &dwc_control_usb;
1410                         rk_usb,bvalid     = <0x4bc 23 1>;
1411                         rk_usb,iddig      = <0x4bc 26 1>;
1412                         rk_usb,vdmsrcen   = <0x718 12 1>;
1413                         rk_usb,vdpsrcen   = <0x718 11 1>;
1414                         rk_usb,rdmpden    = <0x718 10 1>;
1415                         rk_usb,idpsrcen   = <0x718  9 1>;
1416                         rk_usb,idmsinken  = <0x718  8 1>;
1417                         rk_usb,idpsinken  = <0x718  7 1>;
1418                         rk_usb,dpattach   = <0x4b8 31 1>;
1419                         rk_usb,cpdet      = <0x4b8 30 1>;
1420                         rk_usb,dcpattach  = <0x4b8 29 1>;
1421                 };
1422         };
1423
1424         usbphy: phy {
1425                 compatible = "rockchip,rk3368-usb-phy";
1426                 rockchip,grf = <&grf>;
1427                 #address-cells = <1>;
1428                 #size-cells = <0>;
1429
1430                 usbphy0: usb-phy0 {
1431                         #phy-cells = <0>;
1432                         reg = <0x700>;
1433                 };
1434
1435                 usbphy1: usb-phy1 {
1436                         #phy-cells = <0>;
1437                         reg = <0x728>;
1438                 };
1439         };
1440
1441         usb0: usb@ff580000 {
1442                 compatible = "rockchip,rk3368_usb20_otg";
1443                 reg = <0x0 0xff580000 0x0 0x40000>;
1444                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1445                 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1446                 clock-names = "clk_usbphy0", "hclk_otg";
1447                 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1448                                 <&reset RK3368_SRST_USBOTGC0>;
1449                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1450                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1451                 rockchip,usb-mode = <0>;
1452         };
1453
1454         usb_ehci: usb@ff500000 {
1455                 compatible = "generic-ehci";
1456                 reg = <0x0 0xff500000 0x0 0x20000>;
1457                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1458                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1459                 clock-names = "clk_usbphy0", "hclk_ehci";
1460                 phys = <&usbphy1>;
1461                 phy-names = "usb";
1462                 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1463                 //              <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1464                 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1465         };
1466
1467         usb_ohci: usb@ff520000 {
1468                 compatible = "generic-ohci";
1469                 reg = <0x0 0xff520000 0x0 0x20000>;
1470                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1471                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1472                 clock-names =  "clk_usbphy0", "hclk_ohci";
1473         };
1474
1475         usb_ehci1: usb@ff5c0000 {
1476                 compatible = "rockchip,rk3288_rk_ehci1_host";
1477                 reg = <0x0 0xff5c0000 0x0 0x40000>;
1478                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1479 /*
1480                 clocks = <&ehci1phy_480m>, <&clk_gates7 8>,
1481                          <&ehci1phy_12m>, <&usbphy_480m>,
1482                          <&otgphy1_480m>, <&otgphy2_480m>;
1483                 clock-names = "ehci1phy_480m", "hclk_ehci1",
1484                               "ehci1phy_12m", "usbphy_480m",
1485                               "ehci1_usbphy1", "ehci1_usbphy2";
1486                 resets = <&reset RK3368_SRST_EHCI1>, <&reset RK3368_SRST_EHCI1_AUX>,
1487                                 <&reset RK3368_SRST_EHCI1PHY>;
1488                 reset-names = "ehci1_ahb", "ehci1_aux", "ehci1_phy";
1489 */
1490                 status = "disabled";
1491         };
1492
1493         pinctrl: pinctrl {
1494                 compatible = "rockchip,rk3368-pinctrl";
1495                 rockchip,grf = <&grf>;
1496                 rockchip,pmugrf = <&pmugrf>;
1497                 #address-cells = <2>;
1498                 #size-cells = <2>;
1499                 ranges;
1500
1501                 gpio0: gpio0@ff750000 {
1502                         compatible = "rockchip,gpio-bank";
1503                         reg =   <0x0 0xff750000 0x0 0x100>;
1504                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1505                         clocks = <&clk_gates23 4>;
1506
1507                         gpio-controller;
1508                         #gpio-cells = <2>;
1509
1510                         interrupt-controller;
1511                         #interrupt-cells = <2>;
1512                 };
1513
1514                 gpio1: gpio1@ff780000 {
1515                         compatible = "rockchip,gpio-bank";
1516                         reg = <0x0 0xff780000 0x0 0x100>;
1517                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1518                         clocks = <&clk_gates22 1>;
1519
1520                         gpio-controller;
1521                         #gpio-cells = <2>;
1522
1523                         interrupt-controller;
1524                         #interrupt-cells = <2>;
1525                 };
1526
1527                 gpio2: gpio2@ff790000 {
1528                         compatible = "rockchip,gpio-bank";
1529                         reg = <0x0 0xff790000 0x0 0x100>;
1530                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1531                         clocks = <&clk_gates22 2>;
1532
1533                         gpio-controller;
1534                         #gpio-cells = <2>;
1535
1536                         interrupt-controller;
1537                         #interrupt-cells = <2>;
1538                 };
1539
1540                 gpio3: gpio3@ff7a0000 {
1541                         compatible = "rockchip,gpio-bank";
1542                         reg = <0x0 0xff7a0000 0x0 0x100>;
1543                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1544                         clocks = <&clk_gates22 3>;
1545
1546                         gpio-controller;
1547                         #gpio-cells = <2>;
1548
1549                         interrupt-controller;
1550                         #interrupt-cells = <2>;
1551                 };
1552
1553                 pcfg_pull_up: pcfg-pull-up {
1554                         bias-pull-up;
1555                 };
1556
1557                 pcfg_pull_down: pcfg-pull-down {
1558                         bias-pull-down;
1559                 };
1560
1561                 pcfg_pull_none: pcfg-pull-none {
1562                         bias-disable;
1563                 };
1564
1565                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1566                         drive-strength = <8>;
1567                 };
1568
1569                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1570                         drive-strength = <12>;
1571                 };
1572
1573                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1574                         bias-pull-up;
1575                         drive-strength = <8>;
1576                 };
1577
1578                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1579                         drive-strength = <4>;
1580                 };
1581
1582                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1583                         bias-pull-up;
1584                         drive-strength = <4>;
1585                 };
1586
1587                 pcfg_output_high: pcfg-output-high {
1588                         output-high;
1589                 };
1590
1591                 pcfg_output_low: pcfg-output-low {
1592                         output-low;
1593                 };
1594
1595                 pcfg_input_high: pcfg-input-high {
1596                         bias-pull-up;
1597                         input-enable;
1598                 };
1599
1600                 i2c0 {
1601                         i2c0_xfer: i2c0-xfer {
1602                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1603                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1604                         };
1605                         i2c0_gpio: i2c0-gpio {
1606                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1607                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1608                         };
1609                         i2c0_sleep: i2c0-sleep {
1610                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_input_high>,
1611                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_input_high>;
1612                         };
1613                 };
1614
1615                 i2c1 {
1616                         i2c1_xfer: i2c1-xfer {
1617                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1618                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1619                         };
1620                         i2c1_gpio: i2c1-gpio {
1621                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1622                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1623                         };
1624                         i2c1_sleep: i2c1-sleep {
1625                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_input_high>,
1626                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_input_high>;
1627                         };
1628                 };
1629
1630                 i2c2 {
1631                         i2c2_xfer: i2c2-xfer {
1632                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1633                                                 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1634                         };
1635                         i2c2_gpio: i2c2-gpio {
1636                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1637                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1638                         };
1639                         i2c2_sleep: i2c2-sleep {
1640                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_input_high>,
1641                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_input_high>;
1642                         };
1643                 };
1644
1645                 i2c3 {
1646                         i2c3_xfer: i2c3-xfer {
1647                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1648                                                 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1649                         };
1650                         i2c3_gpio: i2c3-gpio {
1651                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1652                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1653                         };
1654                         i2c3_sleep: i2c3-sleep {
1655                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_input_high>,
1656                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_input_high>;
1657                         };
1658                 };
1659
1660                 i2c4 {
1661                         i2c4_xfer: i2c4-xfer {
1662                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1663                                                 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1664                         };
1665                         i2c4_gpio: i2c4-gpio {
1666                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1667                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1668                         };
1669                         i2c4_sleep: i2c4-sleep {
1670                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_input_high>,
1671                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_input_high>;
1672                         };
1673                 };
1674
1675                 i2c5 {
1676                         i2c5_xfer: i2c5-xfer {
1677                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1678                                                 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1679                         };
1680                         i2c5_gpio: i2c5-gpio {
1681                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1682                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1683                         };
1684                         i2c5_sleep: i2c5-sleep {
1685                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_input_high>,
1686                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_input_high>;
1687                         };
1688                 };
1689
1690                 uart0 {
1691                         uart0_xfer: uart0-xfer {
1692                                 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1693                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1694                         };
1695
1696                         uart0_cts: uart0-cts {
1697                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1698                         };
1699
1700                         uart0_rts: uart0-rts {
1701                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1702                         };
1703
1704                         uart0_rts_gpio: uart0-rts-gpio {
1705                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1706                         };
1707                 };
1708
1709                 uart1 {
1710                         uart1_xfer: uart1-xfer {
1711                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1712                                                 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1713                         };
1714
1715                         uart1_cts: uart1-cts {
1716                                 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1717                         };
1718
1719                         uart1_rts: uart1-rts {
1720                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1721                         };
1722                 };
1723
1724                 uart2 {
1725                         uart2_xfer: uart2-xfer {
1726                                 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1727                                                 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1728                         };
1729                 };
1730
1731                 uart3 {
1732                         uart3_xfer: uart3-xfer {
1733                                 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1734                                                 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1735                         };
1736
1737                         uart3_cts: uart3-cts {
1738                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1739                         };
1740
1741                         uart3_rts: uart3-rts {
1742                                 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1743                         };
1744                 };
1745
1746                 uart4 {
1747                         uart4_xfer: uart4-xfer {
1748                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1749                                                 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1750                         };
1751
1752                         uart4_cts: uart4-cts {
1753                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1754                         };
1755
1756                         uart4_rts: uart4-rts {
1757                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1758                         };
1759                 };
1760
1761                 spi0 {
1762                         spi0_clk: spi0-clk {
1763                                 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1764                         };
1765                         spi0_cs0: spi0-cs0 {
1766                                 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1767                         };
1768                         spi0_tx: spi0-tx {
1769                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1770                         };
1771                         spi0_rx: spi0-rx {
1772                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1773                         };
1774                         spi0_cs1: spi0-cs1 {
1775                                 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1776                         };
1777                 };
1778
1779                 spi1 {
1780                         spi1_clk: spi1-clk {
1781                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1782                         };
1783                         spi1_cs0: spi1-cs0 {
1784                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1785                         };
1786                         spi1_rx: spi1-rx {
1787                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1788                         };
1789                         spi1_tx: spi1-tx {
1790                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1791                         };
1792                         spi1_cs1: spi1-cs1 {
1793                                 rockchip,pins = <3 GPIO_D4 RK_FUNC_2 &pcfg_pull_up>;
1794                         };
1795                 };
1796
1797                 spi2 {
1798                         spi2_clk: spi2-clk {
1799                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1800                         };
1801                         spi2_cs0: spi2-cs0 {
1802                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1803                         };
1804                         spi2_rx: spi2-rx {
1805                                 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1806                         };
1807                         spi2_tx: spi2-tx {
1808                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1809                         };
1810                 };
1811
1812                 i2s {
1813                         i2s_mclk: i2s-mclk {
1814                                 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1815                         };
1816
1817                         i2s_sclk:i2s-sclk {
1818                                 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1819                         };
1820
1821                         i2s_lrckrx:i2s-lrckrx {
1822                                 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1823                         };
1824
1825                         i2s_lrcktx:i2s-lrcktx {
1826                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1827                         };
1828
1829                         i2s_sdi:i2s-sdi {
1830                                 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1831                         };
1832
1833                         i2s_sdo0:i2s-sdo0 {
1834                                 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1835                         };
1836
1837                         i2s_sdo1:i2s-sdo1 {
1838                                 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1839                         };
1840
1841                         i2s_sdo2:i2s-sdo2 {
1842                                 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1843                         };
1844
1845                         i2s_sdo3:i2s-sdo3 {
1846                                 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1847                         };
1848
1849                         i2s_gpio: i2s-gpio {
1850                                 rockchip,pins = <2 GPIO_C4  RK_FUNC_GPIO &pcfg_pull_none>,
1851                                                 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1852                                                 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1853                                                 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1854                                                 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1855                                                 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1856                                                 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1857                                                 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1858                                                 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1859                         };
1860                 };
1861
1862                 spdif {
1863                         spdif_tx: spdif-tx {
1864                                 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1865                         };
1866                 };
1867
1868                 sdmmc {
1869                         sdmmc_clk: sdmmc-clk {
1870                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1871                         };
1872
1873                         sdmmc_cmd: sdmmc-cmd {
1874                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1875                         };
1876
1877                         sdmmc_dectn: sdmmc-dectn {
1878                                 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1879                         };
1880
1881                         sdmmc_bus1: sdmmc-bus1 {
1882                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1883                         };
1884
1885                         sdmmc_bus4: sdmmc-bus4 {
1886                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1887                                                 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1888                                                 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1889                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1890                         };
1891
1892                         sdmmc_gpio: sdmmc-gpio {
1893                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1894                                                 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1895                                                 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1896                                                 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1897                                                 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1898                                                 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1899                                                 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1900                         };
1901                 };
1902
1903                 sdio0 {
1904                         sdio0_bus1: sdio0-bus1 {
1905                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1906                         };
1907
1908                         sdio0_bus4: sdio0-bus4 {
1909                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1910                                                 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1911                                                 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1912                                                 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1913                         };
1914
1915                         sdio0_cmd: sdio0-cmd {
1916                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1917                         };
1918
1919                         sdio0_clk: sdio0-clk {
1920                                 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1921                         };
1922
1923                         sdio0_dectn: sdio0-dectn {
1924                                 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1925                         };
1926
1927                         sdio0_wrprt: sdio0-wrprt {
1928                                 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1929                         };
1930
1931                         sdio0_pwren: sdio0-pwren {
1932                                 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1933                         };
1934
1935                         sdio0_bkpwr: sdio0-bkpwr {
1936                                 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1937                         };
1938
1939                         sdio0_int: sdio0-int {
1940                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1941                         };
1942
1943                         sdio0_gpio: sdio0-gpio {
1944                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1945                                                 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1946                                                 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1947                                                 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1948                                                 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1949                                                 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1950                                                 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1951                                                 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1952                                                 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1953                                                 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1954                                                 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1955                         };
1956                 };
1957
1958                 emmc {
1959                         emmc_clk: emmc-clk {
1960                                 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1961                         };
1962
1963                         emmc_cmd: emmc-cmd {
1964                                 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1965                         };
1966
1967                         emmc_pwren: emmc-pwren {
1968                                 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1969                         };
1970
1971                         emmc_rstnout: emmc_rstnout {
1972                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1973                         };
1974
1975                         emmc_bus1: emmc-bus1 {
1976                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1977                         };
1978
1979                         emmc_bus4: emmc-bus4 {
1980                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1981                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1982                                                 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1983                                                 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1984                         };
1985                 };
1986
1987                 pwm0 {
1988                         pwm0_pin: pwm0-pin {
1989                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1990                         };
1991
1992                         vop_pwm_pin:vop-pwm {
1993                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1994                         };
1995                 };
1996
1997                 pwm1 {
1998                         pwm1_pin: pwm1-pin {
1999                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
2000                         };
2001                 };
2002
2003                 pwm3 {
2004                         pwm3_pin: pwm3-pin {
2005                                 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
2006                         };
2007                 };
2008
2009                 lcdc {
2010                         lcdc_lcdc: lcdc-lcdc {
2011                                 rockchip,pins =
2012                                                 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
2013                                                 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
2014                                                 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
2015                                                 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
2016                                                 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
2017                                                 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
2018                                                 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
2019                                                 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
2020                                                 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
2021                                                 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
2022                                                 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
2023                                                 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
2024                                                 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
2025                                                 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
2026                                                 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
2027                                                 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
2028                                                 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
2029                                                 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
2030                         };
2031
2032                         lcdc_gpio: lcdc-gpio {
2033                                 rockchip,pins =
2034                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
2035                                                 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
2036                                                 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
2037                                                 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
2038                                                 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
2039                                                 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
2040                                                 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
2041                                                 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
2042                                                 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
2043                                                 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
2044                                                 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
2045                                                 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
2046                                                 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
2047                                                 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
2048                                                 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
2049                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
2050                                                 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
2051                                                 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
2052                         };
2053                 };
2054
2055                 isp {
2056                         cif_clkout: cif-clkout {
2057                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2058                         };
2059
2060                         isp_dvp_d2d9: isp-dvp-d2d9 {
2061                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2062                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2063                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2064                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2065                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2066                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2067                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2068                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2069                                                 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
2070                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
2071                                                 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
2072                                                 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2073                         };
2074
2075                         isp_dvp_d0d1: isp-dvp-d0d1 {
2076                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2077                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
2078                         };
2079
2080                         isp_dvp_d10d11:isp_d10d11       {
2081                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2082                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2083                         };
2084
2085                         isp_dvp_d0d7: isp-dvp-d0d7 {
2086                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2087                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
2088                                                 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2089                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2090                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2091                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2092                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2093                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
2094                         };
2095
2096                         isp_dvp_d4d11: isp-dvp-d4d11 {
2097                                 rockchip,pins =
2098                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2099                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2100                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2101                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2102                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2103                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2104                                                 <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2105                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2106                         };
2107
2108                         isp_shutter: isp-shutter {
2109                                 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2110                                                 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2111                         };
2112
2113                         isp_flash_trigger: isp-flash-trigger {
2114                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2115                         };
2116
2117                         isp_prelight: isp-prelight {
2118                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2119                         };
2120
2121                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2122                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
2123                         };
2124                 };
2125
2126                 gps {
2127                         gps_mag: gps-mag {
2128                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
2129                         };
2130
2131                         gps_sig: gps-sig {
2132                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
2133
2134                         };
2135
2136                         gps_rfclk: gps-rfclk {
2137                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
2138                         };
2139                 };
2140
2141                 gmac {
2142                         rgmii_pins: rgmii-pins {
2143                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2144                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2145                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2146                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2147                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2148                                                 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
2149                                                 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
2150                                                 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
2151                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2152                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2153                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2154                                                 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
2155                                                 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
2156                                                 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
2157                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
2158                         };
2159
2160                         rmii_pins: rmii-pins {
2161                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2162                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2163                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2164                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2165                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2166                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2167                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2168                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2169                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
2170                                                 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
2171                         };
2172                 };
2173
2174                 tsadc_pin {
2175                         tsadc_int: tsadc-int {
2176                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
2177                         };
2178                         tsadc_gpio: tsadc-gpio {
2179                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
2180                         };
2181                 };
2182
2183                 hdmi_pin {
2184                         hdmi_cec: hdmi-cec {
2185                                 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
2186                         };
2187                 };
2188
2189                 hdmi_i2c {
2190                         hdmii2c_xfer: hdmii2c-xfer {
2191                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
2192                                                 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
2193                         };
2194                 };
2195
2196                 cpu_jtag {
2197                         cpu_jtag: cpu-jtag {
2198                                 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_up>,
2199                                                 <2 GPIO_B0 RK_FUNC_2 &pcfg_pull_up>;
2200                         };
2201                 };
2202
2203                 mcu_jtag {
2204                         mcu_jtag: mcu-jtag {
2205                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>,
2206                                                 <2 GPIO_B1 RK_FUNC_2 &pcfg_pull_up>;
2207                         };
2208                 };
2209         };
2210
2211         reboot {
2212                 compatible = "rockchip,rk3368-reboot";
2213                 rockchip,cru = <&cru>;
2214                 rockchip,pmugrf = <&pmugrf>;
2215         };
2216 };