arch/arm64/boot/dts/rk3368.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/sensor-dev.h>
   6 #include <dt-bindings/clock/rk_system_status.h>
   7
   8 #include "rk3368-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk3368";
  12
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &uart_bt;
  20                 serial1 = &uart_bb;
  21                 serial2 = &uart_dbg;
  22                 serial3 = &uart_gps;
  23                 serial4 = &uart_exp;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &spi0;
  31                 spi1 = &spi1;
  32                 spi2 = &spi2;
  33                 lcdc = &lcdc;
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 big0: cpu@100 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a53", "arm,armv8";
  43                         reg = <0x0 0x100>;
  44                         enable-method = "psci";
  45                 };
  46                 big1: cpu@101 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a53", "arm,armv8";
  49                         reg = <0x0 0x101>;
  50                         enable-method = "psci";
  51                 };
  52                 big2: cpu@102 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a53", "arm,armv8";
  55                         reg = <0x0 0x102>;
  56                         enable-method = "psci";
  57                 };
  58                 big3: cpu@103 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53", "arm,armv8";
  61                         reg = <0x0 0x103>;
  62                         enable-method = "psci";
  63                 };
  64                 little0: cpu@0 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a53", "arm,armv8";
  67                         reg = <0x0 0x0>;
  68                         enable-method = "psci";
  69                 };
  70                 little1: cpu@1 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a53", "arm,armv8";
  73                         reg = <0x0 0x1>;
  74                         enable-method = "psci";
  75                 };
  76                 little2: cpu@2 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a53", "arm,armv8";
  79                         reg = <0x0 0x2>;
  80                         enable-method = "psci";
  81                 };
  82                 little3: cpu@3 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53", "arm,armv8";
  85                         reg = <0x0 0x3>;
  86                         enable-method = "psci";
  87                 };
  88
  89                 cpu-map {
  90                         cluster0 {
  91                                 core0 {
  92                                         cpu = <&big0>;
  93                                 };
  94                                 core1 {
  95                                         cpu = <&big1>;
  96                                 };
  97                                 core2 {
  98                                         cpu = <&big2>;
  99                                 };
 100                                 core3 {
 101                                         cpu = <&big3>;
 102                                 };
 103                         };
 104                         cluster1 {
 105                                 core0 {
 106                                         cpu = <&little0>;
 107                                 };
 108                                 core1 {
 109                                         cpu = <&little1>;
 110                                 };
 111                                 core2 {
 112                                         cpu = <&little2>;
 113                                 };
 114                                 core3 {
 115                                         cpu = <&little3>;
 116                                 };
 117                         };
 118                 };
 119         };
 120
 121         psci {
 122                 compatible = "arm,psci";
 123                 method = "smc";
 124                 cpu_on = <0xC4000003>;
 125         };
 126
 127         gic: interrupt-controller@ffb70000 {
 128                 compatible = "arm,cortex-a15-gic";
 129                 #interrupt-cells = <3>;
 130                 #address-cells = <0>;
 131                 interrupt-controller;
 132                 reg = <0x0 0xffb71000 0 0x1000>,
 133                       <0x0 0xffb72000 0 0x1000>;
 134         };
 135
 136         pmu_grf: syscon@ff738000 {
 137                 compatible = "rockchip,rk3368-pmu-grf", "rockchip,pmu-grf", "syscon";
 138                 reg = <0x0 0xff738000 0x0 0x100>;
 139         };
 140
 141         sgrf: syscon@ff740000 {
 142                 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
 143                 reg = <0x0 0xff740000 0x0 0x1000>;
 144
 145         };
 146
 147         cru: syscon@ff760000 {
 148                 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
 149                 reg = <0x0 0xff760000 0x0 0x1000>;
 150         };
 151
 152         grf: syscon@ff770000 {
 153                 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
 154                 reg = <0x0 0xff770000 0x0 0x1000>;
 155         };
 156
 157         arm-pmu {
 158                 compatible = "arm,armv8-pmuv3";
 159                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 160                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 161                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 162                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 163                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 164                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 167         };
 168
 169         cpu_axi_bus: cpu_axi_bus {
 170                 compatible = "rockchip,cpu_axi_bus";
 171                 #address-cells = <2>;
 172                 #size-cells = <2>;
 173                 ranges;
 174
 175                 qos {
 176                         #address-cells = <2>;
 177                         #size-cells = <2>;
 178                         ranges;
 179
 180                         dmac {
 181                                 reg = <0x0 0xffa80000 0x0 0x20>;
 182                         };
 183                         crypto {
 184                                 reg = <0x0 0xffa80080 0x0 0x20>;
 185                         };
 186                         bus_cpup {
 187                                 reg = <0x0 0xffa90000 0x0 0x20>;
 188                         };
 189                         cci_r {
 190                                 reg = <0x0 0xffaa0000 0x0 0x20>;
 191                         };
 192                         cci_w {
 193                                 reg = <0x0 0xffaa0080 0x0 0x20>;
 194                         };
 195                         peri {
 196                                 reg = <0x0 0xffab0000 0x0 0x20>;
 197                         };
 198                         iep {
 199                                 reg = <0x0 0xffad0000 0x0 0x20>;
 200                         };
 201                         isp_r0 {
 202                                 reg = <0x0 0xffad0080 0x0 0x20>;
 203                         };
 204                         isp_r1 {
 205                                 reg = <0x0 0xffad0100 0x0 0x20>;
 206                         };
 207                         isp_w0 {
 208                                 reg = <0x0 0xffad0180 0x0 0x20>;
 209                                 rockchip,priority = <2 2>;
 210                         };
 211                         isp_w1 {
 212                                 reg = <0x0 0xffad0200 0x0 0x20>;
 213                                 rockchip,priority = <2 2>;
 214                         };
 215                         vip {
 216                                 reg = <0x0 0xffad0280 0x0 0x20>;
 217                         };
 218                         vop {
 219                                 reg = <0x0 0xffad0300 0x0 0x20>;
 220                                 rockchip,priority = <2 2>;
 221                         };
 222                         rga_r {
 223                                 reg = <0x0 0xffad0380 0x0 0x20>;
 224                         };
 225                         rga_w {
 226                                 reg = <0x0 0xffad0400 0x0 0x20>;
 227                         };
 228                         hevc_r {
 229                                 reg = <0x0 0xffae0000 0x0 0x20>;
 230                         };
 231                         vpu_r {
 232                                 reg = <0x0 0xffae0080 0x0 0x20>;
 233                         };
 234                         vpu_w {
 235                                 reg = <0x0 0xffae0100 0x0 0x20>;
 236                         };
 237                 };
 238
 239                 msch {
 240                         #address-cells = <2>;
 241                         #size-cells = <2>;
 242                         ranges;
 243
 244                         msch {
 245                                 reg = <0x0 0xffac0000 0x0 0x3c>;
 246                                 rockchip,read-latency = <0x34>;
 247                         };
 248                 };
 249         };
 250
 251         timer {
 252                 compatible = "arm,armv8-timer";
 253                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 254                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 255                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 256                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 257                 clock-frequency = <24000000>;
 258         };
 259
 260         timer@ff810000 {
 261                 compatible = "rockchip,timer";
 262                 reg = <0x0 0xff810000 0x0 0x20>;
 263                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 264                 rockchip,broadcast = <1>;
 265         };
 266
 267         sram: sram@ff8c0000 {
 268                 compatible = "mmio-sram";
 269                 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
 270                 map-exec;
 271         };
 272
 273         watchdog: wdt@ff800000 {
 274                 compatible = "rockchip,watch dog";
 275                 reg = <0x0 0xff800000 0x0 0x100>;
 276                 clocks = <&pclk_alive_pre>;
 277                 clock-names = "pclk_wdt";
 278                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 279                 rockchip,irq = <1>;
 280                 rockchip,timeout = <60>;
 281                 rockchip,atboot = <1>;
 282                 rockchip,debug = <0>;
 283                 status = "disabled";
 284         };
 285
 286         amba {
 287                 #address-cells = <2>;
 288                 #size-cells = <2>;
 289                 compatible = "arm,amba-bus";
 290                 interrupt-parent = <&gic>;
 291                 ranges;
 292
 293                 pdma0: pdma@ff600000 {
 294                         compatible = "arm,pl330", "arm,primecell";
 295                         reg = <0x0 0xff600000 0x0 0x4000>;
 296                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 297                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 298                         #dma-cells = <1>;
 299                 };
 300
 301                 pdma1: pdma@ff250000 {
 302                         compatible = "arm,pl330", "arm,primecell";
 303                         reg = <0x0 0xff250000 0x0 0x4000>;
 304                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 305                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 306                         #dma-cells = <1>;
 307                 };
 308         };
 309
 310         reset: reset@ff760300{
 311                 compatible = "rockchip,reset";
 312                 reg = <0x0 0xff760300 0x0 0x38>;
 313                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 314                 #reset-cells = <1>;
 315         };
 316
 317         nandc0: nandc@ff400000 {
 318                 compatible = "rockchip,rk-nandc";
 319                 reg = <0x0 0xff400000 0x0 0x4000>;
 320                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 321                 nandc_id = <0>;
 322                 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
 323                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 324         };
 325
 326         nandc0reg: nandc0@ff400000 {
 327                 compatible = "rockchip,rk-nandc";
 328                 reg = <0x0 0xff400000 0x0 0x4000>;
 329         };
 330
 331         emmc: rksdmmc@ff0f0000 {
 332                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 333                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 334                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 335                 #address-cells = <1>;
 336                 #size-cells = <0>;
 337                 clocks = <&clk_emmc>, <&clk_gates21 2>;
 338                 clock-names = "clk_mmc", "hclk_mmc";
 339                 num-slots = <1>;
 340                 fifo-depth = <0x100>;
 341                 bus-width = <8>;
 342         };
 343
 344         sdmmc: rksdmmc@ff0c0000 {
 345                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 346                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 347                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 348                 #address-cells = <1>;
 349                 #size-cells = <0>;
 350                 pinctrl-names = "default", "idle";
 351                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 352                 pinctrl-1 = <&sdmmc_gpio>;
 353                 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 354                 clocks = <&clk_sdmmc0>, <&clk_gates21 0>;
 355                 clock-names = "clk_mmc", "hclk_mmc";
 356                 num-slots = <1>;
 357                 fifo-depth = <0x100>;
 358                 bus-width = <4>;
 359         };
 360
 361         sdio: rksdmmc@ff0d0000 {
 362                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 363                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 364                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 365                 #address-cells = <1>;
 366                 #size-cells = <0>;
 367                 pinctrl-names = "default","idle";
 368                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
 369                 pinctrl-1 = <&sdio0_gpio>;
 370                 clocks = <&clk_sdio0>, <&clk_gates21 1>;
 371                 clock-names = "clk_mmc", "hclk_mmc";
 372                 num-slots = <1>;
 373                 fifo-depth = <0x100>;
 374                 bus-width = <4>;
 375         };
 376
 377         spi0: spi@ff110000 {
 378                 compatible = "rockchip,rockchip-spi";
 379                 reg = <0x0 0xff110000 0x0 0x1000>;
 380                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 381                 #address-cells = <1>;
 382                 #size-cells = <0>;
 383                 pinctrl-names = "default";
 384                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 385                 rockchip,spi-src-clk = <0>;
 386                 num-cs = <2>;
 387                 clocks =<&clk_spi0>, <&clk_gates19 4>;
 388                 clock-names = "spi", "pclk_spi0";
 389                 //dmas = <&pdma1 11>, <&pdma1 12>;
 390                 //#dma-cells = <2>;
 391                 //dma-names = "tx", "rx";
 392                 status = "disabled";
 393         };
 394
 395         spi1: spi@ff120000 {
 396                 compatible = "rockchip,rockchip-spi";
 397                 reg = <0x0 0xff120000 0x0 0x1000>;
 398                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 399                 #address-cells = <1>;
 400                 #size-cells = <0>;
 401                 pinctrl-names = "default";
 402                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 403                 rockchip,spi-src-clk = <1>;
 404                 num-cs = <1>;
 405                 clocks = <&clk_spi1>, <&clk_gates19 5>;
 406                 clock-names = "spi", "pclk_spi1";
 407                 //dmas = <&pdma1 13>, <&pdma1 14>;
 408                 //#dma-cells = <2>;
 409                 //dma-names = "tx", "rx";
 410                 status = "disabled";
 411         };
 412
 413         spi2: spi@ff130000 {
 414                 compatible = "rockchip,rockchip-spi";
 415                 reg = <0x0 0xff130000 0x0 0x1000>;
 416                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 pinctrl-names = "default";
 420                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 421                 rockchip,spi-src-clk = <2>;
 422                 num-cs = <1>;
 423                 clocks = <&clk_spi2>, <&clk_gates19 6>;
 424                 clock-names = "spi", "pclk_spi2";
 425                 //dmas = <&pdma1 15>, <&pdma1 16>;
 426                 //#dma-cells = <2>;
 427                 //dma-names = "tx", "rx";
 428                 status = "disabled";
 429         };
 430
 431         uart_bt: serial@ff180000 {
 432                 compatible = "rockchip,serial";
 433                 reg = <0x0 0xff180000 0x0 0x100>;
 434                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 435                 clock-frequency = <24000000>;
 436                 clocks = <&clk_uart0>, <&clk_gates19 7>;
 437                 clock-names = "sclk_uart", "pclk_uart";
 438                 reg-shift = <2>;
 439                 reg-io-width = <4>;
 440                 //dmas = <&pdma1 1>, <&pdma1 2>;
 441                 //#dma-cells = <2>;
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 444                 status = "disabled";
 445         };
 446
 447         uart_bb: serial@ff190000 {
 448                 compatible = "rockchip,serial";
 449                 reg = <0x0 0xff190000 0x0 0x100>;
 450                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 451                 clock-frequency = <24000000>;
 452                 clocks = <&clk_uart1>, <&clk_gates19 8>;
 453                 clock-names = "sclk_uart", "pclk_uart";
 454                 reg-shift = <2>;
 455                 reg-io-width = <4>;
 456                 //dmas = <&pdma1 3>, <&pdma1 4>;
 457                 //#dma-cells = <2>;
 458                 pinctrl-names = "default";
 459                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 460                 status = "disabled";
 461         };
 462
 463         uart_dbg: serial@ff690000 {
 464                 compatible = "rockchip,serial";
 465                 reg = <0x0 0xff690000 0x0 0x100>;
 466                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 467                 clock-frequency = <24000000>;
 468                 clocks = <&clk_uart2>, <&clk_gates13 5>;
 469                 clock-names = "sclk_uart", "pclk_uart";
 470                 reg-shift = <2>;
 471                 reg-io-width = <4>;
 472                 //dmas = <&pdma0 4>, <&pdma0 5>;
 473                 //#dma-cells = <2>;
 474                 //pinctrl-names = "default";
 475                 //pinctrl-0 = <&uart2_xfer>;
 476                 status = "disabled";
 477         };
 478
 479         uart_gps: serial@ff1b0000 {
 480                 compatible = "rockchip,serial";
 481                 reg = <0x0 0xff1b0000 0x0 0x100>;
 482                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 483                 clock-frequency = <24000000>;
 484                 clocks = <&clk_uart3>, <&clk_gates19 9>;
 485                 clock-names = "sclk_uart", "pclk_uart";
 486                 current-speed = <115200>;
 487                 reg-shift = <2>;
 488                 reg-io-width = <4>;
 489                 //dmas = <&pdma1 7>, <&pdma1 8>;
 490                 //#dma-cells = <2>;
 491                 pinctrl-names = "default";
 492                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 493                 status = "disabled";
 494         };
 495
 496         uart_exp: serial@ff1c0000 {
 497                 compatible = "rockchip,serial";
 498                 reg = <0x0 0xff1c0000 0x0 0x100>;
 499                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 500                 clock-frequency = <24000000>;
 501                 clocks = <&clk_uart4>, <&clk_gates19 10>;
 502                 clock-names = "sclk_uart", "pclk_uart";
 503                 reg-shift = <2>;
 504                 reg-io-width = <4>;
 505                 //dmas = <&pdma1 9>, <&pdma1 10>;
 506                 //#dma-cells = <2>;
 507                 pinctrl-names = "default";
 508                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 509                 status = "disabled";
 510         };
 511
 512         rockchip_clocks_init: clocks-init{
 513                 compatible = "rockchip,clocks-init";
 514                 rockchip,clocks-init-parent =
 515                         <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
 516                         <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
 517                         <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
 518                         <&clk_cs &clk_gpll>;
 519                 rockchip,clocks-init-rate =
 520                         <&clk_gpll 576000000>,          <&clk_core_b 792000000>,
 521                         <&clk_core_l 600000000>,        <&clk_cpll 400000000>,
 522                         /*<&clk_npll 500000000>,*/      <&aclk_bus 300000000>,
 523                         <&hclk_bus 150000000>,          <&pclk_bus 75000000>,
 524                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 525                         <&hclk_peri 150000000>,         <&pclk_peri 75000000>,
 526                         <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
 527                         <&clk_cs 300000000>,            <&clkin_trace 300000000>,
 528                         <&aclk_cci 600000000>,          <&clk_mac 50000000>,
 529                         <&aclk_vio0 400000000>,         <&hclk_vio 100000000>,
 530                         <&aclk_rga_pre 400000000>,      <&clk_rga 400000000>,
 531                         <&clk_isp 400000000>,           <&clk_edp 200000000>,
 532                         <&clk_gpu_core 400000000>,      <&aclk_gpu_mem 400000000>,
 533                         <&aclk_gpu_cfg 400000000>,      <&aclk_vepu 400000000>,
 534                         <&aclk_vdpu 400000000>,         <&clk_hevc_core 300000000>,
 535                         <&clk_hevc_cabac 300000000>;
 536 /*
 537                 rockchip,clocks-uboot-has-init =
 538                         <&aclk_vio0>;
 539 */
 540         };
 541
 542         rockchip_clocks_enable: clocks-enable {
 543                 compatible = "rockchip,clocks-enable";
 544                 clocks =
 545                         /*PLL*/
 546                         <&clk_apllb>,
 547                         <&clk_aplll>,
 548                         <&clk_dpll>,
 549                         <&clk_gpll>,
 550                         <&clk_cpll>,
 551
 552                         /*PD_CORE*/
 553                         <&clk_cs>,
 554                         <&clkin_trace>,
 555
 556                         /*PD_BUS*/
 557                         <&aclk_bus>,
 558                         <&hclk_bus>,
 559                         <&pclk_bus>,
 560                         <&clk_gates12 12>,/*aclk_strc_sys*/
 561                         <&clk_gates12 6>,/*aclk_intmem1*/
 562                         <&clk_gates12 5>,/*aclk_intmem0*/
 563                         <&clk_gates12 4>,/*aclk_intmem*/
 564                         <&clk_gates13 9>,/*aclk_gic400*/
 565
 566                         /*PD_ALIVE*/
 567                         <&clk_gates22 13>,/*pclk_timer1*/
 568                         <&clk_gates22 12>,/*pclk_timer0*/
 569                         <&clk_gates22 9>,/*pclk_alive_niu*/
 570                         <&clk_gates22 8>,/*pclk_grf*/
 571
 572                         /*PD_PMU*/
 573                         <&clk_gates23 5>,/*pclk_pmugrf*/
 574                         <&clk_gates23 3>,/*pclk_sgrf*/
 575                         <&clk_gates23 2>,/*pclk_pmu_noc*/
 576                         <&clk_gates23 1>,/*pclk_intmem1*/
 577                         <&clk_gates23 0>,/*pclk_pmu*/
 578
 579                         /*PD_PERI*/
 580                         <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
 581                         <&clk_gates20 8>,/*aclk_peri_niu*/
 582                         <&clk_gates21 4>,/*aclk_peri_mmu*/
 583                         <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
 584                         <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
 585                         <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
 586         };
 587
 588         /* I2C_PMU */
 589         i2c0: i2c@ff650000 {
 590                 compatible = "rockchip,rk30-i2c";
 591                 reg = <0x0 0xff650000 0x0 0x1000>;
 592                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 593                 #address-cells = <1>;
 594                 #size-cells = <0>;
 595                 pinctrl-names = "default", "gpio";
 596                 pinctrl-0 = <&i2c0_xfer>;
 597                 pinctrl-1 = <&i2c0_gpio>;
 598                 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
 599                 clocks = <&clk_gates12 2>;
 600                 rockchip,check-idle = <1>;
 601                 status = "disabled";
 602         };
 603
 604         /* I2C_AUDIO */
 605         i2c1: i2c@ff660000 {
 606                 compatible = "rockchip,rk30-i2c";
 607                 reg = <0x0 0xff660000 0x0 0x1000>;
 608                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 609                 #address-cells = <1>;
 610                 #size-cells = <0>;
 611                 pinctrl-names = "default", "gpio";
 612                 pinctrl-0 = <&i2c1_xfer>;
 613                 pinctrl-1 = <&i2c1_gpio>;
 614                 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
 615                 clocks = <&clk_gates12 3>;
 616                 rockchip,check-idle = <1>;
 617                 status = "disabled";
 618         };
 619
 620         /* I2C_SENSOR */
 621         i2c2: i2c@ff140000 {
 622                 compatible = "rockchip,rk30-i2c";
 623                 reg = <0x0 0xff140000 0x0 0x1000>;
 624                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 625                 #address-cells = <1>;
 626                 #size-cells = <0>;
 627                 pinctrl-names = "default", "gpio";
 628                 pinctrl-0 = <&i2c2_xfer>;
 629                 pinctrl-1 = <&i2c2_gpio>;
 630                 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 631                 clocks = <&clk_gates19 11>;
 632                 rockchip,check-idle = <1>;
 633                 status = "disabled";
 634         };
 635
 636         /* I2C_CAM */
 637         i2c3: i2c@ff150000 {
 638                 compatible = "rockchip,rk30-i2c";
 639                 reg = <0x0 0xff150000 0x0 0x1000>;
 640                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 641                 #address-cells = <1>;
 642                 #size-cells = <0>;
 643                 pinctrl-names = "default", "gpio";
 644                 pinctrl-0 = <&i2c3_xfer>;
 645                 pinctrl-1 = <&i2c3_gpio>;
 646                 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
 647                 clocks = <&clk_gates19 12>;
 648                 rockchip,check-idle = <1>;
 649                 status = "disabled";
 650         };
 651
 652         /* I2C_TP */
 653         i2c4: i2c@ff160000 {
 654                 compatible = "rockchip,rk30-i2c";
 655                 reg = <0x0 0xff160000 0x0 0x1000>;
 656                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 657                 #address-cells = <1>;
 658                 #size-cells = <0>;
 659                 pinctrl-names = "default", "gpio";
 660                 pinctrl-0 = <&i2c4_xfer>;
 661                 pinctrl-1 = <&i2c4_gpio>;
 662                 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
 663                 clocks = <&clk_gates19 13>;
 664                 rockchip,check-idle = <1>;
 665                 status = "disabled";
 666         };
 667
 668         /* I2C_HDMI */
 669         i2c5: i2c@ff170000 {
 670                 compatible = "rockchip,rk30-i2c";
 671                 reg = <0x0 0xff170000 0x0 0x1000>;
 672                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 673                 #address-cells = <1>;
 674                 #size-cells = <0>;
 675                 pinctrl-names = "default", "gpio";
 676                 pinctrl-0 = <&i2c5_xfer>;
 677                 pinctrl-1 = <&i2c5_gpio>;
 678                 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
 679                 clocks = <&clk_gates19 14>;
 680                 rockchip,check-idle = <1>;
 681                 status = "disabled";
 682         };
 683
 684         fb: fb {
 685                 compatible = "rockchip,rk-fb";
 686                 rockchip,disp-mode = <NO_DUAL>;
 687         };
 688
 689
 690         rk_screen: rk_screen {
 691                 compatible = "rockchip,screen";
 692         };
 693
 694         dsihost0: mipi@ff960000{
 695                 compatible = "rockchip,rk33x-dsi";
 696                 rockchip,prop = <0>;
 697                 reg = <0xff960000 0x4000>, <0xff968000 0x4000>;
 698                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 699                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 700                 clocks = <&clk_gates4 14>, <&clk_gates17 3>, <&clk_gates22 10>;
 701                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi_host", "pclk_mipi_dsi_phy";
 702                 status = "okay";
 703         };
 704
 705         lvds: lvds@ff968000 {
 706                 compatible = "rockchip,rk3368-lvds";
 707                 rockchip,grf = <&grf>;
 708                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600b0 0x0 0x01>;
 709                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 710                 clocks = <&clk_gates22 10>, <&clk_gates17 3>;
 711                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 712                 status = "disabled";
 713         };
 714
 715         edp: edp@ff970000 {
 716                 compatible = "rockchip,rk32-edp";
 717                 reg = <0x0 0xff970000 0x0 0x4000>;
 718                 rockchip,grf = <&grf>;
 719                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 720                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
 721                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 722                 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
 723                 reset-names = "edp_24m", "edp_apb";
 724         };
 725
 726         hdmi: hdmi@ff980000 {
 727                 compatible = "rockchip,rk3368-hdmi";
 728                 reg = <0x0 0xff980000 0x0 0x20000>;
 729                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 730                 pinctrl-names = "default", "gpio";
 731                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 732                 pinctrl-1 = <&i2c5_gpio>;
 733                 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
 734                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 735                 status = "disabled";
 736         };
 737
 738         hdmi_hdcp2: hdmi_hdcp2@ff978000 {
 739                 compatible = "rockchip,rk3368-hdmi-hdcp2";
 740                 reg = <0x0 0xff978000 0x0 0x2000>;
 741                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 742                 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
 743                 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
 744                 status = "disabled";
 745         };
 746
 747         lcdc: lcdc@ff930000 {
 748                  compatible = "rockchip,rk3368-lcdc";
 749                  rockchip,grf = <&grf>;
 750                  rockchip,pmu = <&pmu_grf>;
 751                  rockchip,prop = <PRMRY>;
 752                  rockchip,pwr18 = <0>;
 753                  rockchip,iommu-enabled = <0>;
 754                  reg = <0x0 0xff930000 0x0 0x10000>;
 755                  interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 756                 /*pinctrl-names = "default", "gpio";
 757                  *pinctrl-0 = <&lcdc_lcdc>;
 758                  *pinctrl-1 = <&lcdc_gpio>;
 759                  */
 760                  status = "disabled";
 761                  clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
 762                  clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
 763         };
 764
 765         adc: adc@ff100000 {
 766                 compatible = "rockchip,saradc";
 767                 reg = <0x0 0xff100000 0x0 0x100>;
 768                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 769                 #io-channel-cells = <1>;
 770                 io-channel-ranges;
 771                 rockchip,adc-vref = <1800>;
 772                 clock-frequency = <1000000>;
 773                 clocks = <&clk_saradc>, <&clk_gates19 15>;
 774                 clock-names = "saradc", "pclk_saradc";
 775                 status = "disabled";
 776         };
 777
 778         rga@ff920000 {
 779                 compatible = "rockchip,rk3368-rga2";
 780                 reg = <0x0 0xff920000 0x0 0x1000>;
 781                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 782                 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
 783                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 784         };
 785
 786         i2s0: i2s0@ff898000 {
 787                 compatible = "rockchip-i2s";
 788                 reg = <0x0 0xff898000 0x0 0x1000>;
 789                 i2s-id = <0>;
 790                 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 791                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 792                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 793                 dmas = <&pdma0 0>, <&pdma0 1>;
 794                 #dma-cells = <2>;
 795                 dma-names = "tx", "rx";
 796                 pinctrl-names = "default", "sleep";
 797                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 798                 pinctrl-1 = <&i2s_gpio>;
 799         };
 800
 801         i2s1: i2s1@ff890000 {
 802                 compatible = "rockchip-i2s";
 803                 reg = <0x0 0xff890000 0x0 0x1000>;
 804                 i2s-id = <1>;
 805                 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
 806                 clock-names = "i2s_clk", "i2s_hclk";
 807                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 808                 dmas = <&pdma0 6>, <&pdma0 7>;
 809                 #dma-cells = <2>;
 810                 dma-names = "tx", "rx";
 811         };
 812
 813         spdif: spdif@ff880000 {
 814                 compatible = "rockchip-spdif";
 815                 reg = <0x0 0xff880000 0x0 0x1000>;
 816                 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
 817                 clock-names = "spdif_mclk", "spdif_hclk";
 818                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 819                 dmas = <&pdma0 3>;
 820                 #dma-cells = <1>;
 821                 dma-names = "tx";
 822                 pinctrl-names = "default";
 823                 pinctrl-0 = <&spdif_tx>;
 824         };
 825
 826         pwm0: pwm@ff680000 {
 827                 compatible = "rockchip,rk-pwm";
 828                 reg = <0x0 0xff680000 0x0 0x10>;
 829                 #pwm-cells = <2>;
 830                 pinctrl-names = "default";
 831                 pinctrl-0 = <&pwm0_pin>;
 832                 clocks = <&clk_gates13 6>;
 833                 clock-names = "pclk_pwm";
 834                 status = "disabled";
 835         };
 836
 837         pwm1: pwm@ff680010 {
 838                 compatible = "rockchip,rk-pwm";
 839                 reg = <0x0 0xff680010 0x0 0x10>;
 840                 #pwm-cells = <2>;
 841                 pinctrl-names = "default";
 842                 pinctrl-0 = <&pwm1_pin>;
 843                 clocks = <&clk_gates13 6>;
 844                 clock-names = "pclk_pwm";
 845                 status = "disabled";
 846         };
 847
 848         pwm2: pwm@ff680020 {
 849                 compatible = "rockchip,rk-pwm";
 850                 reg = <0x0 0xff680020 0x0 0x10>;
 851                 #pwm-cells = <2>;
 852                 //pinctrl-names = "default";
 853                 //pinctrl-0 = <&pwm1_pin>;
 854                 clocks = <&clk_gates13 6>;
 855                 clock-names = "pclk_pwm";
 856                 status = "disabled";
 857         };
 858
 859         pwm3: pwm@ff680030 {
 860                 compatible = "rockchip,rk-pwm";
 861                 reg = <0x0 0xff680030 0x0 0x10>;
 862                 #pwm-cells = <2>;
 863                 pinctrl-names = "default";
 864                 pinctrl-0 = <&pwm3_pin>;
 865                 clocks = <&clk_gates13 6>;
 866                 clock-names = "pclk_pwm";
 867                 status = "disabled";
 868         };
 869
 870         voppwm: pwm@ff9301a0 {
 871                 compatible = "rockchip,vop-pwm";
 872                 reg = <0x0 0xff9301a0 0x0 0x10>;
 873                 #pwm-cells = <2>;
 874                 pinctrl-names = "default";
 875                 pinctrl-0 = <&vop_pwm_pin>;
 876                 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
 877                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 878                 status = "disabled";
 879         };
 880
 881         pvtm {
 882                 compatible = "rockchip,rk3368-pvtm";
 883                 rockchip,grf = <&grf>;
 884         };
 885
 886         cpufreq {
 887                 compatible = "rockchip,rk3368-cpufreq";
 888                 rockchip,grf = <&grf>;
 889         };
 890
 891         dvfs {
 892
 893                 vd_arm: vd_arm {
 894                         regulator_name = "vdd_arm";
 895                         suspend_volt = <1000>; //mV
 896                         pd_core {
 897                                 clk_core_b_dvfs_table: clk_core_b {
 898                                         operating-points = <
 899                                                 /* KHz    uV */
 900                                                 312000 1200000
 901                                                 504000 1200000
 902                                                 816000 1200000
 903                                                 1008000 1200000
 904                                                 >;
 905                                         status = "okay";
 906                                 };
 907                                 clk_core_l_dvfs_table: clk_core_l {
 908                                         operating-points = <
 909                                                 /* KHz    uV */
 910                                                 312000 1200000
 911                                                 504000 1200000
 912                                                 816000 1200000
 913                                                 1008000 1200000
 914                                                 >;
 915                                         status = "okay";
 916                                 };
 917                         };
 918                 };
 919
 920                 vd_logic: vd_logic {
 921                         regulator_name = "vdd_logic";
 922                         suspend_volt = <1000>; //mV
 923                         pd_ddr {
 924                                 clk_ddr_dvfs_table: clk_ddr {
 925                                         operating-points = <
 926                                                 /* KHz    uV */
 927                                                 200000 1200000
 928                                                 300000 1200000
 929                                                 400000 1200000
 930                                                 >;
 931                                         channel = <2>;
 932                                         status = "disabled";
 933                                 };
 934                         };
 935
 936                         pd_gpu {
 937                                 clk_gpu_dvfs_table: clk_gpu {
 938                                         operating-points = <
 939                                                 /* KHz    uV */
 940                                                 200000 1200000
 941                                                 300000 1200000
 942                                                 400000 1200000
 943                                                 >;
 944                                         channel = <1>;
 945                                         status = "okay";
 946                                         regu-mode-table = <
 947                                                 /*freq     mode*/
 948                                                 200000     4
 949                                                 0          3
 950                                         >;
 951                                         regu-mode-en = <0>;
 952                                 };
 953                         };
 954                 };
 955         };
 956
 957         ion {
 958                 compatible = "rockchip,ion";
 959                 #address-cells = <1>;
 960                 #size-cells = <0>;
 961
 962                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
 963                         compatible = "rockchip,ion-heap";
 964                         rockchip,ion_heap = <4>;
 965                         reg = <0x00000000 0x08000000>; /* 512MB */
 966                 };
 967                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
 968                         compatible = "rockchip,ion-heap";
 969                         rockchip,ion_heap = <0>;
 970                 };
 971         };
 972
 973         vpu: vpu_service {
 974                 compatible = "rockchip,vpu_sub";
 975                 iommu_enabled = <0>;
 976                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 977                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 978                 interrupt-names = "irq_enc", "irq_dec";
 979                 dev_mode = <0>;
 980                 name = "vpu_service";
 981         };
 982
 983         hevc: hevc_service {
 984                 compatible = "rockchip,hevc_sub";
 985                 iommu_enabled = <0>;
 986                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 987                 interrupts-names = "irq_dec";
 988                 dev_mode = <1>;
 989                 name = "hevc_service";
 990         };
 991
 992         vpu_combo: vpu_combo@ff9a0000 {
 993                 compatible = "rockchip,vpu_combo";
 994                 reg = <0x0 0xff9a0000 0x0 0x800>;
 995                 rockchip,grf = <&grf>;
 996                 subcnt = <2>;
 997                 rockchip,sub = <&vpu>, <&hevc>;
 998                 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
 999                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1000                 mode_bit = <12>;
1001                 mode_ctrl = <0x418>;
1002                 name = "vpu_combo";
1003                 status = "okay";
1004         };
1005
1006         iep: iep@ff900000 {
1007                 compatible = "rockchip,iep";
1008                 iommu_enabled = <0>;
1009                 reg = <0x0 0xff900000 0x0 0x800>;
1010                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1011                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1012                 clock-names = "aclk_iep", "hclk_iep";
1013                 status = "okay";
1014         };
1015
1016         gmac: eth@ff290000 {
1017                 compatible = "rockchip,rk3368-gmac";
1018                 reg = <0x0 0xff290000 0x0 0x10000>;
1019                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1020                 interrupt-names = "macirq";
1021
1022                 clocks = <&clk_mac>, <&clk_gates5 0>,
1023                          <&clk_gates5 1>, <&clk_gates5 2>,
1024                          <&clk_gates5 3>, <&clk_gates8 0>,
1025                          <&clk_gates8 1>;
1026                 clock-names = "clk_mac", "mac_clk_rx",
1027                               "mac_clk_tx", "clk_mac_ref",
1028                               "clk_mac_refout", "aclk_mac",
1029                               "pclk_mac";
1030
1031                 phy-mode = "rgmii";
1032                 pinctrl-names = "default";
1033                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1034         };
1035
1036         gpu {
1037                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1038                 reg = <0x0 0xffa30000 0x0 0x10000>;
1039                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1040                 interrupt-names = "GPU";
1041         };
1042
1043         iep_mmu {
1044                 dbgname = "iep";
1045                 compatible = "rockchip,iep_mmu";
1046                 reg = <0x0 0xff900800 0x0 0x100>;
1047                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1048                 interrupt-names = "iep_mmu";
1049         };
1050
1051         vip_mmu {
1052                 dbgname = "vip";
1053                 compatible = "rockchip,vip_mmu";
1054                 reg = <0x0 0xff950800 0x0 0x100>;
1055                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1056                 interrupt-names = "vip_mmu";
1057         };
1058
1059         vop_mmu {
1060                 dbgname = "vop";
1061                 compatible = "rockchip,vop_mmu";
1062                 reg = <0x0 0xff930300 0x0 0x100>;
1063                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1064                 interrupt-names = "vop_mmu";
1065         };
1066
1067         isp_mmu {
1068                 dbgname = "isp_mmu";
1069                 compatible = "rockchip,isp_mmu";
1070                 reg = <0x0 0xff914000 0x0 0x100>,
1071                 <0x0 0xff915000 0x0 0x100>;
1072                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1073                 interrupt-names = "isp_mmu";
1074         };
1075
1076         hdcp_mmu {
1077                 dbgname = "hdcp_mmu";
1078                 compatible = "rockchip,hdcp_mmu";
1079                 reg = <0x0 0xff940000 0x0 0x100>;
1080                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1081                 interrupt-names = "hdcp_mmu";
1082         };
1083
1084         hevc_mmu {
1085                 dbgname = "hevc";
1086                 compatible = "rockchip,hevc_mmu";
1087                 reg = <0x0 0xff9c0440 0x0 0x40>,                      /*need to fix*/
1088                           <0x0 0xff9c0480 0x0 0x40>;
1089                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;        /*need to fix*/
1090                 interrupt-names = "hevc_mmu";
1091         };
1092
1093         vpu_mmu {
1094                 dbgname = "vpu";
1095                 compatible = "rockchip,vpu_mmu";
1096                 reg = <0x0 0xff9a0800 0x0 0x100>;                    /*need to fix*/
1097                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;       /*need to fix*/
1098                 interrupt-names = "vpu_mmu";
1099         };
1100
1101         rockchip_suspend {
1102                 rockchip,ctrbits = <
1103                         (0
1104                          |RKPM_CTR_PWR_DMNS
1105                          |RKPM_CTR_GTCLKS
1106                          |RKPM_CTR_PLLS
1107                          |RKPM_CTR_GPIOS
1108                         /*
1109                          |RKPM_CTR_SYSCLK_DIV
1110                          |RKPM_CTR_IDLEAUTO_MD
1111                          |RKPM_CTR_ARMOFF_LPMD
1112                         */
1113                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1114                         )
1115                         >;
1116                 rockchip,pmic-suspend_gpios = <
1117                                  /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1118                         >;
1119                 rockchip,pmic-resume_gpios = <
1120                                 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1121                         >;
1122         };
1123
1124         isp: isp@ff910000{
1125                 compatible = "rockchip,isp";
1126                 reg = <0x0 0xff910000 0x0 0x10000>;
1127                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1128                 clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
1129                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
1130                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1131                 pinctrl-0 = <&cif_clkout>;
1132                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1133                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1134                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1135                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1136                 pinctrl-5 = <&cif_clkout>;
1137                 pinctrl-6 = <&cif_clkout &isp_prelight>;
1138                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1139                 pinctrl-8 = <&isp_flash_trigger>;
1140                 rockchip,isp,mipiphy = <2>;
1141                 rockchip,isp,cifphy = <1>;
1142                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1143                 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1144                 rockchip,isp,iommu_enable = <1>;
1145                 status = "okay";
1146         };
1147
1148         tsadc: tsadc@ff280000 {
1149                 compatible = "rockchip,tsadc";
1150                 reg = <0x0 0xff280000 0x0 0x100>;
1151                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1152                 #io-channel-cells = <1>;
1153                 io-channel-ranges;
1154                 clock-frequency = <10000>;
1155                 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1156                 clock-names = "tsadc", "pclk_tsadc";
1157                 pinctrl-names = "default", "tsadc_int";
1158                 pinctrl-0 = <&tsadc_gpio>;
1159                 pinctrl-1 = <&tsadc_int>;
1160                 tsadc-ht-temp = <120>;
1161                 tsadc-ht-reset-cru = <1>;
1162                 tsadc-ht-pull-gpio = <0>;
1163                 status = "disabled";
1164         };
1165
1166         tsp: tsp@FF8B0000 {
1167                 compatible = "rockchip,rk3368-tsp";
1168                 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1169                 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1170                 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1171                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1172                 interrupt-names = "irq_tsp";
1173                 // pinctrl-names = "default";
1174                 // pinctrl-0 = <&isp_hsadc>;
1175                 status = "okay";
1176         };
1177
1178         crypto: crypto@FF8A0000{
1179                 compatible = "rockchip,rk3368-crypto";
1180                 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1181                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1182                 interrupt-names = "irq_crypto";
1183                         clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1184                 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1185                 status = "okay";
1186         };
1187         dwc_control_usb: dwc-control-usb {
1188                 compatible = "rockchip,rk3368-dwc-control-usb";
1189                 rockchip,grf = <&grf>;
1190                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1191                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1192                 interrupt-names = "otg_id", "otg_bvalid",
1193                                   "otg_linestate", "host0_linestate";
1194                 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1195                 clock-names = "hclk_usb_peri", "usbphy_480m";
1196                 //resets = <&reset RK3128_RST_USBPOR>;
1197                 //reset-names = "usbphy_por";
1198                 usb_bc{
1199                         compatible = "inno,phy";
1200                         regbase = &dwc_control_usb;
1201                         rk_usb,bvalid     = <0x04b 23 1>;
1202                         rk_usb,iddig      = <0x04b 26 1>;
1203                         rk_usb,vdmsrcen   = <0x718 12 1>;
1204                         rk_usb,vdpsrcen   = <0x718 11 1>;
1205                         rk_usb,rdmpden    = <0x718 10 1>;
1206                         rk_usb,idpsrcen   = <0x718  9 1>;
1207                         rk_usb,idmsinken  = <0x718  8 1>;
1208                         rk_usb,idpsinken  = <0x718  7 1>;
1209                         rk_usb,dpattach   = <0x4b8 31 1>;
1210                         rk_usb,cpdet      = <0x4b8 30 1>;
1211                         rk_usb,dcpattach  = <0x4b8 29 1>;
1212                 };
1213         };
1214
1215         usb0: usb@ff580000 {
1216                 compatible = "rockchip,rk3368_usb20_otg";
1217                 reg = <0x0 0xff580000 0x0 0x40000>;
1218                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1219                 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1220                 clock-names = "clk_usbphy0", "hclk_otg";
1221                 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1222                                 <&reset RK3368_SRST_USBOTGC0>;
1223                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1224                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1225                 rockchip,usb-mode = <0>;
1226         };
1227
1228         usb_ehci: usb@ff500000 {
1229                 compatible = "generic-ehci";
1230                 reg = <0x0 0xff500000 0x0 0x20000>;
1231                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1232                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1233                 clock-names = "clk_usbphy0", "hclk_ehci";
1234                 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1235                 //              <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1236                 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1237         };
1238
1239         usb_ohci: usb@ff520000 {
1240                 compatible = "generic-ohci";
1241                 reg = <0x0 0xff520000 0x0 0x20000>;
1242                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1243                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1244                 clock-names =  "clk_usbphy0", "hclk_ohci";
1245         };
1246
1247         usb_hsic: usb@ff5c0000 {
1248                 compatible = "rockchip,rk3288_rk_hsic_host";
1249                 reg = <0x0 0xff5c0000 0x0 0x40000>;
1250                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1251 /*
1252                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1253                          <&hsicphy_12m>, <&usbphy_480m>,
1254                          <&otgphy1_480m>, <&otgphy2_480m>;
1255                 clock-names = "hsicphy_480m", "hclk_hsic",
1256                               "hsicphy_12m", "usbphy_480m",
1257                               "hsic_usbphy1", "hsic_usbphy2";
1258                 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1259                                 <&reset RK3288_SOFT_RST_HSICPHY>;
1260                 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1261 */
1262                 status = "disabled";
1263         };
1264
1265         pinctrl: pinctrl {
1266                 compatible = "rockchip,rk3368-pinctrl";
1267                 rockchip,grf = <&grf>;
1268                 rockchip,pmu = <&pmu_grf>;
1269                 #address-cells = <2>;
1270                 #size-cells = <2>;
1271                 ranges;
1272
1273                 gpio0: gpio0@ff750000 {
1274                         compatible = "rockchip,gpio-bank";
1275                         reg =   <0x0 0xff750000 0x0 0x100>;
1276                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1277                         clocks = <&clk_gates23 4>;
1278
1279                         gpio-controller;
1280                         #gpio-cells = <2>;
1281
1282                         interrupt-controller;
1283                         #interrupt-cells = <2>;
1284                 };
1285
1286                 gpio1: gpio1@ff780000 {
1287                         compatible = "rockchip,gpio-bank";
1288                         reg = <0x0 0xff780000 0x0 0x100>;
1289                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1290                         clocks = <&clk_gates22 1>;
1291
1292                         gpio-controller;
1293                         #gpio-cells = <2>;
1294
1295                         interrupt-controller;
1296                         #interrupt-cells = <2>;
1297                 };
1298
1299                 gpio2: gpio2@ff790000 {
1300                         compatible = "rockchip,gpio-bank";
1301                         reg = <0x0 0xff790000 0x0 0x100>;
1302                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1303                         clocks = <&clk_gates22 2>;
1304
1305                         gpio-controller;
1306                         #gpio-cells = <2>;
1307
1308                         interrupt-controller;
1309                         #interrupt-cells = <2>;
1310                 };
1311
1312                 gpio3: gpio3@ff7a0000 {
1313                         compatible = "rockchip,gpio-bank";
1314                         reg = <0x0 0xff7a0000 0x0 0x100>;
1315                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1316                         clocks = <&clk_gates22 3>;
1317
1318                         gpio-controller;
1319                         #gpio-cells = <2>;
1320
1321                         interrupt-controller;
1322                         #interrupt-cells = <2>;
1323                 };
1324
1325                 pcfg_pull_up: pcfg-pull-up {
1326                         bias-pull-up;
1327                 };
1328
1329                 pcfg_pull_down: pcfg-pull-down {
1330                         bias-pull-down;
1331                 };
1332
1333                 pcfg_pull_none: pcfg-pull-none {
1334                         bias-disable;
1335                 };
1336
1337                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1338                         drive-strength = <8>;
1339                 };
1340
1341                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1342                         bias-pull-up;
1343                         drive-strength = <8>;
1344                 };
1345
1346                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1347                         drive-strength = <4>;
1348                 };
1349
1350                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1351                         bias-pull-up;
1352                         drive-strength = <4>;
1353                 };
1354
1355                 pcfg_output_high: pcfg-output-high {
1356                         output-high;
1357                 };
1358
1359                 pcfg_output_low: pcfg-output-low {
1360                         output-low;
1361                 };
1362
1363                 i2c0 {
1364                         i2c0_xfer: i2c0-xfer {
1365                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1366                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1367                         };
1368                         i2c0_gpio: i2c0-gpio {
1369                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1370                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1371                         };
1372                 };
1373
1374                 i2c1 {
1375                         i2c1_xfer: i2c1-xfer {
1376                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1377                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1378                         };
1379                         i2c1_gpio: i2c1-gpio {
1380                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1381                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1382                         };
1383                 };
1384
1385                 i2c2 {
1386                         i2c2_xfer: i2c2-xfer {
1387                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1388                                                 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1389                         };
1390                         i2c2_gpio: i2c2-gpio {
1391                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1392                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1393             };
1394                 };
1395
1396                 i2c3 {
1397                         i2c3_xfer: i2c3-xfer {
1398                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1399                                                 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1400                         };
1401                         i2c3_gpio: i2c3-gpio {
1402                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1403                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1404                         };
1405                 };
1406
1407                 i2c4 {
1408                         i2c4_xfer: i2c4-xfer {
1409                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1410                                                 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1411                         };
1412                         i2c4_gpio: i2c4-gpio {
1413                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1414                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1415                         };
1416                 };
1417
1418                 i2c5 {
1419                         i2c5_xfer: i2c5-xfer {
1420                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1421                                                 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1422                         };
1423                         i2c5_gpio: i2c5-gpio {
1424                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1425                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1426                         };
1427                 };
1428
1429                 uart0 {
1430                         uart0_xfer: uart0-xfer {
1431                                 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1432                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1433                         };
1434
1435                         uart0_cts: uart0-cts {
1436                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1437                         };
1438
1439                         uart0_rts: uart0-rts {
1440                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1441                         };
1442
1443                         uart0_rts_gpio: uart0-rts-gpio {
1444                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1445                         };
1446                 };
1447
1448                 uart1 {
1449                         uart1_xfer: uart1-xfer {
1450                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1451                                                 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1452                         };
1453
1454                         uart1_cts: uart1-cts {
1455                                 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1456                         };
1457
1458                         uart1_rts: uart1-rts {
1459                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1460                         };
1461                 };
1462
1463                 uart2 {
1464                         uart2_xfer: uart2-xfer {
1465                                 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1466                                                 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1467                         };
1468                 };
1469
1470                 uart3 {
1471                         uart3_xfer: uart3-xfer {
1472                                 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1473                                                 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1474                         };
1475
1476                         uart3_cts: uart3-cts {
1477                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1478                         };
1479
1480                         uart3_rts: uart3-rts {
1481                                 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1482                         };
1483                 };
1484
1485                 uart4 {
1486                         uart4_xfer: uart4-xfer {
1487                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1488                                                 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1489                         };
1490
1491                         uart4_cts: uart4-cts {
1492                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1493                         };
1494
1495                         uart4_rts: uart4-rts {
1496                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1497                         };
1498                 };
1499
1500                 spi0 {
1501                         spi0_clk: spi0-clk {
1502                                 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1503                         };
1504                         spi0_cs0: spi0-cs0 {
1505                                 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1506                         };
1507                         spi0_tx: spi0-tx {
1508                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1509                         };
1510                         spi0_rx: spi0-rx {
1511                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1512                         };
1513                         spi0_cs1: spi0-cs1 {
1514                                 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1515                         };
1516                 };
1517
1518                 spi1 {
1519                         spi1_clk: spi1-clk {
1520                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1521                         };
1522                         spi1_cs0: spi1-cs0 {
1523                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1524                         };
1525                         spi1_rx: spi1-rx {
1526                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1527                         };
1528                         spi1_tx: spi1-tx {
1529                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1530                         };
1531                 };
1532
1533                 spi2 {
1534                         spi2_clk: spi2-clk {
1535                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1536                         };
1537                         spi2_cs0: spi2-cs0 {
1538                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1539                         };
1540                         spi2_rx: spi2-rx {
1541                                 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1542                         };
1543                         spi2_tx: spi2-tx {
1544                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1545                         };
1546                 };
1547
1548                 i2s {
1549                         i2s_mclk: i2s-mclk {
1550                                 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1551                         };
1552
1553                         i2s_sclk:i2s-sclk {
1554                                 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1555                         };
1556
1557                         i2s_lrckrx:i2s-lrckrx {
1558                                 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1559                         };
1560
1561                         i2s_lrcktx:i2s-lrcktx {
1562                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1563                         };
1564
1565                         i2s_sdi:i2s-sdi {
1566                                 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1567                         };
1568
1569                         i2s_sdo0:i2s-sdo0 {
1570                                 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1571                         };
1572
1573                         i2s_sdo1:i2s-sdo1 {
1574                                 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1575                         };
1576
1577                         i2s_sdo2:i2s-sdo2 {
1578                                 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1579                         };
1580
1581                         i2s_sdo3:i2s-sdo3 {
1582                                 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1583                         };
1584
1585                         i2s_gpio: i2s-gpio {
1586                                 rockchip,pins = <2 GPIO_C4  RK_FUNC_GPIO &pcfg_pull_none>,
1587                                                 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1588                                                 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1589                                                 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1590                                                 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1591                                                 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1592                                                 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1593                                                 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1594                                                 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1595                         };
1596                 };
1597
1598                 spdif {
1599                         spdif_tx: spdif-tx {
1600                                 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1601                         };
1602                 };
1603
1604                 sdmmc {
1605                         sdmmc_clk: sdmmc-clk {
1606                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1607                         };
1608
1609                         sdmmc_cmd: sdmmc-cmd {
1610                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1611                         };
1612
1613                         sdmmc_dectn: sdmmc-dectn {
1614                                 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1615                         };
1616
1617                         sdmmc_bus1: sdmmc-bus1 {
1618                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1619                         };
1620
1621                         sdmmc_bus4: sdmmc-bus4 {
1622                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1623                                                 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1624                                                 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1625                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1626                         };
1627
1628                         sdmmc_gpio: sdmmc-gpio {
1629                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1630                                                 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1631                                                 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1632                                                 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1633                                                 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1634                                                 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1635                                                 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1636                         };
1637                 };
1638
1639                 sdio0 {
1640                         sdio0_bus1: sdio0-bus1 {
1641                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1642                         };
1643
1644                         sdio0_bus4: sdio0-bus4 {
1645                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1646                                                 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1647                                                 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1648                                                 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1649                         };
1650
1651                         sdio0_cmd: sdio0-cmd {
1652                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1653                         };
1654
1655                         sdio0_clk: sdio0-clk {
1656                                 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1657                         };
1658
1659                         sdio0_dectn: sdio0-dectn {
1660                                 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1661                         };
1662
1663                         sdio0_wrprt: sdio0-wrprt {
1664                                 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1665                         };
1666
1667                         sdio0_pwren: sdio0-pwren {
1668                                 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1669                         };
1670
1671                         sdio0_bkpwr: sdio0-bkpwr {
1672                                 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1673                         };
1674
1675                         sdio0_int: sdio0-int {
1676                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1677                         };
1678
1679                         sdio0_gpio: sdio0-gpio {
1680                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1681                                                 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1682                                                 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1683                                                 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1684                                                 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1685                                                 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1686                                                 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1687                                                 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1688                                                 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1689                                                 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1690                                                 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1691                         };
1692                 };
1693
1694                 emmc {
1695                         emmc_clk: emmc-clk {
1696                                 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1697                         };
1698
1699                         emmc_cmd: emmc-cmd {
1700                                 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1701                         };
1702
1703                         emmc_pwren: emmc-pwren {
1704                                 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1705                         };
1706
1707                         emmc_rstnout: emmc_rstnout {
1708                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1709                         };
1710
1711                         emmc_bus1: emmc-bus1 {
1712                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1713                         };
1714
1715                         emmc_bus4: emmc-bus4 {
1716                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1717                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1718                                                 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1719                                                 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1720                         };
1721                 };
1722
1723                 pwm0 {
1724                         pwm0_pin: pwm0-pin {
1725                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1726                         };
1727
1728                         vop_pwm_pin:vop-pwm {
1729                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1730                         };
1731                 };
1732
1733                 pwm1 {
1734                         pwm1_pin: pwm1-pin {
1735                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1736                         };
1737                 };
1738
1739                 pwm3 {
1740                         pwm3_pin: pwm3-pin {
1741                                 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1742                         };
1743                 };
1744
1745                 lcdc {
1746                         lcdc_lcdc: lcdc-lcdc {
1747                                 rockchip,pins =
1748                                                 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1749                                                 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1750                                                 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1751                                                 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1752                                                 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1753                                                 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1754                                                 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1755                                                 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1756                                                 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1757                                                 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1758                                                 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1759                                                 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1760                                                 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1761                                                 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1762                                                 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1763                                                 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1764                                                 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1765                                                 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1766                         };
1767
1768                         lcdc_gpio: lcdc-gpio {
1769                                 rockchip,pins =
1770                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1771                                                 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1772                                                 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1773                                                 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1774                                                 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1775                                                 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1776                                                 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1777                                                 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1778                                                 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1779                                                 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1780                                                 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1781                                                 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1782                                                 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1783                                                 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1784                                                 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1785                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1786                                                 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1787                                                 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1788                         };
1789                 };
1790
1791                 isp {
1792                         cif_clkout: cif-clkout {
1793                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1794                         };
1795
1796                         isp_dvp_d2d9: isp-dvp-d2d9 {
1797                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1798                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1799                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1800                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1801                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1802                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1803                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1804                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1805                                                 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1806                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1807                                                 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1808                                                 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1809                         };
1810
1811                         isp_dvp_d0d1: isp-dvp-d0d1 {
1812                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1813                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1814                         };
1815
1816                         isp_dvp_d10d11:isp_d10d11       {
1817                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1818                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1819                         };
1820
1821                         isp_dvp_d0d7: isp-dvp-d0d7 {
1822                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1823                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1824                                                 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1825                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1826                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1827                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1828                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1829                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1830                         };
1831
1832                         isp_shutter: isp-shutter {
1833                                 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1834                                                 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1835                         };
1836
1837                         isp_flash_trigger: isp-flash-trigger {
1838                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1839                         };
1840
1841                         isp_prelight: isp-prelight {
1842                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1843                         };
1844
1845                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1846                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1847                         };
1848                 };
1849
1850                 gps {
1851                         gps_mag: gps-mag {
1852                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1853                         };
1854
1855                         gps_sig: gps-sig {
1856                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1857
1858                         };
1859
1860                         gps_rfclk: gps-rfclk {
1861                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1862                         };
1863                 };
1864
1865                 gmac {
1866                         mac_clk: mac-clk {
1867                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1868                         };
1869
1870                         mac_txpins: mac-txpins {
1871                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//TXD0
1872                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//TXD1
1873                                                 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//TXD2
1874                                                 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//TXD3
1875                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//TXEN
1876                                                 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>;//TXCLK
1877                         };
1878
1879                         mac_rxpins: mac-rxpins {
1880                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1881                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1882                                                 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1883                                                 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1884                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1885                                                 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//RXER
1886                                                 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1887                                                 <3 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;//COL
1888                         };
1889
1890                         mac_crs: mac-crs {
1891                                 rockchip,pins = <3 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>; //CRS
1892                         };
1893
1894                         mac_mdpins: mac-mdpins {
1895                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1896                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;//MDC
1897                         };
1898                 };
1899
1900                 tsadc_pin {
1901                         tsadc_int: tsadc-int {
1902                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
1903                         };
1904                         tsadc_gpio: tsadc-gpio {
1905                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
1906                         };
1907                 };
1908
1909                 hdmi_pin {
1910                         hdmi_cec: hdmi-cec {
1911                                 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1912                         };
1913                 };
1914
1915                 hdmi_i2c {
1916                         hdmii2c_xfer: hdmii2c-xfer {
1917                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
1918                                                 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1919                         };
1920                 };
1921         };
1922
1923         reboot {
1924                 compatible = "rockchip,rk3368-reboot";
1925                 rockchip,cru = <&cru>;
1926                 rockchip,pmugrf = <&pmugrf>;
1927         };
1928 };