1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include <dt-bindings/suspend/rockchip-pm.h>
3 #include <dt-bindings/pinctrl/rockchip.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/sensor-dev.h>
6 #include <dt-bindings/clock/rk_system_status.h>
8 #include "rk3368-clocks.dtsi"
11 compatible = "rockchip,rk3368";
13 rockchip,sram = <&sram>;
14 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a53", "arm,armv8";
44 enable-method = "psci";
48 compatible = "arm,cortex-a53", "arm,armv8";
50 enable-method = "psci";
54 compatible = "arm,cortex-a53", "arm,armv8";
56 enable-method = "psci";
60 compatible = "arm,cortex-a53", "arm,armv8";
62 enable-method = "psci";
66 compatible = "arm,cortex-a53", "arm,armv8";
68 enable-method = "psci";
72 compatible = "arm,cortex-a53", "arm,armv8";
74 enable-method = "psci";
78 compatible = "arm,cortex-a53", "arm,armv8";
80 enable-method = "psci";
84 compatible = "arm,cortex-a53", "arm,armv8";
86 enable-method = "psci";
122 compatible = "arm,psci";
124 cpu_on = <0xC4000003>;
127 gic: interrupt-controller@ffb70000 {
128 compatible = "arm,cortex-a15-gic";
129 #interrupt-cells = <3>;
130 #address-cells = <0>;
131 interrupt-controller;
132 reg = <0x0 0xffb71000 0 0x1000>,
133 <0x0 0xffb72000 0 0x1000>;
136 pmu: syscon@ff730000 {
137 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
138 reg = <0x0 0xff730000 0x0 0x1000>;
141 pmugrf: syscon@ff738000 {
142 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
143 reg = <0x0 0xff738000 0x0 0x1000>;
146 sgrf: syscon@ff740000 {
147 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
148 reg = <0x0 0xff740000 0x0 0x1000>;
152 cru: syscon@ff760000 {
153 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
154 reg = <0x0 0xff760000 0x0 0x1000>;
157 grf: syscon@ff770000 {
158 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
159 reg = <0x0 0xff770000 0x0 0x1000>;
163 compatible = "arm,armv8-pmuv3";
164 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
174 cpu_axi_bus: cpu_axi_bus {
175 compatible = "rockchip,cpu_axi_bus";
176 #address-cells = <2>;
181 #address-cells = <2>;
186 reg = <0x0 0xffa80000 0x0 0x20>;
189 reg = <0x0 0xffa80080 0x0 0x20>;
192 reg = <0x0 0xffa90000 0x0 0x20>;
195 reg = <0x0 0xffaa0000 0x0 0x20>;
198 reg = <0x0 0xffaa0080 0x0 0x20>;
201 reg = <0x0 0xffab0000 0x0 0x20>;
204 reg = <0x0 0xffad0000 0x0 0x20>;
207 reg = <0x0 0xffad0080 0x0 0x20>;
210 reg = <0x0 0xffad0100 0x0 0x20>;
213 reg = <0x0 0xffad0180 0x0 0x20>;
214 rockchip,priority = <2 2>;
217 reg = <0x0 0xffad0200 0x0 0x20>;
218 rockchip,priority = <2 2>;
221 reg = <0x0 0xffad0280 0x0 0x20>;
224 reg = <0x0 0xffad0300 0x0 0x20>;
225 rockchip,priority = <2 2>;
228 reg = <0x0 0xffad0380 0x0 0x20>;
231 reg = <0x0 0xffad0400 0x0 0x20>;
234 reg = <0x0 0xffae0000 0x0 0x20>;
237 reg = <0x0 0xffae0080 0x0 0x20>;
240 reg = <0x0 0xffae0100 0x0 0x20>;
245 #address-cells = <2>;
250 reg = <0x0 0xffac0000 0x0 0x3c>;
251 rockchip,read-latency = <0x34>;
257 compatible = "arm,armv8-timer";
258 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
259 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
260 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
261 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
262 clock-frequency = <24000000>;
266 compatible = "rockchip,timer";
267 reg = <0x0 0xff810000 0x0 0x20>;
268 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
269 rockchip,broadcast = <1>;
272 sram: sram@ff8c0000 {
273 compatible = "mmio-sram";
274 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
278 watchdog: wdt@ff800000 {
279 compatible = "rockchip,watch dog";
280 reg = <0x0 0xff800000 0x0 0x100>;
281 clocks = <&pclk_alive_pre>;
282 clock-names = "pclk_wdt";
283 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
285 rockchip,timeout = <60>;
286 rockchip,atboot = <1>;
287 rockchip,debug = <0>;
292 #address-cells = <2>;
294 compatible = "arm,amba-bus";
295 interrupt-parent = <&gic>;
298 pdma0: pdma@ff600000 {
299 compatible = "arm,pl330", "arm,primecell";
300 reg = <0x0 0xff600000 0x0 0x4000>;
301 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
306 pdma1: pdma@ff250000 {
307 compatible = "arm,pl330", "arm,primecell";
308 reg = <0x0 0xff250000 0x0 0x4000>;
309 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
315 reset: reset@ff760300{
316 compatible = "rockchip,reset";
317 reg = <0x0 0xff760300 0x0 0x38>;
318 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
322 nandc0: nandc@ff400000 {
323 compatible = "rockchip,rk-nandc";
324 reg = <0x0 0xff400000 0x0 0x4000>;
325 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
328 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
331 nandc0reg: nandc0@ff400000 {
332 compatible = "rockchip,rk-nandc";
333 reg = <0x0 0xff400000 0x0 0x4000>;
336 emmc: rksdmmc@ff0f0000 {
337 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
338 reg = <0x0 0xff0f0000 0x0 0x4000>;
339 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
340 #address-cells = <1>;
342 clocks = <&clk_emmc>, <&clk_gates21 2>;
343 clock-names = "clk_mmc", "hclk_mmc";
345 fifo-depth = <0x100>;
349 sdmmc: rksdmmc@ff0c0000 {
350 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
351 reg = <0x0 0xff0c0000 0x0 0x4000>;
352 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
353 #address-cells = <1>;
355 pinctrl-names = "default", "idle";
356 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
357 pinctrl-1 = <&sdmmc_gpio>;
358 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
359 clocks = <&clk_sdmmc0>, <&clk_gates21 0>;
360 clock-names = "clk_mmc", "hclk_mmc";
362 fifo-depth = <0x100>;
366 sdio: rksdmmc@ff0d0000 {
367 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
368 reg = <0x0 0xff0d0000 0x0 0x4000>;
369 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
370 #address-cells = <1>;
372 pinctrl-names = "default","idle";
373 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
374 pinctrl-1 = <&sdio0_gpio>;
375 clocks = <&clk_sdio0>, <&clk_gates21 1>;
376 clock-names = "clk_mmc", "hclk_mmc";
378 fifo-depth = <0x100>;
383 compatible = "rockchip,rockchip-spi";
384 reg = <0x0 0xff110000 0x0 0x1000>;
385 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
386 #address-cells = <1>;
388 pinctrl-names = "default";
389 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
390 rockchip,spi-src-clk = <0>;
392 clocks =<&clk_spi0>, <&clk_gates19 4>;
393 clock-names = "spi", "pclk_spi0";
394 //dmas = <&pdma1 11>, <&pdma1 12>;
396 //dma-names = "tx", "rx";
401 compatible = "rockchip,rockchip-spi";
402 reg = <0x0 0xff120000 0x0 0x1000>;
403 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
404 #address-cells = <1>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
408 rockchip,spi-src-clk = <1>;
410 clocks = <&clk_spi1>, <&clk_gates19 5>;
411 clock-names = "spi", "pclk_spi1";
412 //dmas = <&pdma1 13>, <&pdma1 14>;
414 //dma-names = "tx", "rx";
419 compatible = "rockchip,rockchip-spi";
420 reg = <0x0 0xff130000 0x0 0x1000>;
421 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
422 #address-cells = <1>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
426 rockchip,spi-src-clk = <2>;
428 clocks = <&clk_spi2>, <&clk_gates19 6>;
429 clock-names = "spi", "pclk_spi2";
430 //dmas = <&pdma1 15>, <&pdma1 16>;
432 //dma-names = "tx", "rx";
436 uart_bt: serial@ff180000 {
437 compatible = "rockchip,serial";
438 reg = <0x0 0xff180000 0x0 0x100>;
439 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
440 clock-frequency = <24000000>;
441 clocks = <&clk_uart0>, <&clk_gates19 7>;
442 clock-names = "sclk_uart", "pclk_uart";
445 //dmas = <&pdma1 1>, <&pdma1 2>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
452 uart_bb: serial@ff190000 {
453 compatible = "rockchip,serial";
454 reg = <0x0 0xff190000 0x0 0x100>;
455 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
456 clock-frequency = <24000000>;
457 clocks = <&clk_uart1>, <&clk_gates19 8>;
458 clock-names = "sclk_uart", "pclk_uart";
461 //dmas = <&pdma1 3>, <&pdma1 4>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
468 uart_dbg: serial@ff690000 {
469 compatible = "rockchip,serial";
470 reg = <0x0 0xff690000 0x0 0x100>;
471 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
472 clock-frequency = <24000000>;
473 clocks = <&clk_uart2>, <&clk_gates13 5>;
474 clock-names = "sclk_uart", "pclk_uart";
477 //dmas = <&pdma0 4>, <&pdma0 5>;
479 //pinctrl-names = "default";
480 //pinctrl-0 = <&uart2_xfer>;
484 uart_gps: serial@ff1b0000 {
485 compatible = "rockchip,serial";
486 reg = <0x0 0xff1b0000 0x0 0x100>;
487 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
488 clock-frequency = <24000000>;
489 clocks = <&clk_uart3>, <&clk_gates19 9>;
490 clock-names = "sclk_uart", "pclk_uart";
491 current-speed = <115200>;
494 //dmas = <&pdma1 7>, <&pdma1 8>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
501 uart_exp: serial@ff1c0000 {
502 compatible = "rockchip,serial";
503 reg = <0x0 0xff1c0000 0x0 0x100>;
504 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
505 clock-frequency = <24000000>;
506 clocks = <&clk_uart4>, <&clk_gates19 10>;
507 clock-names = "sclk_uart", "pclk_uart";
510 //dmas = <&pdma1 9>, <&pdma1 10>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
517 rockchip_clocks_init: clocks-init{
518 compatible = "rockchip,clocks-init";
519 rockchip,clocks-init-parent =
520 <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
521 <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
522 <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
524 rockchip,clocks-init-rate =
525 <&clk_gpll 576000000>, <&clk_core_b 792000000>,
526 <&clk_core_l 600000000>, <&clk_cpll 400000000>,
527 /*<&clk_npll 500000000>,*/ <&aclk_bus 300000000>,
528 <&hclk_bus 150000000>, <&pclk_bus 75000000>,
529 <&clk_crypto 150000000>, <&aclk_peri 300000000>,
530 <&hclk_peri 150000000>, <&pclk_peri 75000000>,
531 <&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>,
532 <&clk_cs 300000000>, <&clkin_trace 300000000>,
533 <&aclk_cci 600000000>, <&clk_mac 50000000>,
534 <&aclk_vio0 400000000>, <&hclk_vio 100000000>,
535 <&aclk_rga_pre 400000000>, <&clk_rga 400000000>,
536 <&clk_isp 400000000>, <&clk_edp 200000000>,
537 <&clk_gpu_core 400000000>, <&aclk_gpu_mem 400000000>,
538 <&aclk_gpu_cfg 400000000>, <&aclk_vepu 400000000>,
539 <&aclk_vdpu 400000000>, <&clk_hevc_core 300000000>,
540 <&clk_hevc_cabac 300000000>;
542 rockchip,clocks-uboot-has-init =
547 rockchip_clocks_enable: clocks-enable {
548 compatible = "rockchip,clocks-enable";
565 <&clk_gates12 12>,/*aclk_strc_sys*/
566 <&clk_gates12 6>,/*aclk_intmem1*/
567 <&clk_gates12 5>,/*aclk_intmem0*/
568 <&clk_gates12 4>,/*aclk_intmem*/
569 <&clk_gates13 9>,/*aclk_gic400*/
572 <&clk_gates22 13>,/*pclk_timer1*/
573 <&clk_gates22 12>,/*pclk_timer0*/
574 <&clk_gates22 9>,/*pclk_alive_niu*/
575 <&clk_gates22 8>,/*pclk_grf*/
578 <&clk_gates23 5>,/*pclk_pmugrf*/
579 <&clk_gates23 3>,/*pclk_sgrf*/
580 <&clk_gates23 2>,/*pclk_pmu_noc*/
581 <&clk_gates23 1>,/*pclk_intmem1*/
582 <&clk_gates23 0>,/*pclk_pmu*/
585 <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
586 <&clk_gates20 8>,/*aclk_peri_niu*/
587 <&clk_gates21 4>,/*aclk_peri_mmu*/
588 <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
589 <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
590 <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
595 compatible = "rockchip,rk30-i2c";
596 reg = <0x0 0xff650000 0x0 0x1000>;
597 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
598 #address-cells = <1>;
600 pinctrl-names = "default", "gpio";
601 pinctrl-0 = <&i2c0_xfer>;
602 pinctrl-1 = <&i2c0_gpio>;
603 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
604 clocks = <&clk_gates12 2>;
605 rockchip,check-idle = <1>;
611 compatible = "rockchip,rk30-i2c";
612 reg = <0x0 0xff660000 0x0 0x1000>;
613 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
614 #address-cells = <1>;
616 pinctrl-names = "default", "gpio";
617 pinctrl-0 = <&i2c1_xfer>;
618 pinctrl-1 = <&i2c1_gpio>;
619 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
620 clocks = <&clk_gates12 3>;
621 rockchip,check-idle = <1>;
627 compatible = "rockchip,rk30-i2c";
628 reg = <0x0 0xff140000 0x0 0x1000>;
629 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
630 #address-cells = <1>;
632 pinctrl-names = "default", "gpio";
633 pinctrl-0 = <&i2c2_xfer>;
634 pinctrl-1 = <&i2c2_gpio>;
635 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
636 clocks = <&clk_gates19 11>;
637 rockchip,check-idle = <1>;
643 compatible = "rockchip,rk30-i2c";
644 reg = <0x0 0xff150000 0x0 0x1000>;
645 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
646 #address-cells = <1>;
648 pinctrl-names = "default", "gpio";
649 pinctrl-0 = <&i2c3_xfer>;
650 pinctrl-1 = <&i2c3_gpio>;
651 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
652 clocks = <&clk_gates19 12>;
653 rockchip,check-idle = <1>;
659 compatible = "rockchip,rk30-i2c";
660 reg = <0x0 0xff160000 0x0 0x1000>;
661 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
662 #address-cells = <1>;
664 pinctrl-names = "default", "gpio";
665 pinctrl-0 = <&i2c4_xfer>;
666 pinctrl-1 = <&i2c4_gpio>;
667 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
668 clocks = <&clk_gates19 13>;
669 rockchip,check-idle = <1>;
675 compatible = "rockchip,rk30-i2c";
676 reg = <0x0 0xff170000 0x0 0x1000>;
677 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
678 #address-cells = <1>;
680 pinctrl-names = "default", "gpio";
681 pinctrl-0 = <&i2c5_xfer>;
682 pinctrl-1 = <&i2c5_gpio>;
683 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
684 clocks = <&clk_gates19 14>;
685 rockchip,check-idle = <1>;
690 compatible = "rockchip,rk-fb";
691 rockchip,disp-mode = <NO_DUAL>;
695 rk_screen: rk_screen {
696 compatible = "rockchip,screen";
699 dsihost0: mipi@ff960000{
700 compatible = "rockchip,rk3368-dsi";
702 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
703 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
704 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
705 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>;
706 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
710 lvds: lvds@ff968000 {
711 compatible = "rockchip,rk3368-lvds";
712 rockchip,grf = <&grf>;
713 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600b0 0x0 0x01>;
714 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
715 clocks = <&clk_gates22 10>, <&clk_gates17 3>;
716 clock-names = "pclk_lvds", "pclk_lvds_ctl";
721 compatible = "rockchip,rk32-edp";
722 reg = <0x0 0xff970000 0x0 0x4000>;
723 rockchip,grf = <&grf>;
724 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
726 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
727 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
728 reset-names = "edp_24m", "edp_apb";
731 hdmi: hdmi@ff980000 {
732 compatible = "rockchip,rk3368-hdmi";
733 reg = <0x0 0xff980000 0x0 0x20000>;
734 rockchip,grf = <&grf>;
735 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
736 pinctrl-names = "default", "gpio";
737 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
738 pinctrl-1 = <&i2c5_gpio>;
739 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
740 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
744 hdmi_hdcp2: hdmi_hdcp2@ff978000 {
745 compatible = "rockchip,rk3368-hdmi-hdcp2";
746 reg = <0x0 0xff978000 0x0 0x2000>;
747 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
749 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
753 lcdc: lcdc@ff930000 {
754 compatible = "rockchip,rk3368-lcdc";
755 rockchip,grf = <&grf>;
756 rockchip,pmugrf = <&pmugrf>;
757 rockchip,prop = <PRMRY>;
758 rockchip,pwr18 = <0>;
759 rockchip,iommu-enabled = <0>;
760 reg = <0x0 0xff930000 0x0 0x10000>;
761 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
762 /*pinctrl-names = "default", "gpio";
763 *pinctrl-0 = <&lcdc_lcdc>;
764 *pinctrl-1 = <&lcdc_gpio>;
767 clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
768 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
772 compatible = "rockchip,saradc";
773 reg = <0x0 0xff100000 0x0 0x100>;
774 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
775 #io-channel-cells = <1>;
777 rockchip,adc-vref = <1800>;
778 clock-frequency = <1000000>;
779 clocks = <&clk_saradc>, <&clk_gates19 15>;
780 clock-names = "saradc", "pclk_saradc";
785 compatible = "rockchip,rk3368-rga2";
786 reg = <0x0 0xff920000 0x0 0x1000>;
787 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
789 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
792 i2s0: i2s0@ff898000 {
793 compatible = "rockchip-i2s";
794 reg = <0x0 0xff898000 0x0 0x1000>;
796 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
797 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
798 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
799 dmas = <&pdma0 0>, <&pdma0 1>;
801 dma-names = "tx", "rx";
802 pinctrl-names = "default", "sleep";
803 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
804 pinctrl-1 = <&i2s_gpio>;
807 i2s1: i2s1@ff890000 {
808 compatible = "rockchip-i2s";
809 reg = <0x0 0xff890000 0x0 0x1000>;
811 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
812 clock-names = "i2s_clk", "i2s_hclk";
813 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
814 dmas = <&pdma0 6>, <&pdma0 7>;
816 dma-names = "tx", "rx";
819 spdif: spdif@ff880000 {
820 compatible = "rockchip-spdif";
821 reg = <0x0 0xff880000 0x0 0x1000>;
822 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
823 clock-names = "spdif_mclk", "spdif_hclk";
824 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
828 pinctrl-names = "default";
829 pinctrl-0 = <&spdif_tx>;
833 compatible = "rockchip,rk-pwm";
834 reg = <0x0 0xff680000 0x0 0x10>;
836 pinctrl-names = "default";
837 pinctrl-0 = <&pwm0_pin>;
838 clocks = <&clk_gates13 6>;
839 clock-names = "pclk_pwm";
844 compatible = "rockchip,rk-pwm";
845 reg = <0x0 0xff680010 0x0 0x10>;
847 pinctrl-names = "default";
848 pinctrl-0 = <&pwm1_pin>;
849 clocks = <&clk_gates13 6>;
850 clock-names = "pclk_pwm";
855 compatible = "rockchip,rk-pwm";
856 reg = <0x0 0xff680020 0x0 0x10>;
858 //pinctrl-names = "default";
859 //pinctrl-0 = <&pwm1_pin>;
860 clocks = <&clk_gates13 6>;
861 clock-names = "pclk_pwm";
866 compatible = "rockchip,rk-pwm";
867 reg = <0x0 0xff680030 0x0 0x10>;
869 pinctrl-names = "default";
870 pinctrl-0 = <&pwm3_pin>;
871 clocks = <&clk_gates13 6>;
872 clock-names = "pclk_pwm";
876 voppwm: pwm@ff9301a0 {
877 compatible = "rockchip,vop-pwm";
878 reg = <0x0 0xff9301a0 0x0 0x10>;
880 pinctrl-names = "default";
881 pinctrl-0 = <&vop_pwm_pin>;
882 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
883 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
888 compatible = "rockchip,rk3368-pvtm";
889 rockchip,grf = <&grf>;
893 compatible = "rockchip,rk3368-cpufreq";
894 rockchip,grf = <&grf>;
900 regulator_name = "vdd_arm";
901 suspend_volt = <1000>; //mV
903 clk_core_b_dvfs_table: clk_core_b {
913 clk_core_l_dvfs_table: clk_core_l {
927 regulator_name = "vdd_logic";
928 suspend_volt = <1000>; //mV
930 clk_ddr_dvfs_table: clk_ddr {
943 clk_gpu_dvfs_table: clk_gpu {
964 compatible = "rockchip,ion";
965 #address-cells = <1>;
968 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
969 compatible = "rockchip,ion-heap";
970 rockchip,ion_heap = <4>;
971 reg = <0x00000000 0x08000000>; /* 512MB */
973 rockchip,ion-heap@0 { /* VMALLOC HEAP */
974 compatible = "rockchip,ion-heap";
975 rockchip,ion_heap = <0>;
980 compatible = "rockchip,vpu_sub";
982 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
984 interrupt-names = "irq_enc", "irq_dec";
986 name = "vpu_service";
990 compatible = "rockchip,hevc_sub";
992 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
993 interrupts-names = "irq_dec";
995 name = "hevc_service";
998 vpu_combo: vpu_combo@ff9a0000 {
999 compatible = "rockchip,vpu_combo";
1000 reg = <0x0 0xff9a0000 0x0 0x800>;
1001 rockchip,grf = <&grf>;
1003 rockchip,sub = <&vpu>, <&hevc>;
1004 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1005 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1007 mode_ctrl = <0x418>;
1013 compatible = "rockchip,iep";
1014 iommu_enabled = <0>;
1015 reg = <0x0 0xff900000 0x0 0x800>;
1016 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1017 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1018 clock-names = "aclk_iep", "hclk_iep";
1022 gmac: eth@ff290000 {
1023 compatible = "rockchip,rk3368-gmac";
1024 reg = <0x0 0xff290000 0x0 0x10000>;
1025 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
1026 interrupt-names = "macirq";
1028 clocks = <&clk_mac>, <&clk_gates5 0>,
1029 <&clk_gates5 1>, <&clk_gates5 2>,
1030 <&clk_gates5 3>, <&clk_gates8 0>,
1032 clock-names = "clk_mac", "mac_clk_rx",
1033 "mac_clk_tx", "clk_mac_ref",
1034 "clk_mac_refout", "aclk_mac",
1038 pinctrl-names = "default";
1039 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1043 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1044 reg = <0x0 0xffa30000 0x0 0x10000>;
1045 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1046 interrupt-names = "GPU";
1051 compatible = "rockchip,iep_mmu";
1052 reg = <0x0 0xff900800 0x0 0x100>;
1053 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1054 interrupt-names = "iep_mmu";
1059 compatible = "rockchip,vip_mmu";
1060 reg = <0x0 0xff950800 0x0 0x100>;
1061 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1062 interrupt-names = "vip_mmu";
1067 compatible = "rockchip,vop_mmu";
1068 reg = <0x0 0xff930300 0x0 0x100>;
1069 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1070 interrupt-names = "vop_mmu";
1074 dbgname = "isp_mmu";
1075 compatible = "rockchip,isp_mmu";
1076 reg = <0x0 0xff914000 0x0 0x100>,
1077 <0x0 0xff915000 0x0 0x100>;
1078 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1079 interrupt-names = "isp_mmu";
1083 dbgname = "hdcp_mmu";
1084 compatible = "rockchip,hdcp_mmu";
1085 reg = <0x0 0xff940000 0x0 0x100>;
1086 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1087 interrupt-names = "hdcp_mmu";
1092 compatible = "rockchip,hevc_mmu";
1093 reg = <0x0 0xff9c0440 0x0 0x40>, /*need to fix*/
1094 <0x0 0xff9c0480 0x0 0x40>;
1095 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1096 interrupt-names = "hevc_mmu";
1101 compatible = "rockchip,vpu_mmu";
1102 reg = <0x0 0xff9a0800 0x0 0x100>; /*need to fix*/
1103 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1104 interrupt-names = "vpu_mmu";
1108 rockchip,ctrbits = <
1115 |RKPM_CTR_SYSCLK_DIV
1116 |RKPM_CTR_IDLEAUTO_MD
1117 |RKPM_CTR_ARMOFF_LPMD
1119 |RKPM_CTR_ARMOFF_LOGDP_LPMD
1122 rockchip,pmic-suspend_gpios = <
1123 /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1125 rockchip,pmic-resume_gpios = <
1126 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1131 compatible = "rockchip,isp";
1132 reg = <0x0 0xff910000 0x0 0x10000>;
1133 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1134 clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
1135 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
1136 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1137 pinctrl-0 = <&cif_clkout>;
1138 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1139 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1140 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1141 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1142 pinctrl-5 = <&cif_clkout>;
1143 pinctrl-6 = <&cif_clkout &isp_prelight>;
1144 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1145 pinctrl-8 = <&isp_flash_trigger>;
1146 rockchip,isp,mipiphy = <2>;
1147 rockchip,isp,cifphy = <1>;
1148 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1149 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1150 rockchip,isp,iommu_enable = <1>;
1154 tsadc: tsadc@ff280000 {
1155 compatible = "rockchip,tsadc";
1156 reg = <0x0 0xff280000 0x0 0x100>;
1157 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1158 #io-channel-cells = <1>;
1160 clock-frequency = <10000>;
1161 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1162 clock-names = "tsadc", "pclk_tsadc";
1163 pinctrl-names = "default", "tsadc_int";
1164 pinctrl-0 = <&tsadc_gpio>;
1165 pinctrl-1 = <&tsadc_int>;
1166 tsadc-ht-temp = <120>;
1167 tsadc-ht-reset-cru = <1>;
1168 tsadc-ht-pull-gpio = <0>;
1169 status = "disabled";
1173 compatible = "rockchip,rk3368-tsp";
1174 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1175 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1176 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1177 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1178 interrupt-names = "irq_tsp";
1179 // pinctrl-names = "default";
1180 // pinctrl-0 = <&isp_hsadc>;
1184 crypto: crypto@FF8A0000{
1185 compatible = "rockchip,rk3368-crypto";
1186 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1187 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1188 interrupt-names = "irq_crypto";
1189 clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1190 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1193 dwc_control_usb: dwc-control-usb {
1194 compatible = "rockchip,rk3368-dwc-control-usb";
1195 rockchip,grf = <&grf>;
1196 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1197 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1198 interrupt-names = "otg_id", "otg_bvalid",
1199 "otg_linestate", "host0_linestate";
1200 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1201 clock-names = "hclk_usb_peri", "usbphy_480m";
1202 //resets = <&reset RK3128_RST_USBPOR>;
1203 //reset-names = "usbphy_por";
1205 compatible = "inno,phy";
1206 regbase = &dwc_control_usb;
1207 rk_usb,bvalid = <0x04b 23 1>;
1208 rk_usb,iddig = <0x04b 26 1>;
1209 rk_usb,vdmsrcen = <0x718 12 1>;
1210 rk_usb,vdpsrcen = <0x718 11 1>;
1211 rk_usb,rdmpden = <0x718 10 1>;
1212 rk_usb,idpsrcen = <0x718 9 1>;
1213 rk_usb,idmsinken = <0x718 8 1>;
1214 rk_usb,idpsinken = <0x718 7 1>;
1215 rk_usb,dpattach = <0x4b8 31 1>;
1216 rk_usb,cpdet = <0x4b8 30 1>;
1217 rk_usb,dcpattach = <0x4b8 29 1>;
1221 usb0: usb@ff580000 {
1222 compatible = "rockchip,rk3368_usb20_otg";
1223 reg = <0x0 0xff580000 0x0 0x40000>;
1224 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1225 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1226 clock-names = "clk_usbphy0", "hclk_otg";
1227 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1228 <&reset RK3368_SRST_USBOTGC0>;
1229 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1230 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1231 rockchip,usb-mode = <0>;
1234 usb_ehci: usb@ff500000 {
1235 compatible = "generic-ehci";
1236 reg = <0x0 0xff500000 0x0 0x20000>;
1237 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1238 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1239 clock-names = "clk_usbphy0", "hclk_ehci";
1240 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1241 // <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1242 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1245 usb_ohci: usb@ff520000 {
1246 compatible = "generic-ohci";
1247 reg = <0x0 0xff520000 0x0 0x20000>;
1248 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1249 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1250 clock-names = "clk_usbphy0", "hclk_ohci";
1253 usb_hsic: usb@ff5c0000 {
1254 compatible = "rockchip,rk3288_rk_hsic_host";
1255 reg = <0x0 0xff5c0000 0x0 0x40000>;
1256 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1258 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1259 <&hsicphy_12m>, <&usbphy_480m>,
1260 <&otgphy1_480m>, <&otgphy2_480m>;
1261 clock-names = "hsicphy_480m", "hclk_hsic",
1262 "hsicphy_12m", "usbphy_480m",
1263 "hsic_usbphy1", "hsic_usbphy2";
1264 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1265 <&reset RK3288_SOFT_RST_HSICPHY>;
1266 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1268 status = "disabled";
1272 compatible = "rockchip,rk3368-pinctrl";
1273 rockchip,grf = <&grf>;
1274 rockchip,pmugrf = <&pmugrf>;
1275 #address-cells = <2>;
1279 gpio0: gpio0@ff750000 {
1280 compatible = "rockchip,gpio-bank";
1281 reg = <0x0 0xff750000 0x0 0x100>;
1282 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1283 clocks = <&clk_gates23 4>;
1288 interrupt-controller;
1289 #interrupt-cells = <2>;
1292 gpio1: gpio1@ff780000 {
1293 compatible = "rockchip,gpio-bank";
1294 reg = <0x0 0xff780000 0x0 0x100>;
1295 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1296 clocks = <&clk_gates22 1>;
1301 interrupt-controller;
1302 #interrupt-cells = <2>;
1305 gpio2: gpio2@ff790000 {
1306 compatible = "rockchip,gpio-bank";
1307 reg = <0x0 0xff790000 0x0 0x100>;
1308 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1309 clocks = <&clk_gates22 2>;
1314 interrupt-controller;
1315 #interrupt-cells = <2>;
1318 gpio3: gpio3@ff7a0000 {
1319 compatible = "rockchip,gpio-bank";
1320 reg = <0x0 0xff7a0000 0x0 0x100>;
1321 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1322 clocks = <&clk_gates22 3>;
1327 interrupt-controller;
1328 #interrupt-cells = <2>;
1331 pcfg_pull_up: pcfg-pull-up {
1335 pcfg_pull_down: pcfg-pull-down {
1339 pcfg_pull_none: pcfg-pull-none {
1343 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1344 drive-strength = <8>;
1347 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1349 drive-strength = <8>;
1352 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1353 drive-strength = <4>;
1356 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1358 drive-strength = <4>;
1361 pcfg_output_high: pcfg-output-high {
1365 pcfg_output_low: pcfg-output-low {
1370 i2c0_xfer: i2c0-xfer {
1371 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1372 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1374 i2c0_gpio: i2c0-gpio {
1375 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1376 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1381 i2c1_xfer: i2c1-xfer {
1382 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1383 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1385 i2c1_gpio: i2c1-gpio {
1386 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1387 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1392 i2c2_xfer: i2c2-xfer {
1393 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1394 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1396 i2c2_gpio: i2c2-gpio {
1397 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1398 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1403 i2c3_xfer: i2c3-xfer {
1404 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1405 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1407 i2c3_gpio: i2c3-gpio {
1408 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1409 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1414 i2c4_xfer: i2c4-xfer {
1415 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1416 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1418 i2c4_gpio: i2c4-gpio {
1419 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1420 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1425 i2c5_xfer: i2c5-xfer {
1426 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1427 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1429 i2c5_gpio: i2c5-gpio {
1430 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1431 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1436 uart0_xfer: uart0-xfer {
1437 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1438 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1441 uart0_cts: uart0-cts {
1442 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1445 uart0_rts: uart0-rts {
1446 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1449 uart0_rts_gpio: uart0-rts-gpio {
1450 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1455 uart1_xfer: uart1-xfer {
1456 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1457 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1460 uart1_cts: uart1-cts {
1461 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1464 uart1_rts: uart1-rts {
1465 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1470 uart2_xfer: uart2-xfer {
1471 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1472 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1477 uart3_xfer: uart3-xfer {
1478 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1479 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1482 uart3_cts: uart3-cts {
1483 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1486 uart3_rts: uart3-rts {
1487 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1492 uart4_xfer: uart4-xfer {
1493 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1494 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1497 uart4_cts: uart4-cts {
1498 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1501 uart4_rts: uart4-rts {
1502 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1507 spi0_clk: spi0-clk {
1508 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1510 spi0_cs0: spi0-cs0 {
1511 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1514 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1517 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1519 spi0_cs1: spi0-cs1 {
1520 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1525 spi1_clk: spi1-clk {
1526 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1528 spi1_cs0: spi1-cs0 {
1529 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1532 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1535 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1540 spi2_clk: spi2-clk {
1541 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1543 spi2_cs0: spi2-cs0 {
1544 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1547 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1550 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1555 i2s_mclk: i2s-mclk {
1556 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1560 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1563 i2s_lrckrx:i2s-lrckrx {
1564 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1567 i2s_lrcktx:i2s-lrcktx {
1568 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1572 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1576 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1580 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1584 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1588 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1591 i2s_gpio: i2s-gpio {
1592 rockchip,pins = <2 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,
1593 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1594 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1595 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1596 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1597 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1598 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1599 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1600 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1605 spdif_tx: spdif-tx {
1606 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1611 sdmmc_clk: sdmmc-clk {
1612 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1615 sdmmc_cmd: sdmmc-cmd {
1616 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1619 sdmmc_dectn: sdmmc-dectn {
1620 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1623 sdmmc_bus1: sdmmc-bus1 {
1624 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1627 sdmmc_bus4: sdmmc-bus4 {
1628 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1629 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1630 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1631 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1634 sdmmc_gpio: sdmmc-gpio {
1635 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1636 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1637 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1638 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1639 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1640 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1641 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1646 sdio0_bus1: sdio0-bus1 {
1647 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1650 sdio0_bus4: sdio0-bus4 {
1651 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1652 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1653 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1654 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1657 sdio0_cmd: sdio0-cmd {
1658 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1661 sdio0_clk: sdio0-clk {
1662 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1665 sdio0_dectn: sdio0-dectn {
1666 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1669 sdio0_wrprt: sdio0-wrprt {
1670 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1673 sdio0_pwren: sdio0-pwren {
1674 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1677 sdio0_bkpwr: sdio0-bkpwr {
1678 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1681 sdio0_int: sdio0-int {
1682 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1685 sdio0_gpio: sdio0-gpio {
1686 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1687 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1688 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1689 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1690 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1691 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1692 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1693 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1694 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1695 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1696 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1701 emmc_clk: emmc-clk {
1702 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1705 emmc_cmd: emmc-cmd {
1706 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1709 emmc_pwren: emmc-pwren {
1710 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1713 emmc_rstnout: emmc_rstnout {
1714 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1717 emmc_bus1: emmc-bus1 {
1718 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1721 emmc_bus4: emmc-bus4 {
1722 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1723 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1724 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1725 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1730 pwm0_pin: pwm0-pin {
1731 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1734 vop_pwm_pin:vop-pwm {
1735 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1740 pwm1_pin: pwm1-pin {
1741 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1746 pwm3_pin: pwm3-pin {
1747 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1752 lcdc_lcdc: lcdc-lcdc {
1754 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1755 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1756 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1757 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1758 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1759 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1760 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1761 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1762 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1763 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1764 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1765 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1766 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1767 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1768 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1769 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1770 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1771 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1774 lcdc_gpio: lcdc-gpio {
1776 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1777 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1778 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1779 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1780 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1781 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1782 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1783 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1784 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1785 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1786 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1787 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1788 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1789 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1790 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1791 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1792 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1793 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1798 cif_clkout: cif-clkout {
1799 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1802 isp_dvp_d2d9: isp-dvp-d2d9 {
1803 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1804 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1805 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1806 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1807 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1808 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1809 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1810 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1811 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1812 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1813 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1814 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1817 isp_dvp_d0d1: isp-dvp-d0d1 {
1818 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1819 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1822 isp_dvp_d10d11:isp_d10d11 {
1823 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1824 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1827 isp_dvp_d0d7: isp-dvp-d0d7 {
1828 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1829 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1830 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1831 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1832 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1833 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1834 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1835 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1838 isp_shutter: isp-shutter {
1839 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1840 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1843 isp_flash_trigger: isp-flash-trigger {
1844 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1847 isp_prelight: isp-prelight {
1848 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1851 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1852 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1858 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1862 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1866 gps_rfclk: gps-rfclk {
1867 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1873 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1876 mac_txpins: mac-txpins {
1877 rockchip,pins = <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//TXD0
1878 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//TXD1
1879 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//TXD2
1880 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//TXD3
1881 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//TXEN
1882 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>;//TXCLK
1885 mac_rxpins: mac-rxpins {
1886 rockchip,pins = <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1887 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1888 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1889 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1890 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1891 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//RXER
1892 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1893 <3 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;//COL
1897 rockchip,pins = <3 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>; //CRS
1900 mac_mdpins: mac-mdpins {
1901 rockchip,pins = <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1902 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;//MDC
1907 tsadc_int: tsadc-int {
1908 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
1910 tsadc_gpio: tsadc-gpio {
1911 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
1916 hdmi_cec: hdmi-cec {
1917 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1922 hdmii2c_xfer: hdmii2c-xfer {
1923 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
1924 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1930 compatible = "rockchip,rk3368-reboot";
1931 rockchip,cru = <&cru>;
1932 rockchip,pmugrf = <&pmugrf>;