arch/arm64/boot/dts/rk3368.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/sensor-dev.h>
   6 #include <dt-bindings/clock/rk_system_status.h>
   7
   8 #include "rk3368-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk3368";
  12
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &uart_bt;
  20                 serial1 = &uart_bb;
  21                 serial2 = &uart_dbg;
  22                 serial3 = &uart_gps;
  23                 serial4 = &uart_exp;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &spi0;
  31                 spi1 = &spi1;
  32                 spi2 = &spi2;
  33                 lcdc = &lcdc;
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 big0: cpu@100 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a53", "arm,armv8";
  43                         reg = <0x0 0x100>;
  44                         enable-method = "psci";
  45                 };
  46                 big1: cpu@101 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a53", "arm,armv8";
  49                         reg = <0x0 0x101>;
  50                         enable-method = "psci";
  51                 };
  52                 big2: cpu@102 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a53", "arm,armv8";
  55                         reg = <0x0 0x102>;
  56                         enable-method = "psci";
  57                 };
  58                 big3: cpu@103 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53", "arm,armv8";
  61                         reg = <0x0 0x103>;
  62                         enable-method = "psci";
  63                 };
  64                 little0: cpu@0 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a53", "arm,armv8";
  67                         reg = <0x0 0x0>;
  68                         enable-method = "psci";
  69                 };
  70                 little1: cpu@1 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a53", "arm,armv8";
  73                         reg = <0x0 0x1>;
  74                         enable-method = "psci";
  75                 };
  76                 little2: cpu@2 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a53", "arm,armv8";
  79                         reg = <0x0 0x2>;
  80                         enable-method = "psci";
  81                 };
  82                 little3: cpu@3 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53", "arm,armv8";
  85                         reg = <0x0 0x3>;
  86                         enable-method = "psci";
  87                 };
  88
  89                 cpu-map {
  90                         cluster0 {
  91                                 core0 {
  92                                         cpu = <&big0>;
  93                                 };
  94                                 core1 {
  95                                         cpu = <&big1>;
  96                                 };
  97                                 core2 {
  98                                         cpu = <&big2>;
  99                                 };
 100                                 core3 {
 101                                         cpu = <&big3>;
 102                                 };
 103                         };
 104                         cluster1 {
 105                                 core0 {
 106                                         cpu = <&little0>;
 107                                 };
 108                                 core1 {
 109                                         cpu = <&little1>;
 110                                 };
 111                                 core2 {
 112                                         cpu = <&little2>;
 113                                 };
 114                                 core3 {
 115                                         cpu = <&little3>;
 116                                 };
 117                         };
 118                 };
 119         };
 120
 121         psci {
 122                 compatible = "arm,psci";
 123                 method = "smc";
 124                 cpu_on = <0xC4000003>;
 125         };
 126
 127         gic: interrupt-controller@ffb70000 {
 128                 compatible = "arm,cortex-a15-gic";
 129                 #interrupt-cells = <3>;
 130                 #address-cells = <0>;
 131                 interrupt-controller;
 132                 reg = <0x0 0xffb71000 0 0x1000>,
 133                       <0x0 0xffb72000 0 0x1000>;
 134         };
 135
 136         pmu_grf: syscon@ff738000 {
 137                 compatible = "rockchip,rk3368-pmu-grf", "rockchip,pmu-grf", "syscon";
 138                 reg = <0x0 0xff738000 0x0 0x100>;
 139         };
 140
 141         sgrf: syscon@ff740000 {
 142                 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
 143                 reg = <0x0 0xff740000 0x0 0x1000>;
 144
 145         };
 146
 147         grf: syscon@ff770000 {
 148                 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
 149                 reg = <0x0 0xff770000 0x0 0x1000>;
 150         };
 151
 152         arm-pmu {
 153                 compatible = "arm,armv8-pmuv3";
 154                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 155                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 156                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 157                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 158                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 159                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 160                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 161                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 162         };
 163
 164         cpu_axi_bus: cpu_axi_bus {
 165                 compatible = "rockchip,cpu_axi_bus";
 166                 #address-cells = <2>;
 167                 #size-cells = <2>;
 168                 ranges;
 169
 170                 qos {
 171                         #address-cells = <2>;
 172                         #size-cells = <2>;
 173                         ranges;
 174
 175                         dmac {
 176                                 reg = <0x0 0xffa80000 0x0 0x20>;
 177                         };
 178                         crypto {
 179                                 reg = <0x0 0xffa80080 0x0 0x20>;
 180                         };
 181                         bus_cpup {
 182                                 reg = <0x0 0xffa90000 0x0 0x20>;
 183                         };
 184                         cci_r {
 185                                 reg = <0x0 0xffaa0000 0x0 0x20>;
 186                         };
 187                         cci_w {
 188                                 reg = <0x0 0xffaa0080 0x0 0x20>;
 189                         };
 190                         peri {
 191                                 reg = <0x0 0xffab0000 0x0 0x20>;
 192                         };
 193                         iep {
 194                                 reg = <0x0 0xffad0000 0x0 0x20>;
 195                         };
 196                         isp_r0 {
 197                                 reg = <0x0 0xffad0080 0x0 0x20>;
 198                         };
 199                         isp_r1 {
 200                                 reg = <0x0 0xffad0100 0x0 0x20>;
 201                         };
 202                         isp_w0 {
 203                                 reg = <0x0 0xffad0180 0x0 0x20>;
 204                                 rockchip,priority = <2 2>;
 205                         };
 206                         isp_w1 {
 207                                 reg = <0x0 0xffad0200 0x0 0x20>;
 208                                 rockchip,priority = <2 2>;
 209                         };
 210                         vip {
 211                                 reg = <0x0 0xffad0280 0x0 0x20>;
 212                         };
 213                         vop {
 214                                 reg = <0x0 0xffad0300 0x0 0x20>;
 215                                 rockchip,priority = <2 2>;
 216                         };
 217                         rga_r {
 218                                 reg = <0x0 0xffad0380 0x0 0x20>;
 219                         };
 220                         rga_w {
 221                                 reg = <0x0 0xffad0400 0x0 0x20>;
 222                         };
 223                         hevc_r {
 224                                 reg = <0x0 0xffae0000 0x0 0x20>;
 225                         };
 226                         vpu_r {
 227                                 reg = <0x0 0xffae0080 0x0 0x20>;
 228                         };
 229                         vpu_w {
 230                                 reg = <0x0 0xffae0100 0x0 0x20>;
 231                         };
 232                 };
 233
 234                 msch {
 235                         #address-cells = <2>;
 236                         #size-cells = <2>;
 237                         ranges;
 238
 239                         msch {
 240                                 reg = <0x0 0xffac0000 0x0 0x3c>;
 241                                 rockchip,read-latency = <0x34>;
 242                         };
 243                 };
 244         };
 245
 246         timer {
 247                 compatible = "arm,armv8-timer";
 248                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 249                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 250                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 251                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 252                 clock-frequency = <24000000>;
 253         };
 254
 255         timer@ff810000 {
 256                 compatible = "rockchip,timer";
 257                 reg = <0x0 0xff810000 0x0 0x20>;
 258                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 259                 rockchip,broadcast = <1>;
 260         };
 261
 262         sram: sram@ff8c0000 {
 263                 compatible = "mmio-sram";
 264                 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
 265                 map-exec;
 266         };
 267
 268         watchdog: wdt@ff800000 {
 269                 compatible = "rockchip,watch dog";
 270                 reg = <0x0 0xff800000 0x0 0x100>;
 271                 clocks = <&pclk_alive_pre>;
 272                 clock-names = "pclk_wdt";
 273                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 274                 rockchip,irq = <1>;
 275                 rockchip,timeout = <60>;
 276                 rockchip,atboot = <1>;
 277                 rockchip,debug = <0>;
 278                 status = "disabled";
 279         };
 280
 281         amba {
 282                 #address-cells = <2>;
 283                 #size-cells = <2>;
 284                 compatible = "arm,amba-bus";
 285                 interrupt-parent = <&gic>;
 286                 ranges;
 287
 288                 pdma0: pdma@ff600000 {
 289                         compatible = "arm,pl330", "arm,primecell";
 290                         reg = <0x0 0xff600000 0x0 0x4000>;
 291                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 292                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 293                         #dma-cells = <1>;
 294                 };
 295
 296                 pdma1: pdma@ff250000 {
 297                         compatible = "arm,pl330", "arm,primecell";
 298                         reg = <0x0 0xff250000 0x0 0x4000>;
 299                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 300                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 301                         #dma-cells = <1>;
 302                 };
 303         };
 304
 305         reset: reset@ff760300{
 306                 compatible = "rockchip,reset";
 307                 reg = <0x0 0xff760300 0x0 0x38>;
 308                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 309                 #reset-cells = <1>;
 310         };
 311
 312         nandc0: nandc@ff400000 {
 313                 compatible = "rockchip,rk-nandc";
 314                 reg = <0x0 0xff400000 0x0 0x4000>;
 315                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 316                 nandc_id = <0>;
 317                 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
 318                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 319         };
 320
 321         nandc0reg: nandc0@ff400000 {
 322                 compatible = "rockchip,rk-nandc";
 323                 reg = <0x0 0xff400000 0x0 0x4000>;
 324         };
 325
 326         emmc: rksdmmc@ff0f0000 {
 327                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 328                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 329                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 330                 #address-cells = <1>;
 331                 #size-cells = <0>;
 332                 clocks = <&clk_emmc>, <&clk_gates21 2>;
 333                 clock-names = "clk_mmc", "hclk_mmc";
 334                 num-slots = <1>;
 335                 fifo-depth = <0x100>;
 336                 bus-width = <8>;
 337         };
 338
 339         sdmmc: rksdmmc@ff0c0000 {
 340                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 341                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 342                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 343                 #address-cells = <1>;
 344                 #size-cells = <0>;
 345                 pinctrl-names = "default", "idle";
 346                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 347                 pinctrl-1 = <&sdmmc_gpio>;
 348                 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 349                 clocks = <&clk_sdmmc0>, <&clk_gates21 0>;
 350                 clock-names = "clk_mmc", "hclk_mmc";
 351                 num-slots = <1>;
 352                 fifo-depth = <0x100>;
 353                 bus-width = <4>;
 354         };
 355
 356         sdio: rksdmmc@ff0d0000 {
 357                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 358                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 359                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 360                 #address-cells = <1>;
 361                 #size-cells = <0>;
 362                 pinctrl-names = "default","idle";
 363                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
 364                 pinctrl-1 = <&sdio0_gpio>;
 365                 clocks = <&clk_sdio0>, <&clk_gates21 1>;
 366                 clock-names = "clk_mmc", "hclk_mmc";
 367                 num-slots = <1>;
 368                 fifo-depth = <0x100>;
 369                 bus-width = <4>;
 370         };
 371
 372         spi0: spi@ff110000 {
 373                 compatible = "rockchip,rockchip-spi";
 374                 reg = <0x0 0xff110000 0x0 0x1000>;
 375                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 376                 #address-cells = <1>;
 377                 #size-cells = <0>;
 378                 pinctrl-names = "default";
 379                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 380                 rockchip,spi-src-clk = <0>;
 381                 num-cs = <2>;
 382                 clocks =<&clk_spi0>, <&clk_gates19 4>;
 383                 clock-names = "spi", "pclk_spi0";
 384                 //dmas = <&pdma1 11>, <&pdma1 12>;
 385                 //#dma-cells = <2>;
 386                 //dma-names = "tx", "rx";
 387                 status = "disabled";
 388         };
 389
 390         spi1: spi@ff120000 {
 391                 compatible = "rockchip,rockchip-spi";
 392                 reg = <0x0 0xff120000 0x0 0x1000>;
 393                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 394                 #address-cells = <1>;
 395                 #size-cells = <0>;
 396                 pinctrl-names = "default";
 397                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 398                 rockchip,spi-src-clk = <1>;
 399                 num-cs = <1>;
 400                 clocks = <&clk_spi1>, <&clk_gates19 5>;
 401                 clock-names = "spi", "pclk_spi1";
 402                 //dmas = <&pdma1 13>, <&pdma1 14>;
 403                 //#dma-cells = <2>;
 404                 //dma-names = "tx", "rx";
 405                 status = "disabled";
 406         };
 407
 408         spi2: spi@ff130000 {
 409                 compatible = "rockchip,rockchip-spi";
 410                 reg = <0x0 0xff130000 0x0 0x1000>;
 411                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 412                 #address-cells = <1>;
 413                 #size-cells = <0>;
 414                 pinctrl-names = "default";
 415                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 416                 rockchip,spi-src-clk = <2>;
 417                 num-cs = <1>;
 418                 clocks = <&clk_spi2>, <&clk_gates19 6>;
 419                 clock-names = "spi", "pclk_spi2";
 420                 //dmas = <&pdma1 15>, <&pdma1 16>;
 421                 //#dma-cells = <2>;
 422                 //dma-names = "tx", "rx";
 423                 status = "disabled";
 424         };
 425
 426         uart_bt: serial@ff180000 {
 427                 compatible = "rockchip,serial";
 428                 reg = <0x0 0xff180000 0x0 0x100>;
 429                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 430                 clock-frequency = <24000000>;
 431                 clocks = <&clk_uart0>, <&clk_gates19 7>;
 432                 clock-names = "sclk_uart", "pclk_uart";
 433                 reg-shift = <2>;
 434                 reg-io-width = <4>;
 435                 //dmas = <&pdma1 1>, <&pdma1 2>;
 436                 //#dma-cells = <2>;
 437                 pinctrl-names = "default";
 438                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 439                 status = "disabled";
 440         };
 441
 442         uart_bb: serial@ff190000 {
 443                 compatible = "rockchip,serial";
 444                 reg = <0x0 0xff190000 0x0 0x100>;
 445                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 446                 clock-frequency = <24000000>;
 447                 clocks = <&clk_uart1>, <&clk_gates19 8>;
 448                 clock-names = "sclk_uart", "pclk_uart";
 449                 reg-shift = <2>;
 450                 reg-io-width = <4>;
 451                 //dmas = <&pdma1 3>, <&pdma1 4>;
 452                 //#dma-cells = <2>;
 453                 pinctrl-names = "default";
 454                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 455                 status = "disabled";
 456         };
 457
 458         uart_dbg: serial@ff690000 {
 459                 compatible = "rockchip,serial";
 460                 reg = <0x0 0xff690000 0x0 0x100>;
 461                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 462                 clock-frequency = <24000000>;
 463                 clocks = <&clk_uart2>, <&clk_gates13 5>;
 464                 clock-names = "sclk_uart", "pclk_uart";
 465                 reg-shift = <2>;
 466                 reg-io-width = <4>;
 467                 //dmas = <&pdma0 4>, <&pdma0 5>;
 468                 //#dma-cells = <2>;
 469                 //pinctrl-names = "default";
 470                 //pinctrl-0 = <&uart2_xfer>;
 471                 status = "disabled";
 472         };
 473
 474         uart_gps: serial@ff1b0000 {
 475                 compatible = "rockchip,serial";
 476                 reg = <0x0 0xff1b0000 0x0 0x100>;
 477                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 478                 clock-frequency = <24000000>;
 479                 clocks = <&clk_uart3>, <&clk_gates19 9>;
 480                 clock-names = "sclk_uart", "pclk_uart";
 481                 current-speed = <115200>;
 482                 reg-shift = <2>;
 483                 reg-io-width = <4>;
 484                 //dmas = <&pdma1 7>, <&pdma1 8>;
 485                 //#dma-cells = <2>;
 486                 pinctrl-names = "default";
 487                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 488                 status = "disabled";
 489         };
 490
 491         uart_exp: serial@ff1c0000 {
 492                 compatible = "rockchip,serial";
 493                 reg = <0x0 0xff1c0000 0x0 0x100>;
 494                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 495                 clock-frequency = <24000000>;
 496                 clocks = <&clk_uart4>, <&clk_gates19 10>;
 497                 clock-names = "sclk_uart", "pclk_uart";
 498                 reg-shift = <2>;
 499                 reg-io-width = <4>;
 500                 //dmas = <&pdma1 9>, <&pdma1 10>;
 501                 //#dma-cells = <2>;
 502                 pinctrl-names = "default";
 503                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 504                 status = "disabled";
 505         };
 506
 507         rockchip_clocks_init: clocks-init{
 508                 compatible = "rockchip,clocks-init";
 509                 rockchip,clocks-init-parent =
 510                         <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
 511                         <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
 512                         <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
 513                         <&clk_cs &clk_gpll>;
 514                 rockchip,clocks-init-rate =
 515                         <&clk_gpll 576000000>,          <&clk_core_b 792000000>,
 516                         <&clk_core_l 600000000>,        <&clk_cpll 400000000>,
 517                         /*<&clk_npll 500000000>,*/      <&aclk_bus 300000000>,
 518                         <&hclk_bus 150000000>,          <&pclk_bus 75000000>,
 519                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 520                         <&hclk_peri 150000000>,         <&pclk_peri 75000000>,
 521                         <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
 522                         <&clk_cs 300000000>,            <&clkin_trace 300000000>,
 523                         <&aclk_cci 600000000>,          <&clk_mac 50000000>,
 524                         <&aclk_vio0 400000000>,         <&hclk_vio 100000000>,
 525                         <&aclk_rga_pre 400000000>,      <&clk_rga 400000000>,
 526                         <&clk_isp 400000000>,           <&clk_edp 200000000>,
 527                         <&clk_gpu_core 400000000>,      <&aclk_gpu_mem 400000000>,
 528                         <&aclk_gpu_cfg 400000000>,      <&aclk_vepu 400000000>,
 529                         <&aclk_vdpu 400000000>,         <&clk_hevc_core 300000000>,
 530                         <&clk_hevc_cabac 300000000>;
 531 /*
 532                 rockchip,clocks-uboot-has-init =
 533                         <&aclk_vio0>;
 534 */
 535         };
 536
 537         rockchip_clocks_enable: clocks-enable {
 538                 compatible = "rockchip,clocks-enable";
 539                 clocks =
 540                         /*PLL*/
 541                         <&clk_apllb>,
 542                         <&clk_aplll>,
 543                         <&clk_dpll>,
 544                         <&clk_gpll>,
 545                         <&clk_cpll>,
 546
 547                         /*PD_CORE*/
 548                         <&clk_cs>,
 549                         <&clkin_trace>,
 550
 551                         /*PD_BUS*/
 552                         <&aclk_bus>,
 553                         <&hclk_bus>,
 554                         <&pclk_bus>,
 555                         <&clk_gates12 12>,/*aclk_strc_sys*/
 556                         <&clk_gates12 6>,/*aclk_intmem1*/
 557                         <&clk_gates12 5>,/*aclk_intmem0*/
 558                         <&clk_gates12 4>,/*aclk_intmem*/
 559                         <&clk_gates13 9>,/*aclk_gic400*/
 560
 561                         /*PD_ALIVE*/
 562                         <&clk_gates22 13>,/*pclk_timer1*/
 563                         <&clk_gates22 12>,/*pclk_timer0*/
 564                         <&clk_gates22 9>,/*pclk_alive_niu*/
 565                         <&clk_gates22 8>,/*pclk_grf*/
 566
 567                         /*PD_PMU*/
 568                         <&clk_gates23 5>,/*pclk_pmugrf*/
 569                         <&clk_gates23 3>,/*pclk_sgrf*/
 570                         <&clk_gates23 2>,/*pclk_pmu_noc*/
 571                         <&clk_gates23 1>,/*pclk_intmem1*/
 572                         <&clk_gates23 0>,/*pclk_pmu*/
 573
 574                         /*PD_PERI*/
 575                         <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
 576                         <&clk_gates20 8>,/*aclk_peri_niu*/
 577                         <&clk_gates21 4>,/*aclk_peri_mmu*/
 578                         <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
 579                         <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
 580                         <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
 581         };
 582
 583         /* I2C_PMU */
 584         i2c0: i2c@ff650000 {
 585                 compatible = "rockchip,rk30-i2c";
 586                 reg = <0x0 0xff650000 0x0 0x1000>;
 587                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 588                 #address-cells = <1>;
 589                 #size-cells = <0>;
 590                 pinctrl-names = "default", "gpio";
 591                 pinctrl-0 = <&i2c0_xfer>;
 592                 pinctrl-1 = <&i2c0_gpio>;
 593                 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
 594                 clocks = <&clk_gates12 2>;
 595                 rockchip,check-idle = <1>;
 596                 status = "disabled";
 597         };
 598
 599         /* I2C_AUDIO */
 600         i2c1: i2c@ff660000 {
 601                 compatible = "rockchip,rk30-i2c";
 602                 reg = <0x0 0xff660000 0x0 0x1000>;
 603                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 604                 #address-cells = <1>;
 605                 #size-cells = <0>;
 606                 pinctrl-names = "default", "gpio";
 607                 pinctrl-0 = <&i2c1_xfer>;
 608                 pinctrl-1 = <&i2c1_gpio>;
 609                 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
 610                 clocks = <&clk_gates12 3>;
 611                 rockchip,check-idle = <1>;
 612                 status = "disabled";
 613         };
 614
 615         /* I2C_SENSOR */
 616         i2c2: i2c@ff140000 {
 617                 compatible = "rockchip,rk30-i2c";
 618                 reg = <0x0 0xff140000 0x0 0x1000>;
 619                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 620                 #address-cells = <1>;
 621                 #size-cells = <0>;
 622                 pinctrl-names = "default", "gpio";
 623                 pinctrl-0 = <&i2c2_xfer>;
 624                 pinctrl-1 = <&i2c2_gpio>;
 625                 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 626                 clocks = <&clk_gates19 11>;
 627                 rockchip,check-idle = <1>;
 628                 status = "disabled";
 629         };
 630
 631         /* I2C_CAM */
 632         i2c3: i2c@ff150000 {
 633                 compatible = "rockchip,rk30-i2c";
 634                 reg = <0x0 0xff150000 0x0 0x1000>;
 635                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 636                 #address-cells = <1>;
 637                 #size-cells = <0>;
 638                 pinctrl-names = "default", "gpio";
 639                 pinctrl-0 = <&i2c3_xfer>;
 640                 pinctrl-1 = <&i2c3_gpio>;
 641                 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
 642                 clocks = <&clk_gates19 12>;
 643                 rockchip,check-idle = <1>;
 644                 status = "disabled";
 645         };
 646
 647         /* I2C_TP */
 648         i2c4: i2c@ff160000 {
 649                 compatible = "rockchip,rk30-i2c";
 650                 reg = <0x0 0xff160000 0x0 0x1000>;
 651                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 652                 #address-cells = <1>;
 653                 #size-cells = <0>;
 654                 pinctrl-names = "default", "gpio";
 655                 pinctrl-0 = <&i2c4_xfer>;
 656                 pinctrl-1 = <&i2c4_gpio>;
 657                 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
 658                 clocks = <&clk_gates19 13>;
 659                 rockchip,check-idle = <1>;
 660                 status = "disabled";
 661         };
 662
 663         /* I2C_HDMI */
 664         i2c5: i2c@ff170000 {
 665                 compatible = "rockchip,rk30-i2c";
 666                 reg = <0x0 0xff170000 0x0 0x1000>;
 667                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 668                 #address-cells = <1>;
 669                 #size-cells = <0>;
 670                 pinctrl-names = "default", "gpio";
 671                 pinctrl-0 = <&i2c5_xfer>;
 672                 pinctrl-1 = <&i2c5_gpio>;
 673                 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
 674                 clocks = <&clk_gates19 14>;
 675                 rockchip,check-idle = <1>;
 676                 status = "disabled";
 677         };
 678
 679         fb: fb {
 680                 compatible = "rockchip,rk-fb";
 681                 rockchip,disp-mode = <NO_DUAL>;
 682         };
 683
 684
 685         rk_screen: rk_screen {
 686                 compatible = "rockchip,screen";
 687         };
 688
 689         dsihost0: mipi@ff960000{
 690                 compatible = "rockchip,rk33x-dsi";
 691                 rockchip,prop = <0>;
 692                 reg = <0xff960000 0x4000>, <0xff968000 0x4000>;
 693                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 694                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 695                 clocks = <&clk_gates4 14>, <&clk_gates17 3>, <&clk_gates22 10>;
 696                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi_host", "pclk_mipi_dsi_phy";
 697                 status = "okay";
 698         };
 699
 700         lvds: lvds@ff968000 {
 701                 compatible = "rockchip,rk3368-lvds";
 702                 rockchip,grf = <&grf>;
 703                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600b0 0x0 0x01>;
 704                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 705                 clocks = <&clk_gates22 10>, <&clk_gates17 3>;
 706                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 707                 status = "disabled";
 708         };
 709
 710         edp: edp@ff970000 {
 711                 compatible = "rockchip,rk32-edp";
 712                 reg = <0x0 0xff970000 0x0 0x4000>;
 713                 rockchip,grf = <&grf>;
 714                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 715                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
 716                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 717                 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
 718                 reset-names = "edp_24m", "edp_apb";
 719         };
 720
 721         hdmi: hdmi@ff980000 {
 722                 compatible = "rockchip,rk3368-hdmi";
 723                 reg = <0x0 0xff980000 0x0 0x20000>;
 724                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 725                 pinctrl-names = "default", "gpio";
 726                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 727                 pinctrl-1 = <&i2c5_gpio>;
 728                 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
 729                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 730                 status = "disabled";
 731         };
 732
 733         hdmi_hdcp2: hdmi_hdcp2@ff978000 {
 734                 compatible = "rockchip,rk3368-hdmi-hdcp2";
 735                 reg = <0x0 0xff978000 0x0 0x2000>;
 736                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 737                 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
 738                 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
 739                 status = "disabled";
 740         };
 741
 742         lcdc: lcdc@ff930000 {
 743                  compatible = "rockchip,rk3368-lcdc";
 744                  rockchip,grf = <&grf>;
 745                  rockchip,pmu = <&pmu_grf>;
 746                  rockchip,prop = <PRMRY>;
 747                  rockchip,pwr18 = <0>;
 748                  rockchip,iommu-enabled = <0>;
 749                  reg = <0x0 0xff930000 0x0 0x10000>;
 750                  interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 751                 /*pinctrl-names = "default", "gpio";
 752                  *pinctrl-0 = <&lcdc_lcdc>;
 753                  *pinctrl-1 = <&lcdc_gpio>;
 754                  */
 755                  status = "disabled";
 756                  clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
 757                  clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
 758         };
 759
 760         adc: adc@ff100000 {
 761                 compatible = "rockchip,saradc";
 762                 reg = <0x0 0xff100000 0x0 0x100>;
 763                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 764                 #io-channel-cells = <1>;
 765                 io-channel-ranges;
 766                 rockchip,adc-vref = <1800>;
 767                 clock-frequency = <1000000>;
 768                 clocks = <&clk_saradc>, <&clk_gates19 15>;
 769                 clock-names = "saradc", "pclk_saradc";
 770                 status = "disabled";
 771         };
 772
 773         rga@ff920000 {
 774                 compatible = "rockchip,rk3368-rga2";
 775                 reg = <0x0 0xff920000 0x0 0x1000>;
 776                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 777                 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
 778                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 779         };
 780
 781         i2s0: i2s0@ff898000 {
 782                 compatible = "rockchip-i2s";
 783                 reg = <0x0 0xff898000 0x0 0x1000>;
 784                 i2s-id = <0>;
 785                 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 786                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 787                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 788                 dmas = <&pdma0 0>, <&pdma0 1>;
 789                 #dma-cells = <2>;
 790                 dma-names = "tx", "rx";
 791                 pinctrl-names = "default", "sleep";
 792                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 793                 pinctrl-1 = <&i2s_gpio>;
 794         };
 795
 796         i2s1: i2s1@ff890000 {
 797                 compatible = "rockchip-i2s";
 798                 reg = <0x0 0xff890000 0x0 0x1000>;
 799                 i2s-id = <1>;
 800                 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
 801                 clock-names = "i2s_clk", "i2s_hclk";
 802                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 803                 dmas = <&pdma0 6>, <&pdma0 7>;
 804                 #dma-cells = <2>;
 805                 dma-names = "tx", "rx";
 806         };
 807
 808         spdif: spdif@ff880000 {
 809                 compatible = "rockchip-spdif";
 810                 reg = <0x0 0xff880000 0x0 0x1000>;
 811                 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
 812                 clock-names = "spdif_mclk", "spdif_hclk";
 813                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 814                 dmas = <&pdma0 3>;
 815                 #dma-cells = <1>;
 816                 dma-names = "tx";
 817                 pinctrl-names = "default";
 818                 pinctrl-0 = <&spdif_tx>;
 819         };
 820
 821         pwm0: pwm@ff680000 {
 822                 compatible = "rockchip,rk-pwm";
 823                 reg = <0x0 0xff680000 0x0 0x10>;
 824                 #pwm-cells = <2>;
 825                 pinctrl-names = "default";
 826                 pinctrl-0 = <&pwm0_pin>;
 827                 clocks = <&clk_gates13 6>;
 828                 clock-names = "pclk_pwm";
 829                 status = "disabled";
 830         };
 831
 832         pwm1: pwm@ff680010 {
 833                 compatible = "rockchip,rk-pwm";
 834                 reg = <0x0 0xff680010 0x0 0x10>;
 835                 #pwm-cells = <2>;
 836                 pinctrl-names = "default";
 837                 pinctrl-0 = <&pwm1_pin>;
 838                 clocks = <&clk_gates13 6>;
 839                 clock-names = "pclk_pwm";
 840                 status = "disabled";
 841         };
 842
 843         pwm2: pwm@ff680020 {
 844                 compatible = "rockchip,rk-pwm";
 845                 reg = <0x0 0xff680020 0x0 0x10>;
 846                 #pwm-cells = <2>;
 847                 //pinctrl-names = "default";
 848                 //pinctrl-0 = <&pwm1_pin>;
 849                 clocks = <&clk_gates13 6>;
 850                 clock-names = "pclk_pwm";
 851                 status = "disabled";
 852         };
 853
 854         pwm3: pwm@ff680030 {
 855                 compatible = "rockchip,rk-pwm";
 856                 reg = <0x0 0xff680030 0x0 0x10>;
 857                 #pwm-cells = <2>;
 858                 pinctrl-names = "default";
 859                 pinctrl-0 = <&pwm3_pin>;
 860                 clocks = <&clk_gates13 6>;
 861                 clock-names = "pclk_pwm";
 862                 status = "disabled";
 863         };
 864
 865         voppwm: pwm@ff9301a0 {
 866                 compatible = "rockchip,vop-pwm";
 867                 reg = <0x0 0xff9301a0 0x0 0x10>;
 868                 #pwm-cells = <2>;
 869                 pinctrl-names = "default";
 870                 pinctrl-0 = <&vop_pwm_pin>;
 871                 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
 872                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 873                 status = "disabled";
 874         };
 875
 876         dvfs {
 877
 878                 vd_arm: vd_arm {
 879                         regulator_name = "vdd_arm";
 880                         suspend_volt = <1000>; //mV
 881                         pd_core {
 882                                 clk_core_dvfs_table: clk_core {
 883                                         operating-points = <
 884                                                 /* KHz    uV */
 885                                                 312000 1100000
 886                                                 504000 1100000
 887                                                 816000 1100000
 888                                                 1008000 1100000
 889                                                 >;
 890                                         channel = <0>;
 891                                         temp-limit-enable = <0>;
 892                                         target-temp = <80>;
 893                                         normal-temp-limit = <
 894                                         /*delta-temp    delta-freq*/
 895                                                 3       96000
 896                                                 6       144000
 897                                                 9       192000
 898                                                 15      384000
 899                                                 >;
 900                                         performance-temp-limit = <
 901                                                 /*temp    freq*/
 902                                                 100     816000
 903                                                 >;
 904                                         status = "okay";
 905                                         regu-mode-table = <
 906                                                 /*freq     mode*/
 907                                                 1008000    4
 908                                                 0          3
 909                                         >;
 910                                         regu-mode-en = <0>;
 911                                 };
 912                         };
 913                 };
 914
 915                 vd_logic: vd_logic {
 916                         regulator_name = "vdd_logic";
 917                         suspend_volt = <1000>; //mV
 918                         pd_ddr {
 919                                 clk_ddr_dvfs_table: clk_ddr {
 920                                         operating-points = <
 921                                                 /* KHz    uV */
 922                                                 200000 1200000
 923                                                 300000 1200000
 924                                                 400000 1200000
 925                                                 >;
 926                                         channel = <2>;
 927                                         status = "disabled";
 928                                 };
 929                         };
 930
 931                         pd_vio {
 932                                 aclk_vio1_dvfs_table: aclk_vio1 {
 933                                         operating-points = <
 934                                                 /* KHz    uV */
 935                                                 100000 1100000
 936                                                 500000 1100000
 937                                                 >;
 938                                         status = "okay";
 939                                 };
 940                         };
 941                 };
 942
 943                 vd_gpu: vd_gpu {
 944                         regulator_name = "vdd_gpu";
 945                         suspend_volt = <1000>; //mV
 946                         pd_gpu {
 947                                 clk_gpu_dvfs_table: clk_gpu {
 948                                         operating-points = <
 949                                                 /* KHz    uV */
 950                                                 200000 1200000
 951                                                 300000 1200000
 952                                                 400000 1200000
 953                                                 >;
 954                                         channel = <1>;
 955                                         status = "okay";
 956                                         regu-mode-table = <
 957                                                 /*freq     mode*/
 958                                                 200000     4
 959                                                 0          3
 960                                         >;
 961                                         regu-mode-en = <0>;
 962                                 };
 963                         };
 964                 };
 965         };
 966
 967         ion {
 968                 compatible = "rockchip,ion";
 969                 #address-cells = <1>;
 970                 #size-cells = <0>;
 971
 972                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
 973                         compatible = "rockchip,ion-heap";
 974                         rockchip,ion_heap = <4>;
 975                         reg = <0x00000000 0x08000000>; /* 512MB */
 976                 };
 977                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
 978                         compatible = "rockchip,ion-heap";
 979                         rockchip,ion_heap = <0>;
 980                 };
 981         };
 982
 983         vpu: vpu_service {
 984                 compatible = "rockchip,vpu_sub";
 985                 iommu_enabled = <0>;
 986                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 987                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 988                 interrupt-names = "irq_enc", "irq_dec";
 989                 dev_mode = <0>;
 990                 name = "vpu_service";
 991         };
 992
 993         hevc: hevc_service {
 994                 compatible = "rockchip,hevc_sub";
 995                 iommu_enabled = <0>;
 996                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 997                 interrupts-names = "irq_dec";
 998                 dev_mode = <1>;
 999                 name = "hevc_service";
1000         };
1001
1002         vpu_combo: vpu_combo@ff9a0000 {
1003                 compatible = "rockchip,vpu_combo";
1004                 reg = <0x0 0xff9a0000 0x0 0x800>;
1005                 rockchip,grf = <&grf>;
1006                 subcnt = <2>;
1007                 rockchip,sub = <&vpu>, <&hevc>;
1008                 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1009                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1010                 mode_bit = <12>;
1011                 mode_ctrl = <0x418>;
1012                 name = "vpu_combo";
1013                 status = "okay";
1014         };
1015
1016         iep: iep@ff900000 {
1017                 compatible = "rockchip,iep";
1018                 iommu_enabled = <0>;
1019                 reg = <0x0 0xff900000 0x0 0x800>;
1020                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1021                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1022                 clock-names = "aclk_iep", "hclk_iep";
1023                 status = "okay";
1024         };
1025
1026         gmac: eth@ff290000 {
1027                 compatible = "rockchip,rk3368-gmac";
1028                 reg = <0x0 0xff290000 0x0 0x10000>;
1029                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1030                 interrupt-names = "macirq";
1031
1032                 clocks = <&clk_mac>, <&clk_gates5 0>,
1033                          <&clk_gates5 1>, <&clk_gates5 2>,
1034                          <&clk_gates5 3>, <&clk_gates8 0>,
1035                          <&clk_gates8 1>;
1036                 clock-names = "clk_mac", "mac_clk_rx",
1037                               "mac_clk_tx", "clk_mac_ref",
1038                               "clk_mac_refout", "aclk_mac",
1039                               "pclk_mac";
1040
1041                 phy-mode = "rgmii";
1042                 pinctrl-names = "default";
1043                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1044         };
1045
1046         gpu {
1047                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1048                 reg = <0x0 0xffa30000 0x0 0x10000>;
1049                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1050                 interrupt-names = "GPU";
1051         };
1052
1053         iep_mmu {
1054                 dbgname = "iep";
1055                 compatible = "rockchip,iep_mmu";
1056                 reg = <0x0 0xff900800 0x0 0x100>;
1057                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1058                 interrupt-names = "iep_mmu";
1059         };
1060
1061         vip_mmu {
1062                 dbgname = "vip";
1063                 compatible = "rockchip,vip_mmu";
1064                 reg = <0x0 0xff950800 0x0 0x100>;
1065                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1066                 interrupt-names = "vip_mmu";
1067         };
1068
1069         vop_mmu {
1070                 dbgname = "vop";
1071                 compatible = "rockchip,vop_mmu";
1072                 reg = <0x0 0xff930300 0x0 0x100>;
1073                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1074                 interrupt-names = "vop_mmu";
1075         };
1076
1077         isp_mmu {
1078                 dbgname = "isp_mmu";
1079                 compatible = "rockchip,isp_mmu";
1080                 reg = <0x0 0xff914000 0x0 0x100>,
1081                 <0x0 0xff915000 0x0 0x100>;
1082                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1083                 interrupt-names = "isp_mmu";
1084         };
1085
1086         hdcp_mmu {
1087                 dbgname = "hdcp_mmu";
1088                 compatible = "rockchip,hdcp_mmu";
1089                 reg = <0x0 0xff940000 0x0 0x100>;
1090                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1091                 interrupt-names = "hdcp_mmu";
1092         };
1093
1094         hevc_mmu {
1095                 dbgname = "hevc";
1096                 compatible = "rockchip,hevc_mmu";
1097                 reg = <0x0 0xff9c0440 0x0 0x40>,                      /*need to fix*/
1098                           <0x0 0xff9c0480 0x0 0x40>;
1099                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;        /*need to fix*/
1100                 interrupt-names = "hevc_mmu";
1101         };
1102
1103         vpu_mmu {
1104                 dbgname = "vpu";
1105                 compatible = "rockchip,vpu_mmu";
1106                 reg = <0x0 0xff9a0800 0x0 0x100>;                    /*need to fix*/
1107                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;       /*need to fix*/
1108                 interrupt-names = "vpu_mmu";
1109         };
1110
1111         rockchip_suspend {
1112                 rockchip,ctrbits = <
1113                         (0
1114                          |RKPM_CTR_PWR_DMNS
1115                          |RKPM_CTR_GTCLKS
1116                          |RKPM_CTR_PLLS
1117                          |RKPM_CTR_GPIOS
1118                         /*
1119                          |RKPM_CTR_SYSCLK_DIV
1120                          |RKPM_CTR_IDLEAUTO_MD
1121                          |RKPM_CTR_ARMOFF_LPMD
1122                         */
1123                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1124                         )
1125                         >;
1126                 rockchip,pmic-suspend_gpios = <
1127                                  /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1128                         >;
1129                 rockchip,pmic-resume_gpios = <
1130                                 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1131                         >;
1132         };
1133
1134         isp: isp@ff910000{
1135                 compatible = "rockchip,isp";
1136                 reg = <0x0 0xff910000 0x0 0x10000>;
1137                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1138                 clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
1139                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
1140                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1141                 pinctrl-0 = <&cif_clkout>;
1142                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1143                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1144                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1145                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1146                 pinctrl-5 = <&cif_clkout>;
1147                 pinctrl-6 = <&cif_clkout &isp_prelight>;
1148                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1149                 pinctrl-8 = <&isp_flash_trigger>;
1150                 rockchip,isp,mipiphy = <2>;
1151                 rockchip,isp,cifphy = <1>;
1152                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1153                 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1154                 rockchip,isp,iommu_enable = <1>;
1155                 status = "okay";
1156         };
1157
1158         tsadc: tsadc@ff280000 {
1159                 compatible = "rockchip,tsadc";
1160                 reg = <0x0 0xff280000 0x0 0x100>;
1161                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1162                 #io-channel-cells = <1>;
1163                 io-channel-ranges;
1164                 clock-frequency = <10000>;
1165                 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1166                 clock-names = "tsadc", "pclk_tsadc";
1167                 pinctrl-names = "default", "tsadc_int";
1168                 pinctrl-0 = <&tsadc_gpio>;
1169                 pinctrl-1 = <&tsadc_int>;
1170                 tsadc-ht-temp = <120>;
1171                 tsadc-ht-reset-cru = <1>;
1172                 tsadc-ht-pull-gpio = <0>;
1173                 status = "disabled";
1174         };
1175
1176         tsp: tsp@FF8B0000 {
1177                 compatible = "rockchip,rk3368-tsp";
1178                 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1179                 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1180                 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1181                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1182                 interrupt-names = "irq_tsp";
1183                 // pinctrl-names = "default";
1184                 // pinctrl-0 = <&isp_hsadc>;
1185                 status = "okay";
1186         };
1187
1188         crypto: crypto@FF8A0000{
1189                 compatible = "rockchip,rk3368-crypto";
1190                 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1191                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1192                 interrupt-names = "irq_crypto";
1193                         clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1194                 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1195                 status = "okay";
1196         };
1197         dwc_control_usb: dwc-control-usb {
1198                 compatible = "rockchip,rk3368-dwc-control-usb";
1199                 rockchip,grf = <&grf>;
1200                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1201                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1202                 interrupt-names = "otg_id", "otg_bvalid",
1203                                   "otg_linestate", "host0_linestate";
1204                 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1205                 clock-names = "hclk_usb_peri", "usbphy_480m";
1206                 //resets = <&reset RK3128_RST_USBPOR>;
1207                 //reset-names = "usbphy_por";
1208                 usb_bc{
1209                         compatible = "inno,phy";
1210                         regbase = &dwc_control_usb;
1211                         rk_usb,bvalid     = <0x04b 23 1>;
1212                         rk_usb,iddig      = <0x04b 26 1>;
1213                         rk_usb,vdmsrcen   = <0x718 12 1>;
1214                         rk_usb,vdpsrcen   = <0x718 11 1>;
1215                         rk_usb,rdmpden    = <0x718 10 1>;
1216                         rk_usb,idpsrcen   = <0x718  9 1>;
1217                         rk_usb,idmsinken  = <0x718  8 1>;
1218                         rk_usb,idpsinken  = <0x718  7 1>;
1219                         rk_usb,dpattach   = <0x4b8 31 1>;
1220                         rk_usb,cpdet      = <0x4b8 30 1>;
1221                         rk_usb,dcpattach  = <0x4b8 29 1>;
1222                 };
1223         };
1224
1225         usb0: usb@ff580000 {
1226                 compatible = "rockchip,rk3368_usb20_otg";
1227                 reg = <0x0 0xff580000 0x0 0x40000>;
1228                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1229                 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1230                 clock-names = "clk_usbphy0", "hclk_otg";
1231                 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1232                                 <&reset RK3368_SRST_USBOTGC0>;
1233                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1234                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1235                 rockchip,usb-mode = <0>;
1236         };
1237
1238         usb_ehci: usb@ff500000 {
1239                 compatible = "generic-ehci";
1240                 reg = <0x0 0xff500000 0x0 0x20000>;
1241                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1242                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1243                 clock-names = "clk_usbphy0", "hclk_ehci";
1244                 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1245                 //              <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1246                 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1247         };
1248
1249         usb_ohci: usb@ff520000 {
1250                 compatible = "generic-ohci";
1251                 reg = <0x0 0xff520000 0x0 0x20000>;
1252                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1253                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1254                 clock-names =  "clk_usbphy0", "hclk_ohci";
1255         };
1256
1257         usb_hsic: usb@ff5c0000 {
1258                 compatible = "rockchip,rk3288_rk_hsic_host";
1259                 reg = <0x0 0xff5c0000 0x0 0x40000>;
1260                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1261 /*
1262                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1263                          <&hsicphy_12m>, <&usbphy_480m>,
1264                          <&otgphy1_480m>, <&otgphy2_480m>;
1265                 clock-names = "hsicphy_480m", "hclk_hsic",
1266                               "hsicphy_12m", "usbphy_480m",
1267                               "hsic_usbphy1", "hsic_usbphy2";
1268                 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1269                                 <&reset RK3288_SOFT_RST_HSICPHY>;
1270                 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1271 */
1272                 status = "disabled";
1273         };
1274
1275         pinctrl: pinctrl {
1276                 compatible = "rockchip,rk3368-pinctrl";
1277                 rockchip,grf = <&grf>;
1278                 rockchip,pmu = <&pmu_grf>;
1279                 #address-cells = <2>;
1280                 #size-cells = <2>;
1281                 ranges;
1282
1283                 gpio0: gpio0@ff750000 {
1284                         compatible = "rockchip,gpio-bank";
1285                         reg =   <0x0 0xff750000 0x0 0x100>;
1286                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1287                         clocks = <&clk_gates23 4>;
1288
1289                         gpio-controller;
1290                         #gpio-cells = <2>;
1291
1292                         interrupt-controller;
1293                         #interrupt-cells = <2>;
1294                 };
1295
1296                 gpio1: gpio1@ff780000 {
1297                         compatible = "rockchip,gpio-bank";
1298                         reg = <0x0 0xff780000 0x0 0x100>;
1299                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1300                         clocks = <&clk_gates22 1>;
1301
1302                         gpio-controller;
1303                         #gpio-cells = <2>;
1304
1305                         interrupt-controller;
1306                         #interrupt-cells = <2>;
1307                 };
1308
1309                 gpio2: gpio2@ff790000 {
1310                         compatible = "rockchip,gpio-bank";
1311                         reg = <0x0 0xff790000 0x0 0x100>;
1312                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1313                         clocks = <&clk_gates22 2>;
1314
1315                         gpio-controller;
1316                         #gpio-cells = <2>;
1317
1318                         interrupt-controller;
1319                         #interrupt-cells = <2>;
1320                 };
1321
1322                 gpio3: gpio3@ff7a0000 {
1323                         compatible = "rockchip,gpio-bank";
1324                         reg = <0x0 0xff7a0000 0x0 0x100>;
1325                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1326                         clocks = <&clk_gates22 3>;
1327
1328                         gpio-controller;
1329                         #gpio-cells = <2>;
1330
1331                         interrupt-controller;
1332                         #interrupt-cells = <2>;
1333                 };
1334
1335                 pcfg_pull_up: pcfg-pull-up {
1336                         bias-pull-up;
1337                 };
1338
1339                 pcfg_pull_down: pcfg-pull-down {
1340                         bias-pull-down;
1341                 };
1342
1343                 pcfg_pull_none: pcfg-pull-none {
1344                         bias-disable;
1345                 };
1346
1347                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1348                         drive-strength = <8>;
1349                 };
1350
1351                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1352                         bias-pull-up;
1353                         drive-strength = <8>;
1354                 };
1355
1356                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1357                         drive-strength = <4>;
1358                 };
1359
1360                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1361                         bias-pull-up;
1362                         drive-strength = <4>;
1363                 };
1364
1365                 pcfg_output_high: pcfg-output-high {
1366                         output-high;
1367                 };
1368
1369                 pcfg_output_low: pcfg-output-low {
1370                         output-low;
1371                 };
1372
1373                 i2c0 {
1374                         i2c0_xfer: i2c0-xfer {
1375                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1376                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1377                         };
1378                         i2c0_gpio: i2c0-gpio {
1379                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1380                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1381                         };
1382                 };
1383
1384                 i2c1 {
1385                         i2c1_xfer: i2c1-xfer {
1386                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1387                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1388                         };
1389                         i2c1_gpio: i2c1-gpio {
1390                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1391                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1392                         };
1393                 };
1394
1395                 i2c2 {
1396                         i2c2_xfer: i2c2-xfer {
1397                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1398                                                 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1399                         };
1400                         i2c2_gpio: i2c2-gpio {
1401                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1402                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1403             };
1404                 };
1405
1406                 i2c3 {
1407                         i2c3_xfer: i2c3-xfer {
1408                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1409                                                 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1410                         };
1411                         i2c3_gpio: i2c3-gpio {
1412                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1413                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1414                         };
1415                 };
1416
1417                 i2c4 {
1418                         i2c4_xfer: i2c4-xfer {
1419                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1420                                                 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1421                         };
1422                         i2c4_gpio: i2c4-gpio {
1423                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1424                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1425                         };
1426                 };
1427
1428                 i2c5 {
1429                         i2c5_xfer: i2c5-xfer {
1430                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1431                                                 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1432                         };
1433                         i2c5_gpio: i2c5-gpio {
1434                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1435                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1436                         };
1437                 };
1438
1439                 uart0 {
1440                         uart0_xfer: uart0-xfer {
1441                                 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1442                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1443                         };
1444
1445                         uart0_cts: uart0-cts {
1446                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1447                         };
1448
1449                         uart0_rts: uart0-rts {
1450                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1451                         };
1452
1453                         uart0_rts_gpio: uart0-rts-gpio {
1454                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1455                         };
1456                 };
1457
1458                 uart1 {
1459                         uart1_xfer: uart1-xfer {
1460                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1461                                                 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1462                         };
1463
1464                         uart1_cts: uart1-cts {
1465                                 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1466                         };
1467
1468                         uart1_rts: uart1-rts {
1469                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1470                         };
1471                 };
1472
1473                 uart2 {
1474                         uart2_xfer: uart2-xfer {
1475                                 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1476                                                 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1477                         };
1478                 };
1479
1480                 uart3 {
1481                         uart3_xfer: uart3-xfer {
1482                                 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1483                                                 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1484                         };
1485
1486                         uart3_cts: uart3-cts {
1487                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1488                         };
1489
1490                         uart3_rts: uart3-rts {
1491                                 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1492                         };
1493                 };
1494
1495                 uart4 {
1496                         uart4_xfer: uart4-xfer {
1497                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1498                                                 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1499                         };
1500
1501                         uart4_cts: uart4-cts {
1502                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1503                         };
1504
1505                         uart4_rts: uart4-rts {
1506                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1507                         };
1508                 };
1509
1510                 spi0 {
1511                         spi0_clk: spi0-clk {
1512                                 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1513                         };
1514                         spi0_cs0: spi0-cs0 {
1515                                 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1516                         };
1517                         spi0_tx: spi0-tx {
1518                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1519                         };
1520                         spi0_rx: spi0-rx {
1521                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1522                         };
1523                         spi0_cs1: spi0-cs1 {
1524                                 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1525                         };
1526                 };
1527
1528                 spi1 {
1529                         spi1_clk: spi1-clk {
1530                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1531                         };
1532                         spi1_cs0: spi1-cs0 {
1533                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1534                         };
1535                         spi1_rx: spi1-rx {
1536                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1537                         };
1538                         spi1_tx: spi1-tx {
1539                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1540                         };
1541                 };
1542
1543                 spi2 {
1544                         spi2_clk: spi2-clk {
1545                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1546                         };
1547                         spi2_cs0: spi2-cs0 {
1548                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1549                         };
1550                         spi2_rx: spi2-rx {
1551                                 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1552                         };
1553                         spi2_tx: spi2-tx {
1554                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1555                         };
1556                 };
1557
1558                 i2s {
1559                         i2s_mclk: i2s-mclk {
1560                                 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1561                         };
1562
1563                         i2s_sclk:i2s-sclk {
1564                                 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1565                         };
1566
1567                         i2s_lrckrx:i2s-lrckrx {
1568                                 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1569                         };
1570
1571                         i2s_lrcktx:i2s-lrcktx {
1572                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1573                         };
1574
1575                         i2s_sdi:i2s-sdi {
1576                                 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1577                         };
1578
1579                         i2s_sdo0:i2s-sdo0 {
1580                                 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1581                         };
1582
1583                         i2s_sdo1:i2s-sdo1 {
1584                                 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1585                         };
1586
1587                         i2s_sdo2:i2s-sdo2 {
1588                                 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1589                         };
1590
1591                         i2s_sdo3:i2s-sdo3 {
1592                                 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1593                         };
1594
1595                         i2s_gpio: i2s-gpio {
1596                                 rockchip,pins = <2 GPIO_C4  RK_FUNC_GPIO &pcfg_pull_none>,
1597                                                 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1598                                                 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1599                                                 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1600                                                 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1601                                                 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1602                                                 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1603                                                 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1604                                                 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1605                         };
1606                 };
1607
1608                 spdif {
1609                         spdif_tx: spdif-tx {
1610                                 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1611                         };
1612                 };
1613
1614                 sdmmc {
1615                         sdmmc_clk: sdmmc-clk {
1616                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1617                         };
1618
1619                         sdmmc_cmd: sdmmc-cmd {
1620                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1621                         };
1622
1623                         sdmmc_dectn: sdmmc-dectn {
1624                                 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1625                         };
1626
1627                         sdmmc_bus1: sdmmc-bus1 {
1628                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1629                         };
1630
1631                         sdmmc_bus4: sdmmc-bus4 {
1632                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1633                                                 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1634                                                 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1635                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1636                         };
1637
1638                         sdmmc_gpio: sdmmc-gpio {
1639                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1640                                                 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1641                                                 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1642                                                 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1643                                                 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1644                                                 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1645                                                 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1646                         };
1647                 };
1648
1649                 sdio0 {
1650                         sdio0_bus1: sdio0-bus1 {
1651                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1652                         };
1653
1654                         sdio0_bus4: sdio0-bus4 {
1655                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1656                                                 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1657                                                 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1658                                                 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1659                         };
1660
1661                         sdio0_cmd: sdio0-cmd {
1662                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1663                         };
1664
1665                         sdio0_clk: sdio0-clk {
1666                                 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1667                         };
1668
1669                         sdio0_dectn: sdio0-dectn {
1670                                 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1671                         };
1672
1673                         sdio0_wrprt: sdio0-wrprt {
1674                                 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1675                         };
1676
1677                         sdio0_pwren: sdio0-pwren {
1678                                 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1679                         };
1680
1681                         sdio0_bkpwr: sdio0-bkpwr {
1682                                 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1683                         };
1684
1685                         sdio0_int: sdio0-int {
1686                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1687                         };
1688
1689                         sdio0_gpio: sdio0-gpio {
1690                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1691                                                 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1692                                                 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1693                                                 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1694                                                 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1695                                                 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1696                                                 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1697                                                 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1698                                                 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1699                                                 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1700                                                 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1701                         };
1702                 };
1703
1704                 emmc {
1705                         emmc_clk: emmc-clk {
1706                                 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1707                         };
1708
1709                         emmc_cmd: emmc-cmd {
1710                                 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1711                         };
1712
1713                         emmc_pwren: emmc-pwren {
1714                                 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1715                         };
1716
1717                         emmc_rstnout: emmc_rstnout {
1718                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1719                         };
1720
1721                         emmc_bus1: emmc-bus1 {
1722                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1723                         };
1724
1725                         emmc_bus4: emmc-bus4 {
1726                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1727                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1728                                                 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1729                                                 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1730                         };
1731                 };
1732
1733                 pwm0 {
1734                         pwm0_pin: pwm0-pin {
1735                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1736                         };
1737
1738                         vop_pwm_pin:vop-pwm {
1739                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1740                         };
1741                 };
1742
1743                 pwm1 {
1744                         pwm1_pin: pwm1-pin {
1745                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1746                         };
1747                 };
1748
1749                 pwm3 {
1750                         pwm3_pin: pwm3-pin {
1751                                 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1752                         };
1753                 };
1754
1755                 lcdc {
1756                         lcdc_lcdc: lcdc-lcdc {
1757                                 rockchip,pins =
1758                                                 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1759                                                 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1760                                                 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1761                                                 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1762                                                 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1763                                                 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1764                                                 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1765                                                 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1766                                                 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1767                                                 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1768                                                 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1769                                                 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1770                                                 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1771                                                 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1772                                                 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1773                                                 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1774                                                 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1775                                                 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1776                         };
1777
1778                         lcdc_gpio: lcdc-gpio {
1779                                 rockchip,pins =
1780                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1781                                                 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1782                                                 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1783                                                 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1784                                                 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1785                                                 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1786                                                 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1787                                                 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1788                                                 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1789                                                 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1790                                                 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1791                                                 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1792                                                 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1793                                                 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1794                                                 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1795                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1796                                                 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1797                                                 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1798                         };
1799                 };
1800
1801                 isp {
1802                         cif_clkout: cif-clkout {
1803                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1804                         };
1805
1806                         isp_dvp_d2d9: isp-dvp-d2d9 {
1807                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1808                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1809                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1810                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1811                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1812                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1813                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1814                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1815                                                 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1816                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1817                                                 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1818                                                 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1819                         };
1820
1821                         isp_dvp_d0d1: isp-dvp-d0d1 {
1822                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1823                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1824                         };
1825
1826                         isp_dvp_d10d11:isp_d10d11       {
1827                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1828                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1829                         };
1830
1831                         isp_dvp_d0d7: isp-dvp-d0d7 {
1832                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1833                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1834                                                 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1835                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1836                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1837                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1838                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1839                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1840                         };
1841
1842                         isp_shutter: isp-shutter {
1843                                 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1844                                                 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1845                         };
1846
1847                         isp_flash_trigger: isp-flash-trigger {
1848                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1849                         };
1850
1851                         isp_prelight: isp-prelight {
1852                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1853                         };
1854
1855                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1856                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1857                         };
1858                 };
1859
1860                 gps {
1861                         gps_mag: gps-mag {
1862                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1863                         };
1864
1865                         gps_sig: gps-sig {
1866                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1867
1868                         };
1869
1870                         gps_rfclk: gps-rfclk {
1871                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1872                         };
1873                 };
1874
1875                 gmac {
1876                         mac_clk: mac-clk {
1877                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1878                         };
1879
1880                         mac_txpins: mac-txpins {
1881                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//TXD0
1882                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//TXD1
1883                                                 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//TXD2
1884                                                 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//TXD3
1885                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//TXEN
1886                                                 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>;//TXCLK
1887                         };
1888
1889                         mac_rxpins: mac-rxpins {
1890                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1891                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1892                                                 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1893                                                 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1894                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1895                                                 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//RXER
1896                                                 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1897                                                 <3 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;//COL
1898                         };
1899
1900                         mac_crs: mac-crs {
1901                                 rockchip,pins = <3 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>; //CRS
1902                         };
1903
1904                         mac_mdpins: mac-mdpins {
1905                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1906                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;//MDC
1907                         };
1908                 };
1909
1910                 tsadc_pin {
1911                         tsadc_int: tsadc-int {
1912                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
1913                         };
1914                         tsadc_gpio: tsadc-gpio {
1915                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
1916                         };
1917                 };
1918
1919                 hdmi_pin {
1920                         hdmi_cec: hdmi-cec {
1921                                 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1922                         };
1923                 };
1924
1925                 hdmi_i2c {
1926                         hdmii2c_xfer: hdmii2c-xfer {
1927                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
1928                                                 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1929                         };
1930                 };
1931         };
1932 };