arch/arm64/boot/dts/rk3368-fpga.dts

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/arm-gic.h>
   4 #include <dt-bindings/rkfb/rk_fb.h>
   5
   6 / {
   7         compatible = "rockchip,rk3368";
   8
   9         interrupt-parent = <&gic>;
  10         #address-cells = <2>;
  11         #size-cells = <2>;
  12
  13         xin24m: xin24m {
  14                 compatible = "fixed-clock";
  15                 #clock-cells = <0>;
  16                 clock-frequency = <24000000>;
  17                 clock-output-names = "xin24m";
  18         };
  19
  20         aliases {
  21                 serial2 = &uart_dbg;
  22         };
  23
  24         cpus {
  25                 #address-cells = <2>;
  26                 #size-cells = <0>;
  27
  28                 cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a53","arm,armv8";
  31                         reg = <0x0 0x0>;
  32                 };
  33         };
  34
  35         chosen {
  36                 bootargs = "console=ttyS2 earlyprintk=uart8250-32bit,0xff690000";
  37         };
  38
  39         timer {
  40                 compatible = "arm,armv8-timer";
  41                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
  42                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
  43                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
  44                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
  45                 clock-frequency = <24000000>;
  46         };
  47
  48         memory@00000000 {
  49                 device_type = "memory";
  50                 reg = <0x00000000 0x00000000 0x0 0x20000000>;
  51         };
  52
  53         uart_dbg: serial@ff690000 {
  54                 compatible = "rockchip,serial";
  55                 reg = <0x0 0xff690000 0x0 0x100>;
  56                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  57                 clock-frequency = <24000000>;
  58                 clocks = <&xin24m>, <&xin24m>;
  59                 clock-names = "sclk_uart", "pclk_uart";
  60                 reg-shift = <2>;
  61                 reg-io-width = <4>;
  62         };
  63
  64         gic: interrupt-controller@ffb70000 {
  65                 compatible = "arm,cortex-a15-gic";
  66                 #interrupt-cells = <3>;
  67                 #address-cells = <0>;
  68                 interrupt-controller;
  69                 reg = <0x0 0xffb71000 0 0x1000>,
  70                       <0x0 0xffb72000 0 0x1000>;
  71         };
  72
  73         ion {
  74                 compatible = "rockchip,ion";
  75                 #address-cells = <1>;
  76                 #size-cells = <0>;
  77
  78                 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
  79                         compatible = "rockchip,ion-heap";
  80                         rockchip,ion_heap = <1>;
  81                         reg = <0x00000000 0x08000000>; /* 512MB */
  82                 };
  83                 rockchip,ion-heap@3 { /* VMALLOC HEAP */
  84                         compatible = "rockchip,ion-heap";
  85                         rockchip,ion_heap = <3>;
  86                 };
  87         };
  88
  89         fb: fb {
  90                 compatible = "rockchip,rk-fb";
  91                 rockchip,disp-mode = <NO_DUAL>;
  92         };
  93
  94
  95         rk_screen: rk_screen {
  96                         compatible = "rockchip,screen";
  97                         disp_timings: display-timings {
  98                         native-mode = <&timing0>;
  99                         timing0: timing0 {
 100                                                 screen-type = <SCREEN_RGB>;
 101                                                 out-face    = <OUT_P888>;
 102                                                 color-mode = <COLOR_RGB>;
 103                                                 clock-frequency = <27000000>;
 104                                                 hactive = <800>;
 105                                                 vactive = <480>;
 106                                                 hback-porch = <206>;
 107                                                 hfront-porch = <1>;
 108                                                 vback-porch = <25>;
 109                                                 vfront-porch = <10>;
 110                                                 hsync-len = <10>;
 111                                                 vsync-len = <10>;
 112                                                 hsync-active = <0>;
 113                                                 vsync-active = <0>;
 114                                                 de-active = <0>;
 115                                                 pixelclk-active = <0>;
 116                                                 swap-rb = <0>;
 117                                                 swap-rg = <0>;
 118                                                 swap-gb = <0>;
 119                         };
 120                 };
 121         };
 122
 123         lvds: lvds@ff968000 {
 124                 compatible = "rockchip,rk3368-lvds";
 125                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600b0 0x0 0x01>;
 126                 //reg = <0xff968000 0x4000>, <0xff9600b0 0x01>;
 127                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 128                 //clocks = <&dummy>, <&dummy>;
 129                 //clock-names = "pclk_lvds", "pclk_lvds_ctl";
 130                 status = "okay";
 131         };
 132
 133         lcdc: lcdc@ff930000 {
 134                 compatible = "rockchip,rk3368-lcdc";
 135                 rockchip,prop = <PRMRY>;
 136                 rockchip,pwr18 = <0>;
 137                 rockchip,iommu-enabled = <0>;
 138                 //reg = <0xff930000 0x10000>;
 139                 reg = <0x0 0xff930000 0x0 0x10000>;
 140                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 141                 //pinctrl-names = "default", "gpio";
 142                 //pinctrl-0 = <&lcdc_lcdc>;
 143                 //pinctrl-1 = <&lcdc_gpio>;
 144                 status = "okay";
 145                 //clocks = <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>;
 146                 //clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc", "sclk_lcdc";
 147                 power_ctr: power_ctr {
 148                 rockchip,debug = <0>;
 149                 /*
 150                 lcd_en:lcd_en {
 151                         rockchip,power_type = <GPIO>;
 152                         gpios = <&gpio7 GPIO_A3 GPIO_ACTIVE_HIGH>;
 153                         rockchip,delay = <10>;
 154                 };
 155                 */
 156                 /*lcd_cs:lcd_cs {
 157                         rockchip,power_type = <REGULATOR>;
 158                         rockchip,delay = <10>;
 159                 };
 160
 161                 lcd_rst:lcd_rst {
 162                         rockchip,power_type = <GPIO>;
 163                         gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
 164                         rockchip,delay = <5>;
 165                 };*/
 166                 };
 167         };
 168 };