arch/arm64/boot/dts/rk3368-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014-2015 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk3368.h>
  15
  16
  17
  18 /{
  19         clocks {
  20                 compatible = "rockchip,rk-clocks";
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23                 ranges;
  24
  25                 fixed_rate_cons {
  26                         compatible = "rockchip,rk-fixed-rate-cons";
  27
  28                         xin24m: xin24m {
  29                                 compatible = "rockchip,rk-fixed-clock";
  30                                 clock-output-names = "xin24m";
  31                                 clock-frequency = <24000000>;
  32                                 #clock-cells = <0>;
  33                         };
  34
  35                         xin12m: xin12m {
  36                                 compatible = "rockchip,rk-fixed-clock";
  37                                 clocks = <&xin24m>;
  38                                 clock-output-names = "xin12m";
  39                                 clock-frequency = <12000000>;
  40                                 #clock-cells = <0>;
  41                         };
  42
  43                         xin32k: xin32k {
  44                                 compatible = "rockchip,rk-fixed-clock";
  45                                 clock-output-names = "xin32k";
  46                                 clock-frequency = <32000>;
  47                                 #clock-cells = <0>;
  48                         };
  49
  50                         dummy: dummy {
  51                                 compatible = "rockchip,rk-fixed-clock";
  52                                 clock-output-names = "dummy";
  53                                 clock-frequency = <0>;
  54                                 #clock-cells = <0>;
  55                         };
  56
  57                         jtag_clkin: jtag_clkin {
  58                                 compatible = "rockchip,rk-fixed-clock";
  59                                 clock-output-names = "jtag_clkin";
  60                                 clock-frequency = <0>;
  61                                 #clock-cells = <0>;
  62                         };
  63
  64                         gmac_clkin: gmac_clkin {
  65                                 compatible = "rockchip,rk-fixed-clock";
  66                                 clock-output-names = "gmac_clkin";
  67                                 clock-frequency = <0>;
  68                                 #clock-cells = <0>;
  69                         };
  70
  71                         pclkin_isp: pclkin_isp {
  72                                 compatible = "rockchip,rk-fixed-clock";
  73                                 clock-output-names = "pclkin_isp";
  74                                 clock-frequency = <0>;
  75                                 #clock-cells = <0>;
  76                         };
  77
  78                         pclkin_vip: pclkin_vip {
  79                                 compatible = "rockchip,rk-fixed-clock";
  80                                 clock-output-names = "pclkin_vip";
  81                                 clock-frequency = <0>;
  82                                 #clock-cells = <0>;
  83                         };
  84
  85                         clkin_hsadc_tsp: clkin_hsadc_tsp {
  86                                 compatible = "rockchip,rk-fixed-clock";
  87                                 clock-output-names = "clkin_hsadc_tsp";
  88                                 clock-frequency = <0>;
  89                                 #clock-cells = <0>;
  90                         };
  91
  92                         i2s_clkin: i2s_clkin {
  93                                 compatible = "rockchip,rk-fixed-clock";
  94                                 clock-output-names = "i2s_clkin";
  95                                 clock-frequency = <0>;
  96                                 #clock-cells = <0>;
  97                         };
  98                 };
  99
 100                 fixed_factor_cons {
 101                         compatible = "rockchip,rk-fixed-factor-cons";
 102
 103                         hclk_vepu: hclk_vepu {
 104                                 compatible = "rockchip,rk-fixed-factor-clock";
 105                                 clocks = <&aclk_vepu>;
 106                                 clock-output-names = "hclk_vepu";
 107                                 clock-div = <4>;
 108                                 clock-mult = <1>;
 109                                 #clock-cells = <0>;
 110                         };
 111
 112                         hclk_vdpu: hclk_vdpu {
 113                                 compatible = "rockchip,rk-fixed-factor-clock";
 114                                 clocks = <&aclk_vdpu>;
 115                                 clock-output-names = "hclk_vdpu";
 116                                 clock-div = <4>;
 117                                 clock-mult = <1>;
 118                                 #clock-cells = <0>;
 119                         };
 120
 121                         usbotg_480m_out: usbotg_480m_out {
 122                                 compatible = "rockchip,rk-fixed-factor-clock";
 123                                 clocks = <&clk_gates8 1>;
 124                                 clock-output-names = "usbotg_480m_out";
 125                                 clock-div = <1>;
 126                                 clock-mult = <20>;
 127                                 #clock-cells = <0>;
 128                         };
 129
 130                         pclkin_isp_inv: pclkin_isp_inv {
 131                                 compatible = "rockchip,rk-fixed-factor-clock";
 132                                 clocks = <&clk_gates17 2>;
 133                                 clock-output-names = "pclkin_isp_inv";
 134                                 clock-div = <1>;
 135                                 clock-mult = <1>;
 136                                 #clock-cells = <0>;
 137                         };
 138
 139                         pclkin_vip_inv: pclkin_vip_inv {
 140                                 compatible = "rockchip,rk-fixed-factor-clock";
 141                                 clocks = <&clk_gates16 13>;
 142                                 clock-output-names = "pclkin_vip_inv";
 143                                 clock-div = <1>;
 144                                 clock-mult = <1>;
 145                                 #clock-cells = <0>;
 146                         };
 147
 148                         pclk_vio: pclk_vio {
 149                                 compatible = "rockchip,rk-fixed-factor-clock";
 150                                 clocks = <&clk_gates16 8>;
 151                                 clock-output-names = "pclk_vio";
 152                                 clock-div = <1>;
 153                                 clock-mult = <1>;
 154                                 #clock-cells = <0>;
 155                         };
 156                 };
 157
 158                 clock_regs {
 159                         compatible = "rockchip,rk-clock-regs";
 160                         #address-cells = <1>;
 161                         #size-cells = <1>;
 162                         ranges = <0x0 0xFF760000 0x0264>;
 163                         reg = <0xFF760000 0x0264>;/* NEED CONFIRM */
 164
 165                         /* PLL control regs */
 166                         pll_cons {
 167                                 compatible = "rockchip,rk-pll-cons";
 168                                 #address-cells = <1>;
 169                                 #size-cells = <1>;
 170                                 ranges;
 171
 172                                 clk_apllb: pll-clk@0000 {
 173                                         compatible = "rockchip,rk3188-pll-clk";
 174                                         reg = <0x0000 0x10>;
 175                                         mode-reg = <0x000c 8>;
 176                                         status-reg = <0x0480 1>;
 177                                         clocks = <&xin24m>;
 178                                         clock-output-names = "clk_apllb";
 179                                         rockchip,pll-type = <CLK_PLL_3368_APLLB>;
 180                                         #clock-cells = <0>;
 181                                 };
 182
 183
 184                                 clk_aplll: pll-clk@0010 {
 185                                         compatible = "rockchip,rk3188-pll-clk";
 186                                         reg = <0x0010 0x10>;
 187                                         mode-reg = <0x001c 8>;
 188                                         status-reg = <0x0480 0>;
 189                                         clocks = <&xin24m>;
 190                                         clock-output-names = "clk_aplll";
 191                                         rockchip,pll-type = <CLK_PLL_3368_APLLL>;
 192                                         #clock-cells = <0>;
 193                                 };
 194
 195                                 clk_dpll: pll-clk@0020 {
 196                                         compatible = "rockchip,rk3188-pll-clk";
 197                                         reg = <0x0020 0x10>;
 198                                         mode-reg = <0x002c 8>;
 199                                         status-reg = <0x0480 2>;
 200                                         clocks = <&xin24m>;
 201                                         clock-output-names = "clk_dpll";
 202                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 203                                         #clock-cells = <0>;
 204                                 };
 205
 206
 207                                 clk_cpll: pll-clk@0030 {
 208                                         compatible = "rockchip,rk3188-pll-clk";
 209                                         reg = <0x0030 0x10>;
 210                                         mode-reg = <0x003c 8>;
 211                                         status-reg = <0x0480 3>;
 212                                         clocks = <&xin24m>;
 213                                         clock-output-names = "clk_cpll";
 214                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 215                                         #clock-cells = <0>;
 216                                         #clock-init-cells = <1>;
 217                                 };
 218
 219                                 clk_gpll: pll-clk@0040 {
 220                                         compatible = "rockchip,rk3188-pll-clk";
 221                                         reg = <0x0040 0x10>;
 222                                         mode-reg = <0x004c 8>;
 223                                         status-reg = <0x0480 4>;
 224                                         clocks = <&xin24m>;
 225                                         clock-output-names = "clk_gpll";
 226                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 227                                         #clock-cells = <0>;
 228                                         #clock-init-cells = <1>;
 229                                 };
 230
 231                                 clk_npll: pll-clk@0050 {
 232                                         compatible = "rockchip,rk3188-pll-clk";
 233                                         reg = <0x0050 0x10>;
 234                                         mode-reg = <0x005c 8>;
 235                                         status-reg = <0x0480 5>;
 236                                         clocks = <&xin24m>;
 237                                         clock-output-names = "clk_npll";
 238                                         rockchip,pll-type = <CLK_PLL_3188PLUS_AUTO>;
 239                                         #clock-cells = <0>;
 240                                         #clock-init-cells = <1>;
 241                                 };
 242                         };
 243
 244                         /* Select control regs */
 245                         clk_sel_cons {
 246                                 compatible = "rockchip,rk-sel-cons";
 247                                 #address-cells = <1>;
 248                                 #size-cells = <1>;
 249                                 ranges;
 250
 251                                 clk_sel_con0: sel-con@0100 {
 252                                         compatible = "rockchip,rk3188-selcon";
 253                                         reg = <0x0100 0x4>;
 254                                         #address-cells = <1>;
 255                                         #size-cells = <1>;
 256
 257                                         clk_core_b_div: clk_core_b_div {
 258                                                 compatible = "rockchip,rk3188-div-con";
 259                                                 rockchip,bits = <0 5>;
 260                                                 clocks = <&clk_core_b>;
 261                                                 clock-output-names = "clk_core_b";
 262                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 263                                                 #clock-cells = <0>;
 264                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 265                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 266                                                                         CLK_SET_RATE_NO_REPARENT)>;
 267                                         };
 268
 269                                         /* 6:5 reserved */
 270
 271                                         clk_core_b: clk_core_b_mux {
 272                                                 compatible = "rockchip,rk3188-mux-con";
 273                                                 rockchip,bits = <7 1>;
 274                                                 clocks = <&clk_apllb>, <&clk_gpll>;
 275                                                 clock-output-names = "clk_core_b";
 276                                                 #clock-cells = <0>;
 277                                                 #clock-init-cells = <1>;
 278                                         };
 279
 280                                         aclkm_core_b: aclkm_core_b_div {
 281                                                 compatible = "rockchip,rk3188-div-con";
 282                                                 rockchip,bits = <8 5>;
 283                                                 clocks = <&clk_core_b>;
 284                                                 clock-output-names = "aclkm_core_b";
 285                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 286                                                 #clock-cells = <0>;
 287                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 288                                         };
 289
 290                                         /* 15:13 reserved */
 291                                 };
 292
 293                                 clk_sel_con1: sel-con@0104 {
 294                                         compatible = "rockchip,rk3188-selcon";
 295                                         reg = <0x0104 0x4>;
 296                                         #address-cells = <1>;
 297                                         #size-cells = <1>;
 298
 299                                         atclk_core_b: atclk_core_b_div {
 300                                                 compatible = "rockchip,rk3188-div-con";
 301                                                 rockchip,bits = <0 5>;
 302                                                 clocks = <&clk_core_b>;
 303                                                 clock-output-names = "atclk_core_b";
 304                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 305                                                 #clock-cells = <0>;
 306                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 307                                         };
 308
 309                                         /* 7:5 reserved */
 310
 311                                         pclk_dbg_b: pclk_dbg_b_div {
 312                                                 compatible = "rockchip,rk3188-div-con";
 313                                                 rockchip,bits = <8 5>;
 314                                                 clocks = <&clk_core_b>;
 315                                                 clock-output-names = "pclk_dbg_b";
 316                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 317                                                 #clock-cells = <0>;
 318                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 319                                         };
 320                                 };
 321
 322                                 clk_sel_con2: sel-con@0108 {
 323                                         compatible = "rockchip,rk3188-selcon";
 324                                         reg = <0x0108 0x4>;
 325                                         #address-cells = <1>;
 326                                         #size-cells = <1>;
 327
 328                                         clk_core_l_div: clk_core_l_div {
 329                                                 compatible = "rockchip,rk3188-div-con";
 330                                                 rockchip,bits = <0 5>;
 331                                                 clocks = <&clk_core_l>;
 332                                                 clock-output-names = "clk_core_l";
 333                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 334                                                 #clock-cells = <0>;
 335                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 336                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 337                                                                         CLK_SET_RATE_NO_REPARENT)>;
 338                                         };
 339
 340                                         /* 6:5 reserved */
 341
 342                                         clk_core_l: clk_core_l_mux {
 343                                                 compatible = "rockchip,rk3188-mux-con";
 344                                                 rockchip,bits = <7 1>;
 345                                                 clocks = <&clk_aplll>, <&clk_gpll>;
 346                                                 clock-output-names = "clk_core_l";
 347                                                 #clock-cells = <0>;
 348                                                 #clock-init-cells = <1>;
 349                                         };
 350
 351                                         aclkm_core_l: aclkm_core_l_div {
 352                                                 compatible = "rockchip,rk3188-div-con";
 353                                                 rockchip,bits = <8 5>;
 354                                                 clocks = <&clk_core_l>;
 355                                                 clock-output-names = "aclkm_core_l";
 356                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 357                                                 #clock-cells = <0>;
 358                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 359                                         };
 360
 361                                         /* 15:13 reserved */
 362                                 };
 363
 364                                 clk_sel_con3: sel-con@010c {
 365                                         compatible = "rockchip,rk3188-selcon";
 366                                         reg = <0x010c 0x4>;
 367                                         #address-cells = <1>;
 368                                         #size-cells = <1>;
 369
 370                                         atclk_core_l: atclk_core_l_div {
 371                                                 compatible = "rockchip,rk3188-div-con";
 372                                                 rockchip,bits = <0 5>;
 373                                                 clocks = <&clk_core_l>;
 374                                                 clock-output-names = "atclk_core_l";
 375                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 376                                                 #clock-cells = <0>;
 377                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 378                                         };
 379
 380                                         /* 7:5 reserved */
 381
 382                                         pclk_dbg_l: pclk_dbg_l_div {
 383                                                 compatible = "rockchip,rk3188-div-con";
 384                                                 rockchip,bits = <8 5>;
 385                                                 clocks = <&clk_core_l>;
 386                                                 clock-output-names = "pclk_dbg_l";
 387                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 388                                                 #clock-cells = <0>;
 389                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 390                                         };
 391                                 };
 392
 393                                 clk_sel_con4: sel-con@0110 {
 394                                         compatible = "rockchip,rk3188-selcon";
 395                                         reg = <0x0110 0x4>;
 396                                         #address-cells = <1>;
 397                                         #size-cells = <1>;
 398
 399                                         clk_cs_div: clk_cs_div {
 400                                                 compatible = "rockchip,rk3188-div-con";
 401                                                 rockchip,bits = <0 5>;
 402                                                 clocks = <&clk_cs>;
 403                                                 clock-output-names = "clk_cs";
 404                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 405                                                 #clock-cells = <0>;
 406                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 407                                         };
 408
 409                                         /* 5 reserved */
 410
 411                                         clk_cs: clk_cs_mux {
 412                                                 compatible = "rockchip,rk3188-mux-con";
 413                                                 rockchip,bits = <6 2>;
 414                                                 clocks = <&clk_gates0 9>, <&clk_gates0 10>, <&clk_gates0 8>, <&dummy>;
 415                                                 clock-output-names = "clk_cs";
 416                                                 #clock-cells = <0>;
 417                                                 #clock-init-cells = <1>;
 418                                         };
 419
 420                                         clkin_trace: clkin_trace_div {
 421                                                 compatible = "rockchip,rk3188-div-con";
 422                                                 rockchip,bits = <8 5>;
 423                                                 clocks = <&clk_cs>;
 424                                                 clock-output-names = "clkin_trace";
 425                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 426                                                 #clock-cells = <0>;
 427                                         };
 428
 429                                 };
 430
 431                                 clk_sel_con5: sel-con@0114 {
 432                                         compatible = "rockchip,rk3188-selcon";
 433                                         reg = <0x0114 0x4>;
 434                                         #address-cells = <1>;
 435                                         #size-cells = <1>;
 436
 437                                         aclk_cci_div: aclk_cci_div {
 438                                                 compatible = "rockchip,rk3188-div-con";
 439                                                 rockchip,bits = <0 5>;
 440                                                 clocks = <&aclk_cci>;
 441                                                 clock-output-names = "aclk_cci";
 442                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 443                                                 #clock-cells = <0>;
 444                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 445                                         };
 446
 447                                         /* 5 reserved */
 448
 449                                         aclk_cci: aclk_cci_mux {
 450                                                 compatible = "rockchip,rk3188-mux-con";
 451                                                 rockchip,bits = <6 2>;
 452                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
 453                                                 clock-output-names = "aclk_cci";
 454                                                 #clock-cells = <0>;
 455                                                 #clock-init-cells = <1>;
 456                                         };
 457                                 };
 458
 459                                 /* sel[7:6] reserved */
 460
 461                                 clk_sel_con8: sel-con@0120 {
 462                                         compatible = "rockchip,rk3188-selcon";
 463                                         reg = <0x0120 0x4>;
 464                                         #address-cells = <1>;
 465                                         #size-cells = <1>;
 466
 467                                         aclk_bus_div: aclk_bus_div {
 468                                                 compatible = "rockchip,rk3188-div-con";
 469                                                 rockchip,bits = <0 5>;
 470                                                 clocks = <&aclk_bus>;
 471                                                 clock-output-names = "aclk_bus_div";
 472                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 473                                                 #clock-cells = <0>;
 474                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 475                                         };
 476
 477                                         /* 6:5 reserved */
 478
 479                                         aclk_bus: aclk_bus_mux {
 480                                                 compatible = "rockchip,rk3188-mux-con";
 481                                                 rockchip,bits = <7 1>;
 482                                                 clocks = <&clk_gates1 11>, <&clk_gates1 10>;
 483                                                 clock-output-names = "aclk_bus";
 484                                                 #clock-cells = <0>;
 485                                                 #clock-init-cells = <1>;
 486                                         };
 487
 488                                         hclk_bus: hclk_bus_div {
 489                                                 compatible = "rockchip,rk3188-div-con";
 490                                                 rockchip,bits = <8 2>;
 491                                                 clocks = <&aclk_bus>;
 492                                                 clock-output-names = "hclk_bus";
 493                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 494                                                 #clock-cells = <0>;
 495                                                 #clock-init-cells = <1>;
 496                                         };
 497
 498                                         /* 11:10 reserved */
 499
 500                                         pclk_bus: pclk_bus_div {
 501                                                 compatible = "rockchip,rk3188-div-con";
 502                                                 rockchip,bits = <12 3>;
 503                                                 clocks = <&aclk_bus>;
 504                                                 clock-output-names = "pclk_bus";
 505                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 506                                                 #clock-cells = <0>;
 507                                                 #clock-init-cells = <1>;
 508                                         };
 509                                 };
 510
 511                                 clk_sel_con9: sel-con@0124 {
 512                                         compatible = "rockchip,rk3188-selcon";
 513                                         reg = <0x0124 0x4>;
 514                                         #address-cells = <1>;
 515                                         #size-cells = <1>;
 516
 517                                         aclk_peri_div: aclk_peri_div {
 518                                                 compatible = "rockchip,rk3188-div-con";
 519                                                 rockchip,bits = <0 5>;
 520                                                 clocks = <&aclk_peri>;
 521                                                 clock-output-names = "aclk_peri_div";
 522                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 523                                                 #clock-cells = <0>;
 524                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 525                                         };
 526
 527                                         /* 6:5 reserved */
 528
 529                                         aclk_peri: aclk_peri_mux {
 530                                                 compatible = "rockchip,rk3188-mux-con";
 531                                                 rockchip,bits = <7 1>;
 532                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 533                                                 clock-output-names = "aclk_peri";
 534                                                 #clock-cells = <0>;
 535                                                 #clock-init-cells = <1>;
 536                                         };
 537
 538                                         hclk_peri: hclk_peri_div {
 539                                                 compatible = "rockchip,rk3188-div-con";
 540                                                 rockchip,bits = <8 2>;
 541                                                 clocks = <&aclk_peri>;
 542                                                 clock-output-names = "hclk_peri";
 543                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 544                                                 rockchip,div-relations =
 545                                                                 <0x0 1
 546                                                                  0x1 2
 547                                                                  0x2 4>;
 548                                                 #clock-cells = <0>;
 549                                                 #clock-init-cells = <1>;
 550                                         };
 551
 552                                         /* 11:10 reserved */
 553
 554                                         pclk_peri: pclk_peri_div {
 555                                                 compatible = "rockchip,rk3188-div-con";
 556                                                 rockchip,bits = <12 2>;
 557                                                 clocks = <&aclk_peri>;
 558                                                 clock-output-names = "pclk_peri";
 559                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 560                                                 rockchip,div-relations =
 561                                                                 <0x0 1
 562                                                                  0x1 2
 563                                                                  0x2 4
 564                                                                  0x3 8>;
 565                                                 #clock-cells = <0>;
 566                                                 #clock-init-cells = <1>;
 567                                         };
 568                                 };
 569
 570                                 clk_sel_con10: sel-con@0128 {
 571                                         compatible = "rockchip,rk3188-selcon";
 572                                         reg = <0x0128 0x4>;
 573                                         #address-cells = <1>;
 574                                         #size-cells = <1>;
 575
 576                                         pclk_pmu_pre: pclk_pmu_pre_div {
 577                                                 compatible = "rockchip,rk3188-div-con";
 578                                                 rockchip,bits = <0 5>;
 579                                                 clocks = <&clk_gpll>;
 580                                                 clock-output-names = "pclk_pmu_pre";
 581                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 582                                                 #clock-cells = <0>;
 583                                         };
 584
 585                                         /* 7:5 reserved */
 586
 587                                         pclk_alive_pre: pclk_alive_pre_div {
 588                                                 compatible = "rockchip,rk3188-div-con";
 589                                                 rockchip,bits = <8 5>;
 590                                                 clocks = <&clk_gpll>;
 591                                                 clock-output-names = "pclk_alive_pre";
 592                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 593                                                 #clock-cells = <0>;
 594                                         };
 595
 596                                         /* 13 reserved */
 597
 598                                         clk_crypto: clk_crypto_div {
 599                                                 compatible = "rockchip,rk3188-div-con";
 600                                                 rockchip,bits = <14 2>;
 601                                                 clocks = <&aclk_bus>;
 602                                                 clock-output-names = "clk_crypto";
 603                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 604                                                 #clock-cells = <0>;
 605                                                 #clock-init-cells = <1>;
 606                                         };
 607                                 };
 608
 609                                 /* sel[11]: reserved */
 610
 611                                 clk_sel_con12: sel-con@0130 {
 612                                         compatible = "rockchip,rk3188-selcon";
 613                                         reg = <0x0130 0x4>;
 614                                         #address-cells = <1>;
 615                                         #size-cells = <1>;
 616
 617                                         fclk_mcu_div: fclk_mcu_div {
 618                                                 compatible = "rockchip,rk3188-div-con";
 619                                                 rockchip,bits = <0 5>;
 620                                                 clocks = <&fclk_mcu>;
 621                                                 clock-output-names = "fclk_mcu";
 622                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 623                                                 #clock-cells = <0>;
 624                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 625                                         };
 626
 627                                         /* 6:5 reserved */
 628
 629                                         fclk_mcu: fclk_mcu_mux {
 630                                                 compatible = "rockchip,rk3188-mux-con";
 631                                                 rockchip,bits = <7 1>;
 632                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 633                                                 clock-output-names = "fclk_mcu";
 634                                                 #clock-cells = <0>;
 635                                                 #clock-init-cells = <1>;
 636                                         };
 637
 638                                         stclk_mcu: stclk_mcu_div {
 639                                                 compatible = "rockchip,rk3188-div-con";
 640                                                 rockchip,bits = <8 3>;
 641                                                 clocks = <&fclk_mcu>;
 642                                                 clock-output-names = "stclk_mcu";
 643                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 644                                                 #clock-cells = <0>;
 645                                         };
 646                                 };
 647
 648                                 clk_sel_con13: sel-con@0134 {
 649                                         compatible = "rockchip,rk3188-selcon";
 650                                         reg = <0x0134 0x4>;
 651                                         #address-cells = <1>;
 652                                         #size-cells = <1>;
 653
 654                                         clk_ddr_div: clk_ddr_div {
 655                                                 compatible = "rockchip,rk3188-div-con";
 656                                                 rockchip,bits = <0 2>;
 657                                                 clocks = <&clk_ddr>;
 658                                                 clock-output-names = "clk_ddr";
 659                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 660                                                 #clock-cells = <0>;
 661                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 662                                                                         CLK_SET_RATE_NO_REPARENT)>;
 663                                                 rockchip,clkops-idx =
 664                                                         <CLKOPS_RATE_DDR_DIV4>;
 665                                         };
 666
 667                                         /* 3:2 reserved */
 668
 669                                         clk_ddr: clk_ddr_mux {
 670                                                 compatible = "rockchip,rk3188-mux-con";
 671                                                 rockchip,bits = <4 1>;
 672                                                 clocks = <&clk_dpll>, <&clk_gpll>;
 673                                                 clock-output-names = "clk_ddr";
 674                                                 #clock-cells = <0>;
 675                                         };
 676
 677                                         /* 7:5 reserved */
 678
 679                                         /* usbphy_480m_en */
 680
 681                                         usbphy_480m: usbphy_480m_mux {
 682                                                 compatible = "rockchip,rk3188-mux-con";
 683                                                 rockchip,bits = <8 1>;
 684                                                 clocks = <&xin24m>, <&usbotg_480m_out>;
 685                                                 clock-output-names = "usbphy_480m";
 686                                                 #clock-cells = <0>;
 687                                                 rockchip,clkops-idx =
 688                                                         <CLKOPS_RATE_RK3288_USB480M>;
 689                                                 #clock-init-cells = <1>;
 690                                         };
 691
 692                                         clk4x_ddr: clk4x_ddr_mux {
 693                                                 compatible = "rockchip,rk3188-mux-con";
 694                                                 rockchip,bits = <4 1>;
 695                                                 clocks = <&clk_dpll>, <&clk_gpll>;
 696                                                 clock-output-names = "clk4x_ddr";
 697                                                 #clock-cells = <0>;
 698                                         };
 699                                 };
 700
 701                                 clk_sel_con14: sel-con@0138 {
 702                                         compatible = "rockchip,rk3188-selcon";
 703                                         reg = <0x0138 0x4>;
 704                                         #address-cells = <1>;
 705                                         #size-cells = <1>;
 706
 707                                         clk_gpu_core_div: clk_gpu_core_div {
 708                                                 compatible = "rockchip,rk3188-div-con";
 709                                                 rockchip,bits = <0 5>;
 710                                                 clocks = <&clk_gpu_core>;
 711                                                 clock-output-names = "clk_gpu_core";
 712                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 713                                                 #clock-cells = <0>;
 714                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 715                                                 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
 716                                         };
 717
 718                                         /* 5 reserved */
 719
 720                                         clk_gpu_core: clk_gpu_core_mux {
 721                                                 compatible = "rockchip,rk3188-mux-con";
 722                                                 rockchip,bits = <6 2>;
 723                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
 724                                                 clock-output-names = "clk_gpu_core";
 725                                                 #clock-cells = <0>;
 726                                                 #clock-init-cells = <1>;
 727                                         };
 728
 729                                         aclk_gpu_mem: aclk_gpu_mem_div {
 730                                                 compatible = "rockchip,rk3188-div-con";
 731                                                 rockchip,bits = <8 5>;
 732                                                 clocks = <&aclk_gpu>;
 733                                                 clock-output-names = "aclk_gpu_mem";
 734                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 735                                                 #clock-cells = <0>;
 736                                         };
 737
 738                                         /* 13 reserved */
 739
 740                                         aclk_gpu: aclk_gpu_mux {
 741                                                 compatible = "rockchip,rk3188-mux-con";
 742                                                 rockchip,bits = <14 1>;
 743                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 744                                                 clock-output-names = "aclk_gpu";
 745                                                 #clock-cells = <0>;
 746                                                 #clock-init-cells = <1>;
 747                                         };
 748                                 };
 749
 750                                 clk_sel_con15: sel-con@013c {
 751                                         compatible = "rockchip,rk3188-selcon";
 752                                         reg = <0x013c 0x4>;
 753                                         #address-cells = <1>;
 754                                         #size-cells = <1>;
 755
 756                                         aclk_vepu_div: aclk_vepu_div {
 757                                                 compatible = "rockchip,rk3188-div-con";
 758                                                 rockchip,bits = <0 5>;
 759                                                 clocks = <&aclk_vepu>;
 760                                                 clock-output-names = "aclk_vepu";
 761                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 762                                                 #clock-cells = <0>;
 763                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 764                                         };
 765
 766                                         /* 5 reserved */
 767
 768                                         aclk_vepu: aclk_vepu_mux {
 769                                                 compatible = "rockchip,rk3188-mux-con";
 770                                                 rockchip,bits = <6 2>;
 771                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 772                                                 clock-output-names = "aclk_vepu";
 773                                                 #clock-cells = <0>;
 774                                                 #clock-init-cells = <1>;
 775                                         };
 776
 777                                         aclk_vdpu_div: aclk_vdpu_div {
 778                                                 compatible = "rockchip,rk3188-div-con";
 779                                                 rockchip,bits = <8 5>;
 780                                                 clocks = <&aclk_vdpu>;
 781                                                 clock-output-names = "aclk_vdpu";
 782                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 783                                                 #clock-cells = <0>;
 784                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 785                                         };
 786
 787                                         /* 13 reserved */
 788
 789                                         aclk_vdpu: aclk_vdpu_mux {
 790                                                 compatible = "rockchip,rk3188-mux-con";
 791                                                 rockchip,bits = <14 2>;
 792                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 793                                                 clock-output-names = "aclk_vdpu";
 794                                                 #clock-cells = <0>;
 795                                                 #clock-init-cells = <1>;
 796                                         };
 797                                 };
 798
 799                                 clk_sel_con16: sel-con@0140 {
 800                                         compatible = "rockchip,rk3188-selcon";
 801                                         reg = <0x0140 0x4>;
 802                                         #address-cells = <1>;
 803                                         #size-cells = <1>;
 804
 805                                         aclk_gpu_cfg: aclk_gpu_cfg_div {
 806                                                 compatible = "rockchip,rk3188-div-con";
 807                                                 rockchip,bits = <8 5>;
 808                                                 clocks = <&aclk_gpu>;
 809                                                 clock-output-names = "aclk_gpu_cfg";
 810                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 811                                                 #clock-cells = <0>;
 812                                         };
 813                                 };
 814
 815                                 clk_sel_con17: sel-con@0144 {
 816                                         compatible = "rockchip,rk3188-selcon";
 817                                         reg = <0x0144 0x4>;
 818                                         #address-cells = <1>;
 819                                         #size-cells = <1>;
 820
 821                                         clk_hevc_cabac_div: clk_hevc_cabac_div {
 822                                                 compatible = "rockchip,rk3188-div-con";
 823                                                 rockchip,bits = <0 5>;
 824                                                 clocks = <&clk_hevc_cabac>;
 825                                                 clock-output-names = "clk_hevc_cabac";
 826                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 827                                                 #clock-cells = <0>;
 828                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 829                                         };
 830
 831                                         /* 5 reserved */
 832
 833                                         clk_hevc_cabac: clk_hevc_cabac_mux {
 834                                                 compatible = "rockchip,rk3188-mux-con";
 835                                                 rockchip,bits = <6 2>;
 836                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 837                                                 clock-output-names = "clk_hevc_cabac";
 838                                                 #clock-cells = <0>;
 839                                                 #clock-init-cells = <1>;
 840                                         };
 841
 842                                         clk_hevc_core_div: clk_hevc_core_div {
 843                                                 compatible = "rockchip,rk3188-div-con";
 844                                                 rockchip,bits = <8 5>;
 845                                                 clocks = <&clk_hevc_core>;
 846                                                 clock-output-names = "clk_hevc_core";
 847                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 848                                                 #clock-cells = <0>;
 849                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 850                                         };
 851
 852                                         /* 13 reserved */
 853
 854                                         clk_hevc_core: clk_hevc_core_mux {
 855                                                 compatible = "rockchip,rk3188-mux-con";
 856                                                 rockchip,bits = <14 2>;
 857                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 858                                                 clock-output-names = "clk_hevc_core";
 859                                                 #clock-cells = <0>;
 860                                                 #clock-init-cells = <1>;
 861                                         };
 862                                 };
 863
 864                                 clk_sel_con18: sel-con@0148 {
 865                                         compatible = "rockchip,rk3188-selcon";
 866                                         reg = <0x0148 0x4>;
 867                                         #address-cells = <1>;
 868                                         #size-cells = <1>;
 869
 870                                         clk_rga_div: clk_rga_div {
 871                                                 compatible = "rockchip,rk3188-div-con";
 872                                                 rockchip,bits = <0 5>;
 873                                                 clocks = <&clk_rga>;
 874                                                 clock-output-names = "clk_rga";
 875                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 876                                                 #clock-cells = <0>;
 877                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 878                                         };
 879
 880                                         /* 5 reserved */
 881
 882                                         clk_rga: clk_rga_mux {
 883                                                 compatible = "rockchip,rk3188-mux-con";
 884                                                 rockchip,bits = <6 2>;
 885                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
 886                                                 clock-output-names = "clk_rga";
 887                                                 #clock-cells = <0>;
 888                                                 #clock-init-cells = <1>;
 889                                         };
 890
 891                                         aclk_rga_div: aclk_rga_div {
 892                                                 compatible = "rockchip,rk3188-div-con";
 893                                                 rockchip,bits = <8 5>;
 894                                                 clocks = <&aclk_rga_pre>;
 895                                                 clock-output-names = "aclk_rga_pre";
 896                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 897                                                 #clock-cells = <0>;
 898                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 899                                         };
 900
 901                                         /* 13 reserved */
 902
 903                                         aclk_rga_pre: aclk_rga_mux {
 904                                                 compatible = "rockchip,rk3188-mux-con";
 905                                                 rockchip,bits = <14 2>;
 906                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
 907                                                 clock-output-names = "aclk_rga_pre";
 908                                                 #clock-cells = <0>;
 909                                                 #clock-init-cells = <1>;
 910                                         };
 911                                 };
 912
 913                                 clk_sel_con19: sel-con@014c {
 914                                         compatible = "rockchip,rk3188-selcon";
 915                                         reg = <0x014c 0x4>;
 916                                         #address-cells = <1>;
 917                                         #size-cells = <1>;
 918
 919                                         aclk_vio0_div: aclk_vio0_div {
 920                                                 compatible = "rockchip,rk3188-div-con";
 921                                                 rockchip,bits = <0 5>;
 922                                                 clocks = <&aclk_vio0>;
 923                                                 clock-output-names = "aclk_vio0";
 924                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 925                                                 #clock-cells = <0>;
 926                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 927                                         };
 928
 929                                         /* 5 reserved */
 930
 931                                         aclk_vio0: aclk_vio0_mux {
 932                                                 compatible = "rockchip,rk3188-mux-con";
 933                                                 rockchip,bits = <6 2>;
 934                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
 935                                                 clock-output-names = "aclk_vio0";
 936                                                 #clock-cells = <0>;
 937                                                 #clock-init-cells = <1>;
 938                                         };
 939                                 };
 940
 941                                 clk_sel_con20: sel-con@0150 {
 942                                         compatible = "rockchip,rk3188-selcon";
 943                                         reg = <0x0150 0x4>;
 944                                         #address-cells = <1>;
 945                                         #size-cells = <1>;
 946
 947                                         dclk_vop0_div: dclk_vop0_div {
 948                                                 compatible = "rockchip,rk3188-div-con";
 949                                                 rockchip,bits = <0 8>;
 950                                                 clocks = <&dclk_vop0>;
 951                                                 clock-output-names = "dclk_vop0";
 952                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 953                                                 #clock-cells = <0>;
 954                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 955                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 956                                         };
 957
 958                                         dclk_vop0: dclk_vop0_mux {
 959                                                 compatible = "rockchip,rk3188-mux-con";
 960                                                 rockchip,bits = <8 2>;
 961                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&dummy>;
 962                                                 clock-output-names = "dclk_vop0";
 963                                                 #clock-cells = <0>;
 964                                                 #clock-init-cells = <1>;
 965                                         };
 966
 967                                         /* 15:10 reserved */
 968                                 };
 969
 970                                 clk_sel_con21: sel-con@0154 {
 971                                         compatible = "rockchip,rk3188-selcon";
 972                                         reg = <0x0154 0x4>;
 973                                         #address-cells = <1>;
 974                                         #size-cells = <1>;
 975
 976                                         hclk_vio: hclk_vio_div {
 977                                                 compatible = "rockchip,rk3188-div-con";
 978                                                 rockchip,bits = <0 5>;
 979                                                 clocks = <&aclk_vio0>;
 980                                                 clock-output-names = "hclk_vio";
 981                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 982                                                 #clock-cells = <0>;
 983                                                 #clock-init-cells = <1>;
 984                                         };
 985
 986                                         /* 5 reserved */
 987
 988                                         pclk_isp: pclk_isp_mux {
 989                                                 compatible = "rockchip,rk3188-mux-con";
 990                                                 rockchip,bits = <6 1>;
 991                                                 clocks = <&clk_gates17 2>, <&pclkin_isp_inv>;
 992                                                 clock-output-names = "pclk_isp";
 993                                                 #clock-cells = <0>;
 994                                         };
 995
 996                                         /* 7 reserved */
 997
 998                                         clk_vip_div: clk_vip_div {
 999                                                 compatible = "rockchip,rk3188-div-con";
1000                                                 rockchip,bits = <8 5>;
1001                                                 clocks = <&clk_vip>;
1002                                                 clock-output-names = "clk_vip";
1003                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1004                                                 #clock-cells = <0>;
1005                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1006                                         };
1007
1008                                         pclk_vip: pclk_vip_mux {
1009                                                 compatible = "rockchip,rk3188-mux-con";
1010                                                 rockchip,bits = <13 1>;
1011                                                 clocks = <&clk_gates16 13>, <&pclkin_vip_inv>;
1012                                                 clock-output-names = "pclk_vip";
1013                                                 #clock-cells = <0>;
1014                                         };
1015
1016                                         clk_vip: clk_vip_mux {
1017                                                 compatible = "rockchip,rk3188-mux-con";
1018                                                 rockchip,bits = <14 2>;
1019                                                 clocks = <&clk_cpll>, <&xin24m>, <&clk_gpll>, <&xin24m>;
1020                                                 clock-output-names = "clk_vip";
1021                                                 #clock-cells = <0>;
1022                                                 #clock-init-cells = <1>;
1023                                         };
1024                                 };
1025
1026                                 clk_sel_con22: sel-con@0158 {
1027                                         compatible = "rockchip,rk3188-selcon";
1028                                         reg = <0x0158 0x4>;
1029                                         #address-cells = <1>;
1030                                         #size-cells = <1>;
1031
1032                                         clk_isp_div: clk_isp_div {
1033                                                 compatible = "rockchip,rk3188-div-con";
1034                                                 rockchip,bits = <0 6>;
1035                                                 clocks = <&clk_isp>;
1036                                                 clock-output-names = "clk_isp";
1037                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1038                                                 #clock-cells = <0>;
1039                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1040                                         };
1041
1042                                         clk_isp: clk_isp_mux {
1043                                                 compatible = "rockchip,rk3188-mux-con";
1044                                                 rockchip,bits = <6 2>;
1045                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1046                                                 clock-output-names = "clk_isp";
1047                                                 #clock-cells = <0>;
1048                                                 #clock-init-cells = <1>;
1049                                         };
1050                                 };
1051
1052                                 clk_sel_con23: sel-con@015c {
1053                                         compatible = "rockchip,rk3188-selcon";
1054                                         reg = <0x015c 0x4>;
1055                                         #address-cells = <1>;
1056                                         #size-cells = <1>;
1057
1058                                         clk_edp_div: clk_edp_div {
1059                                                 compatible = "rockchip,rk3188-div-con";
1060                                                 rockchip,bits = <0 6>;
1061                                                 clocks = <&clk_edp>;
1062                                                 clock-output-names = "clk_edp";
1063                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1064                                                 #clock-cells = <0>;
1065                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1066                                         };
1067
1068                                         clk_edp: clk_edp_mux {
1069                                                 compatible = "rockchip,rk3188-mux-con";
1070                                                 rockchip,bits = <6 2>;
1071                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1072                                                 clock-output-names = "clk_edp";
1073                                                 #clock-cells = <0>;
1074                                         };
1075
1076                                         clk_edp_24m: clk_edp_24m_mux {
1077                                                 compatible = "rockchip,rk3188-mux-con";
1078                                                 rockchip,bits = <8 1>;
1079                                                 clocks = <&xin24m>, <&dummy>;
1080                                                 clock-output-names = "clk_edp_24m";
1081                                                 #clock-cells = <0>;
1082                                         };
1083                                 };
1084
1085                                 /* sel[24]: reserved */
1086
1087                                 clk_sel_con25: sel-con@0164 {
1088                                         compatible = "rockchip,rk3188-selcon";
1089                                         reg = <0x0164 0x4>;
1090                                         #address-cells = <1>;
1091                                         #size-cells = <1>;
1092
1093                                         clk_tsadc: clk_tsadc_div {
1094                                                 compatible = "rockchip,rk3188-div-con";
1095                                                 rockchip,bits = <0 6>;
1096                                                 clocks = <&clk_32k_mux>;
1097                                                 clock-output-names = "clk_tsadc";
1098                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1099                                                 #clock-cells = <0>;
1100                                         };
1101
1102                                         clk_saradc: clk_saradc_div {
1103                                                 compatible = "rockchip,rk3188-div-con";
1104                                                 rockchip,bits = <8 8>;
1105                                                 clocks = <&xin24m>;
1106                                                 clock-output-names = "clk_saradc";
1107                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1108                                                 #clock-cells = <0>;
1109                                         };
1110                                 };
1111
1112                                 clk_sel_con26: sel-con@0168 {
1113                                         compatible = "rockchip,rk3188-selcon";
1114                                         reg = <0x0168 0x4>;
1115                                         #address-cells = <1>;
1116                                         #size-cells = <1>;
1117
1118                                         /* 7:0 reserved */
1119
1120                                         hsic_usb_480m: hsic_usb_480m_mux {
1121                                                 compatible = "rockchip,rk3188-mux-con";
1122                                                 rockchip,bits = <8 1>;
1123                                                 clocks = <&usbotg_480m_out>, <&dummy>;
1124                                                 clock-output-names = "hsic_usb_480m";
1125                                                 #clock-cells = <0>;
1126                                         };
1127
1128                                         /* 11:9 reserved */
1129
1130                                         hsicphy_480m: hsicphy_480m_mux {
1131                                                 compatible = "rockchip,rk3188-mux-con";
1132                                                 rockchip,bits = <12 2>;
1133                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&hsic_usb_480m>, <&hsic_usb_480m>;
1134                                                 clock-output-names = "hsicphy_480m";
1135                                                 #clock-cells = <0>;
1136                                         };
1137                                 };
1138
1139                                 clk_sel_con27: sel-con@016c {
1140                                         compatible = "rockchip,rk3188-selcon";
1141                                         reg = <0x016c 0x4>;
1142                                         #address-cells = <1>;
1143                                         #size-cells = <1>;
1144
1145                                         i2s_pll_div: i2s_pll_div {
1146                                                 compatible = "rockchip,rk3188-div-con";
1147                                                 rockchip,bits = <0 7>;
1148                                                 clocks = <&i2s_pll>;
1149                                                 clock-output-names = "i2s_pll";
1150                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1151                                                 #clock-cells = <0>;
1152                                                 rockchip,clkops-idx =
1153                                                         <CLKOPS_RATE_MUX_DIV>;
1154                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1155                                         };
1156
1157                                         /* 7 reserved */
1158
1159                                         clk_i2s: clk_i2s_mux {
1160                                                 compatible = "rockchip,rk3188-mux-con";
1161                                                 rockchip,bits = <8 2>;
1162                                                 clocks = <&i2s_pll>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
1163                                                 clock-output-names = "clk_i2s";
1164                                                 #clock-cells = <0>;
1165                                                 rockchip,clkops-idx =
1166                                                         <CLKOPS_RATE_RK3288_I2S>;
1167                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1168                                         };
1169
1170                                         /* 11:10 reserved */
1171
1172                                         i2s_pll: i2s_pll_mux {
1173                                                 compatible = "rockchip,rk3188-mux-con";
1174                                                 rockchip,bits = <12 1>;
1175                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1176                                                 clock-output-names = "i2s_pll";
1177                                                 #clock-cells = <0>;
1178                                         };
1179
1180                                         /* 14:13 reserved */
1181
1182                                         i2s_out: i2s_out_mux {
1183                                                 compatible = "rockchip,rk3188-mux-con";
1184                                                 rockchip,bits = <15 1>;
1185                                                 clocks = <&clk_i2s>, <&xin12m>;
1186                                                 clock-output-names = "i2s_out";
1187                                                 #clock-cells = <0>;
1188                                         };
1189                                 };
1190
1191                                 clk_sel_con28: sel-con@0170 {
1192                                         compatible = "rockchip,rk3188-selcon";
1193                                         reg = <0x0170 0x4>;
1194                                         #address-cells = <1>;
1195                                         #size-cells = <1>;
1196
1197                                         i2s_frac: i2s_frac {
1198                                                 compatible = "rockchip,rk3188-frac-con";
1199                                                 clocks = <&i2s_pll>;
1200                                                 clock-output-names = "i2s_frac";
1201                                                 /* numerator    denominator */
1202                                                 rockchip,bits = <0 32>;
1203                                                 rockchip,clkops-idx =
1204                                                         <CLKOPS_RATE_FRAC>;
1205                                                 #clock-cells = <0>;
1206                                         };
1207                                 };
1208
1209                                 /* sel[30:29] reserved */
1210
1211                                 clk_sel_con31: sel-con@017c {
1212                                         compatible = "rockchip,rk3188-selcon";
1213                                         reg = <0x017c 0x4>;
1214                                         #address-cells = <1>;
1215                                         #size-cells = <1>;
1216
1217
1218                                         spdif_8ch_pll_div: spdif_8ch_pll_div {
1219                                                 compatible = "rockchip,rk3188-div-con";
1220                                                 rockchip,bits = <0 7>;
1221                                                 clocks = <&spdif_8ch_pll>;
1222                                                 clock-output-names = "spdif_8ch_pll";
1223                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1224                                                 #clock-cells = <0>;
1225                                                 rockchip,clkops-idx =
1226                                                         <CLKOPS_RATE_MUX_DIV>;
1227                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1228                                         };
1229
1230                                         /* 7 reserved */
1231
1232                                         clk_spidf_8ch: clk_spidf_8ch_mux {
1233                                                 compatible = "rockchip,rk3188-mux-con";
1234                                                 rockchip,bits = <8 2>;
1235                                                 clocks = <&spdif_8ch_pll>, <&spdif_8ch_frac>, <&i2s_clkin>, <&xin12m>;
1236                                                 clock-output-names = "clk_spidf_8ch";
1237                                                 #clock-cells = <0>;
1238                                                 rockchip,clkops-idx =
1239                                                         <CLKOPS_RATE_RK3288_I2S>;
1240                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1241                                         };
1242
1243                                         /* 11:10 reserved */
1244
1245                                         spdif_8ch_pll: spdif_8ch_pll_mux {
1246                                                 compatible = "rockchip,rk3188-mux-con";
1247                                                 rockchip,bits = <12 1>;
1248                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1249                                                 clock-output-names = "spdif_8ch_pll";
1250                                                 #clock-cells = <0>;
1251                                         };
1252
1253                                         /* 15:13 reserved */
1254                                 };
1255
1256                                 clk_sel_con32: sel-con@0180 {
1257                                         compatible = "rockchip,rk3188-selcon";
1258                                         reg = <0x0180 0x4>;
1259                                         #address-cells = <1>;
1260                                         #size-cells = <1>;
1261
1262                                         spdif_8ch_frac: spdif_8ch_frac {
1263                                                 compatible = "rockchip,rk3188-frac-con";
1264                                                 clocks = <&spdif_8ch_pll>;
1265                                                 clock-output-names = "spdif_8ch_frac";
1266                                                 /* numerator    denominator */
1267                                                 rockchip,bits = <0 32>;
1268                                                 rockchip,clkops-idx =
1269                                                         <CLKOPS_RATE_FRAC>;
1270                                                 #clock-cells = <0>;
1271                                         };
1272                                 };
1273
1274                                 clk_sel_con33: sel-con@0184 {
1275                                         compatible = "rockchip,rk3188-selcon";
1276                                         reg = <0x0184 0x4>;
1277                                         #address-cells = <1>;
1278                                         #size-cells = <1>;
1279
1280                                         clk_uart0_pll_div: clk_uart0_pll_div {
1281                                                 compatible = "rockchip,rk3188-div-con";
1282                                                 rockchip,bits = <0 7>;
1283                                                 clocks = <&clk_uart0_pll>;
1284                                                 clock-output-names = "clk_uart0_pll";
1285                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1286                                                 #clock-cells = <0>;
1287                                                 rockchip,clkops-idx =
1288                                                         <CLKOPS_RATE_MUX_DIV>;
1289                                         };
1290
1291                                         /* 7: reserved */
1292
1293                                         clk_uart0: clk_uart0_mux {
1294                                                 compatible = "rockchip,rk3188-mux-con";
1295                                                 rockchip,bits = <8 2>;
1296                                                 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>, <&xin24m>;
1297                                                 clock-output-names = "clk_uart0";
1298                                                 #clock-cells = <0>;
1299                                                 rockchip,clkops-idx =
1300                                                         <CLKOPS_RATE_RK3288_I2S>;
1301                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1302                                         };
1303
1304                                         /* 11:10 reserved */
1305
1306                                         clk_uart0_pll: clk_uart0_pll_mux {
1307                                                 compatible = "rockchip,rk3188-mux-con";
1308                                                 rockchip,bits = <12 2>;
1309                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
1310                                                 clock-output-names = "clk_uart0_pll";
1311                                                 #clock-cells = <0>;
1312                                         };
1313                                 };
1314
1315                                 clk_sel_con34: sel-con@0188 {
1316                                         compatible = "rockchip,rk3188-selcon";
1317                                         reg = <0x0188 0x4>;
1318                                         #address-cells = <1>;
1319                                         #size-cells = <1>;
1320
1321                                         uart0_frac: uart0_frac {
1322                                                 compatible = "rockchip,rk3188-frac-con";
1323                                                 clocks = <&clk_uart0_pll>;
1324                                                 clock-output-names = "uart0_frac";
1325                                                 /* numerator    denominator */
1326                                                 rockchip,bits = <0 32>;
1327                                                 rockchip,clkops-idx =
1328                                                         <CLKOPS_RATE_FRAC>;
1329                                                 #clock-cells = <0>;
1330                                         };
1331                                 };
1332
1333                                 clk_sel_con35: sel-con@018c {
1334                                         compatible = "rockchip,rk3188-selcon";
1335                                         reg = <0x018c 0x4>;
1336                                         #address-cells = <1>;
1337                                         #size-cells = <1>;
1338
1339                                         uart1_div: uart1_div {
1340                                                 compatible = "rockchip,rk3188-div-con";
1341                                                 rockchip,bits = <0 7>;
1342                                                 clocks = <&clk_uart_pll>;
1343                                                 clock-output-names = "uart1_div";
1344                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1345                                                 #clock-cells = <0>;
1346                                         };
1347
1348                                         /* 7 reserved */
1349
1350                                         clk_uart1: clk_uart1_mux {
1351                                                 compatible = "rockchip,rk3188-mux-con";
1352                                                 rockchip,bits = <8 2>;
1353                                                 clocks = <&uart1_div>, <&uart1_frac>, <&xin24m>, <&xin24m>;
1354                                                 clock-output-names = "clk_uart1";
1355                                                 #clock-cells = <0>;
1356                                                 rockchip,clkops-idx =
1357                                                         <CLKOPS_RATE_RK3288_I2S>;
1358                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1359                                         };
1360
1361                                         /* 11:10 reserved */
1362
1363                                         clk_uart_pll: clk_uart_pll_mux {
1364                                                 compatible = "rockchip,rk3188-mux-con";
1365                                                 rockchip,bits = <12 1>;
1366                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1367                                                 clock-output-names = "clk_uart_pll";
1368                                                 #clock-cells = <0>;
1369                                         };
1370
1371                                         /* 14:13 reserved */
1372                                 };
1373
1374                                 clk_sel_con36: sel-con@0190 {
1375                                         compatible = "rockchip,rk3188-selcon";
1376                                         reg = <0x0190 0x4>;
1377                                         #address-cells = <1>;
1378                                         #size-cells = <1>;
1379
1380                                         uart1_frac: uart1_frac {
1381                                                 compatible = "rockchip,rk3188-frac-con";
1382                                                 clocks = <&uart1_div>;
1383                                                 clock-output-names = "uart1_frac";
1384                                                 /* numerator    denominator */
1385                                                 rockchip,bits = <0 32>;
1386                                                 rockchip,clkops-idx =
1387                                                         <CLKOPS_RATE_FRAC>;
1388                                                 #clock-cells = <0>;
1389                                         };
1390                                 };
1391
1392                                 clk_sel_con37: sel-con@0194 {
1393                                         compatible = "rockchip,rk3188-selcon";
1394                                         reg = <0x0194 0x4>;
1395                                         #address-cells = <1>;
1396                                         #size-cells = <1>;
1397
1398                                         uart2_div: uart2_div {
1399                                                 compatible = "rockchip,rk3188-div-con";
1400                                                 rockchip,bits = <0 7>;
1401                                                 clocks = <&clk_uart_pll>;
1402                                                 clock-output-names = "uart2_div";
1403                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1404                                                 #clock-cells = <0>;
1405                                         };
1406
1407                                         /* 7 reserved */
1408
1409                                         clk_uart2: clk_uart2_mux {
1410                                                 compatible = "rockchip,rk3188-mux-con";
1411                                                 rockchip,bits = <8 1>;
1412                                                 clocks = <&uart2_div>, <&xin24m>;
1413                                                 clock-output-names = "clk_uart2";
1414                                                 #clock-cells = <0>;
1415                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1416                                         };
1417                                 };
1418
1419                                 /* sel[38] reserved */
1420
1421                                 clk_sel_con39: sel-con@019c {
1422                                         compatible = "rockchip,rk3188-selcon";
1423                                         reg = <0x019c 0x4>;
1424                                         #address-cells = <1>;
1425                                         #size-cells = <1>;
1426
1427                                         uart3_div: uart3_div {
1428                                                 compatible = "rockchip,rk3188-div-con";
1429                                                 rockchip,bits = <0 7>;
1430                                                 clocks = <&clk_uart_pll>;
1431                                                 clock-output-names = "uart3_div";
1432                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1433                                                 #clock-cells = <0>;
1434                                         };
1435
1436                                         /* 7 reserved */
1437
1438                                         clk_uart3: clk_uart3_mux {
1439                                                 compatible = "rockchip,rk3188-mux-con";
1440                                                 rockchip,bits = <8 2>;
1441                                                 clocks = <&uart3_div>, <&uart3_frac>, <&xin24m>, <&xin24m>;
1442                                                 clock-output-names = "clk_uart3";
1443                                                 #clock-cells = <0>;
1444                                                 rockchip,clkops-idx =
1445                                                         <CLKOPS_RATE_RK3288_I2S>;
1446                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1447                                         };
1448                                 };
1449
1450                                 clk_sel_con40: sel-con@01a0 {
1451                                         compatible = "rockchip,rk3188-selcon";
1452                                         reg = <0x01a0 0x4>;
1453                                         #address-cells = <1>;
1454                                         #size-cells = <1>;
1455
1456                                         uart3_frac: uart3_frac {
1457                                                 compatible = "rockchip,rk3188-frac-con";
1458                                                 clocks = <&uart3_div>;
1459                                                 clock-output-names = "uart3_frac";
1460                                                 /* numerator    denominator */
1461                                                 rockchip,bits = <0 32>;
1462                                                 rockchip,clkops-idx =
1463                                                         <CLKOPS_RATE_FRAC>;
1464                                                 #clock-cells = <0>;
1465                                         };
1466                                 };
1467
1468                                 clk_sel_con41: sel-con@01a4 {
1469                                         compatible = "rockchip,rk3188-selcon";
1470                                         reg = <0x01a4 0x4>;
1471                                         #address-cells = <1>;
1472                                         #size-cells = <1>;
1473
1474                                         uart4_div: uart4_div {
1475                                                 compatible = "rockchip,rk3188-div-con";
1476                                                 rockchip,bits = <0 7>;
1477                                                 clocks = <&clk_uart_pll>;
1478                                                 clock-output-names = "uart4_div";
1479                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1480                                                 #clock-cells = <0>;
1481                                         };
1482
1483                                         /* 7 reserved */
1484
1485                                         clk_uart4: clk_uart4_mux {
1486                                                 compatible = "rockchip,rk3188-mux-con";
1487                                                 rockchip,bits = <8 2>;
1488                                                 clocks = <&uart4_div>, <&uart4_frac>, <&xin24m>, <&xin24m>;
1489                                                 clock-output-names = "clk_uart4";
1490                                                 #clock-cells = <0>;
1491                                                 rockchip,clkops-idx =
1492                                                         <CLKOPS_RATE_RK3288_I2S>;
1493                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1494                                         };
1495                                 };
1496
1497                                 clk_sel_con42: sel-con@01a8 {
1498                                         compatible = "rockchip,rk3188-selcon";
1499                                         reg = <0x01a8 0x4>;
1500                                         #address-cells = <1>;
1501                                         #size-cells = <1>;
1502
1503                                         uart4_frac: uart4_frac {
1504                                                 compatible = "rockchip,rk3188-frac-con";
1505                                                 clocks = <&uart4_div>;
1506                                                 clock-output-names = "uart4_frac";
1507                                                 /* numerator    denominator */
1508                                                 rockchip,bits = <0 32>;
1509                                                 rockchip,clkops-idx =
1510                                                         <CLKOPS_RATE_FRAC>;
1511                                                 #clock-cells = <0>;
1512                                         };
1513                                 };
1514
1515                                 clk_sel_con43: sel-con@01ac {
1516                                         compatible = "rockchip,rk3188-selcon";
1517                                         reg = <0x01ac 0x4>;
1518                                         #address-cells = <1>;
1519                                         #size-cells = <1>;
1520
1521                                         clk_mac_pll_div: clk_mac_pll_div {
1522                                                 compatible = "rockchip,rk3188-div-con";
1523                                                 rockchip,bits = <0 5>;
1524                                                 clocks = <&clk_mac_pll>;
1525                                                 clock-output-names = "clk_mac_pll";
1526                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1527                                                 #clock-cells = <0>;
1528                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1529                                         };
1530
1531                                         /* 5 reserved */
1532
1533                                         clk_mac_pll: clk_mac_pll_mux {
1534                                                 compatible = "rockchip,rk3188-mux-con";
1535                                                 rockchip,bits = <6 2>;
1536                                                 clocks = <&clk_npll>, <&clk_cpll>, <&clk_gpll>, <&clk_gpll>;
1537                                                 clock-output-names = "clk_mac_pll";
1538                                                 #clock-cells = <0>;
1539                                         };
1540
1541                                         clk_mac: clk_mac_mux {
1542                                                 compatible = "rockchip,rk3188-mux-con";
1543                                                 rockchip,bits = <8 1>;
1544                                                 clocks = <&clk_mac_pll>, <&gmac_clkin>;
1545                                                 clock-output-names = "clk_mac";
1546                                                 #clock-cells = <0>;
1547                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1548                                         };
1549
1550                                         /* 11:9 reserved */
1551
1552                                         /* 12: test_clk: wifi_pll_sel */
1553
1554                                         /* 15:13 reserved */
1555                                 };
1556
1557                                 clk_sel_con44: sel-con@01b0 {
1558                                         compatible = "rockchip,rk3188-selcon";
1559                                         reg = <0x01b0 0x4>;
1560                                         #address-cells = <1>;
1561                                         #size-cells = <1>;
1562
1563                                         /* test_clk: wifi_frac */
1564                                 };
1565
1566                                 clk_sel_con45: sel-con@01b4 {
1567                                         compatible = "rockchip,rk3188-selcon";
1568                                         reg = <0x01b4 0x4>;
1569                                         #address-cells = <1>;
1570                                         #size-cells = <1>;
1571
1572                                         clk_spi0_div: clk_spi0_div {
1573                                                 compatible = "rockchip,rk3188-div-con";
1574                                                 rockchip,bits = <0 7>;
1575                                                 clocks = <&clk_spi0>;
1576                                                 clock-output-names = "clk_spi0";
1577                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1578                                                 #clock-cells = <0>;
1579                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1580                                         };
1581
1582                                         clk_spi0: clk_spi0_mux {
1583                                                 compatible = "rockchip,rk3188-mux-con";
1584                                                 rockchip,bits = <7 1>;
1585                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1586                                                 clock-output-names = "clk_spi0";
1587                                                 #clock-cells = <0>;
1588                                         };
1589
1590                                         clk_spi1_div: clk_spi1_div {
1591                                                 compatible = "rockchip,rk3188-div-con";
1592                                                 rockchip,bits = <8 7>;
1593                                                 clocks = <&clk_spi1>;
1594                                                 clock-output-names = "clk_spi1";
1595                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1596                                                 #clock-cells = <0>;
1597                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1598                                         };
1599
1600                                         clk_spi1: clk_spi1_mux {
1601                                                 compatible = "rockchip,rk3188-mux-con";
1602                                                 rockchip,bits = <15 1>;
1603                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1604                                                 clock-output-names = "clk_spi1";
1605                                                 #clock-cells = <0>;
1606                                         };
1607                                 };
1608
1609                                 clk_sel_con46: sel-con@01b8 {
1610                                         compatible = "rockchip,rk3188-selcon";
1611                                         reg = <0x01b8 0x4>;
1612                                         #address-cells = <1>;
1613                                         #size-cells = <1>;
1614
1615                                         clk_tsp_div: clk_tsp_div {
1616                                                 compatible = "rockchip,rk3188-div-con";
1617                                                 rockchip,bits = <0 5>;
1618                                                 clocks = <&clk_tsp>;
1619                                                 clock-output-names = "clk_tsp";
1620                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1621                                                 #clock-cells = <0>;
1622                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1623                                         };
1624
1625                                         /* 5 reserved */
1626
1627                                         clk_tsp: clk_tsp_mux {
1628                                                 compatible = "rockchip,rk3188-mux-con";
1629                                                 rockchip,bits = <6 2>;
1630                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1631                                                 clock-output-names = "clk_tsp";
1632                                                 #clock-cells = <0>;
1633                                         };
1634
1635                                         clk_spi2_div: clk_spi2_div {
1636                                                 compatible = "rockchip,rk3188-div-con";
1637                                                 rockchip,bits = <8 7>;
1638                                                 clocks = <&clk_spi2>;
1639                                                 clock-output-names = "clk_spi2";
1640                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1641                                                 #clock-cells = <0>;
1642                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1643                                         };
1644
1645                                         clk_spi2: clk_spi2_mux {
1646                                                 compatible = "rockchip,rk3188-mux-con";
1647                                                 rockchip,bits = <15 1>;
1648                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1649                                                 clock-output-names = "clk_spi2";
1650                                                 #clock-cells = <0>;
1651                                         };
1652                                 };
1653
1654                                 clk_sel_con47: sel-con@01bc {
1655                                         compatible = "rockchip,rk3188-selcon";
1656                                         reg = <0x01bc 0x4>;
1657                                         #address-cells = <1>;
1658                                         #size-cells = <1>;
1659
1660                                         clk_nandc0_div: clk_nandc0_div {
1661                                                 compatible = "rockchip,rk3188-div-con";
1662                                                 rockchip,bits = <0 5>;
1663                                                 clocks = <&clk_nandc0>;
1664                                                 clock-output-names = "clk_nandc0";
1665                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1666                                                 #clock-cells = <0>;
1667                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1668                                         };
1669
1670                                         /* 6:5 reserved */
1671
1672                                         clk_nandc0: clk_nandc0_mux {
1673                                                 compatible = "rockchip,rk3188-mux-con";
1674                                                 rockchip,bits = <7 1>;
1675                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1676                                                 clock-output-names = "clk_nandc0";
1677                                                 #clock-cells = <0>;
1678                                         };
1679
1680                                         /* 12:8 test_div */
1681
1682                                         /* 15:13 reserved */
1683                                 };
1684
1685                                 clk_sel_con48: sel-con@01c0 {
1686                                         compatible = "rockchip,rk3188-selcon";
1687                                         reg = <0x01c0 0x4>;
1688                                         #address-cells = <1>;
1689                                         #size-cells = <1>;
1690
1691                                         clk_sdio0_div: clk_sdio0_div {
1692                                                 compatible = "rockchip,rk3188-div-con";
1693                                                 rockchip,bits = <0 7>;
1694                                                 clocks = <&clk_sdio0>;
1695                                                 clock-output-names = "clk_sdio0";
1696                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1697                                                 #clock-cells = <0>;
1698                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1699                                         };
1700
1701                                         /* 7 reserved */
1702
1703                                         clk_sdio0: clk_sdio0_mux {
1704                                                 compatible = "rockchip,rk3188-mux-con";
1705                                                 rockchip,bits = <8 2>;
1706                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1707                                                 clock-output-names = "clk_sdio0";
1708                                                 #clock-cells = <0>;
1709                                         };
1710
1711                                         /* 15:10 reserved */
1712                                 };
1713
1714                                 /* sel[49] reserved */
1715
1716                                 clk_sel_con50: sel-con@01c8 {
1717                                         compatible = "rockchip,rk3188-selcon";
1718                                         reg = <0x01c8 0x4>;
1719                                         #address-cells = <1>;
1720                                         #size-cells = <1>;
1721
1722                                         clk_sdmmc0_div: clk_sdmmc0_div {
1723                                                 compatible = "rockchip,rk3188-div-con";
1724                                                 rockchip,bits = <0 7>;
1725                                                 clocks = <&clk_sdmmc0>;
1726                                                 clock-output-names = "clk_sdmmc0";
1727                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1728                                                 #clock-cells = <0>;
1729                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1730                                         };
1731
1732                                         /* 7 reserved */
1733
1734                                         clk_sdmmc0: clk_sdmmc0_mux {
1735                                                 compatible = "rockchip,rk3188-mux-con";
1736                                                 rockchip,bits = <8 2>;
1737                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1738                                                 clock-output-names = "clk_sdmmc0";
1739                                                 #clock-cells = <0>;
1740                                         };
1741
1742                                         /* 15:10 reserved */
1743                                 };
1744
1745                                 clk_sel_con51: sel-con@01cc {
1746                                         compatible = "rockchip,rk3188-selcon";
1747                                         reg = <0x01cc 0x4>;
1748                                         #address-cells = <1>;
1749                                         #size-cells = <1>;
1750
1751                                         clk_emmc_div: clk_emmc_div {
1752                                                 compatible = "rockchip,rk3188-div-con";
1753                                                 rockchip,bits = <0 7>;
1754                                                 clocks = <&clk_emmc>;
1755                                                 clock-output-names = "clk_emmc";
1756                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1757                                                 #clock-cells = <0>;
1758                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1759                                         };
1760
1761                                         /* 7 reserved */
1762
1763                                         clk_emmc: clk_emmc_mux {
1764                                                 compatible = "rockchip,rk3188-mux-con";
1765                                                 rockchip,bits = <8 2>;
1766                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1767                                                 clock-output-names = "clk_emmc";
1768                                                 #clock-cells = <0>;
1769                                         };
1770
1771                                         /* 15:10 reserved */
1772                                 };
1773
1774                                 clk_sel_con52: sel-con@01d0 {
1775                                         compatible = "rockchip,rk3188-selcon";
1776                                         reg = <0x01d0 0x4>;
1777                                         #address-cells = <1>;
1778                                         #size-cells = <1>;
1779
1780                                         clk_sfc_div: clk_sfc_div {
1781                                                 compatible = "rockchip,rk3188-div-con";
1782                                                 rockchip,bits = <0 5>;
1783                                                 clocks = <&clk_sfc>;
1784                                                 clock-output-names = "clk_sfc";
1785                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1786                                                 #clock-cells = <0>;
1787                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1788                                         };
1789
1790                                         /* 6:5 reserved */
1791
1792                                         clk_sfc: clk_sfc_mux {
1793                                                 compatible = "rockchip,rk3188-mux-con";
1794                                                 rockchip,bits = <7 1>;
1795                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1796                                                 clock-output-names = "clk_sfc";
1797                                                 #clock-cells = <0>;
1798                                         };
1799
1800                                         /* 15:8 reserved */
1801                                 };
1802
1803                                 clk_sel_con53: sel-con@01d4 {
1804                                         compatible = "rockchip,rk3188-selcon";
1805                                         reg = <0x01d4 0x4>;
1806                                         #address-cells = <1>;
1807                                         #size-cells = <1>;
1808
1809                                         i2s_2ch_pll_div: i2s_2ch_pll_div {
1810                                                 compatible = "rockchip,rk3188-div-con";
1811                                                 rockchip,bits = <0 7>;
1812                                                 clocks = <&i2s_2ch_pll>;
1813                                                 clock-output-names = "i2s_2ch_pll";
1814                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1815                                                 #clock-cells = <0>;
1816                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1817                                         };
1818
1819                                         /* 7 reserved */
1820
1821                                         clk_i2s_2ch: clk_i2s_2ch_mux {
1822                                                 compatible = "rockchip,rk3188-mux-con";
1823                                                 rockchip,bits = <8 2>;
1824                                                 clocks = <&i2s_2ch_pll>, <&i2s_2ch_frac>, <&dummy>, <&xin12m>;
1825                                                 clock-output-names = "clk_i2s_2ch";
1826                                                 #clock-cells = <0>;
1827                                                 rockchip,clkops-idx =
1828                                                         <CLKOPS_RATE_RK3288_I2S>;
1829                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1830                                         };
1831
1832                                         /* 11:10 reserved */
1833
1834                                         i2s_2ch_pll: i2s_2ch_pll_mux {
1835                                                 compatible = "rockchip,rk3188-mux-con";
1836                                                 rockchip,bits = <12 1>;
1837                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1838                                                 clock-output-names = "i2s_2ch_pll";
1839                                                 #clock-cells = <0>;
1840                                         };
1841
1842                                 };
1843
1844                                 clk_sel_con54: sel-con@01d8 {
1845                                         compatible = "rockchip,rk3188-selcon";
1846                                         reg = <0x01d8 0x4>;
1847                                         #address-cells = <1>;
1848                                         #size-cells = <1>;
1849
1850                                         i2s_2ch_frac: i2s_2ch_frac {
1851                                                 compatible = "rockchip,rk3188-frac-con";
1852                                                 clocks = <&i2s_2ch_pll>;
1853                                                 clock-output-names = "i2s_2ch_frac";
1854                                                 /* numerator    denominator */
1855                                                 rockchip,bits = <0 32>;
1856                                                 rockchip,clkops-idx =
1857                                                         <CLKOPS_RATE_FRAC>;
1858                                                 #clock-cells = <0>;
1859                                         };
1860                                 };
1861
1862                                 clk_sel_con55: sel-con@01dc {
1863                                         compatible = "rockchip,rk3188-selcon";
1864                                         reg = <0x01dc 0x4>;
1865                                         #address-cells = <1>;
1866                                         #size-cells = <1>;
1867
1868                                         clk_hdcp_div: clk_hdcp_div {
1869                                                 compatible = "rockchip,rk3188-div-con";
1870                                                 rockchip,bits = <0 6>;
1871                                                 clocks = <&clk_hdcp>;
1872                                                 clock-output-names = "clk_hdcp";
1873                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1874                                                 #clock-cells = <0>;
1875                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1876                                         };
1877
1878                                         clk_hdcp: clk_hdcp_mux {
1879                                                 compatible = "rockchip,rk3188-mux-con";
1880                                                 rockchip,bits = <6 2>;
1881                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1882                                                 clock-output-names = "clk_hdcp";
1883                                                 #clock-cells = <0>;
1884                                         };
1885                                 };
1886                         };
1887
1888                         /* Gate control regs */
1889                         clk_gate_cons {
1890                                 compatible = "rockchip,rk-gate-cons";
1891                                 #address-cells = <1>;
1892                                 #size-cells = <1>;
1893                                 ranges;
1894
1895                                 clk_gates0: gate-clk@0200 {
1896                                         compatible = "rockchip,rk3188-gate-clk";
1897                                         reg = <0x0200 0x4>;
1898                                         clocks =
1899                                                 <&dummy>,       <&dummy>,
1900                                                 <&dummy>,       <&dummy>,
1901
1902                                                 <&dummy>,       <&dummy>,
1903                                                 <&dummy>,       <&dummy>,
1904
1905                                                 <&clk_gpll>,    <&clk_apllb>,
1906                                                 <&clk_aplll>,   <&dummy>,
1907
1908                                                 <&aclk_cci>,    <&clkin_trace>,
1909                                                 <&dummy>,       <&dummy>;
1910
1911                                         clock-output-names =
1912                                                 "reserved",     "reserved",/* core_b_apll core_b_gpll */
1913                                                 "reserved",     "reserved",
1914
1915                                                 "reserved",     "reserved",/* core_l_apll core_l_gpll */
1916                                                 "reserved",     "reserved",
1917
1918                                                 "g_clk_cs_gpll",        "g_clk_cs_apllb",
1919                                                 "g_clk_cs_aplll",       "reserved",
1920
1921                                                 "aclk_cci",     "clkin_trace",
1922                                                 "reserved",     "reserved";
1923
1924                                         #clock-cells = <1>;
1925                                 };
1926
1927                                 clk_gates1: gate-clk@0204 {
1928                                         compatible = "rockchip,rk3188-gate-clk";
1929                                         reg = <0x0204 0x4>;
1930                                         clocks =
1931                                                 <&aclk_bus>,    <&hclk_bus>,
1932                                                 <&pclk_bus>,    <&fclk_mcu>,
1933
1934                                                 <&dummy>,       <&dummy>,
1935                                                 <&dummy>,       <&dummy>,
1936
1937                                                 <&dummy>,       <&dummy>,
1938                                                 <&clk_gpll>,    <&clk_cpll>,
1939
1940                                                 <&dummy>,       <&dummy>,
1941                                                 <&dummy>,       <&dummy>;
1942
1943                                         clock-output-names =
1944                                                 "aclk_bus",     "hclk_bus",
1945                                                 "pclk_bus",     "fclk_mcu",
1946
1947                                                 "reserved",     "reserved",
1948                                                 "reserved",     "reserved",
1949
1950                                                 "reserved",     "reserved",/* ddr_dpll  ddr_gpll */
1951                                                 "aclk_bus_gpll",        "aclk_bus_cpll",
1952
1953                                                 "reserved",     "reserved",
1954                                                 "reserved",     "reserved";
1955
1956                                         #clock-cells = <1>;
1957                                 };
1958
1959                                 clk_gates2: gate-clk@0208 {
1960                                         compatible = "rockchip,rk3188-gate-clk";
1961                                         reg = <0x0208 0x4>;
1962                                         clocks =
1963                                                 <&clk_uart0_pll>,       <&uart0_frac>,
1964                                                 <&uart1_div>,   <&uart1_frac>,
1965
1966                                                 <&uart2_div>,   <&dummy>,
1967                                                 <&uart3_div>,   <&uart3_frac>,
1968
1969                                                 <&uart4_div>,   <&uart4_frac>,
1970                                                 <&dummy>,       <&dummy>,
1971
1972                                                 <&dummy>,       <&dummy>,
1973                                                 <&dummy>,       <&dummy>;
1974
1975                                         clock-output-names =
1976                                                 "clk_uart0_pll",        "uart0_frac",
1977                                                 "uart1_div",    "uart1_frac",
1978
1979                                                 "uart2_div",    "reserved",
1980                                                 "uart3_div",    "uart3_frac",
1981
1982                                                 "uart4_div",    "uart4_frac",
1983                                                 "reserved",     "reserved",
1984
1985                                                 "reserved",     "reserved",
1986                                                 "reserved",     "reserved";
1987
1988                                         #clock-cells = <1>;
1989                                 };
1990
1991                                 clk_gates3: gate-clk@020c {
1992                                         compatible = "rockchip,rk3188-gate-clk";
1993                                         reg = <0x020c 0x4>;
1994                                         clocks =
1995                                                 <&aclk_peri>,   <&dummy>,
1996                                                 <&hclk_peri>,   <&pclk_peri>,
1997
1998                                                 <&clk_mac_pll>, <&clk_tsadc>,
1999                                                 <&clk_saradc>,  <&clk_spi0>,
2000
2001                                                 <&clk_spi1>,    <&clk_spi2>,
2002                                                 <&dummy>,       <&dummy>,
2003
2004                                                 <&dummy>,       <&dummy>,
2005                                                 <&dummy>,       <&dummy>;
2006
2007                                         clock-output-names =
2008                                                 "aclk_peri",    "reserved", /* bit1: aclk_peri */
2009                                                 "hclk_peri",    "pclk_peri",
2010
2011                                                 "clk_mac_pll",  "clk_tsadc",
2012                                                 "clk_saradc",   "clk_spi0",
2013
2014                                                 "clk_spi1",     "clk_spi2",
2015                                                 "reserved",     "reserved",
2016
2017                                                 "reserved",     "reserved",
2018                                                 "reserved",     "reserved";
2019
2020                                         #clock-cells = <1>;
2021                                 };
2022
2023                                 clk_gates4: gate-clk@0210 {
2024                                         compatible = "rockchip,rk3188-gate-clk";
2025                                         reg = <0x0210 0x4>;
2026                                         clocks =
2027                                                 <&aclk_vio0>,   <&dclk_vop0>,
2028                                                 <&xin24m>,      <&aclk_rga_pre>,
2029
2030                                                 <&clk_rga>,     <&clk_vip>,
2031                                                 <&aclk_vepu>,   <&aclk_vdpu>,
2032
2033                                                 <&dummy>,       <&clk_isp>,
2034                                                 <&dummy>,       <&clk_gpu_core>,
2035
2036                                                 <&xin32k>,      <&xin24m>,
2037                                                 <&xin24m>,      <&dummy>;
2038
2039                                         clock-output-names =
2040                                                 "aclk_vio0",    "dclk_vop0",
2041                                                 "clk_vop0_pwm", "aclk_rga_pre",
2042
2043                                                 "clk_rga",      "clk_vip",
2044                                                 "aclk_vepu",    "aclk_vdpu",
2045
2046                                                 "reserved",     "clk_isp", /* bit8: hclk_vpu */
2047                                                 "reserved",     "clk_gpu_core",
2048
2049                                                 "clk_hdmi_cec", "clk_hdmi_hdcp",
2050                                                 "clk_dsiphy_24m",       "reserved";
2051
2052                                         #clock-cells = <1>;
2053                                 };
2054
2055                                 clk_gates5: gate-clk@0214 {
2056                                         compatible = "rockchip,rk3188-gate-clk";
2057                                         reg = <0x0214 0x4>;
2058                                         clocks =
2059                                                 <&dummy>,       <&clk_hevc_cabac>,
2060                                                 <&clk_hevc_core>,       <&clk_edp>,
2061
2062                                                 <&clk_edp_24m>, <&clk_hdcp>,
2063                                                 <&dummy>,       <&dummy>,
2064
2065                                                 <&aclk_gpu_mem>,        <&aclk_gpu_cfg>,
2066                                                 <&dummy>,       <&dummy>,
2067
2068                                                 <&dummy>,       <&i2s_pll>,
2069                                                 <&i2s_2ch_frac>,        <&clk_i2s_2ch>;
2070
2071                                         clock-output-names =
2072                                                 "reserved",     "clk_hevc_cabac",
2073                                                 "clk_hevc_core",        "clk_edp",
2074
2075                                                 "clk_edp_24m",  "clk_hdcp",
2076                                                 "reserved",     "reserved",
2077
2078                                                 "aclk_gpu_mem", "aclk_gpu_cfg",
2079                                                 "reserved",     "reserved",
2080
2081                                                 "reserved",     "i2s_pll",
2082                                                 "i2s_2ch_frac", "clk_i2s_2ch";
2083
2084                                         #clock-cells = <1>;
2085                                 };
2086
2087                                 clk_gates6: gate-clk@0218 {
2088                                         compatible = "rockchip,rk3188-gate-clk";
2089                                         reg = <0x0218 0x4>;
2090                                         clocks =
2091                                                 <&i2s_out>,     <&i2s_pll>,
2092                                                 <&i2s_frac>,    <&clk_i2s>,
2093
2094                                                 <&spdif_8ch_pll>,       <&spdif_8ch_frac>,
2095                                                 <&clk_spidf_8ch>,       <&clk_sfc>,
2096
2097                                                 <&dummy>,       <&dummy>,
2098                                                 <&dummy>,       <&dummy>,
2099
2100                                                 <&clk_tsp>,     <&dummy>,
2101                                                 <&dummy>,       <&dummy>;
2102
2103                                         clock-output-names =
2104                                                 "i2s_out",      "i2s_pll",
2105                                                 "i2s_frac",     "clk_i2s",
2106
2107                                                 "spdif_8ch_pll",        "spdif_8ch_frac",
2108                                                 "clk_spidf_8ch",        "clk_sfc",
2109
2110                                                 "reserved",     "reserved",
2111                                                 "reserved",     "reserved",
2112
2113                                                 "clk_tsp",      "reserved",
2114                                                 "reserved",     "reserved";/* clk_ddrphy_gate   clk4x_ddrphy_gate */
2115
2116                                         #clock-cells = <1>;
2117                                 };
2118
2119                                 clk_gates7: gate-clk@021c {
2120                                         compatible = "rockchip,rk3188-gate-clk";
2121                                         reg = <0x021c 0x4>;
2122                                         clocks =
2123                                                 <&jtag_clkin>,  <&dummy>,
2124                                                 <&clk_crypto>,  <&xin24m>,
2125
2126                                                 <&dummy>,       <&dummy>,
2127                                                 <&clk_mac>,     <&clk_mac>,
2128
2129                                                 <&clk_nandc0>,  <&pclk_pmu_pre>,
2130                                                 <&xin24m>,      <&xin24m>,
2131
2132                                                 <&dummy>,       <&dummy>,
2133                                                 <&dummy>,       <&dummy>;
2134
2135                                         clock-output-names =
2136                                                 "clk_jtag",     "reserved",/* bit1: test_clk */
2137                                                 "clk_crypto",   "clk_pvtm_pmu",
2138
2139                                                 "reserved",     "reserved",/* clk_mac_rx  clk_mac_tx */
2140                                                 "clk_mac_ref",  "clk_mac_refout",
2141
2142                                                 "clk_nandc0",   "pclk_pmu_pre",
2143                                                 "clk_pvtm_core",        "clk_pvtm_gpu",
2144
2145                                                 "clk_sdmmc0",   "clk_sdio0",
2146                                                 "reserved",     "clk_emmc";
2147
2148                                         #clock-cells = <1>;
2149                                 };
2150
2151                                 clk_gates8: gate-clk@0220 {
2152                                         compatible = "rockchip,rk3188-gate-clk";
2153                                         reg = <0x0220 0x4>;
2154                                         clocks =
2155                                                 <&hsic_usb_480m>,       <&xin24m>,
2156                                                 <&dummy>,       <&dummy>,
2157
2158                                                 <&clk_32k_mux>, <&dummy>,
2159                                                 <&xin12m>,      <&hsicphy_480m>,
2160
2161                                                 <&dummy>,       <&dummy>,
2162                                                 <&dummy>,       <&dummy>,
2163
2164                                                 <&dummy>,       <&dummy>,
2165                                                 <&dummy>,       <&dummy>;
2166
2167                                         clock-output-names =
2168                                                 "hsic_usb_480m",        "clk_otgphy0",
2169                                                 "reserved",     "reserved",
2170
2171                                                 "g_clk_otg_adp",        "reserved",/* bit4: clk_otg_adp */
2172                                                 "hsicphy_12m",  "hsicphy_480m",
2173
2174                                                 "reserved",     "reserved",
2175                                                 "reserved",     "reserved",
2176
2177                                                 "reserved",     "reserved",
2178                                                 "reserved",     "reserved";
2179
2180                                         #clock-cells = <1>;
2181                                 };
2182
2183                                 clk_gates9: gate-clk@0224 {
2184                                         compatible = "rockchip,rk3188-gate-clk";
2185                                         reg = <0x0224 0x4>;
2186                                         clocks =
2187                                                 <&dummy>,       <&dummy>,
2188                                                 <&dummy>,       <&dummy>,
2189
2190                                                 <&dummy>,       <&dummy>,
2191                                                 <&dummy>,       <&dummy>,
2192
2193                                                 <&dummy>,       <&dummy>,
2194                                                 <&dummy>,       <&dummy>,
2195
2196                                                 <&dummy>,       <&dummy>,
2197                                                 <&dummy>,       <&dummy>;
2198
2199                                         clock-output-names =
2200                                                 "reserved",     "reserved",
2201                                                 "reserved",     "reserved",
2202
2203                                                 "reserved",     "reserved",
2204                                                 "reserved",     "reserved",
2205
2206                                                 "reserved",     "reserved",
2207                                                 "reserved",     "reserved",
2208
2209                                                 "reserved",     "reserved",
2210                                                 "reserved",     "reserved";
2211
2212                                         #clock-cells = <1>;
2213                                 };
2214
2215                                 clk_gates10: gate-clk@0228 {
2216                                         compatible = "rockchip,rk3188-gate-clk";
2217                                         reg = <0x0228 0x4>;
2218                                         clocks =
2219                                                 <&dummy>,       <&dummy>,
2220                                                 <&dummy>,       <&dummy>,
2221
2222                                                 <&dummy>,       <&dummy>,
2223                                                 <&dummy>,       <&dummy>,
2224
2225                                                 <&dummy>,       <&dummy>,
2226                                                 <&dummy>,       <&dummy>,
2227
2228                                                 <&dummy>,       <&dummy>,
2229                                                 <&dummy>,       <&dummy>;
2230
2231                                         clock-output-names =
2232                                                 "reserved",     "reserved",
2233                                                 "reserved",     "reserved",
2234
2235                                                 "reserved",     "reserved",
2236                                                 "reserved",     "reserved",
2237
2238                                                 "reserved",     "reserved",
2239                                                 "reserved",     "reserved",
2240
2241                                                 "reserved",     "reserved",
2242                                                 "reserved",     "reserved";
2243
2244                                         #clock-cells = <1>;
2245                                 };
2246
2247                                 clk_gates11: gate-clk@022c {
2248                                         compatible = "rockchip,rk3188-gate-clk";
2249                                         reg = <0x022c 0x4>;
2250                                         clocks =
2251                                                 <&dummy>,       <&dummy>,
2252                                                 <&dummy>,       <&dummy>,
2253
2254                                                 <&dummy>,       <&dummy>,
2255                                                 <&dummy>,       <&dummy>,
2256
2257                                                 <&dummy>,       <&dummy>,
2258                                                 <&dummy>,       <&dummy>,
2259
2260                                                 <&dummy>,       <&dummy>,
2261                                                 <&dummy>,       <&dummy>;
2262
2263                                         clock-output-names =
2264                                                 "reserved",     "reserved",
2265                                                 "reserved",     "reserved",
2266
2267                                                 "reserved",     "reserved",
2268                                                 "reserved",     "reserved",
2269
2270                                                 "reserved",     "reserved",
2271                                                 "reserved",     "reserved",
2272
2273                                                 "reserved",     "reserved",
2274                                                 "reserved",     "reserved";
2275
2276                                         #clock-cells = <1>;
2277                                 };
2278
2279                                 clk_gates12: gate-clk@0230 {
2280                                         compatible = "rockchip,rk3188-gate-clk";
2281                                         reg = <0x0230 0x4>;
2282                                         clocks =
2283                                                 <&pclk_bus>,    <&pclk_bus>,
2284                                                 <&pclk_bus>,    <&pclk_bus>,
2285
2286                                                 <&aclk_bus>,    <&aclk_bus>,
2287                                                 <&aclk_bus>,    <&hclk_bus>,
2288
2289                                                 <&hclk_bus>,    <&hclk_bus>,
2290                                                 <&hclk_bus>,    <&aclk_bus>,
2291
2292                                                 <&aclk_bus>,    <&dummy>,
2293                                                 <&dummy>,       <&dummy>;
2294
2295                                         clock-output-names =
2296                                                 "g_pclk_pwm0",  "g_p_mailbox",
2297                                                 "g_p_i2cpmu",   "g_p_i2caudio",
2298
2299                                                 "g_aclk_intmem",        "g_clk_intmem0",
2300                                                 "g_clk_intmem1",        "g_h_i2s_8ch",
2301
2302                                                 "g_h_i2s_2ch",  "g_hclk_rom",
2303                                                 "g_hclk_spdif", "g_aclk_dmac",
2304
2305                                                 "g_a_strc_sys", "reserved",/* bit13: pclk_ddrupctl */
2306                                                 "reserved",     "reserved";/* bit14: pclk_ddrphy */
2307
2308                                         #clock-cells = <1>;
2309                                 };
2310
2311                                 clk_gates13: gate-clk@0234 {
2312                                         compatible = "rockchip,rk3188-gate-clk";
2313                                         reg = <0x0234 0x4>;
2314                                         clocks =
2315                                                 <&pclk_bus>,    <&pclk_bus>,
2316                                                 <&dummy>,       <&hclk_bus>,
2317
2318                                                 <&hclk_bus>,    <&pclk_bus>,
2319                                                 <&pclk_bus>,    <&clkin_hsadc_tsp>,
2320
2321                                                 <&pclk_bus>,    <&aclk_bus>,
2322                                                 <&hclk_bus>,    <&dummy>,
2323
2324                                                 <&dummy>,       <&dummy>,
2325                                                 <&dummy>,       <&dummy>;
2326
2327                                         clock-output-names =
2328                                                 "g_p_efuse_1024",       "g_p_efuse_256",
2329                                                 "reserved",     "g_mclk_crypto",/* bit2: nclk_ddrupctl */
2330
2331                                                 "g_sclk_crypto",        "g_p_uartdbg",
2332                                                 "g_pclk_pwm1",  "clk_hsadc_tsp",
2333
2334                                                 "g_pclk_sim",   "g_aclk_gic400",
2335                                                 "g_hclk_tsp",   "reserved",
2336
2337                                                 "reserved",     "reserved",
2338                                                 "reserved",     "reserved";
2339
2340                                         #clock-cells = <1>;
2341                                 };
2342
2343                                 clk_gates14: gate-clk@0238 {
2344                                         compatible = "rockchip,rk3188-gate-clk";
2345                                         reg = <0x0238 0x4>;
2346                                         clocks =
2347                                                 <&dummy>,       <&dummy>,
2348                                                 <&dummy>,       <&dummy>,
2349
2350                                                 <&dummy>,       <&dummy>,
2351                                                 <&dummy>,       <&dummy>,
2352
2353                                                 <&dummy>,       <&dummy>,
2354                                                 <&dummy>,       <&dummy>,
2355
2356                                                 <&dummy>,       <&dummy>,
2357                                                 <&dummy>,       <&dummy>;
2358
2359                                         clock-output-names =
2360                                                 "reserved",     "reserved",
2361                                                 "reserved",     "reserved",
2362
2363                                                 "reserved",     "reserved",
2364                                                 "reserved",     "reserved",
2365
2366                                                 "reserved",     "reserved",
2367                                                 "reserved",     "reserved",
2368
2369                                                 "reserved",     "reserved",
2370                                                 "reserved",     "reserved";
2371
2372                                         #clock-cells = <1>;
2373                                 };
2374
2375                                 clk_gates15: gate-clk@023c {
2376                                         compatible = "rockchip,rk3188-gate-clk";
2377                                         reg = <0x023c 0x4>;
2378                                         clocks =
2379                                                 <&dummy>,       <&dummy>,
2380                                                 <&dummy>,       <&dummy>,
2381
2382                                                 <&dummy>,       <&dummy>,
2383                                                 <&dummy>,       <&dummy>,
2384
2385                                                 <&dummy>,       <&dummy>,
2386                                                 <&dummy>,       <&dummy>,
2387
2388                                                 <&dummy>,       <&dummy>,
2389                                                 <&dummy>,       <&dummy>;
2390
2391                                         clock-output-names =
2392                                                 "reserved",     "reserved",/* aclk_video hclk_video */
2393                                                 "reserved",     "reserved",
2394
2395                                                 "reserved",     "reserved",
2396                                                 "reserved",     "reserved",
2397
2398                                                 "reserved",     "reserved",
2399                                                 "reserved",     "reserved",
2400
2401                                                 "reserved",     "reserved",
2402                                                 "reserved",     "reserved";
2403
2404                                         #clock-cells = <1>;
2405                                 };
2406
2407                                 clk_gates16: gate-clk@0240 {
2408                                         compatible = "rockchip,rk3188-gate-clk";
2409                                         reg = <0x0240 0x4>;
2410                                         clocks =
2411                                                 <&clk_gates16 10>,      <&clk_gates16 8>,
2412                                                 <&clk_gates16 9>,       <&clk_gates16 8>,
2413
2414                                                 <&clk_gates16 9>,       <&clk_gates16 9>,
2415                                                 <&clk_gates16 8>,       <&clk_gates16 8>,
2416
2417                                                 <&hclk_vio>,    <&aclk_vio0>,
2418                                                 <&aclk_rga_pre>,        <&clk_gates16 9>,
2419
2420                                                 <&clk_gates16 8>,       <&pclkin_vip>,
2421                                                 <&clk_isp>,     <&dummy>;
2422
2423                                         clock-output-names =
2424                                                 "g_aclk_rga",   "g_hclk_rga",
2425                                                 "g_aclk_iep",   "g_hclk_iep",
2426
2427                                                 "g_aclk_vop_iep",       "g_aclk_vop",
2428                                                 "g_hclk_vop",   "g_h_vio_ahb_arbi",
2429
2430                                                 "g_hclk_vio_noc",       "g_aclk_vio0_noc",
2431                                                 "g_aclk_vio1_noc",      "g_aclk_vip",
2432
2433                                                 "g_hclk_vip",   "g_pclkin_vip",
2434                                                 "g_hclk_isp",   "reserved";
2435
2436                                         #clock-cells = <1>;
2437                                 };
2438
2439                                 clk_gates17: gate-clk@0244 {
2440                                         compatible = "rockchip,rk3188-gate-clk";
2441                                         reg = <0x0244 0x4>;
2442                                         clocks =
2443                                                 <&clk_isp>,     <&dummy>,
2444                                                 <&pclkin_isp>,  <&pclk_vio>,
2445
2446                                                 <&pclk_vio>,    <&dummy>,
2447                                                 <&pclk_vio>,    <&clk_gates16 8>,
2448
2449                                                 <&pclk_vio>,    <&pclk_vio>,
2450                                                 <&clk_gates16 10>,      <&pclk_vio>,
2451
2452                                                 <&clk_gates16 8>,       <&dummy>,
2453                                                 <&dummy>,       <&dummy>;
2454
2455                                         clock-output-names =
2456                                                 "g_aclk_isp",   "reserved",
2457                                                 "g_pclkin_isp", "g_p_mipi_dsi0",
2458
2459                                                 "g_p_mipi_csi", "reserved",
2460                                                 "g_p_hdmi_ctrl",        "g_hclk_vio_h2p",
2461
2462                                                 "g_pclk_vio_h2p",       "g_p_edp_ctrl",
2463                                                 "g_aclk_hdcp",  "g_pclk_hdcp",
2464
2465                                                 "g_h_hdcpmmu",  "reserved",
2466                                                 "reserved",     "reserved";
2467
2468                                         #clock-cells = <1>;
2469                                 };
2470
2471                                 clk_gates18: gate-clk@0248 {
2472                                         compatible = "rockchip,rk3188-gate-clk";
2473                                         reg = <0x0248 0x4>;
2474                                         clocks =
2475                                                 <&dummy>,       <&dummy>,
2476                                                 <&dummy>,       <&dummy>,
2477
2478                                                 <&dummy>,       <&dummy>,
2479                                                 <&dummy>,       <&dummy>,
2480
2481                                                 <&dummy>,       <&dummy>,
2482                                                 <&dummy>,       <&dummy>,
2483
2484                                                 <&dummy>,       <&dummy>,
2485                                                 <&dummy>,       <&dummy>;
2486
2487                                         clock-output-names =
2488                                                 "reserved",     "reserved",/* bit0-1: aclk_gpu_cfg aclk_gpu_mem */
2489                                                 "reserved",     "reserved",/* bit2: clk_gpu_core */
2490
2491                                                 "reserved",     "reserved",
2492                                                 "reserved",     "reserved",
2493
2494                                                 "reserved",     "reserved",
2495                                                 "reserved",     "reserved",
2496
2497                                                 "reserved",     "reserved",
2498                                                 "reserved",     "reserved";
2499
2500                                         #clock-cells = <1>;
2501                                 };
2502
2503                                 clk_gates19: gate-clk@024c {
2504                                         compatible = "rockchip,rk3188-gate-clk";
2505                                         reg = <0x024c 0x4>;
2506                                         clocks =
2507                                                 <&hclk_peri>,   <&pclk_peri>,
2508                                                 <&aclk_peri>,   <&aclk_peri>,
2509
2510                                                 <&pclk_peri>,   <&pclk_peri>,
2511                                                 <&pclk_peri>,   <&pclk_peri>,
2512
2513                                                 <&pclk_peri>,   <&pclk_peri>,
2514                                                 <&pclk_peri>,   <&pclk_peri>,
2515
2516                                                 <&pclk_peri>,   <&pclk_peri>,
2517                                                 <&pclk_peri>,   <&pclk_peri>;
2518
2519                                         clock-output-names =
2520                                                 "g_h_p_axi_matrix",     "g_p_p_axi_matrix",
2521                                                 "g_a_p_axi_matrix",     "g_a_dmac_peri",
2522
2523                                                 "g_pclk_spi0",  "g_pclk_spi1",
2524                                                 "g_pclk_spi2",  "g_pclk_uart0",
2525
2526                                                 "g_pclk_uart1", "g_pclk_uart3",
2527                                                 "g_pclk_uart4", "g_pclk_i2c2",
2528
2529                                                 "g_pclk_i2c3",  "g_pclk_i2c4",
2530                                                 "g_pclk_i2c5",  "g_pclk_saradc";
2531
2532                                         #clock-cells = <1>;
2533                                 };
2534
2535                                 clk_gates20: gate-clk@0250 {
2536                                         compatible = "rockchip,rk3188-gate-clk";
2537                                         reg = <0x0250 0x4>;
2538                                         clocks =
2539                                                 <&pclk_peri>,   <&hclk_peri>,
2540                                                 <&hclk_peri>,   <&hclk_peri>,
2541
2542                                                 <&dummy>,       <&hclk_peri>,
2543                                                 <&hclk_peri>,   <&hclk_peri>,
2544
2545                                                 <&aclk_peri>,   <&hclk_peri>,
2546                                                 <&hclk_peri>,   <&hclk_peri>,
2547
2548                                                 <&dummy>,       <&aclk_peri>,
2549                                                 <&pclk_peri>,   <&aclk_peri>;
2550
2551                                         clock-output-names =
2552                                                 "g_pclk_tsadc", "g_hclk_otg0",
2553                                                 "g_h_pmu_otg0", "g_hclk_host0",
2554
2555                                                 "reserved",     "g_hclk_hsic",
2556                                                 "g_h_usb_peri", "g_h_p_ahb_arbi",
2557
2558                                                 "g_a_peri_niu", "g_h_emem_peri",
2559                                                 "g_h_mmc_peri", "g_hclk_nand0",
2560
2561                                                 "reserved",     "g_aclk_gmac",
2562                                                 "g_pclk_gmac",  "g_hclk_sfc";
2563
2564                                         #clock-cells = <1>;
2565                                 };
2566
2567                                 clk_gates21: gate-clk@0254 {
2568                                         compatible = "rockchip,rk3188-gate-clk";
2569                                         reg = <0x0254 0x4>;
2570                                         clocks =
2571                                                 <&hclk_peri>,   <&hclk_peri>,
2572                                                 <&hclk_peri>,   <&hclk_peri>,
2573
2574                                                 <&aclk_peri>,   <&dummy>,
2575                                                 <&dummy>,       <&dummy>,
2576
2577                                                 <&dummy>,       <&dummy>,
2578                                                 <&dummy>,       <&dummy>,
2579
2580                                                 <&dummy>,       <&dummy>,
2581                                                 <&dummy>,       <&dummy>;
2582
2583                                         clock-output-names =
2584                                                 "g_hclk_sdmmc", "g_hclk_sdio0",
2585                                                 "g_hclk_emmc",  "g_hclk_hsadc",
2586
2587                                                 "g_aclk_peri_mmu",      "reserved",
2588                                                 "reserved",     "reserved",
2589
2590                                                 "reserved",     "reserved",
2591                                                 "reserved",     "reserved",
2592
2593                                                 "reserved",     "reserved",
2594                                                 "reserved",     "reserved";
2595
2596                                         #clock-cells = <1>;
2597                                 };
2598
2599                                 clk_gates22: gate-clk@0258 {
2600                                         compatible = "rockchip,rk3188-gate-clk";
2601                                         reg = <0x0258 0x4>;
2602                                         clocks =
2603                                                 <&dummy>,       <&pclk_alive_pre>,
2604                                                 <&pclk_alive_pre>,      <&pclk_alive_pre>,
2605
2606                                                 <&dummy>,       <&dummy>,
2607                                                 <&dummy>,       <&dummy>,
2608
2609                                                 <&pclk_alive_pre>,      <&pclk_alive_pre>,
2610                                                 <&pclk_vio>,    <&pclk_vio>,
2611
2612                                                 <&pclk_alive_pre>,      <&pclk_alive_pre>,
2613                                                 <&dummy>,       <&dummy>;
2614
2615                                         clock-output-names =
2616                                                 "reserved",     "g_pclk_gpio1",
2617                                                 "g_pclk_gpio2", "g_pclk_gpio3",
2618
2619                                                 "reserved",     "reserved",
2620                                                 "reserved",     "reserved",
2621
2622                                                 "g_pclk_grf",   "g_p_alive_niu",
2623                                                 "g_pclk_dphytx0",       "g_pclk_dphyrx",
2624
2625                                                 "g_pclk_timer0",        "g_pclk_timer1",
2626                                                 "reserved",     "reserved";
2627
2628                                         #clock-cells = <1>;
2629                                 };
2630
2631                                 clk_gates23: gate-clk@025c {
2632                                         compatible = "rockchip,rk3188-gate-clk";
2633                                         reg = <0x025c 0x4>;
2634                                         clocks =
2635                                                 <&pclk_pmu_pre>,        <&pclk_pmu_pre>,
2636                                                 <&pclk_pmu_pre>,        <&pclk_pmu_pre>,
2637
2638                                                 <&pclk_pmu_pre>,        <&pclk_pmu_pre>,
2639                                                 <&dummy>,       <&dummy>,
2640
2641                                                 <&dummy>,       <&dummy>,
2642                                                 <&dummy>,       <&dummy>,
2643
2644                                                 <&dummy>,       <&dummy>,
2645                                                 <&dummy>,       <&dummy>;
2646
2647                                         clock-output-names =
2648                                                 "g_pclk_pmu",   "g_pclk_intmem1",
2649                                                 "g_pclk_pmu_noc",       "g_pclk_sgrf",
2650
2651                                                 "g_pclk_gpio0", "g_pclk_pmugrf",
2652                                                 "reserved",     "reserved",
2653
2654                                                 "reserved",     "reserved",
2655                                                 "reserved",     "reserved",
2656
2657                                                 "reserved",     "reserved",
2658                                                 "reserved",     "reserved";
2659
2660                                         #clock-cells = <1>;
2661                                 };
2662
2663                                 clk_gates24: gate-clk@0260 {
2664                                         compatible = "rockchip,rk3188-gate-clk";
2665                                         reg = <0x0260 0x4>;
2666                                         clocks =
2667                                                 <&xin24m>,      <&xin24m>,
2668                                                 <&xin24m>,      <&xin24m>,
2669
2670                                                 <&xin24m>,      <&xin24m>,
2671                                                 <&xin24m>,      <&xin24m>,
2672
2673                                                 <&xin24m>,      <&xin24m>,
2674                                                 <&xin24m>,      <&xin24m>,
2675
2676                                                 <&dummy>,       <&dummy>,
2677                                                 <&dummy>,       <&dummy>;
2678
2679                                         clock-output-names =
2680                                                 "g_clk_timer0", "g_clk_timer1",
2681                                                 "g_clk_timer2", "g_clk_timer3",
2682
2683                                                 "g_clk_timer4", "g_clk_timer5",
2684                                                 "g_clk_timer10",        "g_clk_timer11",
2685
2686                                                 "g_clk_timer12",        "g_clk_timer13",
2687                                                 "g_clk_timer14",        "g_clk_timer15",
2688
2689                                                 "reserved",     "reserved",
2690                                                 "reserved",     "reserved";
2691
2692                                         #clock-cells = <1>;
2693                                 };
2694                         };
2695                 };
2696
2697                 special_regs {
2698                         compatible = "rockchip,rk-clock-special-regs";
2699                         #address-cells = <1>;
2700                         #size-cells = <1>;
2701                         ranges;
2702
2703                         clk_32k_mux: clk_32k_mux {
2704                                 compatible = "rockchip,rk3188-mux-con";
2705                                 reg = <0xff738100 0x4>;
2706                                 rockchip,bits = <6 1>;
2707                                 clocks = <&xin32k>, <&clk_gates7 3>;
2708                                 clock-output-names = "clk_32k_mux";
2709                                 #clock-cells = <0>;
2710                                 #clock-init-cells = <1>;
2711                         };
2712                 };
2713         };
2714 };