arch/arm64/boot/dts/rk3368-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014-2015 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk3368.h>
  15
  16 /{
  17         clocks {
  18                 compatible = "rockchip,rk-clocks";
  19                 #address-cells = <1>;
  20                 #size-cells = <1>;
  21                 ranges;
  22
  23                 fixed_rate_cons {
  24                         compatible = "rockchip,rk-fixed-rate-cons";
  25
  26                         xin24m: xin24m {
  27                                 compatible = "rockchip,rk-fixed-clock";
  28                                 clock-output-names = "xin24m";
  29                                 clock-frequency = <24000000>;
  30                                 #clock-cells = <0>;
  31                         };
  32
  33                         xin12m: xin12m {
  34                                 compatible = "rockchip,rk-fixed-clock";
  35                                 clocks = <&xin24m>;
  36                                 clock-output-names = "xin12m";
  37                                 clock-frequency = <12000000>;
  38                                 #clock-cells = <0>;
  39                         };
  40
  41                         xin32k: xin32k {
  42                                 compatible = "rockchip,rk-fixed-clock";
  43                                 clock-output-names = "xin32k";
  44                                 clock-frequency = <32000>;
  45                                 #clock-cells = <0>;
  46                         };
  47
  48                         dummy: dummy {
  49                                 compatible = "rockchip,rk-fixed-clock";
  50                                 clock-output-names = "dummy";
  51                                 clock-frequency = <0>;
  52                                 #clock-cells = <0>;
  53                         };
  54
  55                         jtag_clkin: jtag_clkin {
  56                                 compatible = "rockchip,rk-fixed-clock";
  57                                 clock-output-names = "jtag_clkin";
  58                                 clock-frequency = <0>;
  59                                 #clock-cells = <0>;
  60                         };
  61
  62                         gmac_clkin: gmac_clkin {
  63                                 compatible = "rockchip,rk-fixed-clock";
  64                                 clock-output-names = "gmac_clkin";
  65                                 clock-frequency = <0>;
  66                                 #clock-cells = <0>;
  67                         };
  68
  69                         pclkin_isp: pclkin_isp {
  70                                 compatible = "rockchip,rk-fixed-clock";
  71                                 clock-output-names = "pclkin_isp";
  72                                 clock-frequency = <0>;
  73                                 #clock-cells = <0>;
  74                         };
  75
  76                         pclkin_vip: pclkin_vip {
  77                                 compatible = "rockchip,rk-fixed-clock";
  78                                 clock-output-names = "pclkin_vip";
  79                                 clock-frequency = <0>;
  80                                 #clock-cells = <0>;
  81                         };
  82
  83                         clkin_hsadc_tsp: clkin_hsadc_tsp {
  84                                 compatible = "rockchip,rk-fixed-clock";
  85                                 clock-output-names = "clkin_hsadc_tsp";
  86                                 clock-frequency = <0>;
  87                                 #clock-cells = <0>;
  88                         };
  89
  90                         i2s_clkin: i2s_clkin {
  91                                 compatible = "rockchip,rk-fixed-clock";
  92                                 clock-output-names = "i2s_clkin";
  93                                 clock-frequency = <0>;
  94                                 #clock-cells = <0>;
  95                         };
  96                 };
  97
  98                 fixed_factor_cons {
  99                         compatible = "rockchip,rk-fixed-factor-cons";
 100
 101                         hclk_vepu: hclk_vepu {
 102                                 compatible = "rockchip,rk-fixed-factor-clock";
 103                                 clocks = <&aclk_vepu>;
 104                                 clock-output-names = "hclk_vepu";
 105                                 clock-div = <4>;
 106                                 clock-mult = <1>;
 107                                 #clock-cells = <0>;
 108                         };
 109
 110                         hclk_vdpu: hclk_vdpu {
 111                                 compatible = "rockchip,rk-fixed-factor-clock";
 112                                 clocks = <&aclk_vdpu>;
 113                                 clock-output-names = "hclk_vdpu";
 114                                 clock-div = <4>;
 115                                 clock-mult = <1>;
 116                                 #clock-cells = <0>;
 117                         };
 118
 119                         usbotg_480m_out: usbotg_480m_out {
 120                                 compatible = "rockchip,rk-fixed-factor-clock";
 121                                 clocks = <&clk_gates8 1>;
 122                                 clock-output-names = "usbotg_480m_out";
 123                                 clock-div = <1>;
 124                                 clock-mult = <20>;
 125                                 #clock-cells = <0>;
 126                         };
 127
 128                         pclkin_isp_inv: pclkin_isp_inv {
 129                                 compatible = "rockchip,rk-fixed-factor-clock";
 130                                 clocks = <&clk_gates17 2>;
 131                                 clock-output-names = "pclkin_isp_inv";
 132                                 clock-div = <1>;
 133                                 clock-mult = <1>;
 134                                 #clock-cells = <0>;
 135                         };
 136
 137                         pclkin_vip_inv: pclkin_vip_inv {
 138                                 compatible = "rockchip,rk-fixed-factor-clock";
 139                                 clocks = <&clk_gates16 13>;
 140                                 clock-output-names = "pclkin_vip_inv";
 141                                 clock-div = <1>;
 142                                 clock-mult = <1>;
 143                                 #clock-cells = <0>;
 144                         };
 145
 146                         pclk_vio: pclk_vio {
 147                                 compatible = "rockchip,rk-fixed-factor-clock";
 148                                 clocks = <&clk_gates16 8>;
 149                                 clock-output-names = "pclk_vio";
 150                                 clock-div = <1>;
 151                                 clock-mult = <1>;
 152                                 #clock-cells = <0>;
 153                         };
 154                 };
 155
 156                 clock_regs {
 157                         compatible = "rockchip,rk-clock-regs";
 158                         #address-cells = <1>;
 159                         #size-cells = <1>;
 160                         ranges = <0x0 0xFF760000 0x0264>;
 161                         reg = <0xFF760000 0x0264>;/* NEED CONFIRM */
 162
 163                         /* PLL control regs */
 164                         pll_cons {
 165                                 compatible = "rockchip,rk-pll-cons";
 166                                 #address-cells = <1>;
 167                                 #size-cells = <1>;
 168                                 ranges;
 169
 170                                 clk_apllb: pll-clk@0000 {
 171                                         compatible = "rockchip,rk3188-pll-clk";
 172                                         reg = <0x0000 0x10>;
 173                                         mode-reg = <0x000c 8>;
 174                                         status-reg = <0x0480 1>;
 175                                         clocks = <&xin24m>;
 176                                         clock-output-names = "clk_apllb";
 177                                         rockchip,pll-type = <CLK_PLL_3368_APLLB>;
 178                                         #clock-cells = <0>;
 179                                 };
 180
 181
 182                                 clk_aplll: pll-clk@0010 {
 183                                         compatible = "rockchip,rk3188-pll-clk";
 184                                         reg = <0x0010 0x10>;
 185                                         mode-reg = <0x001c 8>;
 186                                         status-reg = <0x0480 0>;
 187                                         clocks = <&xin24m>;
 188                                         clock-output-names = "clk_aplll";
 189                                         rockchip,pll-type = <CLK_PLL_3368_APLLL>;
 190                                         #clock-cells = <0>;
 191                                 };
 192
 193                                 clk_dpll: pll-clk@0020 {
 194                                         compatible = "rockchip,rk3188-pll-clk";
 195                                         reg = <0x0020 0x10>;
 196                                         mode-reg = <0x002c 8>;
 197                                         status-reg = <0x0480 2>;
 198                                         clocks = <&xin24m>;
 199                                         clock-output-names = "clk_dpll";
 200                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 201                                         #clock-cells = <0>;
 202                                 };
 203
 204
 205                                 clk_cpll: pll-clk@0030 {
 206                                         compatible = "rockchip,rk3188-pll-clk";
 207                                         reg = <0x0030 0x10>;
 208                                         mode-reg = <0x003c 8>;
 209                                         status-reg = <0x0480 3>;
 210                                         clocks = <&xin24m>;
 211                                         clock-output-names = "clk_cpll";
 212                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 213                                         #clock-cells = <0>;
 214                                         #clock-init-cells = <1>;
 215                                 };
 216
 217                                 clk_gpll: pll-clk@0040 {
 218                                         compatible = "rockchip,rk3188-pll-clk";
 219                                         reg = <0x0040 0x10>;
 220                                         mode-reg = <0x004c 8>;
 221                                         status-reg = <0x0480 4>;
 222                                         clocks = <&xin24m>;
 223                                         clock-output-names = "clk_gpll";
 224                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 225                                         #clock-cells = <0>;
 226                                         #clock-init-cells = <1>;
 227                                 };
 228
 229                                 clk_npll: pll-clk@0050 {
 230                                         compatible = "rockchip,rk3188-pll-clk";
 231                                         reg = <0x0050 0x10>;
 232                                         mode-reg = <0x005c 8>;
 233                                         status-reg = <0x0480 5>;
 234                                         clocks = <&xin24m>;
 235                                         clock-output-names = "clk_npll";
 236                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 237                                         #clock-cells = <0>;
 238                                         #clock-init-cells = <1>;
 239                                 };
 240                         };
 241
 242                         /* Select control regs */
 243                         clk_sel_cons {
 244                                 compatible = "rockchip,rk-sel-cons";
 245                                 #address-cells = <1>;
 246                                 #size-cells = <1>;
 247                                 ranges;
 248
 249                                 clk_sel_con0: sel-con@0100 {
 250                                         compatible = "rockchip,rk3188-selcon";
 251                                         reg = <0x0100 0x4>;
 252                                         #address-cells = <1>;
 253                                         #size-cells = <1>;
 254
 255                                         clk_core_b_div: clk_core_b_div {
 256                                                 compatible = "rockchip,rk3188-div-con";
 257                                                 rockchip,bits = <0 5>;
 258                                                 clocks = <&clk_core_b>;
 259                                                 clock-output-names = "clk_core_b";
 260                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 261                                                 #clock-cells = <0>;
 262                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 263                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 264                                                                         CLK_SET_RATE_NO_REPARENT)>;
 265                                         };
 266
 267                                         /* 6:5 reserved */
 268
 269                                         clk_core_b: clk_core_b_mux {
 270                                                 compatible = "rockchip,rk3188-mux-con";
 271                                                 rockchip,bits = <7 1>;
 272                                                 clocks = <&clk_apllb>, <&clk_gpll>;
 273                                                 clock-output-names = "clk_core_b";
 274                                                 #clock-cells = <0>;
 275                                                 #clock-init-cells = <1>;
 276                                         };
 277
 278                                         aclkm_core_b: aclkm_core_b_div {
 279                                                 compatible = "rockchip,rk3188-div-con";
 280                                                 rockchip,bits = <8 5>;
 281                                                 clocks = <&clk_core_b>;
 282                                                 clock-output-names = "aclkm_core_b";
 283                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 284                                                 #clock-cells = <0>;
 285                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 286                                         };
 287
 288                                         /* 15:13 reserved */
 289                                 };
 290
 291                                 clk_sel_con1: sel-con@0104 {
 292                                         compatible = "rockchip,rk3188-selcon";
 293                                         reg = <0x0104 0x4>;
 294                                         #address-cells = <1>;
 295                                         #size-cells = <1>;
 296
 297                                         atclk_core_b: atclk_core_b_div {
 298                                                 compatible = "rockchip,rk3188-div-con";
 299                                                 rockchip,bits = <0 5>;
 300                                                 clocks = <&clk_core_b>;
 301                                                 clock-output-names = "atclk_core_b";
 302                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 303                                                 #clock-cells = <0>;
 304                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 305                                         };
 306
 307                                         /* 7:5 reserved */
 308
 309                                         pclk_dbg_b: pclk_dbg_b_div {
 310                                                 compatible = "rockchip,rk3188-div-con";
 311                                                 rockchip,bits = <8 5>;
 312                                                 clocks = <&clk_core_b>;
 313                                                 clock-output-names = "pclk_dbg_b";
 314                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 315                                                 #clock-cells = <0>;
 316                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 317                                         };
 318                                 };
 319
 320                                 clk_sel_con2: sel-con@0108 {
 321                                         compatible = "rockchip,rk3188-selcon";
 322                                         reg = <0x0108 0x4>;
 323                                         #address-cells = <1>;
 324                                         #size-cells = <1>;
 325
 326                                         clk_core_l_div: clk_core_l_div {
 327                                                 compatible = "rockchip,rk3188-div-con";
 328                                                 rockchip,bits = <0 5>;
 329                                                 clocks = <&clk_core_l>;
 330                                                 clock-output-names = "clk_core_l";
 331                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 332                                                 #clock-cells = <0>;
 333                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 334                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 335                                                                         CLK_SET_RATE_NO_REPARENT)>;
 336                                         };
 337
 338                                         /* 6:5 reserved */
 339
 340                                         clk_core_l: clk_core_l_mux {
 341                                                 compatible = "rockchip,rk3188-mux-con";
 342                                                 rockchip,bits = <7 1>;
 343                                                 clocks = <&clk_aplll>, <&clk_gpll>;
 344                                                 clock-output-names = "clk_core_l";
 345                                                 #clock-cells = <0>;
 346                                                 #clock-init-cells = <1>;
 347                                         };
 348
 349                                         aclkm_core_l: aclkm_core_l_div {
 350                                                 compatible = "rockchip,rk3188-div-con";
 351                                                 rockchip,bits = <8 5>;
 352                                                 clocks = <&clk_core_l>;
 353                                                 clock-output-names = "aclkm_core_l";
 354                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 355                                                 #clock-cells = <0>;
 356                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 357                                         };
 358
 359                                         /* 15:13 reserved */
 360                                 };
 361
 362                                 clk_sel_con3: sel-con@010c {
 363                                         compatible = "rockchip,rk3188-selcon";
 364                                         reg = <0x010c 0x4>;
 365                                         #address-cells = <1>;
 366                                         #size-cells = <1>;
 367
 368                                         atclk_core_l: atclk_core_l_div {
 369                                                 compatible = "rockchip,rk3188-div-con";
 370                                                 rockchip,bits = <0 5>;
 371                                                 clocks = <&clk_core_l>;
 372                                                 clock-output-names = "atclk_core_l";
 373                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 374                                                 #clock-cells = <0>;
 375                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 376                                         };
 377
 378                                         /* 7:5 reserved */
 379
 380                                         pclk_dbg_l: pclk_dbg_l_div {
 381                                                 compatible = "rockchip,rk3188-div-con";
 382                                                 rockchip,bits = <8 5>;
 383                                                 clocks = <&clk_core_l>;
 384                                                 clock-output-names = "pclk_dbg_l";
 385                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 386                                                 #clock-cells = <0>;
 387                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 388                                         };
 389                                 };
 390
 391                                 clk_sel_con4: sel-con@0110 {
 392                                         compatible = "rockchip,rk3188-selcon";
 393                                         reg = <0x0110 0x4>;
 394                                         #address-cells = <1>;
 395                                         #size-cells = <1>;
 396
 397                                         clk_cs_div: clk_cs_div {
 398                                                 compatible = "rockchip,rk3188-div-con";
 399                                                 rockchip,bits = <0 5>;
 400                                                 clocks = <&clk_cs>;
 401                                                 clock-output-names = "clk_cs";
 402                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 403                                                 #clock-cells = <0>;
 404                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 405                                         };
 406
 407                                         /* 5 reserved */
 408
 409                                         clk_cs: clk_cs_mux {
 410                                                 compatible = "rockchip,rk3188-mux-con";
 411                                                 rockchip,bits = <6 2>;
 412                                                 clocks = <&clk_gates0 9>, <&clk_gates0 10>, <&clk_gates0 8>, <&dummy>;
 413                                                 clock-output-names = "clk_cs";
 414                                                 #clock-cells = <0>;
 415                                                 #clock-init-cells = <1>;
 416                                         };
 417
 418                                         clkin_trace: clkin_trace_div {
 419                                                 compatible = "rockchip,rk3188-div-con";
 420                                                 rockchip,bits = <8 5>;
 421                                                 clocks = <&clk_cs>;
 422                                                 clock-output-names = "clkin_trace";
 423                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 424                                                 #clock-cells = <0>;
 425                                         };
 426
 427                                 };
 428
 429                                 clk_sel_con5: sel-con@0114 {
 430                                         compatible = "rockchip,rk3188-selcon";
 431                                         reg = <0x0114 0x4>;
 432                                         #address-cells = <1>;
 433                                         #size-cells = <1>;
 434
 435                                         aclk_cci_div: aclk_cci_div {
 436                                                 compatible = "rockchip,rk3188-div-con";
 437                                                 rockchip,bits = <0 5>;
 438                                                 clocks = <&aclk_cci>;
 439                                                 clock-output-names = "aclk_cci";
 440                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 441                                                 #clock-cells = <0>;
 442                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 443                                         };
 444
 445                                         /* 5 reserved */
 446
 447                                         aclk_cci: aclk_cci_mux {
 448                                                 compatible = "rockchip,rk3188-mux-con";
 449                                                 rockchip,bits = <6 2>;
 450                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
 451                                                 clock-output-names = "aclk_cci";
 452                                                 #clock-cells = <0>;
 453                                                 #clock-init-cells = <1>;
 454                                         };
 455                                 };
 456
 457                                 /* sel[7:6] reserved */
 458
 459                                 clk_sel_con8: sel-con@0120 {
 460                                         compatible = "rockchip,rk3188-selcon";
 461                                         reg = <0x0120 0x4>;
 462                                         #address-cells = <1>;
 463                                         #size-cells = <1>;
 464
 465                                         aclk_bus_div: aclk_bus_div {
 466                                                 compatible = "rockchip,rk3188-div-con";
 467                                                 rockchip,bits = <0 5>;
 468                                                 clocks = <&aclk_bus>;
 469                                                 clock-output-names = "aclk_bus_div";
 470                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 471                                                 #clock-cells = <0>;
 472                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 473                                         };
 474
 475                                         /* 6:5 reserved */
 476
 477                                         aclk_bus: aclk_bus_mux {
 478                                                 compatible = "rockchip,rk3188-mux-con";
 479                                                 rockchip,bits = <7 1>;
 480                                                 clocks = <&clk_gates1 11>, <&clk_gates1 10>;
 481                                                 clock-output-names = "aclk_bus";
 482                                                 #clock-cells = <0>;
 483                                                 #clock-init-cells = <1>;
 484                                         };
 485
 486                                         hclk_bus: hclk_bus_div {
 487                                                 compatible = "rockchip,rk3188-div-con";
 488                                                 rockchip,bits = <8 2>;
 489                                                 clocks = <&aclk_bus>;
 490                                                 clock-output-names = "hclk_bus";
 491                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 492                                                 #clock-cells = <0>;
 493                                         };
 494
 495                                         /* 11:10 reserved */
 496
 497                                         pclk_bus: pclk_bus_div {
 498                                                 compatible = "rockchip,rk3188-div-con";
 499                                                 rockchip,bits = <12 3>;
 500                                                 clocks = <&aclk_bus>;
 501                                                 clock-output-names = "pclk_bus";
 502                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 503                                                 #clock-cells = <0>;
 504                                         };
 505                                 };
 506
 507                                 clk_sel_con9: sel-con@0124 {
 508                                         compatible = "rockchip,rk3188-selcon";
 509                                         reg = <0x0124 0x4>;
 510                                         #address-cells = <1>;
 511                                         #size-cells = <1>;
 512
 513                                         aclk_peri_div: aclk_peri_div {
 514                                                 compatible = "rockchip,rk3188-div-con";
 515                                                 rockchip,bits = <0 5>;
 516                                                 clocks = <&aclk_peri>;
 517                                                 clock-output-names = "aclk_peri_div";
 518                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 519                                                 #clock-cells = <0>;
 520                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 521                                         };
 522
 523                                         /* 6:5 reserved */
 524
 525                                         aclk_peri: aclk_peri_mux {
 526                                                 compatible = "rockchip,rk3188-mux-con";
 527                                                 rockchip,bits = <7 1>;
 528                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 529                                                 clock-output-names = "aclk_peri";
 530                                                 #clock-cells = <0>;
 531                                                 #clock-init-cells = <1>;
 532                                         };
 533
 534                                         hclk_peri: hclk_peri_div {
 535                                                 compatible = "rockchip,rk3188-div-con";
 536                                                 rockchip,bits = <8 2>;
 537                                                 clocks = <&aclk_peri>;
 538                                                 clock-output-names = "hclk_peri";
 539                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 540                                                 rockchip,div-relations =
 541                                                                 <0x0 1
 542                                                                  0x1 2
 543                                                                  0x2 4>;
 544                                                 #clock-cells = <0>;
 545                                                 #clock-init-cells = <1>;
 546                                         };
 547
 548                                         /* 11:10 reserved */
 549
 550                                         pclk_peri: pclk_peri_div {
 551                                                 compatible = "rockchip,rk3188-div-con";
 552                                                 rockchip,bits = <12 2>;
 553                                                 clocks = <&aclk_peri>;
 554                                                 clock-output-names = "pclk_peri";
 555                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 556                                                 rockchip,div-relations =
 557                                                                 <0x0 1
 558                                                                  0x1 2
 559                                                                  0x2 4
 560                                                                  0x3 8>;
 561                                                 #clock-cells = <0>;
 562                                                 #clock-init-cells = <1>;
 563                                         };
 564                                 };
 565
 566                                 clk_sel_con10: sel-con@0128 {
 567                                         compatible = "rockchip,rk3188-selcon";
 568                                         reg = <0x0128 0x4>;
 569                                         #address-cells = <1>;
 570                                         #size-cells = <1>;
 571
 572                                         pclk_pmu_pre: pclk_pmu_pre_div {
 573                                                 compatible = "rockchip,rk3188-div-con";
 574                                                 rockchip,bits = <0 5>;
 575                                                 clocks = <&clk_gpll>;
 576                                                 clock-output-names = "pclk_pmu_pre";
 577                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 578                                                 #clock-cells = <0>;
 579                                         };
 580
 581                                         /* 7:5 reserved */
 582
 583                                         pclk_alive_pre: pclk_alive_pre_div {
 584                                                 compatible = "rockchip,rk3188-div-con";
 585                                                 rockchip,bits = <8 5>;
 586                                                 clocks = <&clk_gpll>;
 587                                                 clock-output-names = "pclk_alive_pre";
 588                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 589                                                 #clock-cells = <0>;
 590                                         };
 591
 592                                         /* 13 reserved */
 593
 594                                         clk_crypto: clk_crypto_div {
 595                                                 compatible = "rockchip,rk3188-div-con";
 596                                                 rockchip,bits = <14 2>;
 597                                                 clocks = <&aclk_bus>;
 598                                                 clock-output-names = "clk_crypto";
 599                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 600                                                 #clock-cells = <0>;
 601                                         };
 602                                 };
 603
 604                                 /* sel[11]: reserved */
 605
 606                                 clk_sel_con12: sel-con@0130 {
 607                                         compatible = "rockchip,rk3188-selcon";
 608                                         reg = <0x0130 0x4>;
 609                                         #address-cells = <1>;
 610                                         #size-cells = <1>;
 611
 612                                         fclk_mcu_div: fclk_mcu_div {
 613                                                 compatible = "rockchip,rk3188-div-con";
 614                                                 rockchip,bits = <0 5>;
 615                                                 clocks = <&fclk_mcu>;
 616                                                 clock-output-names = "fclk_mcu";
 617                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 618                                                 #clock-cells = <0>;
 619                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 620                                         };
 621
 622                                         /* 6:5 reserved */
 623
 624                                         fclk_mcu: fclk_mcu_mux {
 625                                                 compatible = "rockchip,rk3188-mux-con";
 626                                                 rockchip,bits = <7 1>;
 627                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 628                                                 clock-output-names = "fclk_mcu";
 629                                                 #clock-cells = <0>;
 630                                                 #clock-init-cells = <1>;
 631                                         };
 632
 633                                         stclk_mcu: stclk_mcu_div {
 634                                                 compatible = "rockchip,rk3188-div-con";
 635                                                 rockchip,bits = <8 3>;
 636                                                 clocks = <&fclk_mcu>;
 637                                                 clock-output-names = "stclk_mcu";
 638                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 639                                                 #clock-cells = <0>;
 640                                         };
 641                                 };
 642
 643                                 clk_sel_con13: sel-con@0134 {
 644                                         compatible = "rockchip,rk3188-selcon";
 645                                         reg = <0x0134 0x4>;
 646                                         #address-cells = <1>;
 647                                         #size-cells = <1>;
 648
 649                                         clk_ddr_div: clk_ddr_div {
 650                                                 compatible = "rockchip,rk3188-div-con";
 651                                                 rockchip,bits = <0 2>;
 652                                                 clocks = <&clk_ddr>;
 653                                                 clock-output-names = "clk_ddr";
 654                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 655                                                 #clock-cells = <0>;
 656                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 657                                                                         CLK_SET_RATE_NO_REPARENT)>;
 658                                                 rockchip,clkops-idx =
 659                                                         <CLKOPS_RATE_DDR_DIV4>;
 660                                         };
 661
 662                                         /* 3:2 reserved */
 663
 664                                         clk_ddr: clk_ddr_mux {
 665                                                 compatible = "rockchip,rk3188-mux-con";
 666                                                 rockchip,bits = <4 1>;
 667                                                 clocks = <&clk_dpll>, <&clk_gpll>;
 668                                                 clock-output-names = "clk_ddr";
 669                                                 #clock-cells = <0>;
 670                                         };
 671
 672                                         /* 7:5 reserved */
 673
 674                                         /* usbphy_480m_en */
 675
 676                                         usbphy_480m: usbphy_480m_mux {
 677                                                 compatible = "rockchip,rk3188-mux-con";
 678                                                 rockchip,bits = <8 1>;
 679                                                 clocks = <&xin24m>, <&usbotg_480m_out>;
 680                                                 clock-output-names = "usbphy_480m";
 681                                                 #clock-cells = <0>;
 682                                                 rockchip,clkops-idx =
 683                                                         <CLKOPS_RATE_RK3288_USB480M>;
 684                                                 #clock-init-cells = <1>;
 685                                         };
 686
 687                                         clk4x_ddr: clk4x_ddr_mux {
 688                                                 compatible = "rockchip,rk3188-mux-con";
 689                                                 rockchip,bits = <4 1>;
 690                                                 clocks = <&clk_dpll>, <&clk_gpll>;
 691                                                 clock-output-names = "clk4x_ddr";
 692                                                 #clock-cells = <0>;
 693                                         };
 694                                 };
 695
 696                                 clk_sel_con14: sel-con@0138 {
 697                                         compatible = "rockchip,rk3188-selcon";
 698                                         reg = <0x0138 0x4>;
 699                                         #address-cells = <1>;
 700                                         #size-cells = <1>;
 701
 702                                         clk_gpu_core_div: clk_gpu_core_div {
 703                                                 compatible = "rockchip,rk3188-div-con";
 704                                                 rockchip,bits = <0 5>;
 705                                                 clocks = <&clk_gpu_core>;
 706                                                 clock-output-names = "clk_gpu_core";
 707                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 708                                                 #clock-cells = <0>;
 709                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 710                                                 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
 711                                         };
 712
 713                                         /* 5 reserved */
 714
 715                                         clk_gpu_core: clk_gpu_core_mux {
 716                                                 compatible = "rockchip,rk3188-mux-con";
 717                                                 rockchip,bits = <6 2>;
 718                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
 719                                                 clock-output-names = "clk_gpu_core";
 720                                                 #clock-cells = <0>;
 721                                                 #clock-init-cells = <1>;
 722                                         };
 723
 724                                         aclk_gpu_mem: aclk_gpu_mem_div {
 725                                                 compatible = "rockchip,rk3188-div-con";
 726                                                 rockchip,bits = <8 5>;
 727                                                 clocks = <&aclk_gpu>;
 728                                                 clock-output-names = "aclk_gpu_mem";
 729                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 730                                                 #clock-cells = <0>;
 731                                         };
 732
 733                                         /* 13 reserved */
 734
 735                                         aclk_gpu: aclk_gpu_mux {
 736                                                 compatible = "rockchip,rk3188-mux-con";
 737                                                 rockchip,bits = <14 1>;
 738                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 739                                                 clock-output-names = "aclk_gpu";
 740                                                 #clock-cells = <0>;
 741                                                 #clock-init-cells = <1>;
 742                                         };
 743                                 };
 744
 745                                 clk_sel_con15: sel-con@013c {
 746                                         compatible = "rockchip,rk3188-selcon";
 747                                         reg = <0x013c 0x4>;
 748                                         #address-cells = <1>;
 749                                         #size-cells = <1>;
 750
 751                                         aclk_vepu_div: aclk_vepu_div {
 752                                                 compatible = "rockchip,rk3188-div-con";
 753                                                 rockchip,bits = <0 5>;
 754                                                 clocks = <&aclk_vepu>;
 755                                                 clock-output-names = "aclk_vepu";
 756                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 757                                                 #clock-cells = <0>;
 758                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 759                                         };
 760
 761                                         /* 5 reserved */
 762
 763                                         aclk_vepu: aclk_vepu_mux {
 764                                                 compatible = "rockchip,rk3188-mux-con";
 765                                                 rockchip,bits = <6 2>;
 766                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 767                                                 clock-output-names = "aclk_vepu";
 768                                                 #clock-cells = <0>;
 769                                                 #clock-init-cells = <1>;
 770                                         };
 771
 772                                         aclk_vdpu_div: aclk_vdpu_div {
 773                                                 compatible = "rockchip,rk3188-div-con";
 774                                                 rockchip,bits = <8 5>;
 775                                                 clocks = <&aclk_vdpu>;
 776                                                 clock-output-names = "aclk_vdpu";
 777                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 778                                                 #clock-cells = <0>;
 779                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 780                                         };
 781
 782                                         /* 13 reserved */
 783
 784                                         aclk_vdpu: aclk_vdpu_mux {
 785                                                 compatible = "rockchip,rk3188-mux-con";
 786                                                 rockchip,bits = <14 2>;
 787                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 788                                                 clock-output-names = "aclk_vdpu";
 789                                                 #clock-cells = <0>;
 790                                                 #clock-init-cells = <1>;
 791                                         };
 792                                 };
 793
 794                                 clk_sel_con16: sel-con@0140 {
 795                                         compatible = "rockchip,rk3188-selcon";
 796                                         reg = <0x0140 0x4>;
 797                                         #address-cells = <1>;
 798                                         #size-cells = <1>;
 799
 800                                         aclk_gpu_cfg: aclk_gpu_cfg_div {
 801                                                 compatible = "rockchip,rk3188-div-con";
 802                                                 rockchip,bits = <8 5>;
 803                                                 clocks = <&aclk_gpu>;
 804                                                 clock-output-names = "aclk_gpu_cfg";
 805                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 806                                                 #clock-cells = <0>;
 807                                         };
 808                                 };
 809
 810                                 clk_sel_con17: sel-con@0144 {
 811                                         compatible = "rockchip,rk3188-selcon";
 812                                         reg = <0x0144 0x4>;
 813                                         #address-cells = <1>;
 814                                         #size-cells = <1>;
 815
 816                                         clk_hevc_cabac_div: clk_hevc_cabac_div {
 817                                                 compatible = "rockchip,rk3188-div-con";
 818                                                 rockchip,bits = <0 5>;
 819                                                 clocks = <&clk_hevc_cabac>;
 820                                                 clock-output-names = "clk_hevc_cabac";
 821                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 822                                                 #clock-cells = <0>;
 823                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 824                                         };
 825
 826                                         /* 5 reserved */
 827
 828                                         clk_hevc_cabac: clk_hevc_cabac_mux {
 829                                                 compatible = "rockchip,rk3188-mux-con";
 830                                                 rockchip,bits = <6 2>;
 831                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 832                                                 clock-output-names = "clk_hevc_cabac";
 833                                                 #clock-cells = <0>;
 834                                                 #clock-init-cells = <1>;
 835                                         };
 836
 837                                         clk_hevc_core_div: clk_hevc_core_div {
 838                                                 compatible = "rockchip,rk3188-div-con";
 839                                                 rockchip,bits = <8 5>;
 840                                                 clocks = <&clk_hevc_core>;
 841                                                 clock-output-names = "clk_hevc_core";
 842                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 843                                                 #clock-cells = <0>;
 844                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 845                                         };
 846
 847                                         /* 13 reserved */
 848
 849                                         clk_hevc_core: clk_hevc_core_mux {
 850                                                 compatible = "rockchip,rk3188-mux-con";
 851                                                 rockchip,bits = <14 2>;
 852                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 853                                                 clock-output-names = "clk_hevc_core";
 854                                                 #clock-cells = <0>;
 855                                                 #clock-init-cells = <1>;
 856                                         };
 857                                 };
 858
 859                                 clk_sel_con18: sel-con@0148 {
 860                                         compatible = "rockchip,rk3188-selcon";
 861                                         reg = <0x0148 0x4>;
 862                                         #address-cells = <1>;
 863                                         #size-cells = <1>;
 864
 865                                         clk_rga_div: clk_rga_div {
 866                                                 compatible = "rockchip,rk3188-div-con";
 867                                                 rockchip,bits = <0 5>;
 868                                                 clocks = <&clk_rga>;
 869                                                 clock-output-names = "clk_rga";
 870                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 871                                                 #clock-cells = <0>;
 872                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 873                                         };
 874
 875                                         /* 5 reserved */
 876
 877                                         clk_rga: clk_rga_mux {
 878                                                 compatible = "rockchip,rk3188-mux-con";
 879                                                 rockchip,bits = <6 2>;
 880                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
 881                                                 clock-output-names = "clk_rga";
 882                                                 #clock-cells = <0>;
 883                                                 #clock-init-cells = <1>;
 884                                         };
 885
 886                                         aclk_rga_div: aclk_rga_div {
 887                                                 compatible = "rockchip,rk3188-div-con";
 888                                                 rockchip,bits = <8 5>;
 889                                                 clocks = <&aclk_rga_pre>;
 890                                                 clock-output-names = "aclk_rga_pre";
 891                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 892                                                 #clock-cells = <0>;
 893                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 894                                         };
 895
 896                                         /* 13 reserved */
 897
 898                                         aclk_rga_pre: aclk_rga_mux {
 899                                                 compatible = "rockchip,rk3188-mux-con";
 900                                                 rockchip,bits = <14 2>;
 901                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
 902                                                 clock-output-names = "aclk_rga_pre";
 903                                                 #clock-cells = <0>;
 904                                                 #clock-init-cells = <1>;
 905                                         };
 906                                 };
 907
 908                                 clk_sel_con19: sel-con@014c {
 909                                         compatible = "rockchip,rk3188-selcon";
 910                                         reg = <0x014c 0x4>;
 911                                         #address-cells = <1>;
 912                                         #size-cells = <1>;
 913
 914                                         aclk_vio0_div: aclk_vio0_div {
 915                                                 compatible = "rockchip,rk3188-div-con";
 916                                                 rockchip,bits = <0 5>;
 917                                                 clocks = <&aclk_vio0>;
 918                                                 clock-output-names = "aclk_vio0";
 919                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 920                                                 #clock-cells = <0>;
 921                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 922                                         };
 923
 924                                         /* 5 reserved */
 925
 926                                         aclk_vio0: aclk_vio0_mux {
 927                                                 compatible = "rockchip,rk3188-mux-con";
 928                                                 rockchip,bits = <6 2>;
 929                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
 930                                                 clock-output-names = "aclk_vio0";
 931                                                 #clock-cells = <0>;
 932                                                 #clock-init-cells = <1>;
 933                                         };
 934                                 };
 935
 936                                 clk_sel_con20: sel-con@0150 {
 937                                         compatible = "rockchip,rk3188-selcon";
 938                                         reg = <0x0150 0x4>;
 939                                         #address-cells = <1>;
 940                                         #size-cells = <1>;
 941
 942                                         dclk_vop0_div: dclk_vop0_div {
 943                                                 compatible = "rockchip,rk3188-div-con";
 944                                                 rockchip,bits = <0 8>;
 945                                                 clocks = <&dclk_vop0>;
 946                                                 clock-output-names = "dclk_vop0";
 947                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 948                                                 #clock-cells = <0>;
 949                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 950                                         };
 951
 952                                         dclk_vop0: dclk_vop0_mux {
 953                                                 compatible = "rockchip,rk3188-mux-con";
 954                                                 rockchip,bits = <8 2>;
 955                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&dummy>;
 956                                                 clock-output-names = "dclk_vop0";
 957                                                 #clock-cells = <0>;
 958                                                 #clock-init-cells = <1>;
 959                                         };
 960
 961                                         /* 15:10 reserved */
 962                                 };
 963
 964                                 clk_sel_con21: sel-con@0154 {
 965                                         compatible = "rockchip,rk3188-selcon";
 966                                         reg = <0x0154 0x4>;
 967                                         #address-cells = <1>;
 968                                         #size-cells = <1>;
 969
 970                                         hclk_vio: hclk_vio_div {
 971                                                 compatible = "rockchip,rk3188-div-con";
 972                                                 rockchip,bits = <0 5>;
 973                                                 clocks = <&aclk_vio0>;
 974                                                 clock-output-names = "hclk_vio";
 975                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 976                                                 #clock-cells = <0>;
 977                                                 #clock-init-cells = <1>;
 978                                         };
 979
 980                                         /* 5 reserved */
 981
 982                                         pclk_isp: pclk_isp_mux {
 983                                                 compatible = "rockchip,rk3188-mux-con";
 984                                                 rockchip,bits = <6 1>;
 985                                                 clocks = <&clk_gates17 2>, <&pclkin_isp_inv>;
 986                                                 clock-output-names = "pclk_isp";
 987                                                 #clock-cells = <0>;
 988                                         };
 989
 990                                         /* 7 reserved */
 991
 992                                         clk_vip_div: clk_vip_div {
 993                                                 compatible = "rockchip,rk3188-div-con";
 994                                                 rockchip,bits = <8 5>;
 995                                                 clocks = <&clk_vip>;
 996                                                 clock-output-names = "clk_vip";
 997                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 998                                                 #clock-cells = <0>;
 999                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1000                                         };
1001
1002                                         pclk_vip: pclk_vip_mux {
1003                                                 compatible = "rockchip,rk3188-mux-con";
1004                                                 rockchip,bits = <13 1>;
1005                                                 clocks = <&clk_gates16 13>, <&pclkin_vip_inv>;
1006                                                 clock-output-names = "pclk_vip";
1007                                                 #clock-cells = <0>;
1008                                         };
1009
1010                                         clk_vip: clk_vip_mux {
1011                                                 compatible = "rockchip,rk3188-mux-con";
1012                                                 rockchip,bits = <14 2>;
1013                                                 clocks = <&clk_cpll>, <&xin24m>, <&clk_gpll>, <&xin24m>;
1014                                                 clock-output-names = "clk_vip";
1015                                                 #clock-cells = <0>;
1016                                                 #clock-init-cells = <1>;
1017                                         };
1018                                 };
1019
1020                                 clk_sel_con22: sel-con@0158 {
1021                                         compatible = "rockchip,rk3188-selcon";
1022                                         reg = <0x0158 0x4>;
1023                                         #address-cells = <1>;
1024                                         #size-cells = <1>;
1025
1026                                         clk_isp_div: clk_isp_div {
1027                                                 compatible = "rockchip,rk3188-div-con";
1028                                                 rockchip,bits = <0 6>;
1029                                                 clocks = <&clk_isp>;
1030                                                 clock-output-names = "clk_isp";
1031                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1032                                                 #clock-cells = <0>;
1033                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1034                                         };
1035
1036                                         clk_isp: clk_isp_mux {
1037                                                 compatible = "rockchip,rk3188-mux-con";
1038                                                 rockchip,bits = <6 2>;
1039                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1040                                                 clock-output-names = "clk_isp";
1041                                                 #clock-cells = <0>;
1042                                                 #clock-init-cells = <1>;
1043                                         };
1044                                 };
1045
1046                                 clk_sel_con23: sel-con@015c {
1047                                         compatible = "rockchip,rk3188-selcon";
1048                                         reg = <0x015c 0x4>;
1049                                         #address-cells = <1>;
1050                                         #size-cells = <1>;
1051
1052                                         clk_edp_div: clk_edp_div {
1053                                                 compatible = "rockchip,rk3188-div-con";
1054                                                 rockchip,bits = <0 6>;
1055                                                 clocks = <&clk_edp>;
1056                                                 clock-output-names = "clk_edp";
1057                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1058                                                 #clock-cells = <0>;
1059                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1060                                         };
1061
1062                                         clk_edp: clk_edp_mux {
1063                                                 compatible = "rockchip,rk3188-mux-con";
1064                                                 rockchip,bits = <6 2>;
1065                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1066                                                 clock-output-names = "clk_edp";
1067                                                 #clock-cells = <0>;
1068                                         };
1069
1070                                         clk_edp_24m: clk_edp_24m_mux {
1071                                                 compatible = "rockchip,rk3188-mux-con";
1072                                                 rockchip,bits = <8 1>;
1073                                                 clocks = <&xin24m>, <&dummy>;
1074                                                 clock-output-names = "clk_edp_24m";
1075                                                 #clock-cells = <0>;
1076                                         };
1077                                 };
1078
1079                                 /* sel[24]: reserved */
1080
1081                                 clk_sel_con25: sel-con@0164 {
1082                                         compatible = "rockchip,rk3188-selcon";
1083                                         reg = <0x0164 0x4>;
1084                                         #address-cells = <1>;
1085                                         #size-cells = <1>;
1086
1087                                         clk_tsadc: clk_tsadc_div {
1088                                                 compatible = "rockchip,rk3188-div-con";
1089                                                 rockchip,bits = <0 6>;
1090                                                 clocks = <&clk_32k_mux>;
1091                                                 clock-output-names = "clk_tsadc";
1092                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1093                                                 #clock-cells = <0>;
1094                                         };
1095
1096                                         clk_saradc: clk_saradc_div {
1097                                                 compatible = "rockchip,rk3188-div-con";
1098                                                 rockchip,bits = <8 8>;
1099                                                 clocks = <&xin24m>;
1100                                                 clock-output-names = "clk_saradc";
1101                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1102                                                 #clock-cells = <0>;
1103                                         };
1104                                 };
1105
1106                                 clk_sel_con26: sel-con@0168 {
1107                                         compatible = "rockchip,rk3188-selcon";
1108                                         reg = <0x0168 0x4>;
1109                                         #address-cells = <1>;
1110                                         #size-cells = <1>;
1111
1112                                         /* 7:0 reserved */
1113
1114                                         hsic_usb_480m: hsic_usb_480m_mux {
1115                                                 compatible = "rockchip,rk3188-mux-con";
1116                                                 rockchip,bits = <8 1>;
1117                                                 clocks = <&usbotg_480m_out>, <&dummy>;
1118                                                 clock-output-names = "hsic_usb_480m";
1119                                                 #clock-cells = <0>;
1120                                         };
1121
1122                                         /* 11:9 reserved */
1123
1124                                         hsicphy_480m: hsicphy_480m_mux {
1125                                                 compatible = "rockchip,rk3188-mux-con";
1126                                                 rockchip,bits = <12 2>;
1127                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&hsic_usb_480m>, <&hsic_usb_480m>;
1128                                                 clock-output-names = "hsicphy_480m";
1129                                                 #clock-cells = <0>;
1130                                         };
1131                                 };
1132
1133                                 clk_sel_con27: sel-con@016c {
1134                                         compatible = "rockchip,rk3188-selcon";
1135                                         reg = <0x016c 0x4>;
1136                                         #address-cells = <1>;
1137                                         #size-cells = <1>;
1138
1139                                         i2s_pll_div: i2s_pll_div {
1140                                                 compatible = "rockchip,rk3188-div-con";
1141                                                 rockchip,bits = <0 7>;
1142                                                 clocks = <&i2s_pll>;
1143                                                 clock-output-names = "i2s_pll";
1144                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1145                                                 #clock-cells = <0>;
1146                                                 rockchip,clkops-idx =
1147                                                         <CLKOPS_RATE_MUX_DIV>;
1148                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1149                                         };
1150
1151                                         /* 7 reserved */
1152
1153                                         clk_i2s: clk_i2s_mux {
1154                                                 compatible = "rockchip,rk3188-mux-con";
1155                                                 rockchip,bits = <8 2>;
1156                                                 clocks = <&i2s_pll>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
1157                                                 clock-output-names = "clk_i2s";
1158                                                 #clock-cells = <0>;
1159                                                 rockchip,clkops-idx =
1160                                                         <CLKOPS_RATE_RK3288_I2S>;
1161                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1162                                         };
1163
1164                                         /* 11:10 reserved */
1165
1166                                         i2s_pll: i2s_pll_mux {
1167                                                 compatible = "rockchip,rk3188-mux-con";
1168                                                 rockchip,bits = <12 1>;
1169                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1170                                                 clock-output-names = "i2s_pll";
1171                                                 #clock-cells = <0>;
1172                                         };
1173
1174                                         /* 14:13 reserved */
1175
1176                                         i2s_out: i2s_out_mux {
1177                                                 compatible = "rockchip,rk3188-mux-con";
1178                                                 rockchip,bits = <15 1>;
1179                                                 clocks = <&clk_i2s>, <&xin12m>;
1180                                                 clock-output-names = "i2s_out";
1181                                                 #clock-cells = <0>;
1182                                         };
1183                                 };
1184
1185                                 clk_sel_con28: sel-con@0170 {
1186                                         compatible = "rockchip,rk3188-selcon";
1187                                         reg = <0x0170 0x4>;
1188                                         #address-cells = <1>;
1189                                         #size-cells = <1>;
1190
1191                                         i2s_frac: i2s_frac {
1192                                                 compatible = "rockchip,rk3188-frac-con";
1193                                                 clocks = <&i2s_pll>;
1194                                                 clock-output-names = "i2s_frac";
1195                                                 /* numerator    denominator */
1196                                                 rockchip,bits = <0 32>;
1197                                                 rockchip,clkops-idx =
1198                                                         <CLKOPS_RATE_FRAC>;
1199                                                 #clock-cells = <0>;
1200                                         };
1201                                 };
1202
1203                                 /* sel[30:29] reserved */
1204
1205                                 clk_sel_con31: sel-con@017c {
1206                                         compatible = "rockchip,rk3188-selcon";
1207                                         reg = <0x017c 0x4>;
1208                                         #address-cells = <1>;
1209                                         #size-cells = <1>;
1210
1211
1212                                         spdif_8ch_pll_div: spdif_8ch_pll_div {
1213                                                 compatible = "rockchip,rk3188-div-con";
1214                                                 rockchip,bits = <0 7>;
1215                                                 clocks = <&spdif_8ch_pll>;
1216                                                 clock-output-names = "spdif_8ch_pll";
1217                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1218                                                 #clock-cells = <0>;
1219                                                 rockchip,clkops-idx =
1220                                                         <CLKOPS_RATE_MUX_DIV>;
1221                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1222                                         };
1223
1224                                         /* 7 reserved */
1225
1226                                         clk_spidf_8ch: clk_spidf_8ch_mux {
1227                                                 compatible = "rockchip,rk3188-mux-con";
1228                                                 rockchip,bits = <8 2>;
1229                                                 clocks = <&spdif_8ch_pll>, <&spdif_8ch_frac>, <&i2s_clkin>, <&xin12m>;
1230                                                 clock-output-names = "clk_spidf_8ch";
1231                                                 #clock-cells = <0>;
1232                                                 rockchip,clkops-idx =
1233                                                         <CLKOPS_RATE_RK3288_I2S>;
1234                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1235                                         };
1236
1237                                         /* 11:10 reserved */
1238
1239                                         spdif_8ch_pll: spdif_8ch_pll_mux {
1240                                                 compatible = "rockchip,rk3188-mux-con";
1241                                                 rockchip,bits = <12 1>;
1242                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1243                                                 clock-output-names = "spdif_8ch_pll";
1244                                                 #clock-cells = <0>;
1245                                         };
1246
1247                                         /* 15:13 reserved */
1248                                 };
1249
1250                                 clk_sel_con32: sel-con@0180 {
1251                                         compatible = "rockchip,rk3188-selcon";
1252                                         reg = <0x0180 0x4>;
1253                                         #address-cells = <1>;
1254                                         #size-cells = <1>;
1255
1256                                         spdif_8ch_frac: spdif_8ch_frac {
1257                                                 compatible = "rockchip,rk3188-frac-con";
1258                                                 clocks = <&spdif_8ch_pll>;
1259                                                 clock-output-names = "spdif_8ch_frac";
1260                                                 /* numerator    denominator */
1261                                                 rockchip,bits = <0 32>;
1262                                                 rockchip,clkops-idx =
1263                                                         <CLKOPS_RATE_FRAC>;
1264                                                 #clock-cells = <0>;
1265                                         };
1266                                 };
1267
1268                                 clk_sel_con33: sel-con@0184 {
1269                                         compatible = "rockchip,rk3188-selcon";
1270                                         reg = <0x0184 0x4>;
1271                                         #address-cells = <1>;
1272                                         #size-cells = <1>;
1273
1274                                         clk_uart0_pll_div: clk_uart0_pll_div {
1275                                                 compatible = "rockchip,rk3188-div-con";
1276                                                 rockchip,bits = <0 7>;
1277                                                 clocks = <&clk_uart0_pll>;
1278                                                 clock-output-names = "clk_uart0_pll";
1279                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1280                                                 #clock-cells = <0>;
1281                                                 rockchip,clkops-idx =
1282                                                         <CLKOPS_RATE_MUX_DIV>;
1283                                         };
1284
1285                                         /* 7: reserved */
1286
1287                                         clk_uart0: clk_uart0_mux {
1288                                                 compatible = "rockchip,rk3188-mux-con";
1289                                                 rockchip,bits = <8 2>;
1290                                                 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>, <&xin24m>;
1291                                                 clock-output-names = "clk_uart0";
1292                                                 #clock-cells = <0>;
1293                                                 rockchip,clkops-idx =
1294                                                         <CLKOPS_RATE_RK3288_I2S>;
1295                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1296                                         };
1297
1298                                         /* 11:10 reserved */
1299
1300                                         clk_uart0_pll: clk_uart0_pll_mux {
1301                                                 compatible = "rockchip,rk3188-mux-con";
1302                                                 rockchip,bits = <12 2>;
1303                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
1304                                                 clock-output-names = "clk_uart0_pll";
1305                                                 #clock-cells = <0>;
1306                                         };
1307                                 };
1308
1309                                 clk_sel_con34: sel-con@0188 {
1310                                         compatible = "rockchip,rk3188-selcon";
1311                                         reg = <0x0188 0x4>;
1312                                         #address-cells = <1>;
1313                                         #size-cells = <1>;
1314
1315                                         uart0_frac: uart0_frac {
1316                                                 compatible = "rockchip,rk3188-frac-con";
1317                                                 clocks = <&clk_uart0_pll>;
1318                                                 clock-output-names = "uart0_frac";
1319                                                 /* numerator    denominator */
1320                                                 rockchip,bits = <0 32>;
1321                                                 rockchip,clkops-idx =
1322                                                         <CLKOPS_RATE_FRAC>;
1323                                                 #clock-cells = <0>;
1324                                         };
1325                                 };
1326
1327                                 clk_sel_con35: sel-con@018c {
1328                                         compatible = "rockchip,rk3188-selcon";
1329                                         reg = <0x018c 0x4>;
1330                                         #address-cells = <1>;
1331                                         #size-cells = <1>;
1332
1333                                         uart1_div: uart1_div {
1334                                                 compatible = "rockchip,rk3188-div-con";
1335                                                 rockchip,bits = <0 7>;
1336                                                 clocks = <&clk_uart_pll>;
1337                                                 clock-output-names = "uart1_div";
1338                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1339                                                 #clock-cells = <0>;
1340                                         };
1341
1342                                         /* 7 reserved */
1343
1344                                         clk_uart1: clk_uart1_mux {
1345                                                 compatible = "rockchip,rk3188-mux-con";
1346                                                 rockchip,bits = <8 2>;
1347                                                 clocks = <&uart1_div>, <&uart1_frac>, <&xin24m>, <&xin24m>;
1348                                                 clock-output-names = "clk_uart1";
1349                                                 #clock-cells = <0>;
1350                                                 rockchip,clkops-idx =
1351                                                         <CLKOPS_RATE_RK3288_I2S>;
1352                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1353                                         };
1354
1355                                         /* 11:10 reserved */
1356
1357                                         clk_uart_pll: clk_uart_pll_mux {
1358                                                 compatible = "rockchip,rk3188-mux-con";
1359                                                 rockchip,bits = <12 1>;
1360                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1361                                                 clock-output-names = "clk_uart_pll";
1362                                                 #clock-cells = <0>;
1363                                         };
1364
1365                                         /* 14:13 reserved */
1366                                 };
1367
1368                                 clk_sel_con36: sel-con@0190 {
1369                                         compatible = "rockchip,rk3188-selcon";
1370                                         reg = <0x0190 0x4>;
1371                                         #address-cells = <1>;
1372                                         #size-cells = <1>;
1373
1374                                         uart1_frac: uart1_frac {
1375                                                 compatible = "rockchip,rk3188-frac-con";
1376                                                 clocks = <&uart1_div>;
1377                                                 clock-output-names = "uart1_frac";
1378                                                 /* numerator    denominator */
1379                                                 rockchip,bits = <0 32>;
1380                                                 rockchip,clkops-idx =
1381                                                         <CLKOPS_RATE_FRAC>;
1382                                                 #clock-cells = <0>;
1383                                         };
1384                                 };
1385
1386                                 clk_sel_con37: sel-con@0194 {
1387                                         compatible = "rockchip,rk3188-selcon";
1388                                         reg = <0x0194 0x4>;
1389                                         #address-cells = <1>;
1390                                         #size-cells = <1>;
1391
1392                                         uart2_div: uart2_div {
1393                                                 compatible = "rockchip,rk3188-div-con";
1394                                                 rockchip,bits = <0 7>;
1395                                                 clocks = <&clk_uart_pll>;
1396                                                 clock-output-names = "uart2_div";
1397                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1398                                                 #clock-cells = <0>;
1399                                         };
1400
1401                                         /* 7 reserved */
1402
1403                                         clk_uart2: clk_uart2_mux {
1404                                                 compatible = "rockchip,rk3188-mux-con";
1405                                                 rockchip,bits = <8 1>;
1406                                                 clocks = <&uart2_div>, <&xin24m>;
1407                                                 clock-output-names = "clk_uart2";
1408                                                 #clock-cells = <0>;
1409                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1410                                         };
1411                                 };
1412
1413                                 /* sel[38] reserved */
1414
1415                                 clk_sel_con39: sel-con@019c {
1416                                         compatible = "rockchip,rk3188-selcon";
1417                                         reg = <0x019c 0x4>;
1418                                         #address-cells = <1>;
1419                                         #size-cells = <1>;
1420
1421                                         uart3_div: uart3_div {
1422                                                 compatible = "rockchip,rk3188-div-con";
1423                                                 rockchip,bits = <0 7>;
1424                                                 clocks = <&clk_uart_pll>;
1425                                                 clock-output-names = "uart3_div";
1426                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1427                                                 #clock-cells = <0>;
1428                                         };
1429
1430                                         /* 7 reserved */
1431
1432                                         clk_uart3: clk_uart3_mux {
1433                                                 compatible = "rockchip,rk3188-mux-con";
1434                                                 rockchip,bits = <8 2>;
1435                                                 clocks = <&uart3_div>, <&uart3_frac>, <&xin24m>, <&xin24m>;
1436                                                 clock-output-names = "clk_uart3";
1437                                                 #clock-cells = <0>;
1438                                                 rockchip,clkops-idx =
1439                                                         <CLKOPS_RATE_RK3288_I2S>;
1440                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1441                                         };
1442                                 };
1443
1444                                 clk_sel_con40: sel-con@01a0 {
1445                                         compatible = "rockchip,rk3188-selcon";
1446                                         reg = <0x01a0 0x4>;
1447                                         #address-cells = <1>;
1448                                         #size-cells = <1>;
1449
1450                                         uart3_frac: uart3_frac {
1451                                                 compatible = "rockchip,rk3188-frac-con";
1452                                                 clocks = <&uart3_div>;
1453                                                 clock-output-names = "uart3_frac";
1454                                                 /* numerator    denominator */
1455                                                 rockchip,bits = <0 32>;
1456                                                 rockchip,clkops-idx =
1457                                                         <CLKOPS_RATE_FRAC>;
1458                                                 #clock-cells = <0>;
1459                                         };
1460                                 };
1461
1462                                 clk_sel_con41: sel-con@01a4 {
1463                                         compatible = "rockchip,rk3188-selcon";
1464                                         reg = <0x01a4 0x4>;
1465                                         #address-cells = <1>;
1466                                         #size-cells = <1>;
1467
1468                                         uart4_div: uart4_div {
1469                                                 compatible = "rockchip,rk3188-div-con";
1470                                                 rockchip,bits = <0 7>;
1471                                                 clocks = <&clk_uart_pll>;
1472                                                 clock-output-names = "uart4_div";
1473                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1474                                                 #clock-cells = <0>;
1475                                         };
1476
1477                                         /* 7 reserved */
1478
1479                                         clk_uart4: clk_uart4_mux {
1480                                                 compatible = "rockchip,rk3188-mux-con";
1481                                                 rockchip,bits = <8 2>;
1482                                                 clocks = <&uart4_div>, <&uart4_frac>, <&xin24m>, <&xin24m>;
1483                                                 clock-output-names = "clk_uart4";
1484                                                 #clock-cells = <0>;
1485                                                 rockchip,clkops-idx =
1486                                                         <CLKOPS_RATE_RK3288_I2S>;
1487                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1488                                         };
1489                                 };
1490
1491                                 clk_sel_con42: sel-con@01a8 {
1492                                         compatible = "rockchip,rk3188-selcon";
1493                                         reg = <0x01a8 0x4>;
1494                                         #address-cells = <1>;
1495                                         #size-cells = <1>;
1496
1497                                         uart4_frac: uart4_frac {
1498                                                 compatible = "rockchip,rk3188-frac-con";
1499                                                 clocks = <&uart4_div>;
1500                                                 clock-output-names = "uart4_frac";
1501                                                 /* numerator    denominator */
1502                                                 rockchip,bits = <0 32>;
1503                                                 rockchip,clkops-idx =
1504                                                         <CLKOPS_RATE_FRAC>;
1505                                                 #clock-cells = <0>;
1506                                         };
1507                                 };
1508
1509                                 clk_sel_con43: sel-con@01ac {
1510                                         compatible = "rockchip,rk3188-selcon";
1511                                         reg = <0x01ac 0x4>;
1512                                         #address-cells = <1>;
1513                                         #size-cells = <1>;
1514
1515                                         clk_mac_pll_div: clk_mac_pll_div {
1516                                                 compatible = "rockchip,rk3188-div-con";
1517                                                 rockchip,bits = <0 5>;
1518                                                 clocks = <&clk_mac_pll>;
1519                                                 clock-output-names = "clk_mac_pll";
1520                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1521                                                 #clock-cells = <0>;
1522                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1523                                         };
1524
1525                                         /* 5 reserved */
1526
1527                                         clk_mac_pll: clk_mac_pll_mux {
1528                                                 compatible = "rockchip,rk3188-mux-con";
1529                                                 rockchip,bits = <6 2>;
1530                                                 clocks = <&clk_npll>, <&clk_cpll>, <&clk_gpll>, <&clk_gpll>;
1531                                                 clock-output-names = "clk_mac_pll";
1532                                                 #clock-cells = <0>;
1533                                         };
1534
1535                                         clk_mac: clk_mac_mux {
1536                                                 compatible = "rockchip,rk3188-mux-con";
1537                                                 rockchip,bits = <8 1>;
1538                                                 clocks = <&clk_mac_pll>, <&gmac_clkin>;
1539                                                 clock-output-names = "clk_mac";
1540                                                 #clock-cells = <0>;
1541                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1542                                         };
1543
1544                                         /* 11:9 reserved */
1545
1546                                         /* 12: test_clk: wifi_pll_sel */
1547
1548                                         /* 15:13 reserved */
1549                                 };
1550
1551                                 clk_sel_con44: sel-con@01b0 {
1552                                         compatible = "rockchip,rk3188-selcon";
1553                                         reg = <0x01b0 0x4>;
1554                                         #address-cells = <1>;
1555                                         #size-cells = <1>;
1556
1557                                         /* test_clk: wifi_frac */
1558                                 };
1559
1560                                 clk_sel_con45: sel-con@01b4 {
1561                                         compatible = "rockchip,rk3188-selcon";
1562                                         reg = <0x01b4 0x4>;
1563                                         #address-cells = <1>;
1564                                         #size-cells = <1>;
1565
1566                                         clk_spi0_div: clk_spi0_div {
1567                                                 compatible = "rockchip,rk3188-div-con";
1568                                                 rockchip,bits = <0 7>;
1569                                                 clocks = <&clk_spi0>;
1570                                                 clock-output-names = "clk_spi0";
1571                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1572                                                 #clock-cells = <0>;
1573                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1574                                         };
1575
1576                                         clk_spi0: clk_spi0_mux {
1577                                                 compatible = "rockchip,rk3188-mux-con";
1578                                                 rockchip,bits = <7 1>;
1579                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1580                                                 clock-output-names = "clk_spi0";
1581                                                 #clock-cells = <0>;
1582                                         };
1583
1584                                         clk_spi1_div: clk_spi1_div {
1585                                                 compatible = "rockchip,rk3188-div-con";
1586                                                 rockchip,bits = <8 7>;
1587                                                 clocks = <&clk_spi1>;
1588                                                 clock-output-names = "clk_spi1";
1589                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1590                                                 #clock-cells = <0>;
1591                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1592                                         };
1593
1594                                         clk_spi1: clk_spi1_mux {
1595                                                 compatible = "rockchip,rk3188-mux-con";
1596                                                 rockchip,bits = <15 1>;
1597                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1598                                                 clock-output-names = "clk_spi1";
1599                                                 #clock-cells = <0>;
1600                                         };
1601                                 };
1602
1603                                 clk_sel_con46: sel-con@01b8 {
1604                                         compatible = "rockchip,rk3188-selcon";
1605                                         reg = <0x01b8 0x4>;
1606                                         #address-cells = <1>;
1607                                         #size-cells = <1>;
1608
1609                                         clk_tsp_div: clk_tsp_div {
1610                                                 compatible = "rockchip,rk3188-div-con";
1611                                                 rockchip,bits = <0 5>;
1612                                                 clocks = <&clk_tsp>;
1613                                                 clock-output-names = "clk_tsp";
1614                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1615                                                 #clock-cells = <0>;
1616                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1617                                         };
1618
1619                                         /* 5 reserved */
1620
1621                                         clk_tsp: clk_tsp_mux {
1622                                                 compatible = "rockchip,rk3188-mux-con";
1623                                                 rockchip,bits = <6 2>;
1624                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1625                                                 clock-output-names = "clk_tsp";
1626                                                 #clock-cells = <0>;
1627                                         };
1628
1629                                         clk_spi2_div: clk_spi2_div {
1630                                                 compatible = "rockchip,rk3188-div-con";
1631                                                 rockchip,bits = <8 7>;
1632                                                 clocks = <&clk_spi2>;
1633                                                 clock-output-names = "clk_spi2";
1634                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1635                                                 #clock-cells = <0>;
1636                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1637                                         };
1638
1639                                         clk_spi2: clk_spi2_mux {
1640                                                 compatible = "rockchip,rk3188-mux-con";
1641                                                 rockchip,bits = <15 1>;
1642                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1643                                                 clock-output-names = "clk_spi2";
1644                                                 #clock-cells = <0>;
1645                                         };
1646                                 };
1647
1648                                 clk_sel_con47: sel-con@01bc {
1649                                         compatible = "rockchip,rk3188-selcon";
1650                                         reg = <0x01bc 0x4>;
1651                                         #address-cells = <1>;
1652                                         #size-cells = <1>;
1653
1654                                         clk_nandc0_div: clk_nandc0_div {
1655                                                 compatible = "rockchip,rk3188-div-con";
1656                                                 rockchip,bits = <0 5>;
1657                                                 clocks = <&clk_nandc0>;
1658                                                 clock-output-names = "clk_nandc0";
1659                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1660                                                 #clock-cells = <0>;
1661                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1662                                         };
1663
1664                                         /* 6:5 reserved */
1665
1666                                         clk_nandc0: clk_nandc0_mux {
1667                                                 compatible = "rockchip,rk3188-mux-con";
1668                                                 rockchip,bits = <7 1>;
1669                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1670                                                 clock-output-names = "clk_nandc0";
1671                                                 #clock-cells = <0>;
1672                                         };
1673
1674                                         /* 12:8 test_div */
1675
1676                                         /* 15:13 reserved */
1677                                 };
1678
1679                                 clk_sel_con48: sel-con@01c0 {
1680                                         compatible = "rockchip,rk3188-selcon";
1681                                         reg = <0x01c0 0x4>;
1682                                         #address-cells = <1>;
1683                                         #size-cells = <1>;
1684
1685                                         clk_sdio0_div: clk_sdio0_div {
1686                                                 compatible = "rockchip,rk3188-div-con";
1687                                                 rockchip,bits = <0 7>;
1688                                                 clocks = <&clk_sdio0>;
1689                                                 clock-output-names = "clk_sdio0";
1690                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1691                                                 #clock-cells = <0>;
1692                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1693                                         };
1694
1695                                         /* 7 reserved */
1696
1697                                         clk_sdio0: clk_sdio0_mux {
1698                                                 compatible = "rockchip,rk3188-mux-con";
1699                                                 rockchip,bits = <8 2>;
1700                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1701                                                 clock-output-names = "clk_sdio0";
1702                                                 #clock-cells = <0>;
1703                                         };
1704
1705                                         /* 15:10 reserved */
1706                                 };
1707
1708                                 /* sel[49] reserved */
1709
1710                                 clk_sel_con50: sel-con@01c8 {
1711                                         compatible = "rockchip,rk3188-selcon";
1712                                         reg = <0x01c8 0x4>;
1713                                         #address-cells = <1>;
1714                                         #size-cells = <1>;
1715
1716                                         clk_sdmmc0_div: clk_sdmmc0_div {
1717                                                 compatible = "rockchip,rk3188-div-con";
1718                                                 rockchip,bits = <0 7>;
1719                                                 clocks = <&clk_sdmmc0>;
1720                                                 clock-output-names = "clk_sdmmc0";
1721                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1722                                                 #clock-cells = <0>;
1723                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1724                                         };
1725
1726                                         /* 7 reserved */
1727
1728                                         clk_sdmmc0: clk_sdmmc0_mux {
1729                                                 compatible = "rockchip,rk3188-mux-con";
1730                                                 rockchip,bits = <8 2>;
1731                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1732                                                 clock-output-names = "clk_sdmmc0";
1733                                                 #clock-cells = <0>;
1734                                         };
1735
1736                                         /* 15:10 reserved */
1737                                 };
1738
1739                                 clk_sel_con51: sel-con@01cc {
1740                                         compatible = "rockchip,rk3188-selcon";
1741                                         reg = <0x01cc 0x4>;
1742                                         #address-cells = <1>;
1743                                         #size-cells = <1>;
1744
1745                                         clk_emmc_div: clk_emmc_div {
1746                                                 compatible = "rockchip,rk3188-div-con";
1747                                                 rockchip,bits = <0 7>;
1748                                                 clocks = <&clk_emmc>;
1749                                                 clock-output-names = "clk_emmc";
1750                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1751                                                 #clock-cells = <0>;
1752                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1753                                         };
1754
1755                                         /* 7 reserved */
1756
1757                                         clk_emmc: clk_emmc_mux {
1758                                                 compatible = "rockchip,rk3188-mux-con";
1759                                                 rockchip,bits = <8 2>;
1760                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1761                                                 clock-output-names = "clk_emmc";
1762                                                 #clock-cells = <0>;
1763                                         };
1764
1765                                         /* 15:10 reserved */
1766                                 };
1767
1768                                 clk_sel_con52: sel-con@01d0 {
1769                                         compatible = "rockchip,rk3188-selcon";
1770                                         reg = <0x01d0 0x4>;
1771                                         #address-cells = <1>;
1772                                         #size-cells = <1>;
1773
1774                                         clk_sfc_div: clk_sfc_div {
1775                                                 compatible = "rockchip,rk3188-div-con";
1776                                                 rockchip,bits = <0 5>;
1777                                                 clocks = <&clk_sfc>;
1778                                                 clock-output-names = "clk_sfc";
1779                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1780                                                 #clock-cells = <0>;
1781                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1782                                         };
1783
1784                                         /* 6:5 reserved */
1785
1786                                         clk_sfc: clk_sfc_mux {
1787                                                 compatible = "rockchip,rk3188-mux-con";
1788                                                 rockchip,bits = <7 1>;
1789                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1790                                                 clock-output-names = "clk_sfc";
1791                                                 #clock-cells = <0>;
1792                                         };
1793
1794                                         /* 15:8 reserved */
1795                                 };
1796
1797                                 clk_sel_con53: sel-con@01d4 {
1798                                         compatible = "rockchip,rk3188-selcon";
1799                                         reg = <0x01d4 0x4>;
1800                                         #address-cells = <1>;
1801                                         #size-cells = <1>;
1802
1803                                         i2s_2ch_pll_div: i2s_2ch_pll_div {
1804                                                 compatible = "rockchip,rk3188-div-con";
1805                                                 rockchip,bits = <0 7>;
1806                                                 clocks = <&i2s_2ch_pll>;
1807                                                 clock-output-names = "i2s_2ch_pll";
1808                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1809                                                 #clock-cells = <0>;
1810                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1811                                         };
1812
1813                                         /* 7 reserved */
1814
1815                                         clk_i2s_2ch: clk_i2s_2ch_mux {
1816                                                 compatible = "rockchip,rk3188-mux-con";
1817                                                 rockchip,bits = <8 2>;
1818                                                 clocks = <&i2s_2ch_pll>, <&i2s_2ch_frac>, <&dummy>, <&xin12m>;
1819                                                 clock-output-names = "clk_i2s_2ch";
1820                                                 #clock-cells = <0>;
1821                                                 rockchip,clkops-idx =
1822                                                         <CLKOPS_RATE_RK3288_I2S>;
1823                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1824                                         };
1825
1826                                         /* 11:10 reserved */
1827
1828                                         i2s_2ch_pll: i2s_2ch_pll_mux {
1829                                                 compatible = "rockchip,rk3188-mux-con";
1830                                                 rockchip,bits = <12 1>;
1831                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1832                                                 clock-output-names = "i2s_2ch_pll";
1833                                                 #clock-cells = <0>;
1834                                         };
1835
1836                                 };
1837
1838                                 clk_sel_con54: sel-con@01d8 {
1839                                         compatible = "rockchip,rk3188-selcon";
1840                                         reg = <0x01d8 0x4>;
1841                                         #address-cells = <1>;
1842                                         #size-cells = <1>;
1843
1844                                         i2s_2ch_frac: i2s_2ch_frac {
1845                                                 compatible = "rockchip,rk3188-frac-con";
1846                                                 clocks = <&i2s_2ch_pll>;
1847                                                 clock-output-names = "i2s_2ch_frac";
1848                                                 /* numerator    denominator */
1849                                                 rockchip,bits = <0 32>;
1850                                                 rockchip,clkops-idx =
1851                                                         <CLKOPS_RATE_FRAC>;
1852                                                 #clock-cells = <0>;
1853                                         };
1854                                 };
1855
1856                                 clk_sel_con55: sel-con@01dc {
1857                                         compatible = "rockchip,rk3188-selcon";
1858                                         reg = <0x01dc 0x4>;
1859                                         #address-cells = <1>;
1860                                         #size-cells = <1>;
1861
1862                                         clk_hdcp_div: clk_hdcp_div {
1863                                                 compatible = "rockchip,rk3188-div-con";
1864                                                 rockchip,bits = <0 6>;
1865                                                 clocks = <&clk_hdcp>;
1866                                                 clock-output-names = "clk_hdcp";
1867                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1868                                                 #clock-cells = <0>;
1869                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1870                                         };
1871
1872                                         clk_hdcp: clk_hdcp_mux {
1873                                                 compatible = "rockchip,rk3188-mux-con";
1874                                                 rockchip,bits = <6 2>;
1875                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1876                                                 clock-output-names = "clk_hdcp";
1877                                                 #clock-cells = <0>;
1878                                         };
1879                                 };
1880                         };
1881
1882                         /* Gate control regs */
1883                         clk_gate_cons {
1884                                 compatible = "rockchip,rk-gate-cons";
1885                                 #address-cells = <1>;
1886                                 #size-cells = <1>;
1887                                 ranges;
1888
1889                                 clk_gates0: gate-clk@0200 {
1890                                         compatible = "rockchip,rk3188-gate-clk";
1891                                         reg = <0x0200 0x4>;
1892                                         clocks =
1893                                                 <&dummy>,       <&dummy>,
1894                                                 <&dummy>,       <&dummy>,
1895
1896                                                 <&dummy>,       <&dummy>,
1897                                                 <&dummy>,       <&dummy>,
1898
1899                                                 <&clk_gpll>,    <&clk_apllb>,
1900                                                 <&clk_aplll>,   <&dummy>,
1901
1902                                                 <&aclk_cci>,    <&clkin_trace>,
1903                                                 <&dummy>,       <&dummy>;
1904
1905                                         clock-output-names =
1906                                                 "reserved",     "reserved",/* core_b_apll core_b_gpll */
1907                                                 "reserved",     "reserved",
1908
1909                                                 "reserved",     "reserved",/* core_l_apll core_l_gpll */
1910                                                 "reserved",     "reserved",
1911
1912                                                 "g_clk_cs_gpll",        "g_clk_cs_apllb",
1913                                                 "g_clk_cs_aplll",       "reserved",
1914
1915                                                 "aclk_cci",     "clkin_trace",
1916                                                 "reserved",     "reserved";
1917
1918                                         #clock-cells = <1>;
1919                                 };
1920
1921                                 clk_gates1: gate-clk@0204 {
1922                                         compatible = "rockchip,rk3188-gate-clk";
1923                                         reg = <0x0204 0x4>;
1924                                         clocks =
1925                                                 <&aclk_bus>,    <&hclk_bus>,
1926                                                 <&pclk_bus>,    <&fclk_mcu>,
1927
1928                                                 <&dummy>,       <&dummy>,
1929                                                 <&dummy>,       <&dummy>,
1930
1931                                                 <&dummy>,       <&dummy>,
1932                                                 <&clk_gpll>,    <&clk_cpll>,
1933
1934                                                 <&dummy>,       <&dummy>,
1935                                                 <&dummy>,       <&dummy>;
1936
1937                                         clock-output-names =
1938                                                 "aclk_bus",     "hclk_bus",
1939                                                 "pclk_bus",     "fclk_mcu",
1940
1941                                                 "reserved",     "reserved",
1942                                                 "reserved",     "reserved",
1943
1944                                                 "reserved",     "reserved",/* ddr_dpll  ddr_gpll */
1945                                                 "aclk_bus_gpll",        "aclk_bus_cpll",
1946
1947                                                 "reserved",     "reserved",
1948                                                 "reserved",     "reserved";
1949
1950                                         #clock-cells = <1>;
1951                                 };
1952
1953                                 clk_gates2: gate-clk@0208 {
1954                                         compatible = "rockchip,rk3188-gate-clk";
1955                                         reg = <0x0208 0x4>;
1956                                         clocks =
1957                                                 <&clk_uart0_pll>,       <&uart0_frac>,
1958                                                 <&uart1_div>,   <&uart1_frac>,
1959
1960                                                 <&uart2_div>,   <&dummy>,
1961                                                 <&uart3_div>,   <&uart3_frac>,
1962
1963                                                 <&uart4_div>,   <&uart4_frac>,
1964                                                 <&dummy>,       <&dummy>,
1965
1966                                                 <&dummy>,       <&dummy>,
1967                                                 <&dummy>,       <&dummy>;
1968
1969                                         clock-output-names =
1970                                                 "clk_uart0_pll",        "uart0_frac",
1971                                                 "uart1_div",    "uart1_frac",
1972
1973                                                 "uart2_div",    "reserved",
1974                                                 "uart3_div",    "uart3_frac",
1975
1976                                                 "uart4_div",    "uart4_frac",
1977                                                 "reserved",     "reserved",
1978
1979                                                 "reserved",     "reserved",
1980                                                 "reserved",     "reserved";
1981
1982                                         #clock-cells = <1>;
1983                                 };
1984
1985                                 clk_gates3: gate-clk@020c {
1986                                         compatible = "rockchip,rk3188-gate-clk";
1987                                         reg = <0x020c 0x4>;
1988                                         clocks =
1989                                                 <&aclk_peri>,   <&dummy>,
1990                                                 <&hclk_peri>,   <&pclk_peri>,
1991
1992                                                 <&clk_mac_pll>, <&clk_tsadc>,
1993                                                 <&clk_saradc>,  <&clk_spi0>,
1994
1995                                                 <&clk_spi1>,    <&clk_spi2>,
1996                                                 <&dummy>,       <&dummy>,
1997
1998                                                 <&dummy>,       <&dummy>,
1999                                                 <&dummy>,       <&dummy>;
2000
2001                                         clock-output-names =
2002                                                 "aclk_peri",    "reserved", /* bit1: aclk_peri */
2003                                                 "hclk_peri",    "pclk_peri",
2004
2005                                                 "clk_mac_pll",  "clk_tsadc",
2006                                                 "clk_saradc",   "clk_spi0",
2007
2008                                                 "clk_spi1",     "clk_spi2",
2009                                                 "reserved",     "reserved",
2010
2011                                                 "reserved",     "reserved",
2012                                                 "reserved",     "reserved";
2013
2014                                         #clock-cells = <1>;
2015                                 };
2016
2017                                 clk_gates4: gate-clk@0210 {
2018                                         compatible = "rockchip,rk3188-gate-clk";
2019                                         reg = <0x0210 0x4>;
2020                                         clocks =
2021                                                 <&aclk_vio0>,   <&dclk_vop0>,
2022                                                 <&xin24m>,      <&aclk_rga_pre>,
2023
2024                                                 <&clk_rga>,     <&clk_vip>,
2025                                                 <&aclk_vepu>,   <&aclk_vdpu>,
2026
2027                                                 <&dummy>,       <&clk_isp>,
2028                                                 <&dummy>,       <&clk_gpu_core>,
2029
2030                                                 <&xin32k>,      <&xin24m>,
2031                                                 <&xin24m>,      <&dummy>;
2032
2033                                         clock-output-names =
2034                                                 "aclk_vio0",    "dclk_vop0",
2035                                                 "clk_vop0_pwm", "aclk_rga_pre",
2036
2037                                                 "clk_rga",      "clk_vip",
2038                                                 "aclk_vepu",    "aclk_vdpu",
2039
2040                                                 "reserved",     "clk_isp", /* bit8: hclk_vpu */
2041                                                 "reserved",     "clk_gpu_core",
2042
2043                                                 "clk_hdmi_cec", "clk_hdmi_hdcp",
2044                                                 "clk_dsiphy_24m",       "reserved";
2045
2046                                         #clock-cells = <1>;
2047                                 };
2048
2049                                 clk_gates5: gate-clk@0214 {
2050                                         compatible = "rockchip,rk3188-gate-clk";
2051                                         reg = <0x0214 0x4>;
2052                                         clocks =
2053                                                 <&dummy>,       <&clk_hevc_cabac>,
2054                                                 <&clk_hevc_core>,       <&clk_edp>,
2055
2056                                                 <&clk_edp_24m>, <&clk_hdcp>,
2057                                                 <&dummy>,       <&dummy>,
2058
2059                                                 <&aclk_gpu_mem>,        <&aclk_gpu_cfg>,
2060                                                 <&dummy>,       <&dummy>,
2061
2062                                                 <&dummy>,       <&i2s_pll>,
2063                                                 <&i2s_2ch_frac>,        <&clk_i2s_2ch>;
2064
2065                                         clock-output-names =
2066                                                 "reserved",     "clk_hevc_cabac",
2067                                                 "clk_hevc_core",        "clk_edp",
2068
2069                                                 "clk_edp_24m",  "clk_hdcp",
2070                                                 "reserved",     "reserved",
2071
2072                                                 "aclk_gpu_mem", "aclk_gpu_cfg",
2073                                                 "reserved",     "reserved",
2074
2075                                                 "reserved",     "i2s_pll",
2076                                                 "i2s_2ch_frac", "clk_i2s_2ch";
2077
2078                                         #clock-cells = <1>;
2079                                 };
2080
2081                                 clk_gates6: gate-clk@0218 {
2082                                         compatible = "rockchip,rk3188-gate-clk";
2083                                         reg = <0x0218 0x4>;
2084                                         clocks =
2085                                                 <&i2s_out>,     <&i2s_pll>,
2086                                                 <&i2s_frac>,    <&clk_i2s>,
2087
2088                                                 <&spdif_8ch_pll>,       <&spdif_8ch_frac>,
2089                                                 <&clk_spidf_8ch>,       <&clk_sfc>,
2090
2091                                                 <&dummy>,       <&dummy>,
2092                                                 <&dummy>,       <&dummy>,
2093
2094                                                 <&clk_tsp>,     <&dummy>,
2095                                                 <&dummy>,       <&dummy>;
2096
2097                                         clock-output-names =
2098                                                 "i2s_out",      "i2s_pll",
2099                                                 "i2s_frac",     "clk_i2s",
2100
2101                                                 "spdif_8ch_pll",        "spdif_8ch_frac",
2102                                                 "clk_spidf_8ch",        "clk_sfc",
2103
2104                                                 "reserved",     "reserved",
2105                                                 "reserved",     "reserved",
2106
2107                                                 "clk_tsp",      "reserved",
2108                                                 "reserved",     "reserved";/* clk_ddrphy_gate   clk4x_ddrphy_gate */
2109
2110                                         #clock-cells = <1>;
2111                                 };
2112
2113                                 clk_gates7: gate-clk@021c {
2114                                         compatible = "rockchip,rk3188-gate-clk";
2115                                         reg = <0x021c 0x4>;
2116                                         clocks =
2117                                                 <&jtag_clkin>,  <&dummy>,
2118                                                 <&clk_crypto>,  <&xin24m>,
2119
2120                                                 <&dummy>,       <&dummy>,
2121                                                 <&clk_mac>,     <&clk_mac>,
2122
2123                                                 <&clk_nandc0>,  <&pclk_pmu_pre>,
2124                                                 <&xin24m>,      <&xin24m>,
2125
2126                                                 <&dummy>,       <&dummy>,
2127                                                 <&dummy>,       <&dummy>;
2128
2129                                         clock-output-names =
2130                                                 "clk_jtag",     "reserved",/* bit1: test_clk */
2131                                                 "clk_crypto",   "clk_pvtm_pmu",
2132
2133                                                 "reserved",     "reserved",/* clk_mac_rx  clk_mac_tx */
2134                                                 "clk_mac_ref",  "clk_mac_refout",
2135
2136                                                 "clk_nandc0",   "pclk_pmu_pre",
2137                                                 "clk_pvtm_core",        "clk_pvtm_gpu",
2138
2139                                                 "clk_sdmmc0",   "clk_sdio0",
2140                                                 "reserved",     "clk_emmc";
2141
2142                                         #clock-cells = <1>;
2143                                 };
2144
2145                                 clk_gates8: gate-clk@0220 {
2146                                         compatible = "rockchip,rk3188-gate-clk";
2147                                         reg = <0x0220 0x4>;
2148                                         clocks =
2149                                                 <&hsic_usb_480m>,       <&xin24m>,
2150                                                 <&dummy>,       <&dummy>,
2151
2152                                                 <&clk_32k_mux>, <&dummy>,
2153                                                 <&xin12m>,      <&hsicphy_480m>,
2154
2155                                                 <&dummy>,       <&dummy>,
2156                                                 <&dummy>,       <&dummy>,
2157
2158                                                 <&dummy>,       <&dummy>,
2159                                                 <&dummy>,       <&dummy>;
2160
2161                                         clock-output-names =
2162                                                 "hsic_usb_480m",        "clk_otgphy0",
2163                                                 "reserved",     "reserved",
2164
2165                                                 "g_clk_otg_adp",        "reserved",/* bit4: clk_otg_adp */
2166                                                 "hsicphy_12m",  "hsicphy_480m",
2167
2168                                                 "reserved",     "reserved",
2169                                                 "reserved",     "reserved",
2170
2171                                                 "reserved",     "reserved",
2172                                                 "reserved",     "reserved";
2173
2174                                         #clock-cells = <1>;
2175                                 };
2176
2177                                 clk_gates9: gate-clk@0224 {
2178                                         compatible = "rockchip,rk3188-gate-clk";
2179                                         reg = <0x0224 0x4>;
2180                                         clocks =
2181                                                 <&dummy>,       <&dummy>,
2182                                                 <&dummy>,       <&dummy>,
2183
2184                                                 <&dummy>,       <&dummy>,
2185                                                 <&dummy>,       <&dummy>,
2186
2187                                                 <&dummy>,       <&dummy>,
2188                                                 <&dummy>,       <&dummy>,
2189
2190                                                 <&dummy>,       <&dummy>,
2191                                                 <&dummy>,       <&dummy>;
2192
2193                                         clock-output-names =
2194                                                 "reserved",     "reserved",
2195                                                 "reserved",     "reserved",
2196
2197                                                 "reserved",     "reserved",
2198                                                 "reserved",     "reserved",
2199
2200                                                 "reserved",     "reserved",
2201                                                 "reserved",     "reserved",
2202
2203                                                 "reserved",     "reserved",
2204                                                 "reserved",     "reserved";
2205
2206                                         #clock-cells = <1>;
2207                                 };
2208
2209                                 clk_gates10: gate-clk@0228 {
2210                                         compatible = "rockchip,rk3188-gate-clk";
2211                                         reg = <0x0228 0x4>;
2212                                         clocks =
2213                                                 <&dummy>,       <&dummy>,
2214                                                 <&dummy>,       <&dummy>,
2215
2216                                                 <&dummy>,       <&dummy>,
2217                                                 <&dummy>,       <&dummy>,
2218
2219                                                 <&dummy>,       <&dummy>,
2220                                                 <&dummy>,       <&dummy>,
2221
2222                                                 <&dummy>,       <&dummy>,
2223                                                 <&dummy>,       <&dummy>;
2224
2225                                         clock-output-names =
2226                                                 "reserved",     "reserved",
2227                                                 "reserved",     "reserved",
2228
2229                                                 "reserved",     "reserved",
2230                                                 "reserved",     "reserved",
2231
2232                                                 "reserved",     "reserved",
2233                                                 "reserved",     "reserved",
2234
2235                                                 "reserved",     "reserved",
2236                                                 "reserved",     "reserved";
2237
2238                                         #clock-cells = <1>;
2239                                 };
2240
2241                                 clk_gates11: gate-clk@022c {
2242                                         compatible = "rockchip,rk3188-gate-clk";
2243                                         reg = <0x022c 0x4>;
2244                                         clocks =
2245                                                 <&dummy>,       <&dummy>,
2246                                                 <&dummy>,       <&dummy>,
2247
2248                                                 <&dummy>,       <&dummy>,
2249                                                 <&dummy>,       <&dummy>,
2250
2251                                                 <&dummy>,       <&dummy>,
2252                                                 <&dummy>,       <&dummy>,
2253
2254                                                 <&dummy>,       <&dummy>,
2255                                                 <&dummy>,       <&dummy>;
2256
2257                                         clock-output-names =
2258                                                 "reserved",     "reserved",
2259                                                 "reserved",     "reserved",
2260
2261                                                 "reserved",     "reserved",
2262                                                 "reserved",     "reserved",
2263
2264                                                 "reserved",     "reserved",
2265                                                 "reserved",     "reserved",
2266
2267                                                 "reserved",     "reserved",
2268                                                 "reserved",     "reserved";
2269
2270                                         #clock-cells = <1>;
2271                                 };
2272
2273                                 clk_gates12: gate-clk@0230 {
2274                                         compatible = "rockchip,rk3188-gate-clk";
2275                                         reg = <0x0230 0x4>;
2276                                         clocks =
2277                                                 <&pclk_bus>,    <&pclk_bus>,
2278                                                 <&pclk_bus>,    <&pclk_bus>,
2279
2280                                                 <&aclk_bus>,    <&aclk_bus>,
2281                                                 <&aclk_bus>,    <&hclk_bus>,
2282
2283                                                 <&hclk_bus>,    <&hclk_bus>,
2284                                                 <&hclk_bus>,    <&aclk_bus>,
2285
2286                                                 <&aclk_bus>,    <&dummy>,
2287                                                 <&dummy>,       <&dummy>;
2288
2289                                         clock-output-names =
2290                                                 "g_pclk_pwm0",  "g_p_mailbox",
2291                                                 "g_p_i2cpmu",   "g_p_i2caudio",
2292
2293                                                 "g_aclk_intmem",        "g_clk_intmem0",
2294                                                 "g_clk_intmem1",        "g_h_i2s_8ch",
2295
2296                                                 "g_h_i2s_2ch",  "g_hclk_rom",
2297                                                 "g_hclk_spdif", "g_aclk_dmac",
2298
2299                                                 "g_a_strc_sys", "reserved",/* bit13: pclk_ddrupctl */
2300                                                 "reserved",     "reserved";/* bit14: pclk_ddrphy */
2301
2302                                         #clock-cells = <1>;
2303                                 };
2304
2305                                 clk_gates13: gate-clk@0234 {
2306                                         compatible = "rockchip,rk3188-gate-clk";
2307                                         reg = <0x0234 0x4>;
2308                                         clocks =
2309                                                 <&pclk_bus>,    <&pclk_bus>,
2310                                                 <&dummy>,       <&hclk_bus>,
2311
2312                                                 <&hclk_bus>,    <&pclk_bus>,
2313                                                 <&pclk_bus>,    <&clkin_hsadc_tsp>,
2314
2315                                                 <&pclk_bus>,    <&aclk_bus>,
2316                                                 <&hclk_bus>,    <&dummy>,
2317
2318                                                 <&dummy>,       <&dummy>,
2319                                                 <&dummy>,       <&dummy>;
2320
2321                                         clock-output-names =
2322                                                 "g_p_efuse_1024",       "g_p_efuse_256",
2323                                                 "reserved",     "g_mclk_crypto",/* bit2: nclk_ddrupctl */
2324
2325                                                 "g_sclk_crypto",        "g_p_uartdbg",
2326                                                 "g_pclk_pwm1",  "clk_hsadc_tsp",
2327
2328                                                 "g_pclk_sim",   "g_aclk_gic400",
2329                                                 "g_hclk_tsp",   "reserved",
2330
2331                                                 "reserved",     "reserved",
2332                                                 "reserved",     "reserved";
2333
2334                                         #clock-cells = <1>;
2335                                 };
2336
2337                                 clk_gates14: gate-clk@0238 {
2338                                         compatible = "rockchip,rk3188-gate-clk";
2339                                         reg = <0x0238 0x4>;
2340                                         clocks =
2341                                                 <&dummy>,       <&dummy>,
2342                                                 <&dummy>,       <&dummy>,
2343
2344                                                 <&dummy>,       <&dummy>,
2345                                                 <&dummy>,       <&dummy>,
2346
2347                                                 <&dummy>,       <&dummy>,
2348                                                 <&dummy>,       <&dummy>,
2349
2350                                                 <&dummy>,       <&dummy>,
2351                                                 <&dummy>,       <&dummy>;
2352
2353                                         clock-output-names =
2354                                                 "reserved",     "reserved",
2355                                                 "reserved",     "reserved",
2356
2357                                                 "reserved",     "reserved",
2358                                                 "reserved",     "reserved",
2359
2360                                                 "reserved",     "reserved",
2361                                                 "reserved",     "reserved",
2362
2363                                                 "reserved",     "reserved",
2364                                                 "reserved",     "reserved";
2365
2366                                         #clock-cells = <1>;
2367                                 };
2368
2369                                 clk_gates15: gate-clk@023c {
2370                                         compatible = "rockchip,rk3188-gate-clk";
2371                                         reg = <0x023c 0x4>;
2372                                         clocks =
2373                                                 <&dummy>,       <&dummy>,
2374                                                 <&dummy>,       <&dummy>,
2375
2376                                                 <&dummy>,       <&dummy>,
2377                                                 <&dummy>,       <&dummy>,
2378
2379                                                 <&dummy>,       <&dummy>,
2380                                                 <&dummy>,       <&dummy>,
2381
2382                                                 <&dummy>,       <&dummy>,
2383                                                 <&dummy>,       <&dummy>;
2384
2385                                         clock-output-names =
2386                                                 "reserved",     "reserved",/* aclk_video hclk_video */
2387                                                 "reserved",     "reserved",
2388
2389                                                 "reserved",     "reserved",
2390                                                 "reserved",     "reserved",
2391
2392                                                 "reserved",     "reserved",
2393                                                 "reserved",     "reserved",
2394
2395                                                 "reserved",     "reserved",
2396                                                 "reserved",     "reserved";
2397
2398                                         #clock-cells = <1>;
2399                                 };
2400
2401                                 clk_gates16: gate-clk@0240 {
2402                                         compatible = "rockchip,rk3188-gate-clk";
2403                                         reg = <0x0240 0x4>;
2404                                         clocks =
2405                                                 <&clk_gates16 10>,      <&clk_gates16 8>,
2406                                                 <&clk_gates16 9>,       <&clk_gates16 8>,
2407
2408                                                 <&clk_gates16 9>,       <&clk_gates16 9>,
2409                                                 <&clk_gates16 8>,       <&clk_gates16 8>,
2410
2411                                                 <&hclk_vio>,    <&aclk_vio0>,
2412                                                 <&aclk_rga_pre>,        <&clk_gates16 9>,
2413
2414                                                 <&clk_gates16 8>,       <&pclkin_vip>,
2415                                                 <&clk_isp>,     <&dummy>;
2416
2417                                         clock-output-names =
2418                                                 "g_aclk_rga",   "g_hclk_rga",
2419                                                 "g_aclk_iep",   "g_hclk_iep",
2420
2421                                                 "g_aclk_vop_iep",       "g_aclk_vop",
2422                                                 "g_hclk_vop",   "g_h_vio_ahb_arbi",
2423
2424                                                 "g_hclk_vio_noc",       "g_aclk_vio0_noc",
2425                                                 "g_aclk_vio1_noc",      "g_aclk_vip",
2426
2427                                                 "g_hclk_vip",   "g_pclkin_vip",
2428                                                 "g_hclk_isp",   "reserved";
2429
2430                                         #clock-cells = <1>;
2431                                 };
2432
2433                                 clk_gates17: gate-clk@0244 {
2434                                         compatible = "rockchip,rk3188-gate-clk";
2435                                         reg = <0x0244 0x4>;
2436                                         clocks =
2437                                                 <&clk_isp>,     <&dummy>,
2438                                                 <&pclkin_isp>,  <&pclk_vio>,
2439
2440                                                 <&pclk_vio>,    <&dummy>,
2441                                                 <&pclk_vio>,    <&clk_gates16 8>,
2442
2443                                                 <&pclk_vio>,    <&pclk_vio>,
2444                                                 <&clk_gates16 10>,      <&pclk_vio>,
2445
2446                                                 <&clk_gates16 8>,       <&dummy>,
2447                                                 <&dummy>,       <&dummy>;
2448
2449                                         clock-output-names =
2450                                                 "g_aclk_isp",   "reserved",
2451                                                 "g_pclkin_isp", "g_p_mipi_dsi0",
2452
2453                                                 "g_p_mipi_csi", "reserved",
2454                                                 "g_p_hdmi_ctrl",        "g_hclk_vio_h2p",
2455
2456                                                 "g_pclk_vio_h2p",       "g_p_edp_ctrl",
2457                                                 "g_aclk_hdcp",  "g_pclk_hdcp",
2458
2459                                                 "g_h_hdcpmmu",  "reserved",
2460                                                 "reserved",     "reserved";
2461
2462                                         #clock-cells = <1>;
2463                                 };
2464
2465                                 clk_gates18: gate-clk@0248 {
2466                                         compatible = "rockchip,rk3188-gate-clk";
2467                                         reg = <0x0248 0x4>;
2468                                         clocks =
2469                                                 <&dummy>,       <&dummy>,
2470                                                 <&dummy>,       <&dummy>,
2471
2472                                                 <&dummy>,       <&dummy>,
2473                                                 <&dummy>,       <&dummy>,
2474
2475                                                 <&dummy>,       <&dummy>,
2476                                                 <&dummy>,       <&dummy>,
2477
2478                                                 <&dummy>,       <&dummy>,
2479                                                 <&dummy>,       <&dummy>;
2480
2481                                         clock-output-names =
2482                                                 "reserved",     "reserved",/* bit0-1: aclk_gpu_cfg aclk_gpu_mem */
2483                                                 "reserved",     "reserved",/* bit2: clk_gpu_core */
2484
2485                                                 "reserved",     "reserved",
2486                                                 "reserved",     "reserved",
2487
2488                                                 "reserved",     "reserved",
2489                                                 "reserved",     "reserved",
2490
2491                                                 "reserved",     "reserved",
2492                                                 "reserved",     "reserved";
2493
2494                                         #clock-cells = <1>;
2495                                 };
2496
2497                                 clk_gates19: gate-clk@024c {
2498                                         compatible = "rockchip,rk3188-gate-clk";
2499                                         reg = <0x024c 0x4>;
2500                                         clocks =
2501                                                 <&hclk_peri>,   <&pclk_peri>,
2502                                                 <&aclk_peri>,   <&aclk_peri>,
2503
2504                                                 <&pclk_peri>,   <&pclk_peri>,
2505                                                 <&pclk_peri>,   <&pclk_peri>,
2506
2507                                                 <&pclk_peri>,   <&pclk_peri>,
2508                                                 <&pclk_peri>,   <&pclk_peri>,
2509
2510                                                 <&pclk_peri>,   <&pclk_peri>,
2511                                                 <&pclk_peri>,   <&pclk_peri>;
2512
2513                                         clock-output-names =
2514                                                 "g_h_p_axi_matrix",     "g_p_p_axi_matrix",
2515                                                 "g_a_p_axi_matrix",     "g_a_dmac_peri",
2516
2517                                                 "g_pclk_spi0",  "g_pclk_spi1",
2518                                                 "g_pclk_spi2",  "g_pclk_uart0",
2519
2520                                                 "g_pclk_uart1", "g_pclk_uart3",
2521                                                 "g_pclk_uart4", "g_pclk_i2c2",
2522
2523                                                 "g_pclk_i2c3",  "g_pclk_i2c4",
2524                                                 "g_pclk_i2c5",  "g_pclk_saradc";
2525
2526                                         #clock-cells = <1>;
2527                                 };
2528
2529                                 clk_gates20: gate-clk@0250 {
2530                                         compatible = "rockchip,rk3188-gate-clk";
2531                                         reg = <0x0250 0x4>;
2532                                         clocks =
2533                                                 <&pclk_peri>,   <&hclk_peri>,
2534                                                 <&hclk_peri>,   <&hclk_peri>,
2535
2536                                                 <&dummy>,       <&hclk_peri>,
2537                                                 <&hclk_peri>,   <&hclk_peri>,
2538
2539                                                 <&aclk_peri>,   <&hclk_peri>,
2540                                                 <&hclk_peri>,   <&hclk_peri>,
2541
2542                                                 <&dummy>,       <&aclk_peri>,
2543                                                 <&pclk_peri>,   <&aclk_peri>;
2544
2545                                         clock-output-names =
2546                                                 "g_pclk_tsadc", "g_hclk_otg0",
2547                                                 "g_h_pmu_otg0", "g_hclk_host0",
2548
2549                                                 "reserved",     "g_hclk_hsic",
2550                                                 "g_h_usb_peri", "g_h_p_ahb_arbi",
2551
2552                                                 "g_a_peri_niu", "g_h_emem_peri",
2553                                                 "g_h_mmc_peri", "g_hclk_nand0",
2554
2555                                                 "reserved",     "g_aclk_gmac",
2556                                                 "g_pclk_gmac",  "g_hclk_sfc";
2557
2558                                         #clock-cells = <1>;
2559                                 };
2560
2561                                 clk_gates21: gate-clk@0254 {
2562                                         compatible = "rockchip,rk3188-gate-clk";
2563                                         reg = <0x0254 0x4>;
2564                                         clocks =
2565                                                 <&hclk_peri>,   <&hclk_peri>,
2566                                                 <&hclk_peri>,   <&hclk_peri>,
2567
2568                                                 <&aclk_peri>,   <&dummy>,
2569                                                 <&dummy>,       <&dummy>,
2570
2571                                                 <&dummy>,       <&dummy>,
2572                                                 <&dummy>,       <&dummy>,
2573
2574                                                 <&dummy>,       <&dummy>,
2575                                                 <&dummy>,       <&dummy>;
2576
2577                                         clock-output-names =
2578                                                 "g_hclk_sdmmc", "g_hclk_sdio0",
2579                                                 "g_hclk_emmc",  "g_hclk_hsadc",
2580
2581                                                 "g_aclk_peri_mmu",      "reserved",
2582                                                 "reserved",     "reserved",
2583
2584                                                 "reserved",     "reserved",
2585                                                 "reserved",     "reserved",
2586
2587                                                 "reserved",     "reserved",
2588                                                 "reserved",     "reserved";
2589
2590                                         #clock-cells = <1>;
2591                                 };
2592
2593                                 clk_gates22: gate-clk@0258 {
2594                                         compatible = "rockchip,rk3188-gate-clk";
2595                                         reg = <0x0258 0x4>;
2596                                         clocks =
2597                                                 <&dummy>,       <&pclk_alive_pre>,
2598                                                 <&pclk_alive_pre>,      <&pclk_alive_pre>,
2599
2600                                                 <&dummy>,       <&dummy>,
2601                                                 <&dummy>,       <&dummy>,
2602
2603                                                 <&pclk_alive_pre>,      <&pclk_alive_pre>,
2604                                                 <&pclk_vio>,    <&pclk_vio>,
2605
2606                                                 <&pclk_alive_pre>,      <&pclk_alive_pre>,
2607                                                 <&dummy>,       <&dummy>;
2608
2609                                         clock-output-names =
2610                                                 "reserved",     "g_pclk_gpio1",
2611                                                 "g_pclk_gpio2", "g_pclk_gpio3",
2612
2613                                                 "reserved",     "reserved",
2614                                                 "reserved",     "reserved",
2615
2616                                                 "g_pclk_grf",   "g_p_alive_niu",
2617                                                 "g_pclk_dphytx0",       "g_pclk_dphyrx",
2618
2619                                                 "g_pclk_timer0",        "g_pclk_timer1",
2620                                                 "reserved",     "reserved";
2621
2622                                         #clock-cells = <1>;
2623                                 };
2624
2625                                 clk_gates23: gate-clk@025c {
2626                                         compatible = "rockchip,rk3188-gate-clk";
2627                                         reg = <0x025c 0x4>;
2628                                         clocks =
2629                                                 <&pclk_pmu_pre>,        <&pclk_pmu_pre>,
2630                                                 <&pclk_pmu_pre>,        <&pclk_pmu_pre>,
2631
2632                                                 <&pclk_pmu_pre>,        <&pclk_pmu_pre>,
2633                                                 <&dummy>,       <&dummy>,
2634
2635                                                 <&dummy>,       <&dummy>,
2636                                                 <&dummy>,       <&dummy>,
2637
2638                                                 <&dummy>,       <&dummy>,
2639                                                 <&dummy>,       <&dummy>;
2640
2641                                         clock-output-names =
2642                                                 "g_pclk_pmu",   "g_pclk_intmem1",
2643                                                 "g_pclk_pmu_noc",       "g_pclk_sgrf",
2644
2645                                                 "g_pclk_gpio0", "g_pclk_pmugrf",
2646                                                 "reserved",     "reserved",
2647
2648                                                 "reserved",     "reserved",
2649                                                 "reserved",     "reserved",
2650
2651                                                 "reserved",     "reserved",
2652                                                 "reserved",     "reserved";
2653
2654                                         #clock-cells = <1>;
2655                                 };
2656
2657                                 clk_gates24: gate-clk@0260 {
2658                                         compatible = "rockchip,rk3188-gate-clk";
2659                                         reg = <0x0260 0x4>;
2660                                         clocks =
2661                                                 <&xin24m>,      <&xin24m>,
2662                                                 <&xin24m>,      <&xin24m>,
2663
2664                                                 <&xin24m>,      <&xin24m>,
2665                                                 <&xin24m>,      <&xin24m>,
2666
2667                                                 <&xin24m>,      <&xin24m>,
2668                                                 <&xin24m>,      <&xin24m>,
2669
2670                                                 <&dummy>,       <&dummy>,
2671                                                 <&dummy>,       <&dummy>;
2672
2673                                         clock-output-names =
2674                                                 "g_clk_timer0", "g_clk_timer1",
2675                                                 "g_clk_timer2", "g_clk_timer3",
2676
2677                                                 "g_clk_timer4", "g_clk_timer5",
2678                                                 "g_clk_timer10",        "g_clk_timer11",
2679
2680                                                 "g_clk_timer12",        "g_clk_timer13",
2681                                                 "g_clk_timer14",        "g_clk_timer15",
2682
2683                                                 "reserved",     "reserved",
2684                                                 "reserved",     "reserved";
2685
2686                                         #clock-cells = <1>;
2687                                 };
2688                         };
2689                 };
2690
2691                 special_regs {
2692                         compatible = "rockchip,rk-clock-special-regs";
2693                         #address-cells = <1>;
2694                         #size-cells = <1>;
2695                         ranges;
2696
2697                         clk_32k_mux: clk_32k_mux {
2698                                 compatible = "rockchip,rk3188-mux-con";
2699                                 reg = <0xff738100 0x4>;
2700                                 rockchip,bits = <6 1>;
2701                                 clocks = <&xin32k>, <&clk_gates7 3>;
2702                                 clock-output-names = "clk_32k_mux";
2703                                 #clock-cells = <0>;
2704                                 #clock-init-cells = <1>;
2705                         };
2706                 };
2707         };
2708 };