arch/arm64/boot/dts/rk3368-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014-2015 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk3368.h>
  15
  16
  17
  18 /{
  19         clocks {
  20                 compatible = "rockchip,rk-clocks";
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23                 ranges;
  24
  25                 fixed_rate_cons {
  26                         compatible = "rockchip,rk-fixed-rate-cons";
  27
  28                         xin24m: xin24m {
  29                                 compatible = "rockchip,rk-fixed-clock";
  30                                 clock-output-names = "xin24m";
  31                                 clock-frequency = <24000000>;
  32                                 #clock-cells = <0>;
  33                         };
  34
  35                         xin12m: xin12m {
  36                                 compatible = "rockchip,rk-fixed-clock";
  37                                 clocks = <&xin24m>;
  38                                 clock-output-names = "xin12m";
  39                                 clock-frequency = <12000000>;
  40                                 #clock-cells = <0>;
  41                         };
  42
  43                         xin32k: xin32k {
  44                                 compatible = "rockchip,rk-fixed-clock";
  45                                 clock-output-names = "xin32k";
  46                                 clock-frequency = <32000>;
  47                                 #clock-cells = <0>;
  48                         };
  49
  50                         dummy: dummy {
  51                                 compatible = "rockchip,rk-fixed-clock";
  52                                 clock-output-names = "dummy";
  53                                 clock-frequency = <0>;
  54                                 #clock-cells = <0>;
  55                         };
  56
  57                         jtag_clkin: jtag_clkin {
  58                                 compatible = "rockchip,rk-fixed-clock";
  59                                 clock-output-names = "jtag_clkin";
  60                                 clock-frequency = <0>;
  61                                 #clock-cells = <0>;
  62                         };
  63
  64                         gmac_clkin: gmac_clkin {
  65                                 compatible = "rockchip,rk-fixed-clock";
  66                                 clock-output-names = "gmac_clkin";
  67                                 clock-frequency = <0>;
  68                                 #clock-cells = <0>;
  69                         };
  70
  71                         pclkin_isp: pclkin_isp {
  72                                 compatible = "rockchip,rk-fixed-clock";
  73                                 clock-output-names = "pclkin_isp";
  74                                 clock-frequency = <0>;
  75                                 #clock-cells = <0>;
  76                         };
  77
  78                         pclkin_vip: pclkin_vip {
  79                                 compatible = "rockchip,rk-fixed-clock";
  80                                 clock-output-names = "pclkin_vip";
  81                                 clock-frequency = <0>;
  82                                 #clock-cells = <0>;
  83                         };
  84
  85                         clkin_hsadc_tsp: clkin_hsadc_tsp {
  86                                 compatible = "rockchip,rk-fixed-clock";
  87                                 clock-output-names = "clkin_hsadc_tsp";
  88                                 clock-frequency = <0>;
  89                                 #clock-cells = <0>;
  90                         };
  91
  92                         i2s_clkin: i2s_clkin {
  93                                 compatible = "rockchip,rk-fixed-clock";
  94                                 clock-output-names = "i2s_clkin";
  95                                 clock-frequency = <0>;
  96                                 #clock-cells = <0>;
  97                         };
  98                 };
  99
 100                 fixed_factor_cons {
 101                         compatible = "rockchip,rk-fixed-factor-cons";
 102
 103                         hclk_vepu: hclk_vepu {
 104                                 compatible = "rockchip,rk-fixed-factor-clock";
 105                                 clocks = <&aclk_vepu>;
 106                                 clock-output-names = "hclk_vepu";
 107                                 clock-div = <4>;
 108                                 clock-mult = <1>;
 109                                 #clock-cells = <0>;
 110                         };
 111
 112                         hclk_vdpu: hclk_vdpu {
 113                                 compatible = "rockchip,rk-fixed-factor-clock";
 114                                 clocks = <&aclk_vdpu>;
 115                                 clock-output-names = "hclk_vdpu";
 116                                 clock-div = <4>;
 117                                 clock-mult = <1>;
 118                                 #clock-cells = <0>;
 119                         };
 120
 121                         usbotg_480m_out: usbotg_480m_out {
 122                                 compatible = "rockchip,rk-fixed-factor-clock";
 123                                 clocks = <&clk_gates8 1>;
 124                                 clock-output-names = "usbotg_480m_out";
 125                                 clock-div = <1>;
 126                                 clock-mult = <20>;
 127                                 #clock-cells = <0>;
 128                         };
 129
 130                         pclkin_isp_inv: pclkin_isp_inv {
 131                                 compatible = "rockchip,rk-fixed-factor-clock";
 132                                 clocks = <&clk_gates17 2>;
 133                                 clock-output-names = "pclkin_isp_inv";
 134                                 clock-div = <1>;
 135                                 clock-mult = <1>;
 136                                 #clock-cells = <0>;
 137                         };
 138
 139                         pclkin_vip_inv: pclkin_vip_inv {
 140                                 compatible = "rockchip,rk-fixed-factor-clock";
 141                                 clocks = <&clk_gates16 13>;
 142                                 clock-output-names = "pclkin_vip_inv";
 143                                 clock-div = <1>;
 144                                 clock-mult = <1>;
 145                                 #clock-cells = <0>;
 146                         };
 147
 148                         pclk_vio: pclk_vio {
 149                                 compatible = "rockchip,rk-fixed-factor-clock";
 150                                 clocks = <&clk_gates16 8>;
 151                                 clock-output-names = "pclk_vio";
 152                                 clock-div = <1>;
 153                                 clock-mult = <1>;
 154                                 #clock-cells = <0>;
 155                         };
 156                 };
 157
 158                 clock_regs {
 159                         compatible = "rockchip,rk-clock-regs";
 160                         #address-cells = <1>;
 161                         #size-cells = <1>;
 162                         ranges = <0x0 0xFF760000 0x0264>;
 163                         reg = <0xFF760000 0x0264>;/* NEED CONFIRM */
 164
 165                         /* PLL control regs */
 166                         pll_cons {
 167                                 compatible = "rockchip,rk-pll-cons";
 168                                 #address-cells = <1>;
 169                                 #size-cells = <1>;
 170                                 ranges;
 171
 172                                 clk_apllb: pll-clk@0000 {
 173                                         compatible = "rockchip,rk3188-pll-clk";
 174                                         reg = <0x0000 0x10>;
 175                                         mode-reg = <0x000c 8>;
 176                                         status-reg = <0x0480 1>;
 177                                         clocks = <&xin24m>;
 178                                         clock-output-names = "clk_apllb";
 179                                         rockchip,pll-type = <CLK_PLL_3368_APLLB>;
 180                                         #clock-cells = <0>;
 181                                 };
 182
 183
 184                                 clk_aplll: pll-clk@0010 {
 185                                         compatible = "rockchip,rk3188-pll-clk";
 186                                         reg = <0x0010 0x10>;
 187                                         mode-reg = <0x001c 8>;
 188                                         status-reg = <0x0480 0>;
 189                                         clocks = <&xin24m>;
 190                                         clock-output-names = "clk_aplll";
 191                                         rockchip,pll-type = <CLK_PLL_3368_APLLL>;
 192                                         #clock-cells = <0>;
 193                                 };
 194
 195                                 clk_dpll: pll-clk@0020 {
 196                                         compatible = "rockchip,rk3188-pll-clk";
 197                                         reg = <0x0020 0x10>;
 198                                         mode-reg = <0x002c 8>;
 199                                         status-reg = <0x0480 2>;
 200                                         clocks = <&xin24m>;
 201                                         clock-output-names = "clk_dpll";
 202                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 203                                         #clock-cells = <0>;
 204                                 };
 205
 206
 207                                 clk_cpll: pll-clk@0030 {
 208                                         compatible = "rockchip,rk3188-pll-clk";
 209                                         reg = <0x0030 0x10>;
 210                                         mode-reg = <0x003c 8>;
 211                                         status-reg = <0x0480 3>;
 212                                         clocks = <&xin24m>;
 213                                         clock-output-names = "clk_cpll";
 214                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 215                                         #clock-cells = <0>;
 216                                         #clock-init-cells = <1>;
 217                                 };
 218
 219                                 clk_gpll: pll-clk@0040 {
 220                                         compatible = "rockchip,rk3188-pll-clk";
 221                                         reg = <0x0040 0x10>;
 222                                         mode-reg = <0x004c 8>;
 223                                         status-reg = <0x0480 4>;
 224                                         clocks = <&xin24m>;
 225                                         clock-output-names = "clk_gpll";
 226                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 227                                         #clock-cells = <0>;
 228                                         #clock-init-cells = <1>;
 229                                 };
 230
 231                                 clk_npll: pll-clk@0050 {
 232                                         compatible = "rockchip,rk3188-pll-clk";
 233                                         reg = <0x0050 0x10>;
 234                                         mode-reg = <0x005c 8>;
 235                                         status-reg = <0x0480 5>;
 236                                         clocks = <&xin24m>;
 237                                         clock-output-names = "clk_npll";
 238                                         rockchip,pll-type = <CLK_PLL_3188PLUS_AUTO>;
 239                                         #clock-cells = <0>;
 240                                         #clock-init-cells = <1>;
 241                                 };
 242                         };
 243
 244                         /* Select control regs */
 245                         clk_sel_cons {
 246                                 compatible = "rockchip,rk-sel-cons";
 247                                 #address-cells = <1>;
 248                                 #size-cells = <1>;
 249                                 ranges;
 250
 251                                 clk_sel_con0: sel-con@0100 {
 252                                         compatible = "rockchip,rk3188-selcon";
 253                                         reg = <0x0100 0x4>;
 254                                         #address-cells = <1>;
 255                                         #size-cells = <1>;
 256
 257                                         clk_core_b_div: clk_core_b_div {
 258                                                 compatible = "rockchip,rk3188-div-con";
 259                                                 rockchip,bits = <0 5>;
 260                                                 clocks = <&clk_core_b>;
 261                                                 clock-output-names = "clk_core_b";
 262                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 263                                                 #clock-cells = <0>;
 264                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 265                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 266                                                                         CLK_SET_RATE_NO_REPARENT)>;
 267                                         };
 268
 269                                         /* 6:5 reserved */
 270
 271                                         clk_core_b: clk_core_b_mux {
 272                                                 compatible = "rockchip,rk3188-mux-con";
 273                                                 rockchip,bits = <7 1>;
 274                                                 clocks = <&clk_apllb>, <&clk_gpll>;
 275                                                 clock-output-names = "clk_core_b";
 276                                                 #clock-cells = <0>;
 277                                                 #clock-init-cells = <1>;
 278                                         };
 279
 280                                         aclkm_core_b: aclkm_core_b_div {
 281                                                 compatible = "rockchip,rk3188-div-con";
 282                                                 rockchip,bits = <8 5>;
 283                                                 clocks = <&clk_core_b>;
 284                                                 clock-output-names = "aclkm_core_b";
 285                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 286                                                 #clock-cells = <0>;
 287                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 288                                         };
 289
 290                                         /* 15:13 reserved */
 291                                 };
 292
 293                                 clk_sel_con1: sel-con@0104 {
 294                                         compatible = "rockchip,rk3188-selcon";
 295                                         reg = <0x0104 0x4>;
 296                                         #address-cells = <1>;
 297                                         #size-cells = <1>;
 298
 299                                         atclk_core_b: atclk_core_b_div {
 300                                                 compatible = "rockchip,rk3188-div-con";
 301                                                 rockchip,bits = <0 5>;
 302                                                 clocks = <&clk_core_b>;
 303                                                 clock-output-names = "atclk_core_b";
 304                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 305                                                 #clock-cells = <0>;
 306                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 307                                         };
 308
 309                                         /* 7:5 reserved */
 310
 311                                         pclk_dbg_b: pclk_dbg_b_div {
 312                                                 compatible = "rockchip,rk3188-div-con";
 313                                                 rockchip,bits = <8 5>;
 314                                                 clocks = <&clk_core_b>;
 315                                                 clock-output-names = "pclk_dbg_b";
 316                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 317                                                 #clock-cells = <0>;
 318                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 319                                         };
 320                                 };
 321
 322                                 clk_sel_con2: sel-con@0108 {
 323                                         compatible = "rockchip,rk3188-selcon";
 324                                         reg = <0x0108 0x4>;
 325                                         #address-cells = <1>;
 326                                         #size-cells = <1>;
 327
 328                                         clk_core_l_div: clk_core_l_div {
 329                                                 compatible = "rockchip,rk3188-div-con";
 330                                                 rockchip,bits = <0 5>;
 331                                                 clocks = <&clk_core_l>;
 332                                                 clock-output-names = "clk_core_l";
 333                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 334                                                 #clock-cells = <0>;
 335                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 336                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 337                                                                         CLK_SET_RATE_NO_REPARENT)>;
 338                                         };
 339
 340                                         /* 6:5 reserved */
 341
 342                                         clk_core_l: clk_core_l_mux {
 343                                                 compatible = "rockchip,rk3188-mux-con";
 344                                                 rockchip,bits = <7 1>;
 345                                                 clocks = <&clk_aplll>, <&clk_gpll>;
 346                                                 clock-output-names = "clk_core_l";
 347                                                 #clock-cells = <0>;
 348                                                 #clock-init-cells = <1>;
 349                                         };
 350
 351                                         aclkm_core_l: aclkm_core_l_div {
 352                                                 compatible = "rockchip,rk3188-div-con";
 353                                                 rockchip,bits = <8 5>;
 354                                                 clocks = <&clk_core_l>;
 355                                                 clock-output-names = "aclkm_core_l";
 356                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 357                                                 #clock-cells = <0>;
 358                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 359                                         };
 360
 361                                         /* 15:13 reserved */
 362                                 };
 363
 364                                 clk_sel_con3: sel-con@010c {
 365                                         compatible = "rockchip,rk3188-selcon";
 366                                         reg = <0x010c 0x4>;
 367                                         #address-cells = <1>;
 368                                         #size-cells = <1>;
 369
 370                                         atclk_core_l: atclk_core_l_div {
 371                                                 compatible = "rockchip,rk3188-div-con";
 372                                                 rockchip,bits = <0 5>;
 373                                                 clocks = <&clk_core_l>;
 374                                                 clock-output-names = "atclk_core_l";
 375                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 376                                                 #clock-cells = <0>;
 377                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 378                                         };
 379
 380                                         /* 7:5 reserved */
 381
 382                                         pclk_dbg_l: pclk_dbg_l_div {
 383                                                 compatible = "rockchip,rk3188-div-con";
 384                                                 rockchip,bits = <8 5>;
 385                                                 clocks = <&clk_core_l>;
 386                                                 clock-output-names = "pclk_dbg_l";
 387                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 388                                                 #clock-cells = <0>;
 389                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 390                                         };
 391                                 };
 392
 393                                 clk_sel_con4: sel-con@0110 {
 394                                         compatible = "rockchip,rk3188-selcon";
 395                                         reg = <0x0110 0x4>;
 396                                         #address-cells = <1>;
 397                                         #size-cells = <1>;
 398
 399                                         clk_cs_div: clk_cs_div {
 400                                                 compatible = "rockchip,rk3188-div-con";
 401                                                 rockchip,bits = <0 5>;
 402                                                 clocks = <&clk_cs>;
 403                                                 clock-output-names = "clk_cs";
 404                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 405                                                 #clock-cells = <0>;
 406                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 407                                         };
 408
 409                                         /* 5 reserved */
 410
 411                                         clk_cs: clk_cs_mux {
 412                                                 compatible = "rockchip,rk3188-mux-con";
 413                                                 rockchip,bits = <6 2>;
 414                                                 clocks = <&clk_gates0 9>, <&clk_gates0 10>, <&clk_gates0 8>, <&dummy>;
 415                                                 clock-output-names = "clk_cs";
 416                                                 #clock-cells = <0>;
 417                                                 #clock-init-cells = <1>;
 418                                         };
 419
 420                                         clkin_trace: clkin_trace_div {
 421                                                 compatible = "rockchip,rk3188-div-con";
 422                                                 rockchip,bits = <8 5>;
 423                                                 clocks = <&clk_cs>;
 424                                                 clock-output-names = "clkin_trace";
 425                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 426                                                 #clock-cells = <0>;
 427                                                 #clock-init-cells = <1>;
 428                                         };
 429
 430                                 };
 431
 432                                 clk_sel_con5: sel-con@0114 {
 433                                         compatible = "rockchip,rk3188-selcon";
 434                                         reg = <0x0114 0x4>;
 435                                         #address-cells = <1>;
 436                                         #size-cells = <1>;
 437
 438                                         aclk_cci_div: aclk_cci_div {
 439                                                 compatible = "rockchip,rk3188-div-con";
 440                                                 rockchip,bits = <0 5>;
 441                                                 clocks = <&aclk_cci>;
 442                                                 clock-output-names = "aclk_cci";
 443                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 444                                                 #clock-cells = <0>;
 445                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 446                                         };
 447
 448                                         /* 5 reserved */
 449
 450                                         aclk_cci: aclk_cci_mux {
 451                                                 compatible = "rockchip,rk3188-mux-con";
 452                                                 rockchip,bits = <6 2>;
 453                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
 454                                                 clock-output-names = "aclk_cci";
 455                                                 #clock-cells = <0>;
 456                                                 #clock-init-cells = <1>;
 457                                         };
 458                                 };
 459
 460                                 /* sel[7:6] reserved */
 461
 462                                 clk_sel_con8: sel-con@0120 {
 463                                         compatible = "rockchip,rk3188-selcon";
 464                                         reg = <0x0120 0x4>;
 465                                         #address-cells = <1>;
 466                                         #size-cells = <1>;
 467
 468                                         aclk_bus_div: aclk_bus_div {
 469                                                 compatible = "rockchip,rk3188-div-con";
 470                                                 rockchip,bits = <0 5>;
 471                                                 clocks = <&aclk_bus>;
 472                                                 clock-output-names = "aclk_bus_div";
 473                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 474                                                 #clock-cells = <0>;
 475                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 476                                         };
 477
 478                                         /* 6:5 reserved */
 479
 480                                         aclk_bus: aclk_bus_mux {
 481                                                 compatible = "rockchip,rk3188-mux-con";
 482                                                 rockchip,bits = <7 1>;
 483                                                 clocks = <&clk_gates1 11>, <&clk_gates1 10>;
 484                                                 clock-output-names = "aclk_bus";
 485                                                 #clock-cells = <0>;
 486                                                 #clock-init-cells = <1>;
 487                                         };
 488
 489                                         hclk_bus: hclk_bus_div {
 490                                                 compatible = "rockchip,rk3188-div-con";
 491                                                 rockchip,bits = <8 2>;
 492                                                 clocks = <&aclk_bus>;
 493                                                 clock-output-names = "hclk_bus";
 494                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 495                                                 #clock-cells = <0>;
 496                                                 #clock-init-cells = <1>;
 497                                         };
 498
 499                                         /* 11:10 reserved */
 500
 501                                         pclk_bus: pclk_bus_div {
 502                                                 compatible = "rockchip,rk3188-div-con";
 503                                                 rockchip,bits = <12 3>;
 504                                                 clocks = <&aclk_bus>;
 505                                                 clock-output-names = "pclk_bus";
 506                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 507                                                 #clock-cells = <0>;
 508                                                 #clock-init-cells = <1>;
 509                                         };
 510                                 };
 511
 512                                 clk_sel_con9: sel-con@0124 {
 513                                         compatible = "rockchip,rk3188-selcon";
 514                                         reg = <0x0124 0x4>;
 515                                         #address-cells = <1>;
 516                                         #size-cells = <1>;
 517
 518                                         aclk_peri_div: aclk_peri_div {
 519                                                 compatible = "rockchip,rk3188-div-con";
 520                                                 rockchip,bits = <0 5>;
 521                                                 clocks = <&aclk_peri>;
 522                                                 clock-output-names = "aclk_peri_div";
 523                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 524                                                 #clock-cells = <0>;
 525                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 526                                         };
 527
 528                                         /* 6:5 reserved */
 529
 530                                         aclk_peri: aclk_peri_mux {
 531                                                 compatible = "rockchip,rk3188-mux-con";
 532                                                 rockchip,bits = <7 1>;
 533                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 534                                                 clock-output-names = "aclk_peri";
 535                                                 #clock-cells = <0>;
 536                                                 #clock-init-cells = <1>;
 537                                         };
 538
 539                                         hclk_peri: hclk_peri_div {
 540                                                 compatible = "rockchip,rk3188-div-con";
 541                                                 rockchip,bits = <8 2>;
 542                                                 clocks = <&aclk_peri>;
 543                                                 clock-output-names = "hclk_peri";
 544                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 545                                                 rockchip,div-relations =
 546                                                                 <0x0 1
 547                                                                  0x1 2
 548                                                                  0x2 4>;
 549                                                 #clock-cells = <0>;
 550                                                 #clock-init-cells = <1>;
 551                                         };
 552
 553                                         /* 11:10 reserved */
 554
 555                                         pclk_peri: pclk_peri_div {
 556                                                 compatible = "rockchip,rk3188-div-con";
 557                                                 rockchip,bits = <12 2>;
 558                                                 clocks = <&aclk_peri>;
 559                                                 clock-output-names = "pclk_peri";
 560                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 561                                                 rockchip,div-relations =
 562                                                                 <0x0 1
 563                                                                  0x1 2
 564                                                                  0x2 4
 565                                                                  0x3 8>;
 566                                                 #clock-cells = <0>;
 567                                                 #clock-init-cells = <1>;
 568                                         };
 569                                 };
 570
 571                                 clk_sel_con10: sel-con@0128 {
 572                                         compatible = "rockchip,rk3188-selcon";
 573                                         reg = <0x0128 0x4>;
 574                                         #address-cells = <1>;
 575                                         #size-cells = <1>;
 576
 577                                         pclk_pmu_pre: pclk_pmu_pre_div {
 578                                                 compatible = "rockchip,rk3188-div-con";
 579                                                 rockchip,bits = <0 5>;
 580                                                 clocks = <&clk_gpll>;
 581                                                 clock-output-names = "pclk_pmu_pre";
 582                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 583                                                 #clock-cells = <0>;
 584                                                 #clock-init-cells = <1>;
 585                                         };
 586
 587                                         /* 7:5 reserved */
 588
 589                                         pclk_alive_pre: pclk_alive_pre_div {
 590                                                 compatible = "rockchip,rk3188-div-con";
 591                                                 rockchip,bits = <8 5>;
 592                                                 clocks = <&clk_gpll>;
 593                                                 clock-output-names = "pclk_alive_pre";
 594                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 595                                                 #clock-cells = <0>;
 596                                                 #clock-init-cells = <1>;
 597                                         };
 598
 599                                         /* 13 reserved */
 600
 601                                         clk_crypto: clk_crypto_div {
 602                                                 compatible = "rockchip,rk3188-div-con";
 603                                                 rockchip,bits = <14 2>;
 604                                                 clocks = <&aclk_bus>;
 605                                                 clock-output-names = "clk_crypto";
 606                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 607                                                 #clock-cells = <0>;
 608                                                 #clock-init-cells = <1>;
 609                                         };
 610                                 };
 611
 612                                 /* sel[11]: reserved */
 613
 614                                 clk_sel_con12: sel-con@0130 {
 615                                         compatible = "rockchip,rk3188-selcon";
 616                                         reg = <0x0130 0x4>;
 617                                         #address-cells = <1>;
 618                                         #size-cells = <1>;
 619
 620                                         fclk_mcu_div: fclk_mcu_div {
 621                                                 compatible = "rockchip,rk3188-div-con";
 622                                                 rockchip,bits = <0 5>;
 623                                                 clocks = <&fclk_mcu>;
 624                                                 clock-output-names = "fclk_mcu";
 625                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 626                                                 #clock-cells = <0>;
 627                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 628                                         };
 629
 630                                         /* 6:5 reserved */
 631
 632                                         fclk_mcu: fclk_mcu_mux {
 633                                                 compatible = "rockchip,rk3188-mux-con";
 634                                                 rockchip,bits = <7 1>;
 635                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 636                                                 clock-output-names = "fclk_mcu";
 637                                                 #clock-cells = <0>;
 638                                                 #clock-init-cells = <1>;
 639                                         };
 640
 641                                         stclk_mcu: stclk_mcu_div {
 642                                                 compatible = "rockchip,rk3188-div-con";
 643                                                 rockchip,bits = <8 3>;
 644                                                 clocks = <&fclk_mcu>;
 645                                                 clock-output-names = "stclk_mcu";
 646                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 647                                                 #clock-cells = <0>;
 648                                         };
 649                                 };
 650
 651                                 clk_sel_con13: sel-con@0134 {
 652                                         compatible = "rockchip,rk3188-selcon";
 653                                         reg = <0x0134 0x4>;
 654                                         #address-cells = <1>;
 655                                         #size-cells = <1>;
 656
 657                                         clk_ddr_div: clk_ddr_div {
 658                                                 compatible = "rockchip,rk3188-div-con";
 659                                                 rockchip,bits = <0 2>;
 660                                                 clocks = <&clk_ddr>;
 661                                                 clock-output-names = "clk_ddr";
 662                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 663                                                 #clock-cells = <0>;
 664                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 665                                                                         CLK_SET_RATE_NO_REPARENT)>;
 666                                                 rockchip,clkops-idx =
 667                                                         <CLKOPS_RATE_DDR_DIV4>;
 668                                         };
 669
 670                                         /* 3:2 reserved */
 671
 672                                         clk_ddr: clk_ddr_mux {
 673                                                 compatible = "rockchip,rk3188-mux-con";
 674                                                 rockchip,bits = <4 1>;
 675                                                 clocks = <&clk_dpll>, <&clk_gpll>;
 676                                                 clock-output-names = "clk_ddr";
 677                                                 #clock-cells = <0>;
 678                                         };
 679
 680                                         /* 7:5 reserved */
 681
 682                                         usbphy_480m: usbphy_480m_mux {
 683                                                 compatible = "rockchip,rk3188-mux-con";
 684                                                 rockchip,bits = <8 1>;
 685                                                 clocks = <&xin24m>, <&usbotg_480m_out>;
 686                                                 clock-output-names = "usbphy_480m";
 687                                                 #clock-cells = <0>;
 688                                                 rockchip,clkops-idx =
 689                                                         <CLKOPS_RATE_RK3288_USB480M>;
 690                                                 #clock-init-cells = <1>;
 691                                         };
 692
 693                                         clk4x_ddr: clk4x_ddr_mux {
 694                                                 compatible = "rockchip,rk3188-mux-con";
 695                                                 rockchip,bits = <4 1>;
 696                                                 clocks = <&clk_dpll>, <&clk_gpll>;
 697                                                 clock-output-names = "clk4x_ddr";
 698                                                 #clock-cells = <0>;
 699                                         };
 700                                 };
 701
 702                                 clk_sel_con14: sel-con@0138 {
 703                                         compatible = "rockchip,rk3188-selcon";
 704                                         reg = <0x0138 0x4>;
 705                                         #address-cells = <1>;
 706                                         #size-cells = <1>;
 707
 708                                         clk_gpu_core_div: clk_gpu_core_div {
 709                                                 compatible = "rockchip,rk3188-div-con";
 710                                                 rockchip,bits = <0 5>;
 711                                                 clocks = <&clk_gpu_core>;
 712                                                 clock-output-names = "clk_gpu_core";
 713                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 714                                                 #clock-cells = <0>;
 715                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 716                                                 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
 717                                         };
 718
 719                                         /* 5 reserved */
 720
 721                                         clk_gpu_core: clk_gpu_core_mux {
 722                                                 compatible = "rockchip,rk3188-mux-con";
 723                                                 rockchip,bits = <6 2>;
 724                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
 725                                                 clock-output-names = "clk_gpu_core";
 726                                                 #clock-cells = <0>;
 727                                                 #clock-init-cells = <1>;
 728                                         };
 729
 730                                         aclk_gpu_mem: aclk_gpu_mem_div {
 731                                                 compatible = "rockchip,rk3188-div-con";
 732                                                 rockchip,bits = <8 5>;
 733                                                 clocks = <&aclk_gpu>;
 734                                                 clock-output-names = "aclk_gpu_mem";
 735                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 736                                                 #clock-cells = <0>;
 737                                                 #clock-init-cells = <1>;
 738                                         };
 739
 740                                         /* 13 reserved */
 741
 742                                         aclk_gpu: aclk_gpu_mux {
 743                                                 compatible = "rockchip,rk3188-mux-con";
 744                                                 rockchip,bits = <14 1>;
 745                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 746                                                 clock-output-names = "aclk_gpu";
 747                                                 #clock-cells = <0>;
 748                                                 #clock-init-cells = <1>;
 749                                         };
 750                                 };
 751
 752                                 clk_sel_con15: sel-con@013c {
 753                                         compatible = "rockchip,rk3188-selcon";
 754                                         reg = <0x013c 0x4>;
 755                                         #address-cells = <1>;
 756                                         #size-cells = <1>;
 757
 758                                         aclk_vepu_div: aclk_vepu_div {
 759                                                 compatible = "rockchip,rk3188-div-con";
 760                                                 rockchip,bits = <0 5>;
 761                                                 clocks = <&aclk_vepu>;
 762                                                 clock-output-names = "aclk_vepu";
 763                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 764                                                 #clock-cells = <0>;
 765                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 766                                         };
 767
 768                                         /* 5 reserved */
 769
 770                                         aclk_vepu: aclk_vepu_mux {
 771                                                 compatible = "rockchip,rk3188-mux-con";
 772                                                 rockchip,bits = <6 2>;
 773                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 774                                                 clock-output-names = "aclk_vepu";
 775                                                 #clock-cells = <0>;
 776                                                 #clock-init-cells = <1>;
 777                                         };
 778
 779                                         aclk_vdpu_div: aclk_vdpu_div {
 780                                                 compatible = "rockchip,rk3188-div-con";
 781                                                 rockchip,bits = <8 5>;
 782                                                 clocks = <&aclk_vdpu>;
 783                                                 clock-output-names = "aclk_vdpu";
 784                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 785                                                 #clock-cells = <0>;
 786                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 787                                         };
 788
 789                                         /* 13 reserved */
 790
 791                                         aclk_vdpu: aclk_vdpu_mux {
 792                                                 compatible = "rockchip,rk3188-mux-con";
 793                                                 rockchip,bits = <14 2>;
 794                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 795                                                 clock-output-names = "aclk_vdpu";
 796                                                 #clock-cells = <0>;
 797                                                 #clock-init-cells = <1>;
 798                                         };
 799                                 };
 800
 801                                 clk_sel_con16: sel-con@0140 {
 802                                         compatible = "rockchip,rk3188-selcon";
 803                                         reg = <0x0140 0x4>;
 804                                         #address-cells = <1>;
 805                                         #size-cells = <1>;
 806
 807                                         aclk_gpu_cfg: aclk_gpu_cfg_div {
 808                                                 compatible = "rockchip,rk3188-div-con";
 809                                                 rockchip,bits = <8 5>;
 810                                                 clocks = <&aclk_gpu>;
 811                                                 clock-output-names = "aclk_gpu_cfg";
 812                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 813                                                 #clock-cells = <0>;
 814                                         };
 815                                 };
 816
 817                                 clk_sel_con17: sel-con@0144 {
 818                                         compatible = "rockchip,rk3188-selcon";
 819                                         reg = <0x0144 0x4>;
 820                                         #address-cells = <1>;
 821                                         #size-cells = <1>;
 822
 823                                         clk_hevc_cabac_div: clk_hevc_cabac_div {
 824                                                 compatible = "rockchip,rk3188-div-con";
 825                                                 rockchip,bits = <0 5>;
 826                                                 clocks = <&clk_hevc_cabac>;
 827                                                 clock-output-names = "clk_hevc_cabac";
 828                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 829                                                 #clock-cells = <0>;
 830                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 831                                         };
 832
 833                                         /* 5 reserved */
 834
 835                                         clk_hevc_cabac: clk_hevc_cabac_mux {
 836                                                 compatible = "rockchip,rk3188-mux-con";
 837                                                 rockchip,bits = <6 2>;
 838                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 839                                                 clock-output-names = "clk_hevc_cabac";
 840                                                 #clock-cells = <0>;
 841                                                 #clock-init-cells = <1>;
 842                                         };
 843
 844                                         clk_hevc_core_div: clk_hevc_core_div {
 845                                                 compatible = "rockchip,rk3188-div-con";
 846                                                 rockchip,bits = <8 5>;
 847                                                 clocks = <&clk_hevc_core>;
 848                                                 clock-output-names = "clk_hevc_core";
 849                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 850                                                 #clock-cells = <0>;
 851                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 852                                         };
 853
 854                                         /* 13 reserved */
 855
 856                                         clk_hevc_core: clk_hevc_core_mux {
 857                                                 compatible = "rockchip,rk3188-mux-con";
 858                                                 rockchip,bits = <14 2>;
 859                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 860                                                 clock-output-names = "clk_hevc_core";
 861                                                 #clock-cells = <0>;
 862                                                 #clock-init-cells = <1>;
 863                                         };
 864                                 };
 865
 866                                 clk_sel_con18: sel-con@0148 {
 867                                         compatible = "rockchip,rk3188-selcon";
 868                                         reg = <0x0148 0x4>;
 869                                         #address-cells = <1>;
 870                                         #size-cells = <1>;
 871
 872                                         clk_rga_div: clk_rga_div {
 873                                                 compatible = "rockchip,rk3188-div-con";
 874                                                 rockchip,bits = <0 5>;
 875                                                 clocks = <&clk_rga>;
 876                                                 clock-output-names = "clk_rga";
 877                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 878                                                 #clock-cells = <0>;
 879                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 880                                         };
 881
 882                                         /* 5 reserved */
 883
 884                                         clk_rga: clk_rga_mux {
 885                                                 compatible = "rockchip,rk3188-mux-con";
 886                                                 rockchip,bits = <6 2>;
 887                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
 888                                                 clock-output-names = "clk_rga";
 889                                                 #clock-cells = <0>;
 890                                                 #clock-init-cells = <1>;
 891                                         };
 892
 893                                         aclk_rga_div: aclk_rga_div {
 894                                                 compatible = "rockchip,rk3188-div-con";
 895                                                 rockchip,bits = <8 5>;
 896                                                 clocks = <&aclk_rga_pre>;
 897                                                 clock-output-names = "aclk_rga_pre";
 898                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 899                                                 #clock-cells = <0>;
 900                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 901                                         };
 902
 903                                         /* 13 reserved */
 904
 905                                         aclk_rga_pre: aclk_rga_mux {
 906                                                 compatible = "rockchip,rk3188-mux-con";
 907                                                 rockchip,bits = <14 2>;
 908                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
 909                                                 clock-output-names = "aclk_rga_pre";
 910                                                 #clock-cells = <0>;
 911                                                 #clock-init-cells = <1>;
 912                                         };
 913                                 };
 914
 915                                 clk_sel_con19: sel-con@014c {
 916                                         compatible = "rockchip,rk3188-selcon";
 917                                         reg = <0x014c 0x4>;
 918                                         #address-cells = <1>;
 919                                         #size-cells = <1>;
 920
 921                                         aclk_vio0_div: aclk_vio0_div {
 922                                                 compatible = "rockchip,rk3188-div-con";
 923                                                 rockchip,bits = <0 5>;
 924                                                 clocks = <&aclk_vio0>;
 925                                                 clock-output-names = "aclk_vio0";
 926                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 927                                                 #clock-cells = <0>;
 928                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 929                                         };
 930
 931                                         /* 5 reserved */
 932
 933                                         aclk_vio0: aclk_vio0_mux {
 934                                                 compatible = "rockchip,rk3188-mux-con";
 935                                                 rockchip,bits = <6 2>;
 936                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
 937                                                 clock-output-names = "aclk_vio0";
 938                                                 #clock-cells = <0>;
 939                                                 #clock-init-cells = <1>;
 940                                         };
 941                                 };
 942
 943                                 clk_sel_con20: sel-con@0150 {
 944                                         compatible = "rockchip,rk3188-selcon";
 945                                         reg = <0x0150 0x4>;
 946                                         #address-cells = <1>;
 947                                         #size-cells = <1>;
 948
 949                                         dclk_vop0_div: dclk_vop0_div {
 950                                                 compatible = "rockchip,rk3188-div-con";
 951                                                 rockchip,bits = <0 8>;
 952                                                 clocks = <&dclk_vop0>;
 953                                                 clock-output-names = "dclk_vop0";
 954                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 955                                                 #clock-cells = <0>;
 956                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 957                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 958                                         };
 959
 960                                         dclk_vop0: dclk_vop0_mux {
 961                                                 compatible = "rockchip,rk3188-mux-con";
 962                                                 rockchip,bits = <8 2>;
 963                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&dummy>;
 964                                                 clock-output-names = "dclk_vop0";
 965                                                 #clock-cells = <0>;
 966                                                 #clock-init-cells = <1>;
 967                                         };
 968
 969                                         /* 15:10 reserved */
 970                                 };
 971
 972                                 clk_sel_con21: sel-con@0154 {
 973                                         compatible = "rockchip,rk3188-selcon";
 974                                         reg = <0x0154 0x4>;
 975                                         #address-cells = <1>;
 976                                         #size-cells = <1>;
 977
 978                                         hclk_vio: hclk_vio_div {
 979                                                 compatible = "rockchip,rk3188-div-con";
 980                                                 rockchip,bits = <0 5>;
 981                                                 clocks = <&aclk_vio0>;
 982                                                 clock-output-names = "hclk_vio";
 983                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 984                                                 #clock-cells = <0>;
 985                                                 #clock-init-cells = <1>;
 986                                         };
 987
 988                                         /* 5 reserved */
 989
 990                                         pclk_isp: pclk_isp_mux {
 991                                                 compatible = "rockchip,rk3188-mux-con";
 992                                                 rockchip,bits = <6 1>;
 993                                                 clocks = <&clk_gates17 2>, <&pclkin_isp_inv>;
 994                                                 clock-output-names = "pclk_isp";
 995                                                 #clock-cells = <0>;
 996                                         };
 997
 998                                         /* 7 reserved */
 999
1000                                         clk_vip_div: clk_vip_div {
1001                                                 compatible = "rockchip,rk3188-div-con";
1002                                                 rockchip,bits = <8 5>;
1003                                                 clocks = <&clk_vip>;
1004                                                 clock-output-names = "clk_vip";
1005                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1006                                                 #clock-cells = <0>;
1007                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1008                                         };
1009
1010                                         pclk_vip: pclk_vip_mux {
1011                                                 compatible = "rockchip,rk3188-mux-con";
1012                                                 rockchip,bits = <13 1>;
1013                                                 clocks = <&clk_gates16 13>, <&pclkin_vip_inv>;
1014                                                 clock-output-names = "pclk_vip";
1015                                                 #clock-cells = <0>;
1016                                         };
1017
1018                                         clk_vip: clk_vip_mux {
1019                                                 compatible = "rockchip,rk3188-mux-con";
1020                                                 rockchip,bits = <14 2>;
1021                                                 clocks = <&clk_cpll>, <&xin24m>, <&clk_gpll>, <&xin24m>;
1022                                                 clock-output-names = "clk_vip";
1023                                                 #clock-cells = <0>;
1024                                                 #clock-init-cells = <1>;
1025                                         };
1026                                 };
1027
1028                                 clk_sel_con22: sel-con@0158 {
1029                                         compatible = "rockchip,rk3188-selcon";
1030                                         reg = <0x0158 0x4>;
1031                                         #address-cells = <1>;
1032                                         #size-cells = <1>;
1033
1034                                         clk_isp_div: clk_isp_div {
1035                                                 compatible = "rockchip,rk3188-div-con";
1036                                                 rockchip,bits = <0 6>;
1037                                                 clocks = <&clk_isp>;
1038                                                 clock-output-names = "clk_isp";
1039                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1040                                                 #clock-cells = <0>;
1041                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1042                                         };
1043
1044                                         clk_isp: clk_isp_mux {
1045                                                 compatible = "rockchip,rk3188-mux-con";
1046                                                 rockchip,bits = <6 2>;
1047                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1048                                                 clock-output-names = "clk_isp";
1049                                                 #clock-cells = <0>;
1050                                                 #clock-init-cells = <1>;
1051                                         };
1052                                 };
1053
1054                                 clk_sel_con23: sel-con@015c {
1055                                         compatible = "rockchip,rk3188-selcon";
1056                                         reg = <0x015c 0x4>;
1057                                         #address-cells = <1>;
1058                                         #size-cells = <1>;
1059
1060                                         clk_edp_div: clk_edp_div {
1061                                                 compatible = "rockchip,rk3188-div-con";
1062                                                 rockchip,bits = <0 6>;
1063                                                 clocks = <&clk_edp>;
1064                                                 clock-output-names = "clk_edp";
1065                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1066                                                 #clock-cells = <0>;
1067                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1068                                         };
1069
1070                                         clk_edp: clk_edp_mux {
1071                                                 compatible = "rockchip,rk3188-mux-con";
1072                                                 rockchip,bits = <6 2>;
1073                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1074                                                 clock-output-names = "clk_edp";
1075                                                 #clock-cells = <0>;
1076                                         };
1077
1078                                         clk_edp_24m: clk_edp_24m_mux {
1079                                                 compatible = "rockchip,rk3188-mux-con";
1080                                                 rockchip,bits = <8 1>;
1081                                                 clocks = <&xin24m>, <&dummy>;
1082                                                 clock-output-names = "clk_edp_24m";
1083                                                 #clock-cells = <0>;
1084                                         };
1085                                 };
1086
1087                                 /* sel[24]: reserved */
1088
1089                                 clk_sel_con25: sel-con@0164 {
1090                                         compatible = "rockchip,rk3188-selcon";
1091                                         reg = <0x0164 0x4>;
1092                                         #address-cells = <1>;
1093                                         #size-cells = <1>;
1094
1095                                         clk_tsadc: clk_tsadc_div {
1096                                                 compatible = "rockchip,rk3188-div-con";
1097                                                 rockchip,bits = <0 6>;
1098                                                 clocks = <&clk_32k_mux>;
1099                                                 clock-output-names = "clk_tsadc";
1100                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1101                                                 #clock-cells = <0>;
1102                                         };
1103
1104                                         clk_saradc: clk_saradc_div {
1105                                                 compatible = "rockchip,rk3188-div-con";
1106                                                 rockchip,bits = <8 8>;
1107                                                 clocks = <&xin24m>;
1108                                                 clock-output-names = "clk_saradc";
1109                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1110                                                 #clock-cells = <0>;
1111                                         };
1112                                 };
1113
1114                                 clk_sel_con26: sel-con@0168 {
1115                                         compatible = "rockchip,rk3188-selcon";
1116                                         reg = <0x0168 0x4>;
1117                                         #address-cells = <1>;
1118                                         #size-cells = <1>;
1119
1120                                         /* 7:0 reserved */
1121
1122                                         hsic_usb_480m: hsic_usb_480m_mux {
1123                                                 compatible = "rockchip,rk3188-mux-con";
1124                                                 rockchip,bits = <8 1>;
1125                                                 clocks = <&usbotg_480m_out>, <&dummy>;
1126                                                 clock-output-names = "hsic_usb_480m";
1127                                                 #clock-cells = <0>;
1128                                         };
1129
1130                                         /* 11:9 reserved */
1131
1132                                         hsicphy_480m: hsicphy_480m_mux {
1133                                                 compatible = "rockchip,rk3188-mux-con";
1134                                                 rockchip,bits = <12 2>;
1135                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&hsic_usb_480m>, <&hsic_usb_480m>;
1136                                                 clock-output-names = "hsicphy_480m";
1137                                                 #clock-cells = <0>;
1138                                         };
1139                                 };
1140
1141                                 clk_sel_con27: sel-con@016c {
1142                                         compatible = "rockchip,rk3188-selcon";
1143                                         reg = <0x016c 0x4>;
1144                                         #address-cells = <1>;
1145                                         #size-cells = <1>;
1146
1147                                         i2s_pll_div: i2s_pll_div {
1148                                                 compatible = "rockchip,rk3188-div-con";
1149                                                 rockchip,bits = <0 7>;
1150                                                 clocks = <&i2s_pll>;
1151                                                 clock-output-names = "i2s_pll";
1152                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1153                                                 #clock-cells = <0>;
1154                                                 rockchip,clkops-idx =
1155                                                         <CLKOPS_RATE_MUX_DIV>;
1156                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1157                                         };
1158
1159                                         /* 7 reserved */
1160
1161                                         clk_i2s: clk_i2s_mux {
1162                                                 compatible = "rockchip,rk3188-mux-con";
1163                                                 rockchip,bits = <8 2>;
1164                                                 clocks = <&i2s_pll>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
1165                                                 clock-output-names = "clk_i2s";
1166                                                 #clock-cells = <0>;
1167                                                 rockchip,clkops-idx =
1168                                                         <CLKOPS_RATE_RK3288_I2S>;
1169                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1170                                         };
1171
1172                                         /* 11:10 reserved */
1173
1174                                         i2s_pll: i2s_pll_mux {
1175                                                 compatible = "rockchip,rk3188-mux-con";
1176                                                 rockchip,bits = <12 1>;
1177                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1178                                                 clock-output-names = "i2s_pll";
1179                                                 #clock-cells = <0>;
1180                                                 #clock-init-cells = <1>;
1181                                         };
1182
1183                                         /* 14:13 reserved */
1184
1185                                         i2s_out: i2s_out_mux {
1186                                                 compatible = "rockchip,rk3188-mux-con";
1187                                                 rockchip,bits = <15 1>;
1188                                                 clocks = <&clk_i2s>, <&xin12m>;
1189                                                 clock-output-names = "i2s_out";
1190                                                 #clock-cells = <0>;
1191                                         };
1192                                 };
1193
1194                                 clk_sel_con28: sel-con@0170 {
1195                                         compatible = "rockchip,rk3188-selcon";
1196                                         reg = <0x0170 0x4>;
1197                                         #address-cells = <1>;
1198                                         #size-cells = <1>;
1199
1200                                         i2s_frac: i2s_frac {
1201                                                 compatible = "rockchip,rk3188-frac-con";
1202                                                 clocks = <&i2s_pll>;
1203                                                 clock-output-names = "i2s_frac";
1204                                                 /* numerator    denominator */
1205                                                 rockchip,bits = <0 32>;
1206                                                 rockchip,clkops-idx =
1207                                                         <CLKOPS_RATE_FRAC>;
1208                                                 #clock-cells = <0>;
1209                                         };
1210                                 };
1211
1212                                 /* sel[30:29] reserved */
1213
1214                                 clk_sel_con31: sel-con@017c {
1215                                         compatible = "rockchip,rk3188-selcon";
1216                                         reg = <0x017c 0x4>;
1217                                         #address-cells = <1>;
1218                                         #size-cells = <1>;
1219
1220
1221                                         spdif_8ch_pll_div: spdif_8ch_pll_div {
1222                                                 compatible = "rockchip,rk3188-div-con";
1223                                                 rockchip,bits = <0 7>;
1224                                                 clocks = <&spdif_8ch_pll>;
1225                                                 clock-output-names = "spdif_8ch_pll";
1226                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1227                                                 #clock-cells = <0>;
1228                                                 rockchip,clkops-idx =
1229                                                         <CLKOPS_RATE_MUX_DIV>;
1230                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1231                                         };
1232
1233                                         /* 7 reserved */
1234
1235                                         clk_spidf_8ch: clk_spidf_8ch_mux {
1236                                                 compatible = "rockchip,rk3188-mux-con";
1237                                                 rockchip,bits = <8 2>;
1238                                                 clocks = <&spdif_8ch_pll>, <&spdif_8ch_frac>, <&i2s_clkin>, <&xin12m>;
1239                                                 clock-output-names = "clk_spidf_8ch";
1240                                                 #clock-cells = <0>;
1241                                                 rockchip,clkops-idx =
1242                                                         <CLKOPS_RATE_RK3288_I2S>;
1243                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1244                                         };
1245
1246                                         /* 11:10 reserved */
1247
1248                                         spdif_8ch_pll: spdif_8ch_pll_mux {
1249                                                 compatible = "rockchip,rk3188-mux-con";
1250                                                 rockchip,bits = <12 1>;
1251                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1252                                                 clock-output-names = "spdif_8ch_pll";
1253                                                 #clock-cells = <0>;
1254                                                 #clock-init-cells = <1>;
1255                                         };
1256
1257                                         /* 15:13 reserved */
1258                                 };
1259
1260                                 clk_sel_con32: sel-con@0180 {
1261                                         compatible = "rockchip,rk3188-selcon";
1262                                         reg = <0x0180 0x4>;
1263                                         #address-cells = <1>;
1264                                         #size-cells = <1>;
1265
1266                                         spdif_8ch_frac: spdif_8ch_frac {
1267                                                 compatible = "rockchip,rk3188-frac-con";
1268                                                 clocks = <&spdif_8ch_pll>;
1269                                                 clock-output-names = "spdif_8ch_frac";
1270                                                 /* numerator    denominator */
1271                                                 rockchip,bits = <0 32>;
1272                                                 rockchip,clkops-idx =
1273                                                         <CLKOPS_RATE_FRAC>;
1274                                                 #clock-cells = <0>;
1275                                         };
1276                                 };
1277
1278                                 clk_sel_con33: sel-con@0184 {
1279                                         compatible = "rockchip,rk3188-selcon";
1280                                         reg = <0x0184 0x4>;
1281                                         #address-cells = <1>;
1282                                         #size-cells = <1>;
1283
1284                                         clk_uart0_pll_div: clk_uart0_pll_div {
1285                                                 compatible = "rockchip,rk3188-div-con";
1286                                                 rockchip,bits = <0 7>;
1287                                                 clocks = <&clk_uart0_pll>;
1288                                                 clock-output-names = "clk_uart0_pll";
1289                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1290                                                 #clock-cells = <0>;
1291                                                 rockchip,clkops-idx =
1292                                                         <CLKOPS_RATE_MUX_DIV>;
1293                                         };
1294
1295                                         /* 7: reserved */
1296
1297                                         clk_uart0: clk_uart0_mux {
1298                                                 compatible = "rockchip,rk3188-mux-con";
1299                                                 rockchip,bits = <8 2>;
1300                                                 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>, <&xin24m>;
1301                                                 clock-output-names = "clk_uart0";
1302                                                 #clock-cells = <0>;
1303                                                 rockchip,clkops-idx =
1304                                                         <CLKOPS_RATE_RK3288_I2S>;
1305                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1306                                         };
1307
1308                                         /* 11:10 reserved */
1309
1310                                         clk_uart0_pll: clk_uart0_pll_mux {
1311                                                 compatible = "rockchip,rk3188-mux-con";
1312                                                 rockchip,bits = <12 2>;
1313                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
1314                                                 clock-output-names = "clk_uart0_pll";
1315                                                 #clock-cells = <0>;
1316                                         };
1317                                 };
1318
1319                                 clk_sel_con34: sel-con@0188 {
1320                                         compatible = "rockchip,rk3188-selcon";
1321                                         reg = <0x0188 0x4>;
1322                                         #address-cells = <1>;
1323                                         #size-cells = <1>;
1324
1325                                         uart0_frac: uart0_frac {
1326                                                 compatible = "rockchip,rk3188-frac-con";
1327                                                 clocks = <&clk_uart0_pll>;
1328                                                 clock-output-names = "uart0_frac";
1329                                                 /* numerator    denominator */
1330                                                 rockchip,bits = <0 32>;
1331                                                 rockchip,clkops-idx =
1332                                                         <CLKOPS_RATE_FRAC>;
1333                                                 #clock-cells = <0>;
1334                                         };
1335                                 };
1336
1337                                 clk_sel_con35: sel-con@018c {
1338                                         compatible = "rockchip,rk3188-selcon";
1339                                         reg = <0x018c 0x4>;
1340                                         #address-cells = <1>;
1341                                         #size-cells = <1>;
1342
1343                                         uart1_div: uart1_div {
1344                                                 compatible = "rockchip,rk3188-div-con";
1345                                                 rockchip,bits = <0 7>;
1346                                                 clocks = <&clk_uart_pll>;
1347                                                 clock-output-names = "uart1_div";
1348                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1349                                                 #clock-cells = <0>;
1350                                         };
1351
1352                                         /* 7 reserved */
1353
1354                                         clk_uart1: clk_uart1_mux {
1355                                                 compatible = "rockchip,rk3188-mux-con";
1356                                                 rockchip,bits = <8 2>;
1357                                                 clocks = <&uart1_div>, <&uart1_frac>, <&xin24m>, <&xin24m>;
1358                                                 clock-output-names = "clk_uart1";
1359                                                 #clock-cells = <0>;
1360                                                 rockchip,clkops-idx =
1361                                                         <CLKOPS_RATE_RK3288_I2S>;
1362                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1363                                         };
1364
1365                                         /* 11:10 reserved */
1366
1367                                         clk_uart_pll: clk_uart_pll_mux {
1368                                                 compatible = "rockchip,rk3188-mux-con";
1369                                                 rockchip,bits = <12 1>;
1370                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1371                                                 clock-output-names = "clk_uart_pll";
1372                                                 #clock-cells = <0>;
1373                                         };
1374
1375                                         /* 14:13 reserved */
1376                                 };
1377
1378                                 clk_sel_con36: sel-con@0190 {
1379                                         compatible = "rockchip,rk3188-selcon";
1380                                         reg = <0x0190 0x4>;
1381                                         #address-cells = <1>;
1382                                         #size-cells = <1>;
1383
1384                                         uart1_frac: uart1_frac {
1385                                                 compatible = "rockchip,rk3188-frac-con";
1386                                                 clocks = <&uart1_div>;
1387                                                 clock-output-names = "uart1_frac";
1388                                                 /* numerator    denominator */
1389                                                 rockchip,bits = <0 32>;
1390                                                 rockchip,clkops-idx =
1391                                                         <CLKOPS_RATE_FRAC>;
1392                                                 #clock-cells = <0>;
1393                                         };
1394                                 };
1395
1396                                 clk_sel_con37: sel-con@0194 {
1397                                         compatible = "rockchip,rk3188-selcon";
1398                                         reg = <0x0194 0x4>;
1399                                         #address-cells = <1>;
1400                                         #size-cells = <1>;
1401
1402                                         uart2_div: uart2_div {
1403                                                 compatible = "rockchip,rk3188-div-con";
1404                                                 rockchip,bits = <0 7>;
1405                                                 clocks = <&clk_uart_pll>;
1406                                                 clock-output-names = "uart2_div";
1407                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1408                                                 #clock-cells = <0>;
1409                                         };
1410
1411                                         /* 7 reserved */
1412
1413                                         clk_uart2: clk_uart2_mux {
1414                                                 compatible = "rockchip,rk3188-mux-con";
1415                                                 rockchip,bits = <8 1>;
1416                                                 clocks = <&uart2_div>, <&xin24m>;
1417                                                 clock-output-names = "clk_uart2";
1418                                                 #clock-cells = <0>;
1419                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1420                                         };
1421                                 };
1422
1423                                 /* sel[38] reserved */
1424
1425                                 clk_sel_con39: sel-con@019c {
1426                                         compatible = "rockchip,rk3188-selcon";
1427                                         reg = <0x019c 0x4>;
1428                                         #address-cells = <1>;
1429                                         #size-cells = <1>;
1430
1431                                         uart3_div: uart3_div {
1432                                                 compatible = "rockchip,rk3188-div-con";
1433                                                 rockchip,bits = <0 7>;
1434                                                 clocks = <&clk_uart_pll>;
1435                                                 clock-output-names = "uart3_div";
1436                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1437                                                 #clock-cells = <0>;
1438                                         };
1439
1440                                         /* 7 reserved */
1441
1442                                         clk_uart3: clk_uart3_mux {
1443                                                 compatible = "rockchip,rk3188-mux-con";
1444                                                 rockchip,bits = <8 2>;
1445                                                 clocks = <&uart3_div>, <&uart3_frac>, <&xin24m>, <&xin24m>;
1446                                                 clock-output-names = "clk_uart3";
1447                                                 #clock-cells = <0>;
1448                                                 rockchip,clkops-idx =
1449                                                         <CLKOPS_RATE_RK3288_I2S>;
1450                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1451                                         };
1452                                 };
1453
1454                                 clk_sel_con40: sel-con@01a0 {
1455                                         compatible = "rockchip,rk3188-selcon";
1456                                         reg = <0x01a0 0x4>;
1457                                         #address-cells = <1>;
1458                                         #size-cells = <1>;
1459
1460                                         uart3_frac: uart3_frac {
1461                                                 compatible = "rockchip,rk3188-frac-con";
1462                                                 clocks = <&uart3_div>;
1463                                                 clock-output-names = "uart3_frac";
1464                                                 /* numerator    denominator */
1465                                                 rockchip,bits = <0 32>;
1466                                                 rockchip,clkops-idx =
1467                                                         <CLKOPS_RATE_FRAC>;
1468                                                 #clock-cells = <0>;
1469                                         };
1470                                 };
1471
1472                                 clk_sel_con41: sel-con@01a4 {
1473                                         compatible = "rockchip,rk3188-selcon";
1474                                         reg = <0x01a4 0x4>;
1475                                         #address-cells = <1>;
1476                                         #size-cells = <1>;
1477
1478                                         uart4_div: uart4_div {
1479                                                 compatible = "rockchip,rk3188-div-con";
1480                                                 rockchip,bits = <0 7>;
1481                                                 clocks = <&clk_uart_pll>;
1482                                                 clock-output-names = "uart4_div";
1483                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1484                                                 #clock-cells = <0>;
1485                                         };
1486
1487                                         /* 7 reserved */
1488
1489                                         clk_uart4: clk_uart4_mux {
1490                                                 compatible = "rockchip,rk3188-mux-con";
1491                                                 rockchip,bits = <8 2>;
1492                                                 clocks = <&uart4_div>, <&uart4_frac>, <&xin24m>, <&xin24m>;
1493                                                 clock-output-names = "clk_uart4";
1494                                                 #clock-cells = <0>;
1495                                                 rockchip,clkops-idx =
1496                                                         <CLKOPS_RATE_RK3288_I2S>;
1497                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1498                                         };
1499                                 };
1500
1501                                 clk_sel_con42: sel-con@01a8 {
1502                                         compatible = "rockchip,rk3188-selcon";
1503                                         reg = <0x01a8 0x4>;
1504                                         #address-cells = <1>;
1505                                         #size-cells = <1>;
1506
1507                                         uart4_frac: uart4_frac {
1508                                                 compatible = "rockchip,rk3188-frac-con";
1509                                                 clocks = <&uart4_div>;
1510                                                 clock-output-names = "uart4_frac";
1511                                                 /* numerator    denominator */
1512                                                 rockchip,bits = <0 32>;
1513                                                 rockchip,clkops-idx =
1514                                                         <CLKOPS_RATE_FRAC>;
1515                                                 #clock-cells = <0>;
1516                                         };
1517                                 };
1518
1519                                 clk_sel_con43: sel-con@01ac {
1520                                         compatible = "rockchip,rk3188-selcon";
1521                                         reg = <0x01ac 0x4>;
1522                                         #address-cells = <1>;
1523                                         #size-cells = <1>;
1524
1525                                         clk_mac_pll_div: clk_mac_pll_div {
1526                                                 compatible = "rockchip,rk3188-div-con";
1527                                                 rockchip,bits = <0 5>;
1528                                                 clocks = <&clk_mac_pll>;
1529                                                 clock-output-names = "clk_mac_pll";
1530                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1531                                                 #clock-cells = <0>;
1532                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1533                                         };
1534
1535                                         /* 5 reserved */
1536
1537                                         clk_mac_pll: clk_mac_pll_mux {
1538                                                 compatible = "rockchip,rk3188-mux-con";
1539                                                 rockchip,bits = <6 2>;
1540                                                 clocks = <&clk_npll>, <&clk_cpll>, <&clk_gpll>, <&clk_gpll>;
1541                                                 clock-output-names = "clk_mac_pll";
1542                                                 #clock-cells = <0>;
1543                                         };
1544
1545                                         clk_mac: clk_mac_mux {
1546                                                 compatible = "rockchip,rk3188-mux-con";
1547                                                 rockchip,bits = <8 1>;
1548                                                 clocks = <&clk_mac_pll>, <&gmac_clkin>;
1549                                                 clock-output-names = "clk_mac";
1550                                                 #clock-cells = <0>;
1551                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1552                                                 #clock-init-cells = <1>;
1553                                         };
1554
1555                                         /* 11:9 reserved */
1556
1557                                         /* 12: test_clk: wifi_pll_sel */
1558
1559                                         /* 15:13 reserved */
1560                                 };
1561
1562                                 clk_sel_con44: sel-con@01b0 {
1563                                         compatible = "rockchip,rk3188-selcon";
1564                                         reg = <0x01b0 0x4>;
1565                                         #address-cells = <1>;
1566                                         #size-cells = <1>;
1567
1568                                         /* test_clk: wifi_frac */
1569                                 };
1570
1571                                 clk_sel_con45: sel-con@01b4 {
1572                                         compatible = "rockchip,rk3188-selcon";
1573                                         reg = <0x01b4 0x4>;
1574                                         #address-cells = <1>;
1575                                         #size-cells = <1>;
1576
1577                                         clk_spi0_div: clk_spi0_div {
1578                                                 compatible = "rockchip,rk3188-div-con";
1579                                                 rockchip,bits = <0 7>;
1580                                                 clocks = <&clk_spi0>;
1581                                                 clock-output-names = "clk_spi0";
1582                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1583                                                 #clock-cells = <0>;
1584                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1585                                         };
1586
1587                                         clk_spi0: clk_spi0_mux {
1588                                                 compatible = "rockchip,rk3188-mux-con";
1589                                                 rockchip,bits = <7 1>;
1590                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1591                                                 clock-output-names = "clk_spi0";
1592                                                 #clock-cells = <0>;
1593                                         };
1594
1595                                         clk_spi1_div: clk_spi1_div {
1596                                                 compatible = "rockchip,rk3188-div-con";
1597                                                 rockchip,bits = <8 7>;
1598                                                 clocks = <&clk_spi1>;
1599                                                 clock-output-names = "clk_spi1";
1600                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1601                                                 #clock-cells = <0>;
1602                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1603                                         };
1604
1605                                         clk_spi1: clk_spi1_mux {
1606                                                 compatible = "rockchip,rk3188-mux-con";
1607                                                 rockchip,bits = <15 1>;
1608                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1609                                                 clock-output-names = "clk_spi1";
1610                                                 #clock-cells = <0>;
1611                                         };
1612                                 };
1613
1614                                 clk_sel_con46: sel-con@01b8 {
1615                                         compatible = "rockchip,rk3188-selcon";
1616                                         reg = <0x01b8 0x4>;
1617                                         #address-cells = <1>;
1618                                         #size-cells = <1>;
1619
1620                                         clk_tsp_div: clk_tsp_div {
1621                                                 compatible = "rockchip,rk3188-div-con";
1622                                                 rockchip,bits = <0 5>;
1623                                                 clocks = <&clk_tsp>;
1624                                                 clock-output-names = "clk_tsp";
1625                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1626                                                 #clock-cells = <0>;
1627                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1628                                         };
1629
1630                                         /* 5 reserved */
1631
1632                                         clk_tsp: clk_tsp_mux {
1633                                                 compatible = "rockchip,rk3188-mux-con";
1634                                                 rockchip,bits = <6 2>;
1635                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1636                                                 clock-output-names = "clk_tsp";
1637                                                 #clock-cells = <0>;
1638                                         };
1639
1640                                         clk_spi2_div: clk_spi2_div {
1641                                                 compatible = "rockchip,rk3188-div-con";
1642                                                 rockchip,bits = <8 7>;
1643                                                 clocks = <&clk_spi2>;
1644                                                 clock-output-names = "clk_spi2";
1645                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1646                                                 #clock-cells = <0>;
1647                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1648                                         };
1649
1650                                         clk_spi2: clk_spi2_mux {
1651                                                 compatible = "rockchip,rk3188-mux-con";
1652                                                 rockchip,bits = <15 1>;
1653                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1654                                                 clock-output-names = "clk_spi2";
1655                                                 #clock-cells = <0>;
1656                                         };
1657                                 };
1658
1659                                 clk_sel_con47: sel-con@01bc {
1660                                         compatible = "rockchip,rk3188-selcon";
1661                                         reg = <0x01bc 0x4>;
1662                                         #address-cells = <1>;
1663                                         #size-cells = <1>;
1664
1665                                         clk_nandc0_div: clk_nandc0_div {
1666                                                 compatible = "rockchip,rk3188-div-con";
1667                                                 rockchip,bits = <0 5>;
1668                                                 clocks = <&clk_nandc0>;
1669                                                 clock-output-names = "clk_nandc0";
1670                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1671                                                 #clock-cells = <0>;
1672                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1673                                         };
1674
1675                                         /* 6:5 reserved */
1676
1677                                         clk_nandc0: clk_nandc0_mux {
1678                                                 compatible = "rockchip,rk3188-mux-con";
1679                                                 rockchip,bits = <7 1>;
1680                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1681                                                 clock-output-names = "clk_nandc0";
1682                                                 #clock-cells = <0>;
1683                                         };
1684
1685                                         /* 12:8 test_div */
1686
1687                                         /* 15:13 reserved */
1688                                 };
1689
1690                                 clk_sel_con48: sel-con@01c0 {
1691                                         compatible = "rockchip,rk3188-selcon";
1692                                         reg = <0x01c0 0x4>;
1693                                         #address-cells = <1>;
1694                                         #size-cells = <1>;
1695
1696                                         clk_sdio0_div: clk_sdio0_div {
1697                                                 compatible = "rockchip,rk3188-div-con";
1698                                                 rockchip,bits = <0 7>;
1699                                                 clocks = <&clk_sdio0>;
1700                                                 clock-output-names = "clk_sdio0";
1701                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1702                                                 #clock-cells = <0>;
1703                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1704                                         };
1705
1706                                         /* 7 reserved */
1707
1708                                         clk_sdio0: clk_sdio0_mux {
1709                                                 compatible = "rockchip,rk3188-mux-con";
1710                                                 rockchip,bits = <8 2>;
1711                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1712                                                 clock-output-names = "clk_sdio0";
1713                                                 #clock-cells = <0>;
1714                                         };
1715
1716                                         /* 15:10 reserved */
1717                                 };
1718
1719                                 /* sel[49] reserved */
1720
1721                                 clk_sel_con50: sel-con@01c8 {
1722                                         compatible = "rockchip,rk3188-selcon";
1723                                         reg = <0x01c8 0x4>;
1724                                         #address-cells = <1>;
1725                                         #size-cells = <1>;
1726
1727                                         clk_sdmmc0_div: clk_sdmmc0_div {
1728                                                 compatible = "rockchip,rk3188-div-con";
1729                                                 rockchip,bits = <0 7>;
1730                                                 clocks = <&clk_sdmmc0>;
1731                                                 clock-output-names = "clk_sdmmc0";
1732                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1733                                                 #clock-cells = <0>;
1734                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1735                                         };
1736
1737                                         /* 7 reserved */
1738
1739                                         clk_sdmmc0: clk_sdmmc0_mux {
1740                                                 compatible = "rockchip,rk3188-mux-con";
1741                                                 rockchip,bits = <8 2>;
1742                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1743                                                 clock-output-names = "clk_sdmmc0";
1744                                                 #clock-cells = <0>;
1745                                         };
1746
1747                                         /* 15:10 reserved */
1748                                 };
1749
1750                                 clk_sel_con51: sel-con@01cc {
1751                                         compatible = "rockchip,rk3188-selcon";
1752                                         reg = <0x01cc 0x4>;
1753                                         #address-cells = <1>;
1754                                         #size-cells = <1>;
1755
1756                                         clk_emmc_div: clk_emmc_div {
1757                                                 compatible = "rockchip,rk3188-div-con";
1758                                                 rockchip,bits = <0 7>;
1759                                                 clocks = <&clk_emmc>;
1760                                                 clock-output-names = "clk_emmc";
1761                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1762                                                 #clock-cells = <0>;
1763                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1764                                         };
1765
1766                                         /* 7 reserved */
1767
1768                                         clk_emmc: clk_emmc_mux {
1769                                                 compatible = "rockchip,rk3188-mux-con";
1770                                                 rockchip,bits = <8 2>;
1771                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1772                                                 clock-output-names = "clk_emmc";
1773                                                 #clock-cells = <0>;
1774                                         };
1775
1776                                         /* 15:10 reserved */
1777                                 };
1778
1779                                 clk_sel_con52: sel-con@01d0 {
1780                                         compatible = "rockchip,rk3188-selcon";
1781                                         reg = <0x01d0 0x4>;
1782                                         #address-cells = <1>;
1783                                         #size-cells = <1>;
1784
1785                                         clk_sfc_div: clk_sfc_div {
1786                                                 compatible = "rockchip,rk3188-div-con";
1787                                                 rockchip,bits = <0 5>;
1788                                                 clocks = <&clk_sfc>;
1789                                                 clock-output-names = "clk_sfc";
1790                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1791                                                 #clock-cells = <0>;
1792                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1793                                         };
1794
1795                                         /* 6:5 reserved */
1796
1797                                         clk_sfc: clk_sfc_mux {
1798                                                 compatible = "rockchip,rk3188-mux-con";
1799                                                 rockchip,bits = <7 1>;
1800                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1801                                                 clock-output-names = "clk_sfc";
1802                                                 #clock-cells = <0>;
1803                                         };
1804
1805                                         /* 15:8 reserved */
1806                                 };
1807
1808                                 clk_sel_con53: sel-con@01d4 {
1809                                         compatible = "rockchip,rk3188-selcon";
1810                                         reg = <0x01d4 0x4>;
1811                                         #address-cells = <1>;
1812                                         #size-cells = <1>;
1813
1814                                         i2s_2ch_pll_div: i2s_2ch_pll_div {
1815                                                 compatible = "rockchip,rk3188-div-con";
1816                                                 rockchip,bits = <0 7>;
1817                                                 clocks = <&i2s_2ch_pll>;
1818                                                 clock-output-names = "i2s_2ch_pll";
1819                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1820                                                 #clock-cells = <0>;
1821                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1822                                         };
1823
1824                                         /* 7 reserved */
1825
1826                                         clk_i2s_2ch: clk_i2s_2ch_mux {
1827                                                 compatible = "rockchip,rk3188-mux-con";
1828                                                 rockchip,bits = <8 2>;
1829                                                 clocks = <&i2s_2ch_pll>, <&i2s_2ch_frac>, <&dummy>, <&xin12m>;
1830                                                 clock-output-names = "clk_i2s_2ch";
1831                                                 #clock-cells = <0>;
1832                                                 rockchip,clkops-idx =
1833                                                         <CLKOPS_RATE_RK3288_I2S>;
1834                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1835                                         };
1836
1837                                         /* 11:10 reserved */
1838
1839                                         i2s_2ch_pll: i2s_2ch_pll_mux {
1840                                                 compatible = "rockchip,rk3188-mux-con";
1841                                                 rockchip,bits = <12 1>;
1842                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1843                                                 clock-output-names = "i2s_2ch_pll";
1844                                                 #clock-cells = <0>;
1845                                                 #clock-init-cells = <1>;
1846                                         };
1847
1848                                 };
1849
1850                                 clk_sel_con54: sel-con@01d8 {
1851                                         compatible = "rockchip,rk3188-selcon";
1852                                         reg = <0x01d8 0x4>;
1853                                         #address-cells = <1>;
1854                                         #size-cells = <1>;
1855
1856                                         i2s_2ch_frac: i2s_2ch_frac {
1857                                                 compatible = "rockchip,rk3188-frac-con";
1858                                                 clocks = <&i2s_2ch_pll>;
1859                                                 clock-output-names = "i2s_2ch_frac";
1860                                                 /* numerator    denominator */
1861                                                 rockchip,bits = <0 32>;
1862                                                 rockchip,clkops-idx =
1863                                                         <CLKOPS_RATE_FRAC>;
1864                                                 #clock-cells = <0>;
1865                                         };
1866                                 };
1867
1868                                 clk_sel_con55: sel-con@01dc {
1869                                         compatible = "rockchip,rk3188-selcon";
1870                                         reg = <0x01dc 0x4>;
1871                                         #address-cells = <1>;
1872                                         #size-cells = <1>;
1873
1874                                         clk_hdcp_div: clk_hdcp_div {
1875                                                 compatible = "rockchip,rk3188-div-con";
1876                                                 rockchip,bits = <0 6>;
1877                                                 clocks = <&clk_hdcp>;
1878                                                 clock-output-names = "clk_hdcp";
1879                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1880                                                 #clock-cells = <0>;
1881                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1882                                         };
1883
1884                                         clk_hdcp: clk_hdcp_mux {
1885                                                 compatible = "rockchip,rk3188-mux-con";
1886                                                 rockchip,bits = <6 2>;
1887                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1888                                                 clock-output-names = "clk_hdcp";
1889                                                 #clock-cells = <0>;
1890                                         };
1891                                 };
1892                         };
1893
1894                         /* Gate control regs */
1895                         clk_gate_cons {
1896                                 compatible = "rockchip,rk-gate-cons";
1897                                 #address-cells = <1>;
1898                                 #size-cells = <1>;
1899                                 ranges;
1900
1901                                 clk_gates0: gate-clk@0200 {
1902                                         compatible = "rockchip,rk3188-gate-clk";
1903                                         reg = <0x0200 0x4>;
1904                                         clocks =
1905                                                 <&dummy>,       <&dummy>,
1906                                                 <&dummy>,       <&dummy>,
1907
1908                                                 <&dummy>,       <&dummy>,
1909                                                 <&dummy>,       <&dummy>,
1910
1911                                                 <&clk_gpll>,    <&clk_apllb>,
1912                                                 <&clk_aplll>,   <&dummy>,
1913
1914                                                 <&aclk_cci>,    <&clkin_trace>,
1915                                                 <&dummy>,       <&dummy>;
1916
1917                                         clock-output-names =
1918                                                 "reserved",     "reserved",/* core_b_apll core_b_gpll */
1919                                                 "reserved",     "reserved",
1920
1921                                                 "reserved",     "reserved",/* core_l_apll core_l_gpll */
1922                                                 "reserved",     "reserved",
1923
1924                                                 "g_clk_cs_gpll",        "g_clk_cs_apllb",
1925                                                 "g_clk_cs_aplll",       "reserved",
1926
1927                                                 "aclk_cci",     "clkin_trace",
1928                                                 "reserved",     "reserved";
1929
1930                                         #clock-cells = <1>;
1931                                 };
1932
1933                                 clk_gates1: gate-clk@0204 {
1934                                         compatible = "rockchip,rk3188-gate-clk";
1935                                         reg = <0x0204 0x4>;
1936                                         clocks =
1937                                                 <&aclk_bus>,    <&hclk_bus>,
1938                                                 <&pclk_bus>,    <&fclk_mcu>,
1939
1940                                                 <&dummy>,       <&dummy>,
1941                                                 <&dummy>,       <&dummy>,
1942
1943                                                 <&dummy>,       <&dummy>,
1944                                                 <&clk_gpll>,    <&clk_cpll>,
1945
1946                                                 <&dummy>,       <&dummy>,
1947                                                 <&dummy>,       <&dummy>;
1948
1949                                         clock-output-names =
1950                                                 "aclk_bus",     "hclk_bus",
1951                                                 "pclk_bus",     "fclk_mcu",
1952
1953                                                 "reserved",     "reserved",
1954                                                 "reserved",     "reserved",
1955
1956                                                 "reserved",     "reserved",/* ddr_dpll  ddr_gpll */
1957                                                 "aclk_bus_gpll",        "aclk_bus_cpll",
1958
1959                                                 "reserved",     "reserved",
1960                                                 "reserved",     "reserved";
1961
1962                                         #clock-cells = <1>;
1963                                 };
1964
1965                                 clk_gates2: gate-clk@0208 {
1966                                         compatible = "rockchip,rk3188-gate-clk";
1967                                         reg = <0x0208 0x4>;
1968                                         clocks =
1969                                                 <&clk_uart0_pll>,       <&uart0_frac>,
1970                                                 <&uart1_div>,   <&uart1_frac>,
1971
1972                                                 <&uart2_div>,   <&dummy>,
1973                                                 <&uart3_div>,   <&uart3_frac>,
1974
1975                                                 <&uart4_div>,   <&uart4_frac>,
1976                                                 <&dummy>,       <&dummy>,
1977
1978                                                 <&dummy>,       <&dummy>,
1979                                                 <&dummy>,       <&dummy>;
1980
1981                                         clock-output-names =
1982                                                 "clk_uart0_pll",        "uart0_frac",
1983                                                 "uart1_div",    "uart1_frac",
1984
1985                                                 "uart2_div",    "reserved",
1986                                                 "uart3_div",    "uart3_frac",
1987
1988                                                 "uart4_div",    "uart4_frac",
1989                                                 "reserved",     "reserved",
1990
1991                                                 "reserved",     "reserved",
1992                                                 "reserved",     "reserved";
1993
1994                                         #clock-cells = <1>;
1995                                 };
1996
1997                                 clk_gates3: gate-clk@020c {
1998                                         compatible = "rockchip,rk3188-gate-clk";
1999                                         reg = <0x020c 0x4>;
2000                                         clocks =
2001                                                 <&aclk_peri>,   <&dummy>,
2002                                                 <&hclk_peri>,   <&pclk_peri>,
2003
2004                                                 <&clk_mac_pll>, <&clk_tsadc>,
2005                                                 <&clk_saradc>,  <&clk_spi0>,
2006
2007                                                 <&clk_spi1>,    <&clk_spi2>,
2008                                                 <&dummy>,       <&dummy>,
2009
2010                                                 <&dummy>,       <&dummy>,
2011                                                 <&dummy>,       <&dummy>;
2012
2013                                         clock-output-names =
2014                                                 "aclk_peri",    "reserved", /* bit1: aclk_peri */
2015                                                 "hclk_peri",    "pclk_peri",
2016
2017                                                 "clk_mac_pll",  "clk_tsadc",
2018                                                 "clk_saradc",   "clk_spi0",
2019
2020                                                 "clk_spi1",     "clk_spi2",
2021                                                 "reserved",     "reserved",
2022
2023                                                 "reserved",     "reserved",
2024                                                 "reserved",     "reserved";
2025
2026                                         #clock-cells = <1>;
2027                                 };
2028
2029                                 clk_gates4: gate-clk@0210 {
2030                                         compatible = "rockchip,rk3188-gate-clk";
2031                                         reg = <0x0210 0x4>;
2032                                         clocks =
2033                                                 <&aclk_vio0>,   <&dclk_vop0>,
2034                                                 <&xin24m>,      <&aclk_rga_pre>,
2035
2036                                                 <&clk_rga>,     <&clk_vip>,
2037                                                 <&aclk_vepu>,   <&aclk_vdpu>,
2038
2039                                                 <&dummy>,       <&clk_isp>,
2040                                                 <&dummy>,       <&clk_gpu_core>,
2041
2042                                                 <&xin32k>,      <&xin24m>,
2043                                                 <&xin24m>,      <&dummy>;
2044
2045                                         clock-output-names =
2046                                                 "aclk_vio0",    "dclk_vop0",
2047                                                 "clk_vop0_pwm", "aclk_rga_pre",
2048
2049                                                 "clk_rga",      "clk_vip",
2050                                                 "aclk_vepu",    "aclk_vdpu",
2051
2052                                                 "reserved",     "clk_isp", /* bit8: hclk_vpu */
2053                                                 "reserved",     "clk_gpu_core",
2054
2055                                                 "clk_hdmi_cec", "clk_hdmi_hdcp",
2056                                                 "clk_dsiphy_24m",       "reserved";
2057
2058                                         #clock-cells = <1>;
2059                                 };
2060
2061                                 clk_gates5: gate-clk@0214 {
2062                                         compatible = "rockchip,rk3188-gate-clk";
2063                                         reg = <0x0214 0x4>;
2064                                         clocks =
2065                                                 <&dummy>,       <&clk_hevc_cabac>,
2066                                                 <&clk_hevc_core>,       <&clk_edp>,
2067
2068                                                 <&clk_edp_24m>, <&clk_hdcp>,
2069                                                 <&dummy>,       <&dummy>,
2070
2071                                                 <&aclk_gpu_mem>,        <&aclk_gpu_cfg>,
2072                                                 <&dummy>,       <&dummy>,
2073
2074                                                 <&dummy>,       <&i2s_pll>,
2075                                                 <&i2s_2ch_frac>,        <&clk_i2s_2ch>;
2076
2077                                         clock-output-names =
2078                                                 "reserved",     "clk_hevc_cabac",
2079                                                 "clk_hevc_core",        "clk_edp",
2080
2081                                                 "clk_edp_24m",  "clk_hdcp",
2082                                                 "reserved",     "reserved",
2083
2084                                                 "aclk_gpu_mem", "aclk_gpu_cfg",
2085                                                 "reserved",     "reserved",
2086
2087                                                 "reserved",     "i2s_pll",
2088                                                 "i2s_2ch_frac", "clk_i2s_2ch";
2089
2090                                         #clock-cells = <1>;
2091                                 };
2092
2093                                 clk_gates6: gate-clk@0218 {
2094                                         compatible = "rockchip,rk3188-gate-clk";
2095                                         reg = <0x0218 0x4>;
2096                                         clocks =
2097                                                 <&i2s_out>,     <&i2s_pll>,
2098                                                 <&i2s_frac>,    <&clk_i2s>,
2099
2100                                                 <&spdif_8ch_pll>,       <&spdif_8ch_frac>,
2101                                                 <&clk_spidf_8ch>,       <&clk_sfc>,
2102
2103                                                 <&dummy>,       <&dummy>,
2104                                                 <&dummy>,       <&dummy>,
2105
2106                                                 <&clk_tsp>,     <&dummy>,
2107                                                 <&dummy>,       <&dummy>;
2108
2109                                         clock-output-names =
2110                                                 "i2s_out",      "i2s_pll",
2111                                                 "i2s_frac",     "clk_i2s",
2112
2113                                                 "spdif_8ch_pll",        "spdif_8ch_frac",
2114                                                 "clk_spidf_8ch",        "clk_sfc",
2115
2116                                                 "reserved",     "reserved",
2117                                                 "reserved",     "reserved",
2118
2119                                                 "clk_tsp",      "reserved",
2120                                                 "reserved",     "reserved";/* clk_ddrphy_gate   clk4x_ddrphy_gate */
2121
2122                                         #clock-cells = <1>;
2123                                 };
2124
2125                                 clk_gates7: gate-clk@021c {
2126                                         compatible = "rockchip,rk3188-gate-clk";
2127                                         reg = <0x021c 0x4>;
2128                                         clocks =
2129                                                 <&jtag_clkin>,  <&dummy>,
2130                                                 <&clk_crypto>,  <&xin24m>,
2131
2132                                                 <&dummy>,       <&dummy>,
2133                                                 <&clk_mac>,     <&clk_mac>,
2134
2135                                                 <&clk_nandc0>,  <&pclk_pmu_pre>,
2136                                                 <&xin24m>,      <&xin24m>,
2137
2138                                                 <&dummy>,       <&dummy>,
2139                                                 <&dummy>,       <&dummy>;
2140
2141                                         clock-output-names =
2142                                                 "clk_jtag",     "reserved",/* bit1: test_clk */
2143                                                 "clk_crypto",   "clk_pvtm_pmu",
2144
2145                                                 "reserved",     "reserved",/* clk_mac_rx  clk_mac_tx */
2146                                                 "clk_mac_ref",  "clk_mac_refout",
2147
2148                                                 "clk_nandc0",   "pclk_pmu_pre",
2149                                                 "clk_pvtm_core",        "clk_pvtm_gpu",
2150
2151                                                 "clk_sdmmc0",   "clk_sdio0",
2152                                                 "reserved",     "clk_emmc";
2153
2154                                         #clock-cells = <1>;
2155                                 };
2156
2157                                 clk_gates8: gate-clk@0220 {
2158                                         compatible = "rockchip,rk3188-gate-clk";
2159                                         reg = <0x0220 0x4>;
2160                                         clocks =
2161                                                 <&hsic_usb_480m>,       <&xin24m>,
2162                                                 <&dummy>,       <&dummy>,
2163
2164                                                 <&clk_32k_mux>, <&dummy>,
2165                                                 <&xin12m>,      <&hsicphy_480m>,
2166
2167                                                 <&dummy>,       <&dummy>,
2168                                                 <&dummy>,       <&dummy>,
2169
2170                                                 <&dummy>,       <&dummy>,
2171                                                 <&dummy>,       <&dummy>;
2172
2173                                         clock-output-names =
2174                                                 "hsic_usb_480m",        "clk_otgphy0",
2175                                                 "reserved",     "reserved",
2176
2177                                                 "g_clk_otg_adp",        "reserved",/* bit4: clk_otg_adp */
2178                                                 "hsicphy_12m",  "hsicphy_480m",
2179
2180                                                 "reserved",     "reserved",
2181                                                 "reserved",     "reserved",
2182
2183                                                 "reserved",     "reserved",
2184                                                 "reserved",     "reserved";
2185
2186                                         #clock-cells = <1>;
2187                                 };
2188
2189                                 clk_gates9: gate-clk@0224 {
2190                                         compatible = "rockchip,rk3188-gate-clk";
2191                                         reg = <0x0224 0x4>;
2192                                         clocks =
2193                                                 <&dummy>,       <&dummy>,
2194                                                 <&dummy>,       <&dummy>,
2195
2196                                                 <&dummy>,       <&dummy>,
2197                                                 <&dummy>,       <&dummy>,
2198
2199                                                 <&dummy>,       <&dummy>,
2200                                                 <&dummy>,       <&dummy>,
2201
2202                                                 <&dummy>,       <&dummy>,
2203                                                 <&dummy>,       <&dummy>;
2204
2205                                         clock-output-names =
2206                                                 "reserved",     "reserved",
2207                                                 "reserved",     "reserved",
2208
2209                                                 "reserved",     "reserved",
2210                                                 "reserved",     "reserved",
2211
2212                                                 "reserved",     "reserved",
2213                                                 "reserved",     "reserved",
2214
2215                                                 "reserved",     "reserved",
2216                                                 "reserved",     "reserved";
2217
2218                                         #clock-cells = <1>;
2219                                 };
2220
2221                                 clk_gates10: gate-clk@0228 {
2222                                         compatible = "rockchip,rk3188-gate-clk";
2223                                         reg = <0x0228 0x4>;
2224                                         clocks =
2225                                                 <&dummy>,       <&dummy>,
2226                                                 <&dummy>,       <&dummy>,
2227
2228                                                 <&dummy>,       <&dummy>,
2229                                                 <&dummy>,       <&dummy>,
2230
2231                                                 <&dummy>,       <&dummy>,
2232                                                 <&dummy>,       <&dummy>,
2233
2234                                                 <&dummy>,       <&dummy>,
2235                                                 <&dummy>,       <&dummy>;
2236
2237                                         clock-output-names =
2238                                                 "reserved",     "reserved",
2239                                                 "reserved",     "reserved",
2240
2241                                                 "reserved",     "reserved",
2242                                                 "reserved",     "reserved",
2243
2244                                                 "reserved",     "reserved",
2245                                                 "reserved",     "reserved",
2246
2247                                                 "reserved",     "reserved",
2248                                                 "reserved",     "reserved";
2249
2250                                         #clock-cells = <1>;
2251                                 };
2252
2253                                 clk_gates11: gate-clk@022c {
2254                                         compatible = "rockchip,rk3188-gate-clk";
2255                                         reg = <0x022c 0x4>;
2256                                         clocks =
2257                                                 <&dummy>,       <&dummy>,
2258                                                 <&dummy>,       <&dummy>,
2259
2260                                                 <&dummy>,       <&dummy>,
2261                                                 <&dummy>,       <&dummy>,
2262
2263                                                 <&dummy>,       <&dummy>,
2264                                                 <&dummy>,       <&dummy>,
2265
2266                                                 <&dummy>,       <&dummy>,
2267                                                 <&dummy>,       <&dummy>;
2268
2269                                         clock-output-names =
2270                                                 "reserved",     "reserved",
2271                                                 "reserved",     "reserved",
2272
2273                                                 "reserved",     "reserved",
2274                                                 "reserved",     "reserved",
2275
2276                                                 "reserved",     "reserved",
2277                                                 "reserved",     "reserved",
2278
2279                                                 "reserved",     "reserved",
2280                                                 "reserved",     "reserved";
2281
2282                                         #clock-cells = <1>;
2283                                 };
2284
2285                                 clk_gates12: gate-clk@0230 {
2286                                         compatible = "rockchip,rk3188-gate-clk";
2287                                         reg = <0x0230 0x4>;
2288                                         clocks =
2289                                                 <&pclk_bus>,    <&pclk_bus>,
2290                                                 <&pclk_bus>,    <&pclk_bus>,
2291
2292                                                 <&aclk_bus>,    <&aclk_bus>,
2293                                                 <&aclk_bus>,    <&hclk_bus>,
2294
2295                                                 <&hclk_bus>,    <&hclk_bus>,
2296                                                 <&hclk_bus>,    <&aclk_bus>,
2297
2298                                                 <&aclk_bus>,    <&dummy>,
2299                                                 <&dummy>,       <&dummy>;
2300
2301                                         clock-output-names =
2302                                                 "g_pclk_pwm0",  "g_p_mailbox",
2303                                                 "g_p_i2cpmu",   "g_p_i2caudio",
2304
2305                                                 "g_aclk_intmem",        "g_clk_intmem0",
2306                                                 "g_clk_intmem1",        "g_h_i2s_8ch",
2307
2308                                                 "g_h_i2s_2ch",  "g_hclk_rom",
2309                                                 "g_hclk_spdif", "g_aclk_dmac",
2310
2311                                                 "g_a_strc_sys", "reserved",/* bit13: pclk_ddrupctl */
2312                                                 "reserved",     "reserved";/* bit14: pclk_ddrphy */
2313
2314                                         #clock-cells = <1>;
2315                                 };
2316
2317                                 clk_gates13: gate-clk@0234 {
2318                                         compatible = "rockchip,rk3188-gate-clk";
2319                                         reg = <0x0234 0x4>;
2320                                         clocks =
2321                                                 <&pclk_bus>,    <&pclk_bus>,
2322                                                 <&dummy>,       <&hclk_bus>,
2323
2324                                                 <&hclk_bus>,    <&pclk_bus>,
2325                                                 <&pclk_bus>,    <&clkin_hsadc_tsp>,
2326
2327                                                 <&pclk_bus>,    <&aclk_bus>,
2328                                                 <&hclk_bus>,    <&dummy>,
2329
2330                                                 <&dummy>,       <&dummy>,
2331                                                 <&dummy>,       <&dummy>;
2332
2333                                         clock-output-names =
2334                                                 "g_p_efuse_1024",       "g_p_efuse_256",
2335                                                 "reserved",     "g_mclk_crypto",/* bit2: nclk_ddrupctl */
2336
2337                                                 "g_sclk_crypto",        "g_p_uartdbg",
2338                                                 "g_pclk_pwm1",  "clk_hsadc_tsp",
2339
2340                                                 "g_pclk_sim",   "g_aclk_gic400",
2341                                                 "g_hclk_tsp",   "reserved",
2342
2343                                                 "reserved",     "reserved",
2344                                                 "reserved",     "reserved";
2345
2346                                         #clock-cells = <1>;
2347                                 };
2348
2349                                 clk_gates14: gate-clk@0238 {
2350                                         compatible = "rockchip,rk3188-gate-clk";
2351                                         reg = <0x0238 0x4>;
2352                                         clocks =
2353                                                 <&dummy>,       <&dummy>,
2354                                                 <&dummy>,       <&dummy>,
2355
2356                                                 <&dummy>,       <&dummy>,
2357                                                 <&dummy>,       <&dummy>,
2358
2359                                                 <&dummy>,       <&dummy>,
2360                                                 <&dummy>,       <&dummy>,
2361
2362                                                 <&dummy>,       <&dummy>,
2363                                                 <&dummy>,       <&dummy>;
2364
2365                                         clock-output-names =
2366                                                 "reserved",     "reserved",
2367                                                 "reserved",     "reserved",
2368
2369                                                 "reserved",     "reserved",
2370                                                 "reserved",     "reserved",
2371
2372                                                 "reserved",     "reserved",
2373                                                 "reserved",     "reserved",
2374
2375                                                 "reserved",     "reserved",
2376                                                 "reserved",     "reserved";
2377
2378                                         #clock-cells = <1>;
2379                                 };
2380
2381                                 clk_gates15: gate-clk@023c {
2382                                         compatible = "rockchip,rk3188-gate-clk";
2383                                         reg = <0x023c 0x4>;
2384                                         clocks =
2385                                                 <&dummy>,       <&dummy>,
2386                                                 <&dummy>,       <&dummy>,
2387
2388                                                 <&dummy>,       <&dummy>,
2389                                                 <&dummy>,       <&dummy>,
2390
2391                                                 <&dummy>,       <&dummy>,
2392                                                 <&dummy>,       <&dummy>,
2393
2394                                                 <&dummy>,       <&dummy>,
2395                                                 <&dummy>,       <&dummy>;
2396
2397                                         clock-output-names =
2398                                                 "reserved",     "reserved",/* aclk_video hclk_video */
2399                                                 "reserved",     "reserved",
2400
2401                                                 "reserved",     "reserved",
2402                                                 "reserved",     "reserved",
2403
2404                                                 "reserved",     "reserved",
2405                                                 "reserved",     "reserved",
2406
2407                                                 "reserved",     "reserved",
2408                                                 "reserved",     "reserved";
2409
2410                                         #clock-cells = <1>;
2411                                 };
2412
2413                                 clk_gates16: gate-clk@0240 {
2414                                         compatible = "rockchip,rk3188-gate-clk";
2415                                         reg = <0x0240 0x4>;
2416                                         clocks =
2417                                                 <&clk_gates16 10>,      <&clk_gates16 8>,
2418                                                 <&clk_gates16 9>,       <&clk_gates16 8>,
2419
2420                                                 <&clk_gates16 9>,       <&clk_gates16 9>,
2421                                                 <&clk_gates16 8>,       <&clk_gates16 8>,
2422
2423                                                 <&hclk_vio>,    <&aclk_vio0>,
2424                                                 <&aclk_rga_pre>,        <&clk_gates16 9>,
2425
2426                                                 <&clk_gates16 8>,       <&pclkin_vip>,
2427                                                 <&clk_isp>,     <&dummy>;
2428
2429                                         clock-output-names =
2430                                                 "g_aclk_rga",   "g_hclk_rga",
2431                                                 "g_aclk_iep",   "g_hclk_iep",
2432
2433                                                 "g_aclk_vop_iep",       "g_aclk_vop",
2434                                                 "g_hclk_vop",   "g_h_vio_ahb_arbi",
2435
2436                                                 "g_hclk_vio_noc",       "g_aclk_vio0_noc",
2437                                                 "g_aclk_vio1_noc",      "g_aclk_vip",
2438
2439                                                 "g_hclk_vip",   "g_pclkin_vip",
2440                                                 "g_hclk_isp",   "reserved";
2441
2442                                         #clock-cells = <1>;
2443                                 };
2444
2445                                 clk_gates17: gate-clk@0244 {
2446                                         compatible = "rockchip,rk3188-gate-clk";
2447                                         reg = <0x0244 0x4>;
2448                                         clocks =
2449                                                 <&clk_isp>,     <&dummy>,
2450                                                 <&pclkin_isp>,  <&pclk_vio>,
2451
2452                                                 <&pclk_vio>,    <&dummy>,
2453                                                 <&pclk_vio>,    <&clk_gates16 8>,
2454
2455                                                 <&pclk_vio>,    <&pclk_vio>,
2456                                                 <&clk_gates16 10>,      <&pclk_vio>,
2457
2458                                                 <&clk_gates16 8>,       <&dummy>,
2459                                                 <&dummy>,       <&dummy>;
2460
2461                                         clock-output-names =
2462                                                 "g_aclk_isp",   "reserved",
2463                                                 "g_pclkin_isp", "g_p_mipi_dsi0",
2464
2465                                                 "g_p_mipi_csi", "reserved",
2466                                                 "g_p_hdmi_ctrl",        "g_hclk_vio_h2p",
2467
2468                                                 "g_pclk_vio_h2p",       "g_p_edp_ctrl",
2469                                                 "g_aclk_hdcp",  "g_pclk_hdcp",
2470
2471                                                 "g_h_hdcpmmu",  "reserved",
2472                                                 "reserved",     "reserved";
2473
2474                                         #clock-cells = <1>;
2475                                 };
2476
2477                                 clk_gates18: gate-clk@0248 {
2478                                         compatible = "rockchip,rk3188-gate-clk";
2479                                         reg = <0x0248 0x4>;
2480                                         clocks =
2481                                                 <&dummy>,       <&dummy>,
2482                                                 <&dummy>,       <&dummy>,
2483
2484                                                 <&dummy>,       <&dummy>,
2485                                                 <&dummy>,       <&dummy>,
2486
2487                                                 <&dummy>,       <&dummy>,
2488                                                 <&dummy>,       <&dummy>,
2489
2490                                                 <&dummy>,       <&dummy>,
2491                                                 <&dummy>,       <&dummy>;
2492
2493                                         clock-output-names =
2494                                                 "reserved",     "reserved",/* bit0-1: aclk_gpu_cfg aclk_gpu_mem */
2495                                                 "reserved",     "reserved",/* bit2: clk_gpu_core */
2496
2497                                                 "reserved",     "reserved",
2498                                                 "reserved",     "reserved",
2499
2500                                                 "reserved",     "reserved",
2501                                                 "reserved",     "reserved",
2502
2503                                                 "reserved",     "reserved",
2504                                                 "reserved",     "reserved";
2505
2506                                         #clock-cells = <1>;
2507                                 };
2508
2509                                 clk_gates19: gate-clk@024c {
2510                                         compatible = "rockchip,rk3188-gate-clk";
2511                                         reg = <0x024c 0x4>;
2512                                         clocks =
2513                                                 <&hclk_peri>,   <&pclk_peri>,
2514                                                 <&aclk_peri>,   <&aclk_peri>,
2515
2516                                                 <&pclk_peri>,   <&pclk_peri>,
2517                                                 <&pclk_peri>,   <&pclk_peri>,
2518
2519                                                 <&pclk_peri>,   <&pclk_peri>,
2520                                                 <&pclk_peri>,   <&pclk_peri>,
2521
2522                                                 <&pclk_peri>,   <&pclk_peri>,
2523                                                 <&pclk_peri>,   <&pclk_peri>;
2524
2525                                         clock-output-names =
2526                                                 "g_h_p_axi_matrix",     "g_p_p_axi_matrix",
2527                                                 "g_a_p_axi_matrix",     "g_a_dmac_peri",
2528
2529                                                 "g_pclk_spi0",  "g_pclk_spi1",
2530                                                 "g_pclk_spi2",  "g_pclk_uart0",
2531
2532                                                 "g_pclk_uart1", "g_pclk_uart3",
2533                                                 "g_pclk_uart4", "g_pclk_i2c2",
2534
2535                                                 "g_pclk_i2c3",  "g_pclk_i2c4",
2536                                                 "g_pclk_i2c5",  "g_pclk_saradc";
2537
2538                                         #clock-cells = <1>;
2539                                 };
2540
2541                                 clk_gates20: gate-clk@0250 {
2542                                         compatible = "rockchip,rk3188-gate-clk";
2543                                         reg = <0x0250 0x4>;
2544                                         clocks =
2545                                                 <&pclk_peri>,   <&hclk_peri>,
2546                                                 <&hclk_peri>,   <&hclk_peri>,
2547
2548                                                 <&dummy>,       <&hclk_peri>,
2549                                                 <&hclk_peri>,   <&hclk_peri>,
2550
2551                                                 <&aclk_peri>,   <&hclk_peri>,
2552                                                 <&hclk_peri>,   <&hclk_peri>,
2553
2554                                                 <&dummy>,       <&aclk_peri>,
2555                                                 <&pclk_peri>,   <&aclk_peri>;
2556
2557                                         clock-output-names =
2558                                                 "g_pclk_tsadc", "g_hclk_otg0",
2559                                                 "g_h_pmu_otg0", "g_hclk_host0",
2560
2561                                                 "reserved",     "g_hclk_hsic",
2562                                                 "g_h_usb_peri", "g_h_p_ahb_arbi",
2563
2564                                                 "g_a_peri_niu", "g_h_emem_peri",
2565                                                 "g_h_mmc_peri", "g_hclk_nand0",
2566
2567                                                 "reserved",     "g_aclk_gmac",
2568                                                 "g_pclk_gmac",  "g_hclk_sfc";
2569
2570                                         #clock-cells = <1>;
2571                                 };
2572
2573                                 clk_gates21: gate-clk@0254 {
2574                                         compatible = "rockchip,rk3188-gate-clk";
2575                                         reg = <0x0254 0x4>;
2576                                         clocks =
2577                                                 <&hclk_peri>,   <&hclk_peri>,
2578                                                 <&hclk_peri>,   <&hclk_peri>,
2579
2580                                                 <&aclk_peri>,   <&dummy>,
2581                                                 <&dummy>,       <&dummy>,
2582
2583                                                 <&dummy>,       <&dummy>,
2584                                                 <&dummy>,       <&dummy>,
2585
2586                                                 <&dummy>,       <&dummy>,
2587                                                 <&dummy>,       <&dummy>;
2588
2589                                         clock-output-names =
2590                                                 "g_hclk_sdmmc", "g_hclk_sdio0",
2591                                                 "g_hclk_emmc",  "g_hclk_hsadc",
2592
2593                                                 "g_aclk_peri_mmu",      "reserved",
2594                                                 "reserved",     "reserved",
2595
2596                                                 "reserved",     "reserved",
2597                                                 "reserved",     "reserved",
2598
2599                                                 "reserved",     "reserved",
2600                                                 "reserved",     "reserved";
2601
2602                                         #clock-cells = <1>;
2603                                 };
2604
2605                                 clk_gates22: gate-clk@0258 {
2606                                         compatible = "rockchip,rk3188-gate-clk";
2607                                         reg = <0x0258 0x4>;
2608                                         clocks =
2609                                                 <&dummy>,       <&pclk_alive_pre>,
2610                                                 <&pclk_alive_pre>,      <&pclk_alive_pre>,
2611
2612                                                 <&dummy>,       <&dummy>,
2613                                                 <&dummy>,       <&dummy>,
2614
2615                                                 <&pclk_alive_pre>,      <&pclk_alive_pre>,
2616                                                 <&pclk_vio>,    <&pclk_vio>,
2617
2618                                                 <&pclk_alive_pre>,      <&pclk_alive_pre>,
2619                                                 <&dummy>,       <&dummy>;
2620
2621                                         clock-output-names =
2622                                                 "reserved",     "g_pclk_gpio1",
2623                                                 "g_pclk_gpio2", "g_pclk_gpio3",
2624
2625                                                 "reserved",     "reserved",
2626                                                 "reserved",     "reserved",
2627
2628                                                 "g_pclk_grf",   "g_p_alive_niu",
2629                                                 "g_pclk_dphytx0",       "g_pclk_dphyrx",
2630
2631                                                 "g_pclk_timer0",        "g_pclk_timer1",
2632                                                 "reserved",     "reserved";
2633
2634                                         #clock-cells = <1>;
2635                                 };
2636
2637                                 clk_gates23: gate-clk@025c {
2638                                         compatible = "rockchip,rk3188-gate-clk";
2639                                         reg = <0x025c 0x4>;
2640                                         clocks =
2641                                                 <&pclk_pmu_pre>,        <&pclk_pmu_pre>,
2642                                                 <&pclk_pmu_pre>,        <&pclk_pmu_pre>,
2643
2644                                                 <&pclk_pmu_pre>,        <&pclk_pmu_pre>,
2645                                                 <&dummy>,       <&dummy>,
2646
2647                                                 <&dummy>,       <&dummy>,
2648                                                 <&dummy>,       <&dummy>,
2649
2650                                                 <&dummy>,       <&dummy>,
2651                                                 <&dummy>,       <&dummy>;
2652
2653                                         clock-output-names =
2654                                                 "g_pclk_pmu",   "g_pclk_intmem1",
2655                                                 "g_pclk_pmu_noc",       "g_pclk_sgrf",
2656
2657                                                 "g_pclk_gpio0", "g_pclk_pmugrf",
2658                                                 "reserved",     "reserved",
2659
2660                                                 "reserved",     "reserved",
2661                                                 "reserved",     "reserved",
2662
2663                                                 "reserved",     "reserved",
2664                                                 "reserved",     "reserved";
2665
2666                                         #clock-cells = <1>;
2667                                 };
2668
2669                                 clk_gates24: gate-clk@0260 {
2670                                         compatible = "rockchip,rk3188-gate-clk";
2671                                         reg = <0x0260 0x4>;
2672                                         clocks =
2673                                                 <&xin24m>,      <&xin24m>,
2674                                                 <&xin24m>,      <&xin24m>,
2675
2676                                                 <&xin24m>,      <&xin24m>,
2677                                                 <&xin24m>,      <&xin24m>,
2678
2679                                                 <&xin24m>,      <&xin24m>,
2680                                                 <&xin24m>,      <&xin24m>,
2681
2682                                                 <&dummy>,       <&dummy>,
2683                                                 <&dummy>,       <&dummy>;
2684
2685                                         clock-output-names =
2686                                                 "g_clk_timer0", "g_clk_timer1",
2687                                                 "g_clk_timer2", "g_clk_timer3",
2688
2689                                                 "g_clk_timer4", "g_clk_timer5",
2690                                                 "g_clk_timer10",        "g_clk_timer11",
2691
2692                                                 "g_clk_timer12",        "g_clk_timer13",
2693                                                 "g_clk_timer14",        "g_clk_timer15",
2694
2695                                                 "reserved",     "reserved",
2696                                                 "reserved",     "reserved";
2697
2698                                         #clock-cells = <1>;
2699                                 };
2700                         };
2701                 };
2702
2703                 special_regs {
2704                         compatible = "rockchip,rk-clock-special-regs";
2705                         #address-cells = <1>;
2706                         #size-cells = <1>;
2707                         ranges;
2708
2709                         clk_32k_mux: clk_32k_mux {
2710                                 compatible = "rockchip,rk3188-mux-con";
2711                                 reg = <0xff738100 0x4>;
2712                                 rockchip,bits = <6 1>;
2713                                 clocks = <&xin32k>, <&clk_gates7 3>;
2714                                 clock-output-names = "clk_32k_mux";
2715                                 #clock-cells = <0>;
2716                                 #clock-init-cells = <1>;
2717                         };
2718                 };
2719         };
2720 };