2 * Copyright (C) 2014-2015 ROCKCHIP, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #include <dt-bindings/clock/rockchip,rk3368.h>
18 compatible = "rockchip,rk-clocks";
24 compatible = "rockchip,rk-fixed-rate-cons";
27 compatible = "rockchip,rk-fixed-clock";
28 clock-output-names = "xin24m";
29 clock-frequency = <24000000>;
34 compatible = "rockchip,rk-fixed-clock";
36 clock-output-names = "xin12m";
37 clock-frequency = <12000000>;
42 compatible = "rockchip,rk-fixed-clock";
43 clock-output-names = "xin32k";
44 clock-frequency = <32000>;
49 compatible = "rockchip,rk-fixed-clock";
50 clock-output-names = "dummy";
51 clock-frequency = <0>;
55 jtag_clkin: jtag_clkin {
56 compatible = "rockchip,rk-fixed-clock";
57 clock-output-names = "jtag_clkin";
58 clock-frequency = <0>;
62 gmac_clkin: gmac_clkin {
63 compatible = "rockchip,rk-fixed-clock";
64 clock-output-names = "gmac_clkin";
65 clock-frequency = <0>;
69 pclkin_isp: pclkin_isp {
70 compatible = "rockchip,rk-fixed-clock";
71 clock-output-names = "pclkin_isp";
72 clock-frequency = <0>;
76 pclkin_vip: pclkin_vip {
77 compatible = "rockchip,rk-fixed-clock";
78 clock-output-names = "pclkin_vip";
79 clock-frequency = <0>;
83 clkin_hsadc_tsp: clkin_hsadc_tsp {
84 compatible = "rockchip,rk-fixed-clock";
85 clock-output-names = "clkin_hsadc_tsp";
86 clock-frequency = <0>;
90 i2s_clkin: i2s_clkin {
91 compatible = "rockchip,rk-fixed-clock";
92 clock-output-names = "i2s_clkin";
93 clock-frequency = <0>;
99 compatible = "rockchip,rk-fixed-factor-cons";
101 hclk_vepu: hclk_vepu {
102 compatible = "rockchip,rk-fixed-factor-clock";
103 clocks = <&aclk_vepu>;
104 clock-output-names = "hclk_vepu";
110 hclk_vdpu: hclk_vdpu {
111 compatible = "rockchip,rk-fixed-factor-clock";
112 clocks = <&aclk_vdpu>;
113 clock-output-names = "hclk_vdpu";
119 usbotg_480m_out: usbotg_480m_out {
120 compatible = "rockchip,rk-fixed-factor-clock";
121 clocks = <&clk_gates8 1>;
122 clock-output-names = "usbotg_480m_out";
128 pclkin_isp_inv: pclkin_isp_inv {
129 compatible = "rockchip,rk-fixed-factor-clock";
130 clocks = <&clk_gates17 2>;
131 clock-output-names = "pclkin_isp_inv";
137 pclkin_vip_inv: pclkin_vip_inv {
138 compatible = "rockchip,rk-fixed-factor-clock";
139 clocks = <&clk_gates16 13>;
140 clock-output-names = "pclkin_vip_inv";
147 compatible = "rockchip,rk-fixed-factor-clock";
148 clocks = <&clk_gates16 8>;
149 clock-output-names = "pclk_vio";
157 compatible = "rockchip,rk-clock-regs";
158 #address-cells = <1>;
160 ranges = <0x0 0xFF760000 0x0264>;
161 reg = <0xFF760000 0x0264>;/* NEED CONFIRM */
163 /* PLL control regs */
165 compatible = "rockchip,rk-pll-cons";
166 #address-cells = <1>;
170 clk_apllb: pll-clk@0000 {
171 compatible = "rockchip,rk3188-pll-clk";
173 mode-reg = <0x000c 8>;
174 status-reg = <0x0480 1>;
176 clock-output-names = "clk_apllb";
177 rockchip,pll-type = <CLK_PLL_3368_APLLB>;
182 clk_aplll: pll-clk@0010 {
183 compatible = "rockchip,rk3188-pll-clk";
185 mode-reg = <0x001c 8>;
186 status-reg = <0x0480 0>;
188 clock-output-names = "clk_aplll";
189 rockchip,pll-type = <CLK_PLL_3368_APLLL>;
193 clk_dpll: pll-clk@0020 {
194 compatible = "rockchip,rk3188-pll-clk";
196 mode-reg = <0x002c 8>;
197 status-reg = <0x0480 2>;
199 clock-output-names = "clk_dpll";
200 rockchip,pll-type = <CLK_PLL_3188PLUS>;
205 clk_cpll: pll-clk@0030 {
206 compatible = "rockchip,rk3188-pll-clk";
208 mode-reg = <0x003c 8>;
209 status-reg = <0x0480 3>;
211 clock-output-names = "clk_cpll";
212 rockchip,pll-type = <CLK_PLL_3188PLUS>;
214 #clock-init-cells = <1>;
217 clk_gpll: pll-clk@0040 {
218 compatible = "rockchip,rk3188-pll-clk";
220 mode-reg = <0x004c 8>;
221 status-reg = <0x0480 4>;
223 clock-output-names = "clk_gpll";
224 rockchip,pll-type = <CLK_PLL_3188PLUS>;
226 #clock-init-cells = <1>;
229 clk_npll: pll-clk@0050 {
230 compatible = "rockchip,rk3188-pll-clk";
232 mode-reg = <0x005c 8>;
233 status-reg = <0x0480 5>;
235 clock-output-names = "clk_npll";
236 rockchip,pll-type = <CLK_PLL_3188PLUS>;
238 #clock-init-cells = <1>;
242 /* Select control regs */
244 compatible = "rockchip,rk-sel-cons";
245 #address-cells = <1>;
249 clk_sel_con0: sel-con@0100 {
250 compatible = "rockchip,rk3188-selcon";
252 #address-cells = <1>;
255 clk_core_b_div: clk_core_b_div {
256 compatible = "rockchip,rk3188-div-con";
257 rockchip,bits = <0 5>;
258 clocks = <&clk_core_b>;
259 clock-output-names = "clk_core_b";
260 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
262 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
263 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
264 CLK_SET_RATE_NO_REPARENT)>;
269 clk_core_b: clk_core_b_mux {
270 compatible = "rockchip,rk3188-mux-con";
271 rockchip,bits = <7 1>;
272 clocks = <&clk_apllb>, <&clk_gpll>;
273 clock-output-names = "clk_core_b";
275 #clock-init-cells = <1>;
278 aclkm_core_b: aclkm_core_b_div {
279 compatible = "rockchip,rk3188-div-con";
280 rockchip,bits = <8 5>;
281 clocks = <&clk_core_b>;
282 clock-output-names = "aclkm_core_b";
283 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
285 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
291 clk_sel_con1: sel-con@0104 {
292 compatible = "rockchip,rk3188-selcon";
294 #address-cells = <1>;
297 atclk_core_b: atclk_core_b_div {
298 compatible = "rockchip,rk3188-div-con";
299 rockchip,bits = <0 5>;
300 clocks = <&clk_core_b>;
301 clock-output-names = "atclk_core_b";
302 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
304 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
309 pclk_dbg_b: pclk_dbg_b_div {
310 compatible = "rockchip,rk3188-div-con";
311 rockchip,bits = <8 5>;
312 clocks = <&clk_core_b>;
313 clock-output-names = "pclk_dbg_b";
314 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
316 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
320 clk_sel_con2: sel-con@0108 {
321 compatible = "rockchip,rk3188-selcon";
323 #address-cells = <1>;
326 clk_core_l_div: clk_core_l_div {
327 compatible = "rockchip,rk3188-div-con";
328 rockchip,bits = <0 5>;
329 clocks = <&clk_core_l>;
330 clock-output-names = "clk_core_l";
331 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
333 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
334 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
335 CLK_SET_RATE_NO_REPARENT)>;
340 clk_core_l: clk_core_l_mux {
341 compatible = "rockchip,rk3188-mux-con";
342 rockchip,bits = <7 1>;
343 clocks = <&clk_aplll>, <&clk_gpll>;
344 clock-output-names = "clk_core_l";
346 #clock-init-cells = <1>;
349 aclkm_core_l: aclkm_core_l_div {
350 compatible = "rockchip,rk3188-div-con";
351 rockchip,bits = <8 5>;
352 clocks = <&clk_core_l>;
353 clock-output-names = "aclkm_core_l";
354 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
356 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
362 clk_sel_con3: sel-con@010c {
363 compatible = "rockchip,rk3188-selcon";
365 #address-cells = <1>;
368 atclk_core_l: atclk_core_l_div {
369 compatible = "rockchip,rk3188-div-con";
370 rockchip,bits = <0 5>;
371 clocks = <&clk_core_l>;
372 clock-output-names = "atclk_core_l";
373 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
375 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
380 pclk_dbg_l: pclk_dbg_l_div {
381 compatible = "rockchip,rk3188-div-con";
382 rockchip,bits = <8 5>;
383 clocks = <&clk_core_l>;
384 clock-output-names = "pclk_dbg_l";
385 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
387 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
391 clk_sel_con4: sel-con@0110 {
392 compatible = "rockchip,rk3188-selcon";
394 #address-cells = <1>;
397 clk_cs_div: clk_cs_div {
398 compatible = "rockchip,rk3188-div-con";
399 rockchip,bits = <0 5>;
401 clock-output-names = "clk_cs";
402 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
404 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
410 compatible = "rockchip,rk3188-mux-con";
411 rockchip,bits = <6 2>;
412 clocks = <&clk_gates0 9>, <&clk_gates0 10>, <&clk_gates0 8>, <&dummy>;
413 clock-output-names = "clk_cs";
415 #clock-init-cells = <1>;
418 clkin_trace: clkin_trace_div {
419 compatible = "rockchip,rk3188-div-con";
420 rockchip,bits = <8 5>;
422 clock-output-names = "clkin_trace";
423 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
429 clk_sel_con5: sel-con@0114 {
430 compatible = "rockchip,rk3188-selcon";
432 #address-cells = <1>;
435 aclk_cci_div: aclk_cci_div {
436 compatible = "rockchip,rk3188-div-con";
437 rockchip,bits = <0 5>;
438 clocks = <&aclk_cci>;
439 clock-output-names = "aclk_cci";
440 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
442 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
447 aclk_cci: aclk_cci_mux {
448 compatible = "rockchip,rk3188-mux-con";
449 rockchip,bits = <6 2>;
450 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
451 clock-output-names = "aclk_cci";
453 #clock-init-cells = <1>;
457 /* sel[7:6] reserved */
459 clk_sel_con8: sel-con@0120 {
460 compatible = "rockchip,rk3188-selcon";
462 #address-cells = <1>;
465 aclk_bus_div: aclk_bus_div {
466 compatible = "rockchip,rk3188-div-con";
467 rockchip,bits = <0 5>;
468 clocks = <&aclk_bus>;
469 clock-output-names = "aclk_bus_div";
470 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
472 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
477 aclk_bus: aclk_bus_mux {
478 compatible = "rockchip,rk3188-mux-con";
479 rockchip,bits = <7 1>;
480 clocks = <&clk_gates1 11>, <&clk_gates1 10>;
481 clock-output-names = "aclk_bus";
483 #clock-init-cells = <1>;
486 hclk_bus: hclk_bus_div {
487 compatible = "rockchip,rk3188-div-con";
488 rockchip,bits = <8 2>;
489 clocks = <&aclk_bus>;
490 clock-output-names = "hclk_bus";
491 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
497 pclk_bus: pclk_bus_div {
498 compatible = "rockchip,rk3188-div-con";
499 rockchip,bits = <12 3>;
500 clocks = <&aclk_bus>;
501 clock-output-names = "pclk_bus";
502 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
507 clk_sel_con9: sel-con@0124 {
508 compatible = "rockchip,rk3188-selcon";
510 #address-cells = <1>;
513 aclk_peri_div: aclk_peri_div {
514 compatible = "rockchip,rk3188-div-con";
515 rockchip,bits = <0 5>;
516 clocks = <&aclk_peri>;
517 clock-output-names = "aclk_peri_div";
518 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
520 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
525 aclk_peri: aclk_peri_mux {
526 compatible = "rockchip,rk3188-mux-con";
527 rockchip,bits = <7 1>;
528 clocks = <&clk_cpll>, <&clk_gpll>;
529 clock-output-names = "aclk_peri";
531 #clock-init-cells = <1>;
534 hclk_peri: hclk_peri_div {
535 compatible = "rockchip,rk3188-div-con";
536 rockchip,bits = <8 2>;
537 clocks = <&aclk_peri>;
538 clock-output-names = "hclk_peri";
539 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
540 rockchip,div-relations =
545 #clock-init-cells = <1>;
550 pclk_peri: pclk_peri_div {
551 compatible = "rockchip,rk3188-div-con";
552 rockchip,bits = <12 2>;
553 clocks = <&aclk_peri>;
554 clock-output-names = "pclk_peri";
555 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
556 rockchip,div-relations =
562 #clock-init-cells = <1>;
566 clk_sel_con10: sel-con@0128 {
567 compatible = "rockchip,rk3188-selcon";
569 #address-cells = <1>;
572 pclk_pmu_pre: pclk_pmu_pre_div {
573 compatible = "rockchip,rk3188-div-con";
574 rockchip,bits = <0 5>;
575 clocks = <&clk_gpll>;
576 clock-output-names = "pclk_pmu_pre";
577 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
583 pclk_alive_pre: pclk_alive_pre_div {
584 compatible = "rockchip,rk3188-div-con";
585 rockchip,bits = <8 5>;
586 clocks = <&clk_gpll>;
587 clock-output-names = "pclk_alive_pre";
588 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
594 clk_crypto: clk_crypto_div {
595 compatible = "rockchip,rk3188-div-con";
596 rockchip,bits = <14 2>;
597 clocks = <&aclk_bus>;
598 clock-output-names = "clk_crypto";
599 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
604 /* sel[11]: reserved */
606 clk_sel_con12: sel-con@0130 {
607 compatible = "rockchip,rk3188-selcon";
609 #address-cells = <1>;
612 fclk_mcu_div: fclk_mcu_div {
613 compatible = "rockchip,rk3188-div-con";
614 rockchip,bits = <0 5>;
615 clocks = <&fclk_mcu>;
616 clock-output-names = "fclk_mcu";
617 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
619 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
624 fclk_mcu: fclk_mcu_mux {
625 compatible = "rockchip,rk3188-mux-con";
626 rockchip,bits = <7 1>;
627 clocks = <&clk_cpll>, <&clk_gpll>;
628 clock-output-names = "fclk_mcu";
630 #clock-init-cells = <1>;
633 stclk_mcu: stclk_mcu_div {
634 compatible = "rockchip,rk3188-div-con";
635 rockchip,bits = <8 3>;
636 clocks = <&fclk_mcu>;
637 clock-output-names = "stclk_mcu";
638 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
643 clk_sel_con13: sel-con@0134 {
644 compatible = "rockchip,rk3188-selcon";
646 #address-cells = <1>;
649 clk_ddr_div: clk_ddr_div {
650 compatible = "rockchip,rk3188-div-con";
651 rockchip,bits = <0 2>;
653 clock-output-names = "clk_ddr";
654 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
656 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
657 CLK_SET_RATE_NO_REPARENT)>;
658 rockchip,clkops-idx =
659 <CLKOPS_RATE_DDR_DIV4>;
664 clk_ddr: clk_ddr_mux {
665 compatible = "rockchip,rk3188-mux-con";
666 rockchip,bits = <4 1>;
667 clocks = <&clk_dpll>, <&clk_gpll>;
668 clock-output-names = "clk_ddr";
676 usbphy_480m: usbphy_480m_mux {
677 compatible = "rockchip,rk3188-mux-con";
678 rockchip,bits = <8 1>;
679 clocks = <&xin24m>, <&usbotg_480m_out>;
680 clock-output-names = "usbphy_480m";
682 rockchip,clkops-idx =
683 <CLKOPS_RATE_RK3288_USB480M>;
684 #clock-init-cells = <1>;
687 clk4x_ddr: clk4x_ddr_mux {
688 compatible = "rockchip,rk3188-mux-con";
689 rockchip,bits = <4 1>;
690 clocks = <&clk_dpll>, <&clk_gpll>;
691 clock-output-names = "clk4x_ddr";
696 clk_sel_con14: sel-con@0138 {
697 compatible = "rockchip,rk3188-selcon";
699 #address-cells = <1>;
702 clk_gpu_core_div: clk_gpu_core_div {
703 compatible = "rockchip,rk3188-div-con";
704 rockchip,bits = <0 5>;
705 clocks = <&clk_gpu_core>;
706 clock-output-names = "clk_gpu_core";
707 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
709 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
710 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
715 clk_gpu_core: clk_gpu_core_mux {
716 compatible = "rockchip,rk3188-mux-con";
717 rockchip,bits = <6 2>;
718 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
719 clock-output-names = "clk_gpu_core";
721 #clock-init-cells = <1>;
724 aclk_gpu_mem: aclk_gpu_mem_div {
725 compatible = "rockchip,rk3188-div-con";
726 rockchip,bits = <8 5>;
727 clocks = <&aclk_gpu>;
728 clock-output-names = "aclk_gpu_mem";
729 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
735 aclk_gpu: aclk_gpu_mux {
736 compatible = "rockchip,rk3188-mux-con";
737 rockchip,bits = <14 1>;
738 clocks = <&clk_cpll>, <&clk_gpll>;
739 clock-output-names = "aclk_gpu";
741 #clock-init-cells = <1>;
745 clk_sel_con15: sel-con@013c {
746 compatible = "rockchip,rk3188-selcon";
748 #address-cells = <1>;
751 aclk_vepu_div: aclk_vepu_div {
752 compatible = "rockchip,rk3188-div-con";
753 rockchip,bits = <0 5>;
754 clocks = <&aclk_vepu>;
755 clock-output-names = "aclk_vepu";
756 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
758 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
763 aclk_vepu: aclk_vepu_mux {
764 compatible = "rockchip,rk3188-mux-con";
765 rockchip,bits = <6 2>;
766 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
767 clock-output-names = "aclk_vepu";
769 #clock-init-cells = <1>;
772 aclk_vdpu_div: aclk_vdpu_div {
773 compatible = "rockchip,rk3188-div-con";
774 rockchip,bits = <8 5>;
775 clocks = <&aclk_vdpu>;
776 clock-output-names = "aclk_vdpu";
777 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
779 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
784 aclk_vdpu: aclk_vdpu_mux {
785 compatible = "rockchip,rk3188-mux-con";
786 rockchip,bits = <14 2>;
787 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
788 clock-output-names = "aclk_vdpu";
790 #clock-init-cells = <1>;
794 clk_sel_con16: sel-con@0140 {
795 compatible = "rockchip,rk3188-selcon";
797 #address-cells = <1>;
800 aclk_gpu_cfg: aclk_gpu_cfg_div {
801 compatible = "rockchip,rk3188-div-con";
802 rockchip,bits = <8 5>;
803 clocks = <&aclk_gpu>;
804 clock-output-names = "aclk_gpu_cfg";
805 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
810 clk_sel_con17: sel-con@0144 {
811 compatible = "rockchip,rk3188-selcon";
813 #address-cells = <1>;
816 clk_hevc_cabac_div: clk_hevc_cabac_div {
817 compatible = "rockchip,rk3188-div-con";
818 rockchip,bits = <0 5>;
819 clocks = <&clk_hevc_cabac>;
820 clock-output-names = "clk_hevc_cabac";
821 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
823 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
828 clk_hevc_cabac: clk_hevc_cabac_mux {
829 compatible = "rockchip,rk3188-mux-con";
830 rockchip,bits = <6 2>;
831 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
832 clock-output-names = "clk_hevc_cabac";
834 #clock-init-cells = <1>;
837 clk_hevc_core_div: clk_hevc_core_div {
838 compatible = "rockchip,rk3188-div-con";
839 rockchip,bits = <8 5>;
840 clocks = <&clk_hevc_core>;
841 clock-output-names = "clk_hevc_core";
842 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
844 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
849 clk_hevc_core: clk_hevc_core_mux {
850 compatible = "rockchip,rk3188-mux-con";
851 rockchip,bits = <14 2>;
852 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
853 clock-output-names = "clk_hevc_core";
855 #clock-init-cells = <1>;
859 clk_sel_con18: sel-con@0148 {
860 compatible = "rockchip,rk3188-selcon";
862 #address-cells = <1>;
865 clk_rga_div: clk_rga_div {
866 compatible = "rockchip,rk3188-div-con";
867 rockchip,bits = <0 5>;
869 clock-output-names = "clk_rga";
870 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
872 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
877 clk_rga: clk_rga_mux {
878 compatible = "rockchip,rk3188-mux-con";
879 rockchip,bits = <6 2>;
880 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
881 clock-output-names = "clk_rga";
883 #clock-init-cells = <1>;
886 aclk_rga_div: aclk_rga_div {
887 compatible = "rockchip,rk3188-div-con";
888 rockchip,bits = <8 5>;
889 clocks = <&aclk_rga_pre>;
890 clock-output-names = "aclk_rga_pre";
891 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
893 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
898 aclk_rga_pre: aclk_rga_mux {
899 compatible = "rockchip,rk3188-mux-con";
900 rockchip,bits = <14 2>;
901 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
902 clock-output-names = "aclk_rga_pre";
904 #clock-init-cells = <1>;
908 clk_sel_con19: sel-con@014c {
909 compatible = "rockchip,rk3188-selcon";
911 #address-cells = <1>;
914 aclk_vio0_div: aclk_vio0_div {
915 compatible = "rockchip,rk3188-div-con";
916 rockchip,bits = <0 5>;
917 clocks = <&aclk_vio0>;
918 clock-output-names = "aclk_vio0";
919 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
921 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
926 aclk_vio0: aclk_vio0_mux {
927 compatible = "rockchip,rk3188-mux-con";
928 rockchip,bits = <6 2>;
929 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
930 clock-output-names = "aclk_vio0";
932 #clock-init-cells = <1>;
936 clk_sel_con20: sel-con@0150 {
937 compatible = "rockchip,rk3188-selcon";
939 #address-cells = <1>;
942 dclk_vop0_div: dclk_vop0_div {
943 compatible = "rockchip,rk3188-div-con";
944 rockchip,bits = <0 8>;
945 clocks = <&dclk_vop0>;
946 clock-output-names = "dclk_vop0";
947 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
949 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
952 dclk_vop0: dclk_vop0_mux {
953 compatible = "rockchip,rk3188-mux-con";
954 rockchip,bits = <8 2>;
955 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&dummy>;
956 clock-output-names = "dclk_vop0";
958 #clock-init-cells = <1>;
964 clk_sel_con21: sel-con@0154 {
965 compatible = "rockchip,rk3188-selcon";
967 #address-cells = <1>;
970 hclk_vio: hclk_vio_div {
971 compatible = "rockchip,rk3188-div-con";
972 rockchip,bits = <0 5>;
973 clocks = <&aclk_vio0>;
974 clock-output-names = "hclk_vio";
975 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
977 #clock-init-cells = <1>;
982 pclk_isp: pclk_isp_mux {
983 compatible = "rockchip,rk3188-mux-con";
984 rockchip,bits = <6 1>;
985 clocks = <&clk_gates17 2>, <&pclkin_isp_inv>;
986 clock-output-names = "pclk_isp";
992 clk_vip_div: clk_vip_div {
993 compatible = "rockchip,rk3188-div-con";
994 rockchip,bits = <8 5>;
996 clock-output-names = "clk_vip";
997 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
999 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1002 pclk_vip: pclk_vip_mux {
1003 compatible = "rockchip,rk3188-mux-con";
1004 rockchip,bits = <13 1>;
1005 clocks = <&clk_gates16 13>, <&pclkin_vip_inv>;
1006 clock-output-names = "pclk_vip";
1010 clk_vip: clk_vip_mux {
1011 compatible = "rockchip,rk3188-mux-con";
1012 rockchip,bits = <14 2>;
1013 clocks = <&clk_cpll>, <&xin24m>, <&clk_gpll>, <&xin24m>;
1014 clock-output-names = "clk_vip";
1016 #clock-init-cells = <1>;
1020 clk_sel_con22: sel-con@0158 {
1021 compatible = "rockchip,rk3188-selcon";
1023 #address-cells = <1>;
1026 clk_isp_div: clk_isp_div {
1027 compatible = "rockchip,rk3188-div-con";
1028 rockchip,bits = <0 6>;
1029 clocks = <&clk_isp>;
1030 clock-output-names = "clk_isp";
1031 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1033 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1036 clk_isp: clk_isp_mux {
1037 compatible = "rockchip,rk3188-mux-con";
1038 rockchip,bits = <6 2>;
1039 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1040 clock-output-names = "clk_isp";
1042 #clock-init-cells = <1>;
1046 clk_sel_con23: sel-con@015c {
1047 compatible = "rockchip,rk3188-selcon";
1049 #address-cells = <1>;
1052 clk_edp_div: clk_edp_div {
1053 compatible = "rockchip,rk3188-div-con";
1054 rockchip,bits = <0 6>;
1055 clocks = <&clk_edp>;
1056 clock-output-names = "clk_edp";
1057 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1059 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1062 clk_edp: clk_edp_mux {
1063 compatible = "rockchip,rk3188-mux-con";
1064 rockchip,bits = <6 2>;
1065 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1066 clock-output-names = "clk_edp";
1070 clk_edp_24m: clk_edp_24m_mux {
1071 compatible = "rockchip,rk3188-mux-con";
1072 rockchip,bits = <8 1>;
1073 clocks = <&xin24m>, <&dummy>;
1074 clock-output-names = "clk_edp_24m";
1079 /* sel[24]: reserved */
1081 clk_sel_con25: sel-con@0164 {
1082 compatible = "rockchip,rk3188-selcon";
1084 #address-cells = <1>;
1087 clk_tsadc: clk_tsadc_div {
1088 compatible = "rockchip,rk3188-div-con";
1089 rockchip,bits = <0 6>;
1090 clocks = <&clk_32k_mux>;
1091 clock-output-names = "clk_tsadc";
1092 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1096 clk_saradc: clk_saradc_div {
1097 compatible = "rockchip,rk3188-div-con";
1098 rockchip,bits = <8 8>;
1100 clock-output-names = "clk_saradc";
1101 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1106 clk_sel_con26: sel-con@0168 {
1107 compatible = "rockchip,rk3188-selcon";
1109 #address-cells = <1>;
1114 hsic_usb_480m: hsic_usb_480m_mux {
1115 compatible = "rockchip,rk3188-mux-con";
1116 rockchip,bits = <8 1>;
1117 clocks = <&usbotg_480m_out>, <&dummy>;
1118 clock-output-names = "hsic_usb_480m";
1124 hsicphy_480m: hsicphy_480m_mux {
1125 compatible = "rockchip,rk3188-mux-con";
1126 rockchip,bits = <12 2>;
1127 clocks = <&clk_cpll>, <&clk_gpll>, <&hsic_usb_480m>, <&hsic_usb_480m>;
1128 clock-output-names = "hsicphy_480m";
1133 clk_sel_con27: sel-con@016c {
1134 compatible = "rockchip,rk3188-selcon";
1136 #address-cells = <1>;
1139 i2s_pll_div: i2s_pll_div {
1140 compatible = "rockchip,rk3188-div-con";
1141 rockchip,bits = <0 7>;
1142 clocks = <&i2s_pll>;
1143 clock-output-names = "i2s_pll";
1144 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1146 rockchip,clkops-idx =
1147 <CLKOPS_RATE_MUX_DIV>;
1148 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1153 clk_i2s: clk_i2s_mux {
1154 compatible = "rockchip,rk3188-mux-con";
1155 rockchip,bits = <8 2>;
1156 clocks = <&i2s_pll>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
1157 clock-output-names = "clk_i2s";
1159 rockchip,clkops-idx =
1160 <CLKOPS_RATE_RK3288_I2S>;
1161 rockchip,flags = <CLK_SET_RATE_PARENT>;
1164 /* 11:10 reserved */
1166 i2s_pll: i2s_pll_mux {
1167 compatible = "rockchip,rk3188-mux-con";
1168 rockchip,bits = <12 1>;
1169 clocks = <&clk_cpll>, <&clk_gpll>;
1170 clock-output-names = "i2s_pll";
1174 /* 14:13 reserved */
1176 i2s_out: i2s_out_mux {
1177 compatible = "rockchip,rk3188-mux-con";
1178 rockchip,bits = <15 1>;
1179 clocks = <&clk_i2s>, <&xin12m>;
1180 clock-output-names = "i2s_out";
1185 clk_sel_con28: sel-con@0170 {
1186 compatible = "rockchip,rk3188-selcon";
1188 #address-cells = <1>;
1191 i2s_frac: i2s_frac {
1192 compatible = "rockchip,rk3188-frac-con";
1193 clocks = <&i2s_pll>;
1194 clock-output-names = "i2s_frac";
1195 /* numerator denominator */
1196 rockchip,bits = <0 32>;
1197 rockchip,clkops-idx =
1203 /* sel[30:29] reserved */
1205 clk_sel_con31: sel-con@017c {
1206 compatible = "rockchip,rk3188-selcon";
1208 #address-cells = <1>;
1212 spdif_8ch_pll_div: spdif_8ch_pll_div {
1213 compatible = "rockchip,rk3188-div-con";
1214 rockchip,bits = <0 7>;
1215 clocks = <&spdif_8ch_pll>;
1216 clock-output-names = "spdif_8ch_pll";
1217 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1219 rockchip,clkops-idx =
1220 <CLKOPS_RATE_MUX_DIV>;
1221 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1226 clk_spidf_8ch: clk_spidf_8ch_mux {
1227 compatible = "rockchip,rk3188-mux-con";
1228 rockchip,bits = <8 2>;
1229 clocks = <&spdif_8ch_pll>, <&spdif_8ch_frac>, <&i2s_clkin>, <&xin12m>;
1230 clock-output-names = "clk_spidf_8ch";
1232 rockchip,clkops-idx =
1233 <CLKOPS_RATE_RK3288_I2S>;
1234 rockchip,flags = <CLK_SET_RATE_PARENT>;
1237 /* 11:10 reserved */
1239 spdif_8ch_pll: spdif_8ch_pll_mux {
1240 compatible = "rockchip,rk3188-mux-con";
1241 rockchip,bits = <12 1>;
1242 clocks = <&clk_cpll>, <&clk_gpll>;
1243 clock-output-names = "spdif_8ch_pll";
1247 /* 15:13 reserved */
1250 clk_sel_con32: sel-con@0180 {
1251 compatible = "rockchip,rk3188-selcon";
1253 #address-cells = <1>;
1256 spdif_8ch_frac: spdif_8ch_frac {
1257 compatible = "rockchip,rk3188-frac-con";
1258 clocks = <&spdif_8ch_pll>;
1259 clock-output-names = "spdif_8ch_frac";
1260 /* numerator denominator */
1261 rockchip,bits = <0 32>;
1262 rockchip,clkops-idx =
1268 clk_sel_con33: sel-con@0184 {
1269 compatible = "rockchip,rk3188-selcon";
1271 #address-cells = <1>;
1274 clk_uart0_pll_div: clk_uart0_pll_div {
1275 compatible = "rockchip,rk3188-div-con";
1276 rockchip,bits = <0 7>;
1277 clocks = <&clk_uart0_pll>;
1278 clock-output-names = "clk_uart0_pll";
1279 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1281 rockchip,clkops-idx =
1282 <CLKOPS_RATE_MUX_DIV>;
1287 clk_uart0: clk_uart0_mux {
1288 compatible = "rockchip,rk3188-mux-con";
1289 rockchip,bits = <8 2>;
1290 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>, <&xin24m>;
1291 clock-output-names = "clk_uart0";
1293 rockchip,clkops-idx =
1294 <CLKOPS_RATE_RK3288_I2S>;
1295 rockchip,flags = <CLK_SET_RATE_PARENT>;
1298 /* 11:10 reserved */
1300 clk_uart0_pll: clk_uart0_pll_mux {
1301 compatible = "rockchip,rk3188-mux-con";
1302 rockchip,bits = <12 2>;
1303 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
1304 clock-output-names = "clk_uart0_pll";
1309 clk_sel_con34: sel-con@0188 {
1310 compatible = "rockchip,rk3188-selcon";
1312 #address-cells = <1>;
1315 uart0_frac: uart0_frac {
1316 compatible = "rockchip,rk3188-frac-con";
1317 clocks = <&clk_uart0_pll>;
1318 clock-output-names = "uart0_frac";
1319 /* numerator denominator */
1320 rockchip,bits = <0 32>;
1321 rockchip,clkops-idx =
1327 clk_sel_con35: sel-con@018c {
1328 compatible = "rockchip,rk3188-selcon";
1330 #address-cells = <1>;
1333 uart1_div: uart1_div {
1334 compatible = "rockchip,rk3188-div-con";
1335 rockchip,bits = <0 7>;
1336 clocks = <&clk_uart_pll>;
1337 clock-output-names = "uart1_div";
1338 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1344 clk_uart1: clk_uart1_mux {
1345 compatible = "rockchip,rk3188-mux-con";
1346 rockchip,bits = <8 2>;
1347 clocks = <&uart1_div>, <&uart1_frac>, <&xin24m>, <&xin24m>;
1348 clock-output-names = "clk_uart1";
1350 rockchip,clkops-idx =
1351 <CLKOPS_RATE_RK3288_I2S>;
1352 rockchip,flags = <CLK_SET_RATE_PARENT>;
1355 /* 11:10 reserved */
1357 clk_uart_pll: clk_uart_pll_mux {
1358 compatible = "rockchip,rk3188-mux-con";
1359 rockchip,bits = <12 1>;
1360 clocks = <&clk_cpll>, <&clk_gpll>;
1361 clock-output-names = "clk_uart_pll";
1365 /* 14:13 reserved */
1368 clk_sel_con36: sel-con@0190 {
1369 compatible = "rockchip,rk3188-selcon";
1371 #address-cells = <1>;
1374 uart1_frac: uart1_frac {
1375 compatible = "rockchip,rk3188-frac-con";
1376 clocks = <&uart1_div>;
1377 clock-output-names = "uart1_frac";
1378 /* numerator denominator */
1379 rockchip,bits = <0 32>;
1380 rockchip,clkops-idx =
1386 clk_sel_con37: sel-con@0194 {
1387 compatible = "rockchip,rk3188-selcon";
1389 #address-cells = <1>;
1392 uart2_div: uart2_div {
1393 compatible = "rockchip,rk3188-div-con";
1394 rockchip,bits = <0 7>;
1395 clocks = <&clk_uart_pll>;
1396 clock-output-names = "uart2_div";
1397 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1403 clk_uart2: clk_uart2_mux {
1404 compatible = "rockchip,rk3188-mux-con";
1405 rockchip,bits = <8 1>;
1406 clocks = <&uart2_div>, <&xin24m>;
1407 clock-output-names = "clk_uart2";
1409 rockchip,flags = <CLK_SET_RATE_PARENT>;
1413 /* sel[38] reserved */
1415 clk_sel_con39: sel-con@019c {
1416 compatible = "rockchip,rk3188-selcon";
1418 #address-cells = <1>;
1421 uart3_div: uart3_div {
1422 compatible = "rockchip,rk3188-div-con";
1423 rockchip,bits = <0 7>;
1424 clocks = <&clk_uart_pll>;
1425 clock-output-names = "uart3_div";
1426 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1432 clk_uart3: clk_uart3_mux {
1433 compatible = "rockchip,rk3188-mux-con";
1434 rockchip,bits = <8 2>;
1435 clocks = <&uart3_div>, <&uart3_frac>, <&xin24m>, <&xin24m>;
1436 clock-output-names = "clk_uart3";
1438 rockchip,clkops-idx =
1439 <CLKOPS_RATE_RK3288_I2S>;
1440 rockchip,flags = <CLK_SET_RATE_PARENT>;
1444 clk_sel_con40: sel-con@01a0 {
1445 compatible = "rockchip,rk3188-selcon";
1447 #address-cells = <1>;
1450 uart3_frac: uart3_frac {
1451 compatible = "rockchip,rk3188-frac-con";
1452 clocks = <&uart3_div>;
1453 clock-output-names = "uart3_frac";
1454 /* numerator denominator */
1455 rockchip,bits = <0 32>;
1456 rockchip,clkops-idx =
1462 clk_sel_con41: sel-con@01a4 {
1463 compatible = "rockchip,rk3188-selcon";
1465 #address-cells = <1>;
1468 uart4_div: uart4_div {
1469 compatible = "rockchip,rk3188-div-con";
1470 rockchip,bits = <0 7>;
1471 clocks = <&clk_uart_pll>;
1472 clock-output-names = "uart4_div";
1473 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1479 clk_uart4: clk_uart4_mux {
1480 compatible = "rockchip,rk3188-mux-con";
1481 rockchip,bits = <8 2>;
1482 clocks = <&uart4_div>, <&uart4_frac>, <&xin24m>, <&xin24m>;
1483 clock-output-names = "clk_uart4";
1485 rockchip,clkops-idx =
1486 <CLKOPS_RATE_RK3288_I2S>;
1487 rockchip,flags = <CLK_SET_RATE_PARENT>;
1491 clk_sel_con42: sel-con@01a8 {
1492 compatible = "rockchip,rk3188-selcon";
1494 #address-cells = <1>;
1497 uart4_frac: uart4_frac {
1498 compatible = "rockchip,rk3188-frac-con";
1499 clocks = <&uart4_div>;
1500 clock-output-names = "uart4_frac";
1501 /* numerator denominator */
1502 rockchip,bits = <0 32>;
1503 rockchip,clkops-idx =
1509 clk_sel_con43: sel-con@01ac {
1510 compatible = "rockchip,rk3188-selcon";
1512 #address-cells = <1>;
1515 clk_mac_pll_div: clk_mac_pll_div {
1516 compatible = "rockchip,rk3188-div-con";
1517 rockchip,bits = <0 5>;
1518 clocks = <&clk_mac_pll>;
1519 clock-output-names = "clk_mac_pll";
1520 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1522 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1527 clk_mac_pll: clk_mac_pll_mux {
1528 compatible = "rockchip,rk3188-mux-con";
1529 rockchip,bits = <6 2>;
1530 clocks = <&clk_npll>, <&clk_cpll>, <&clk_gpll>, <&clk_gpll>;
1531 clock-output-names = "clk_mac_pll";
1535 clk_mac: clk_mac_mux {
1536 compatible = "rockchip,rk3188-mux-con";
1537 rockchip,bits = <8 1>;
1538 clocks = <&clk_mac_pll>, <&gmac_clkin>;
1539 clock-output-names = "clk_mac";
1541 rockchip,flags = <CLK_SET_RATE_PARENT>;
1546 /* 12: test_clk: wifi_pll_sel */
1548 /* 15:13 reserved */
1551 clk_sel_con44: sel-con@01b0 {
1552 compatible = "rockchip,rk3188-selcon";
1554 #address-cells = <1>;
1557 /* test_clk: wifi_frac */
1560 clk_sel_con45: sel-con@01b4 {
1561 compatible = "rockchip,rk3188-selcon";
1563 #address-cells = <1>;
1566 clk_spi0_div: clk_spi0_div {
1567 compatible = "rockchip,rk3188-div-con";
1568 rockchip,bits = <0 7>;
1569 clocks = <&clk_spi0>;
1570 clock-output-names = "clk_spi0";
1571 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1573 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1576 clk_spi0: clk_spi0_mux {
1577 compatible = "rockchip,rk3188-mux-con";
1578 rockchip,bits = <7 1>;
1579 clocks = <&clk_cpll>, <&clk_gpll>;
1580 clock-output-names = "clk_spi0";
1584 clk_spi1_div: clk_spi1_div {
1585 compatible = "rockchip,rk3188-div-con";
1586 rockchip,bits = <8 7>;
1587 clocks = <&clk_spi1>;
1588 clock-output-names = "clk_spi1";
1589 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1591 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1594 clk_spi1: clk_spi1_mux {
1595 compatible = "rockchip,rk3188-mux-con";
1596 rockchip,bits = <15 1>;
1597 clocks = <&clk_cpll>, <&clk_gpll>;
1598 clock-output-names = "clk_spi1";
1603 clk_sel_con46: sel-con@01b8 {
1604 compatible = "rockchip,rk3188-selcon";
1606 #address-cells = <1>;
1609 clk_tsp_div: clk_tsp_div {
1610 compatible = "rockchip,rk3188-div-con";
1611 rockchip,bits = <0 5>;
1612 clocks = <&clk_tsp>;
1613 clock-output-names = "clk_tsp";
1614 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1616 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1621 clk_tsp: clk_tsp_mux {
1622 compatible = "rockchip,rk3188-mux-con";
1623 rockchip,bits = <6 2>;
1624 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1625 clock-output-names = "clk_tsp";
1629 clk_spi2_div: clk_spi2_div {
1630 compatible = "rockchip,rk3188-div-con";
1631 rockchip,bits = <8 7>;
1632 clocks = <&clk_spi2>;
1633 clock-output-names = "clk_spi2";
1634 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1636 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1639 clk_spi2: clk_spi2_mux {
1640 compatible = "rockchip,rk3188-mux-con";
1641 rockchip,bits = <15 1>;
1642 clocks = <&clk_cpll>, <&clk_gpll>;
1643 clock-output-names = "clk_spi2";
1648 clk_sel_con47: sel-con@01bc {
1649 compatible = "rockchip,rk3188-selcon";
1651 #address-cells = <1>;
1654 clk_nandc0_div: clk_nandc0_div {
1655 compatible = "rockchip,rk3188-div-con";
1656 rockchip,bits = <0 5>;
1657 clocks = <&clk_nandc0>;
1658 clock-output-names = "clk_nandc0";
1659 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1661 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1666 clk_nandc0: clk_nandc0_mux {
1667 compatible = "rockchip,rk3188-mux-con";
1668 rockchip,bits = <7 1>;
1669 clocks = <&clk_cpll>, <&clk_gpll>;
1670 clock-output-names = "clk_nandc0";
1676 /* 15:13 reserved */
1679 clk_sel_con48: sel-con@01c0 {
1680 compatible = "rockchip,rk3188-selcon";
1682 #address-cells = <1>;
1685 clk_sdio0_div: clk_sdio0_div {
1686 compatible = "rockchip,rk3188-div-con";
1687 rockchip,bits = <0 7>;
1688 clocks = <&clk_sdio0>;
1689 clock-output-names = "clk_sdio0";
1690 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1692 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1697 clk_sdio0: clk_sdio0_mux {
1698 compatible = "rockchip,rk3188-mux-con";
1699 rockchip,bits = <8 2>;
1700 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1701 clock-output-names = "clk_sdio0";
1705 /* 15:10 reserved */
1708 /* sel[49] reserved */
1710 clk_sel_con50: sel-con@01c8 {
1711 compatible = "rockchip,rk3188-selcon";
1713 #address-cells = <1>;
1716 clk_sdmmc0_div: clk_sdmmc0_div {
1717 compatible = "rockchip,rk3188-div-con";
1718 rockchip,bits = <0 7>;
1719 clocks = <&clk_sdmmc0>;
1720 clock-output-names = "clk_sdmmc0";
1721 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1723 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1728 clk_sdmmc0: clk_sdmmc0_mux {
1729 compatible = "rockchip,rk3188-mux-con";
1730 rockchip,bits = <8 2>;
1731 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1732 clock-output-names = "clk_sdmmc0";
1736 /* 15:10 reserved */
1739 clk_sel_con51: sel-con@01cc {
1740 compatible = "rockchip,rk3188-selcon";
1742 #address-cells = <1>;
1745 clk_emmc_div: clk_emmc_div {
1746 compatible = "rockchip,rk3188-div-con";
1747 rockchip,bits = <0 7>;
1748 clocks = <&clk_emmc>;
1749 clock-output-names = "clk_emmc";
1750 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1752 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1757 clk_emmc: clk_emmc_mux {
1758 compatible = "rockchip,rk3188-mux-con";
1759 rockchip,bits = <8 2>;
1760 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1761 clock-output-names = "clk_emmc";
1765 /* 15:10 reserved */
1768 clk_sel_con52: sel-con@01d0 {
1769 compatible = "rockchip,rk3188-selcon";
1771 #address-cells = <1>;
1774 clk_sfc_div: clk_sfc_div {
1775 compatible = "rockchip,rk3188-div-con";
1776 rockchip,bits = <0 5>;
1777 clocks = <&clk_sfc>;
1778 clock-output-names = "clk_sfc";
1779 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1781 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1786 clk_sfc: clk_sfc_mux {
1787 compatible = "rockchip,rk3188-mux-con";
1788 rockchip,bits = <7 1>;
1789 clocks = <&clk_cpll>, <&clk_gpll>;
1790 clock-output-names = "clk_sfc";
1797 clk_sel_con53: sel-con@01d4 {
1798 compatible = "rockchip,rk3188-selcon";
1800 #address-cells = <1>;
1803 i2s_2ch_pll_div: i2s_2ch_pll_div {
1804 compatible = "rockchip,rk3188-div-con";
1805 rockchip,bits = <0 7>;
1806 clocks = <&i2s_2ch_pll>;
1807 clock-output-names = "i2s_2ch_pll";
1808 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1810 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1815 clk_i2s_2ch: clk_i2s_2ch_mux {
1816 compatible = "rockchip,rk3188-mux-con";
1817 rockchip,bits = <8 2>;
1818 clocks = <&i2s_2ch_pll>, <&i2s_2ch_frac>, <&dummy>, <&xin12m>;
1819 clock-output-names = "clk_i2s_2ch";
1821 rockchip,clkops-idx =
1822 <CLKOPS_RATE_RK3288_I2S>;
1823 rockchip,flags = <CLK_SET_RATE_PARENT>;
1826 /* 11:10 reserved */
1828 i2s_2ch_pll: i2s_2ch_pll_mux {
1829 compatible = "rockchip,rk3188-mux-con";
1830 rockchip,bits = <12 1>;
1831 clocks = <&clk_cpll>, <&clk_gpll>;
1832 clock-output-names = "i2s_2ch_pll";
1838 clk_sel_con54: sel-con@01d8 {
1839 compatible = "rockchip,rk3188-selcon";
1841 #address-cells = <1>;
1844 i2s_2ch_frac: i2s_2ch_frac {
1845 compatible = "rockchip,rk3188-frac-con";
1846 clocks = <&i2s_2ch_pll>;
1847 clock-output-names = "i2s_2ch_frac";
1848 /* numerator denominator */
1849 rockchip,bits = <0 32>;
1850 rockchip,clkops-idx =
1856 clk_sel_con55: sel-con@01dc {
1857 compatible = "rockchip,rk3188-selcon";
1859 #address-cells = <1>;
1862 clk_hdcp_div: clk_hdcp_div {
1863 compatible = "rockchip,rk3188-div-con";
1864 rockchip,bits = <0 6>;
1865 clocks = <&clk_hdcp>;
1866 clock-output-names = "clk_hdcp";
1867 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1869 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1872 clk_hdcp: clk_hdcp_mux {
1873 compatible = "rockchip,rk3188-mux-con";
1874 rockchip,bits = <6 2>;
1875 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1876 clock-output-names = "clk_hdcp";
1882 /* Gate control regs */
1884 compatible = "rockchip,rk-gate-cons";
1885 #address-cells = <1>;
1889 clk_gates0: gate-clk@0200 {
1890 compatible = "rockchip,rk3188-gate-clk";
1899 <&clk_gpll>, <&clk_apllb>,
1900 <&clk_aplll>, <&dummy>,
1902 <&aclk_cci>, <&clkin_trace>,
1905 clock-output-names =
1906 "reserved", "reserved",/* core_b_apll core_b_gpll */
1907 "reserved", "reserved",
1909 "reserved", "reserved",/* core_l_apll core_l_gpll */
1910 "reserved", "reserved",
1912 "g_clk_cs_gpll", "g_clk_cs_apllb",
1913 "g_clk_cs_aplll", "reserved",
1915 "aclk_cci", "clkin_trace",
1916 "reserved", "reserved";
1921 clk_gates1: gate-clk@0204 {
1922 compatible = "rockchip,rk3188-gate-clk";
1925 <&aclk_bus>, <&hclk_bus>,
1926 <&pclk_bus>, <&fclk_mcu>,
1932 <&clk_gpll>, <&clk_cpll>,
1937 clock-output-names =
1938 "aclk_bus", "hclk_bus",
1939 "pclk_bus", "fclk_mcu",
1941 "reserved", "reserved",
1942 "reserved", "reserved",
1944 "reserved", "reserved",/* ddr_dpll ddr_gpll */
1945 "aclk_bus_gpll", "aclk_bus_cpll",
1947 "reserved", "reserved",
1948 "reserved", "reserved";
1953 clk_gates2: gate-clk@0208 {
1954 compatible = "rockchip,rk3188-gate-clk";
1957 <&clk_uart0_pll>, <&uart0_frac>,
1958 <&uart1_div>, <&uart1_frac>,
1960 <&uart2_div>, <&dummy>,
1961 <&uart3_div>, <&uart3_frac>,
1963 <&uart4_div>, <&uart4_frac>,
1969 clock-output-names =
1970 "clk_uart0_pll", "uart0_frac",
1971 "uart1_div", "uart1_frac",
1973 "uart2_div", "reserved",
1974 "uart3_div", "uart3_frac",
1976 "uart4_div", "uart4_frac",
1977 "reserved", "reserved",
1979 "reserved", "reserved",
1980 "reserved", "reserved";
1985 clk_gates3: gate-clk@020c {
1986 compatible = "rockchip,rk3188-gate-clk";
1989 <&aclk_peri>, <&dummy>,
1990 <&hclk_peri>, <&pclk_peri>,
1992 <&clk_mac_pll>, <&clk_tsadc>,
1993 <&clk_saradc>, <&clk_spi0>,
1995 <&clk_spi1>, <&clk_spi2>,
2001 clock-output-names =
2002 "aclk_peri", "reserved", /* bit1: aclk_peri */
2003 "hclk_peri", "pclk_peri",
2005 "clk_mac_pll", "clk_tsadc",
2006 "clk_saradc", "clk_spi0",
2008 "clk_spi1", "clk_spi2",
2009 "reserved", "reserved",
2011 "reserved", "reserved",
2012 "reserved", "reserved";
2017 clk_gates4: gate-clk@0210 {
2018 compatible = "rockchip,rk3188-gate-clk";
2021 <&aclk_vio0>, <&dclk_vop0>,
2022 <&xin24m>, <&aclk_rga_pre>,
2024 <&clk_rga>, <&clk_vip>,
2025 <&aclk_vepu>, <&aclk_vdpu>,
2027 <&dummy>, <&clk_isp>,
2028 <&dummy>, <&clk_gpu_core>,
2030 <&xin32k>, <&xin24m>,
2031 <&xin24m>, <&dummy>;
2033 clock-output-names =
2034 "aclk_vio0", "dclk_vop0",
2035 "clk_vop0_pwm", "aclk_rga_pre",
2037 "clk_rga", "clk_vip",
2038 "aclk_vepu", "aclk_vdpu",
2040 "reserved", "clk_isp", /* bit8: hclk_vpu */
2041 "reserved", "clk_gpu_core",
2043 "clk_hdmi_cec", "clk_hdmi_hdcp",
2044 "clk_dsiphy_24m", "reserved";
2049 clk_gates5: gate-clk@0214 {
2050 compatible = "rockchip,rk3188-gate-clk";
2053 <&dummy>, <&clk_hevc_cabac>,
2054 <&clk_hevc_core>, <&clk_edp>,
2056 <&clk_edp_24m>, <&clk_hdcp>,
2059 <&aclk_gpu_mem>, <&aclk_gpu_cfg>,
2062 <&dummy>, <&i2s_pll>,
2063 <&i2s_2ch_frac>, <&clk_i2s_2ch>;
2065 clock-output-names =
2066 "reserved", "clk_hevc_cabac",
2067 "clk_hevc_core", "clk_edp",
2069 "clk_edp_24m", "clk_hdcp",
2070 "reserved", "reserved",
2072 "aclk_gpu_mem", "aclk_gpu_cfg",
2073 "reserved", "reserved",
2075 "reserved", "i2s_pll",
2076 "i2s_2ch_frac", "clk_i2s_2ch";
2081 clk_gates6: gate-clk@0218 {
2082 compatible = "rockchip,rk3188-gate-clk";
2085 <&i2s_out>, <&i2s_pll>,
2086 <&i2s_frac>, <&clk_i2s>,
2088 <&spdif_8ch_pll>, <&spdif_8ch_frac>,
2089 <&clk_spidf_8ch>, <&clk_sfc>,
2094 <&clk_tsp>, <&dummy>,
2097 clock-output-names =
2098 "i2s_out", "i2s_pll",
2099 "i2s_frac", "clk_i2s",
2101 "spdif_8ch_pll", "spdif_8ch_frac",
2102 "clk_spidf_8ch", "clk_sfc",
2104 "reserved", "reserved",
2105 "reserved", "reserved",
2107 "clk_tsp", "reserved",
2108 "reserved", "reserved";/* clk_ddrphy_gate clk4x_ddrphy_gate */
2113 clk_gates7: gate-clk@021c {
2114 compatible = "rockchip,rk3188-gate-clk";
2117 <&jtag_clkin>, <&dummy>,
2118 <&clk_crypto>, <&xin24m>,
2121 <&clk_mac>, <&clk_mac>,
2123 <&clk_nandc0>, <&pclk_pmu_pre>,
2124 <&xin24m>, <&xin24m>,
2129 clock-output-names =
2130 "clk_jtag", "reserved",/* bit1: test_clk */
2131 "clk_crypto", "clk_pvtm_pmu",
2133 "reserved", "reserved",/* clk_mac_rx clk_mac_tx */
2134 "clk_mac_ref", "clk_mac_refout",
2136 "clk_nandc0", "pclk_pmu_pre",
2137 "clk_pvtm_core", "clk_pvtm_gpu",
2139 "clk_sdmmc0", "clk_sdio0",
2140 "reserved", "clk_emmc";
2145 clk_gates8: gate-clk@0220 {
2146 compatible = "rockchip,rk3188-gate-clk";
2149 <&hsic_usb_480m>, <&xin24m>,
2152 <&clk_32k_mux>, <&dummy>,
2153 <&xin12m>, <&hsicphy_480m>,
2161 clock-output-names =
2162 "hsic_usb_480m", "clk_otgphy0",
2163 "reserved", "reserved",
2165 "g_clk_otg_adp", "reserved",/* bit4: clk_otg_adp */
2166 "hsicphy_12m", "hsicphy_480m",
2168 "reserved", "reserved",
2169 "reserved", "reserved",
2171 "reserved", "reserved",
2172 "reserved", "reserved";
2177 clk_gates9: gate-clk@0224 {
2178 compatible = "rockchip,rk3188-gate-clk";
2193 clock-output-names =
2194 "reserved", "reserved",
2195 "reserved", "reserved",
2197 "reserved", "reserved",
2198 "reserved", "reserved",
2200 "reserved", "reserved",
2201 "reserved", "reserved",
2203 "reserved", "reserved",
2204 "reserved", "reserved";
2209 clk_gates10: gate-clk@0228 {
2210 compatible = "rockchip,rk3188-gate-clk";
2225 clock-output-names =
2226 "reserved", "reserved",
2227 "reserved", "reserved",
2229 "reserved", "reserved",
2230 "reserved", "reserved",
2232 "reserved", "reserved",
2233 "reserved", "reserved",
2235 "reserved", "reserved",
2236 "reserved", "reserved";
2241 clk_gates11: gate-clk@022c {
2242 compatible = "rockchip,rk3188-gate-clk";
2257 clock-output-names =
2258 "reserved", "reserved",
2259 "reserved", "reserved",
2261 "reserved", "reserved",
2262 "reserved", "reserved",
2264 "reserved", "reserved",
2265 "reserved", "reserved",
2267 "reserved", "reserved",
2268 "reserved", "reserved";
2273 clk_gates12: gate-clk@0230 {
2274 compatible = "rockchip,rk3188-gate-clk";
2277 <&pclk_bus>, <&pclk_bus>,
2278 <&pclk_bus>, <&pclk_bus>,
2280 <&aclk_bus>, <&aclk_bus>,
2281 <&aclk_bus>, <&hclk_bus>,
2283 <&hclk_bus>, <&hclk_bus>,
2284 <&hclk_bus>, <&aclk_bus>,
2286 <&aclk_bus>, <&dummy>,
2289 clock-output-names =
2290 "g_pclk_pwm0", "g_p_mailbox",
2291 "g_p_i2cpmu", "g_p_i2caudio",
2293 "g_aclk_intmem", "g_clk_intmem0",
2294 "g_clk_intmem1", "g_h_i2s_8ch",
2296 "g_h_i2s_2ch", "g_hclk_rom",
2297 "g_hclk_spdif", "g_aclk_dmac",
2299 "g_a_strc_sys", "reserved",/* bit13: pclk_ddrupctl */
2300 "reserved", "reserved";/* bit14: pclk_ddrphy */
2305 clk_gates13: gate-clk@0234 {
2306 compatible = "rockchip,rk3188-gate-clk";
2309 <&pclk_bus>, <&pclk_bus>,
2310 <&dummy>, <&hclk_bus>,
2312 <&hclk_bus>, <&pclk_bus>,
2313 <&pclk_bus>, <&clkin_hsadc_tsp>,
2315 <&pclk_bus>, <&aclk_bus>,
2316 <&hclk_bus>, <&dummy>,
2321 clock-output-names =
2322 "g_p_efuse_1024", "g_p_efuse_256",
2323 "reserved", "g_mclk_crypto",/* bit2: nclk_ddrupctl */
2325 "g_sclk_crypto", "g_p_uartdbg",
2326 "g_pclk_pwm1", "clk_hsadc_tsp",
2328 "g_pclk_sim", "g_aclk_gic400",
2329 "g_hclk_tsp", "reserved",
2331 "reserved", "reserved",
2332 "reserved", "reserved";
2337 clk_gates14: gate-clk@0238 {
2338 compatible = "rockchip,rk3188-gate-clk";
2353 clock-output-names =
2354 "reserved", "reserved",
2355 "reserved", "reserved",
2357 "reserved", "reserved",
2358 "reserved", "reserved",
2360 "reserved", "reserved",
2361 "reserved", "reserved",
2363 "reserved", "reserved",
2364 "reserved", "reserved";
2369 clk_gates15: gate-clk@023c {
2370 compatible = "rockchip,rk3188-gate-clk";
2385 clock-output-names =
2386 "reserved", "reserved",/* aclk_video hclk_video */
2387 "reserved", "reserved",
2389 "reserved", "reserved",
2390 "reserved", "reserved",
2392 "reserved", "reserved",
2393 "reserved", "reserved",
2395 "reserved", "reserved",
2396 "reserved", "reserved";
2401 clk_gates16: gate-clk@0240 {
2402 compatible = "rockchip,rk3188-gate-clk";
2405 <&clk_gates16 10>, <&clk_gates16 8>,
2406 <&clk_gates16 9>, <&clk_gates16 8>,
2408 <&clk_gates16 9>, <&clk_gates16 9>,
2409 <&clk_gates16 8>, <&clk_gates16 8>,
2411 <&hclk_vio>, <&aclk_vio0>,
2412 <&aclk_rga_pre>, <&clk_gates16 9>,
2414 <&clk_gates16 8>, <&pclkin_vip>,
2415 <&clk_isp>, <&dummy>;
2417 clock-output-names =
2418 "g_aclk_rga", "g_hclk_rga",
2419 "g_aclk_iep", "g_hclk_iep",
2421 "g_aclk_vop_iep", "g_aclk_vop",
2422 "g_hclk_vop", "g_h_vio_ahb_arbi",
2424 "g_hclk_vio_noc", "g_aclk_vio0_noc",
2425 "g_aclk_vio1_noc", "g_aclk_vip",
2427 "g_hclk_vip", "g_pclkin_vip",
2428 "g_hclk_isp", "reserved";
2433 clk_gates17: gate-clk@0244 {
2434 compatible = "rockchip,rk3188-gate-clk";
2437 <&clk_isp>, <&dummy>,
2438 <&pclkin_isp>, <&pclk_vio>,
2440 <&pclk_vio>, <&dummy>,
2441 <&pclk_vio>, <&clk_gates16 8>,
2443 <&pclk_vio>, <&pclk_vio>,
2444 <&clk_gates16 10>, <&pclk_vio>,
2446 <&clk_gates16 8>, <&dummy>,
2449 clock-output-names =
2450 "g_aclk_isp", "reserved",
2451 "g_pclkin_isp", "g_p_mipi_dsi0",
2453 "g_p_mipi_csi", "reserved",
2454 "g_p_hdmi_ctrl", "g_hclk_vio_h2p",
2456 "g_pclk_vio_h2p", "g_p_edp_ctrl",
2457 "g_aclk_hdcp", "g_pclk_hdcp",
2459 "g_h_hdcpmmu", "reserved",
2460 "reserved", "reserved";
2465 clk_gates18: gate-clk@0248 {
2466 compatible = "rockchip,rk3188-gate-clk";
2481 clock-output-names =
2482 "reserved", "reserved",/* bit0-1: aclk_gpu_cfg aclk_gpu_mem */
2483 "reserved", "reserved",/* bit2: clk_gpu_core */
2485 "reserved", "reserved",
2486 "reserved", "reserved",
2488 "reserved", "reserved",
2489 "reserved", "reserved",
2491 "reserved", "reserved",
2492 "reserved", "reserved";
2497 clk_gates19: gate-clk@024c {
2498 compatible = "rockchip,rk3188-gate-clk";
2501 <&hclk_peri>, <&pclk_peri>,
2502 <&aclk_peri>, <&aclk_peri>,
2504 <&pclk_peri>, <&pclk_peri>,
2505 <&pclk_peri>, <&pclk_peri>,
2507 <&pclk_peri>, <&pclk_peri>,
2508 <&pclk_peri>, <&pclk_peri>,
2510 <&pclk_peri>, <&pclk_peri>,
2511 <&pclk_peri>, <&pclk_peri>;
2513 clock-output-names =
2514 "g_h_p_axi_matrix", "g_p_p_axi_matrix",
2515 "g_a_p_axi_matrix", "g_a_dmac_peri",
2517 "g_pclk_spi0", "g_pclk_spi1",
2518 "g_pclk_spi2", "g_pclk_uart0",
2520 "g_pclk_uart1", "g_pclk_uart3",
2521 "g_pclk_uart4", "g_pclk_i2c2",
2523 "g_pclk_i2c3", "g_pclk_i2c4",
2524 "g_pclk_i2c5", "g_pclk_saradc";
2529 clk_gates20: gate-clk@0250 {
2530 compatible = "rockchip,rk3188-gate-clk";
2533 <&pclk_peri>, <&hclk_peri>,
2534 <&hclk_peri>, <&hclk_peri>,
2536 <&dummy>, <&hclk_peri>,
2537 <&hclk_peri>, <&hclk_peri>,
2539 <&aclk_peri>, <&hclk_peri>,
2540 <&hclk_peri>, <&hclk_peri>,
2542 <&dummy>, <&aclk_peri>,
2543 <&pclk_peri>, <&aclk_peri>;
2545 clock-output-names =
2546 "g_pclk_tsadc", "g_hclk_otg0",
2547 "g_h_pmu_otg0", "g_hclk_host0",
2549 "reserved", "g_hclk_hsic",
2550 "g_h_usb_peri", "g_h_p_ahb_arbi",
2552 "g_a_peri_niu", "g_h_emem_peri",
2553 "g_h_mmc_peri", "g_hclk_nand0",
2555 "reserved", "g_aclk_gmac",
2556 "g_pclk_gmac", "g_hclk_sfc";
2561 clk_gates21: gate-clk@0254 {
2562 compatible = "rockchip,rk3188-gate-clk";
2565 <&hclk_peri>, <&hclk_peri>,
2566 <&hclk_peri>, <&hclk_peri>,
2568 <&aclk_peri>, <&dummy>,
2577 clock-output-names =
2578 "g_hclk_sdmmc", "g_hclk_sdio0",
2579 "g_hclk_emmc", "g_hclk_hsadc",
2581 "g_aclk_peri_mmu", "reserved",
2582 "reserved", "reserved",
2584 "reserved", "reserved",
2585 "reserved", "reserved",
2587 "reserved", "reserved",
2588 "reserved", "reserved";
2593 clk_gates22: gate-clk@0258 {
2594 compatible = "rockchip,rk3188-gate-clk";
2597 <&dummy>, <&pclk_alive_pre>,
2598 <&pclk_alive_pre>, <&pclk_alive_pre>,
2603 <&pclk_alive_pre>, <&pclk_alive_pre>,
2604 <&pclk_vio>, <&pclk_vio>,
2606 <&pclk_alive_pre>, <&pclk_alive_pre>,
2609 clock-output-names =
2610 "reserved", "g_pclk_gpio1",
2611 "g_pclk_gpio2", "g_pclk_gpio3",
2613 "reserved", "reserved",
2614 "reserved", "reserved",
2616 "g_pclk_grf", "g_p_alive_niu",
2617 "g_pclk_dphytx0", "g_pclk_dphyrx",
2619 "g_pclk_timer0", "g_pclk_timer1",
2620 "reserved", "reserved";
2625 clk_gates23: gate-clk@025c {
2626 compatible = "rockchip,rk3188-gate-clk";
2629 <&pclk_pmu_pre>, <&pclk_pmu_pre>,
2630 <&pclk_pmu_pre>, <&pclk_pmu_pre>,
2632 <&pclk_pmu_pre>, <&pclk_pmu_pre>,
2641 clock-output-names =
2642 "g_pclk_pmu", "g_pclk_intmem1",
2643 "g_pclk_pmu_noc", "g_pclk_sgrf",
2645 "g_pclk_gpio0", "g_pclk_pmugrf",
2646 "reserved", "reserved",
2648 "reserved", "reserved",
2649 "reserved", "reserved",
2651 "reserved", "reserved",
2652 "reserved", "reserved";
2657 clk_gates24: gate-clk@0260 {
2658 compatible = "rockchip,rk3188-gate-clk";
2661 <&xin24m>, <&xin24m>,
2662 <&xin24m>, <&xin24m>,
2664 <&xin24m>, <&xin24m>,
2665 <&xin24m>, <&xin24m>,
2667 <&xin24m>, <&xin24m>,
2668 <&xin24m>, <&xin24m>,
2673 clock-output-names =
2674 "g_clk_timer0", "g_clk_timer1",
2675 "g_clk_timer2", "g_clk_timer3",
2677 "g_clk_timer4", "g_clk_timer5",
2678 "g_clk_timer10", "g_clk_timer11",
2680 "g_clk_timer12", "g_clk_timer13",
2681 "g_clk_timer14", "g_clk_timer15",
2683 "reserved", "reserved",
2684 "reserved", "reserved";
2692 compatible = "rockchip,rk-clock-special-regs";
2693 #address-cells = <1>;
2697 clk_32k_mux: clk_32k_mux {
2698 compatible = "rockchip,rk3188-mux-con";
2699 reg = <0xff738100 0x4>;
2700 rockchip,bits = <6 1>;
2701 clocks = <&xin32k>, <&clk_gates7 3>;
2702 clock-output-names = "clk_32k_mux";
2704 #clock-init-cells = <1>;