2 * Copyright (C) 2014-2015 ROCKCHIP, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #include <dt-bindings/clock/rockchip,rk3368.h>
18 compatible = "rockchip,rk-clocks";
19 rockchip,grf = <&grf>;
25 compatible = "rockchip,rk-fixed-rate-cons";
28 compatible = "rockchip,rk-fixed-clock";
29 clock-output-names = "xin24m";
30 clock-frequency = <24000000>;
35 compatible = "rockchip,rk-fixed-clock";
37 clock-output-names = "xin12m";
38 clock-frequency = <12000000>;
43 compatible = "rockchip,rk-fixed-clock";
44 clock-output-names = "xin32k";
45 clock-frequency = <32000>;
49 pvtm_clkout: pvtm_clkout {
50 compatible = "rockchip,rk-fixed-clock";
51 clock-output-names = "pvtm_clkout";
52 clock-frequency = <32000>;
57 compatible = "rockchip,rk-fixed-clock";
58 clock-output-names = "dummy";
59 clock-frequency = <0>;
63 jtag_clkin: jtag_clkin {
64 compatible = "rockchip,rk-fixed-clock";
65 clock-output-names = "jtag_clkin";
66 clock-frequency = <0>;
70 gmac_clkin: gmac_clkin {
71 compatible = "rockchip,rk-fixed-clock";
72 clock-output-names = "gmac_clkin";
73 clock-frequency = <0>;
77 pclkin_isp: pclkin_isp {
78 compatible = "rockchip,rk-fixed-clock";
79 clock-output-names = "pclkin_isp";
80 clock-frequency = <0>;
84 pclkin_vip: pclkin_vip {
85 compatible = "rockchip,rk-fixed-clock";
86 clock-output-names = "pclkin_vip";
87 clock-frequency = <0>;
91 clkin_hsadc_tsp: clkin_hsadc_tsp {
92 compatible = "rockchip,rk-fixed-clock";
93 clock-output-names = "clkin_hsadc_tsp";
94 clock-frequency = <0>;
98 i2s_clkin: i2s_clkin {
99 compatible = "rockchip,rk-fixed-clock";
100 clock-output-names = "i2s_clkin";
101 clock-frequency = <0>;
107 compatible = "rockchip,rk-fixed-factor-cons";
109 hclk_vepu: hclk_vepu {
110 compatible = "rockchip,rk-fixed-factor-clock";
111 clocks = <&aclk_vepu>;
112 clock-output-names = "hclk_vepu";
118 hclk_vdpu: hclk_vdpu {
119 compatible = "rockchip,rk-fixed-factor-clock";
120 clocks = <&aclk_vdpu>;
121 clock-output-names = "hclk_vdpu";
127 usbotg_480m_out: usbotg_480m_out {
128 compatible = "rockchip,rk-fixed-factor-clock";
129 clocks = <&clk_gates8 1>;
130 clock-output-names = "usbotg_480m_out";
136 pclkin_isp_inv: pclkin_isp_inv {
137 compatible = "rockchip,rk-fixed-factor-clock";
138 clocks = <&clk_gates17 2>;
139 clock-output-names = "pclkin_isp_inv";
145 pclkin_vip_inv: pclkin_vip_inv {
146 compatible = "rockchip,rk-fixed-factor-clock";
147 clocks = <&clk_gates16 13>;
148 clock-output-names = "pclkin_vip_inv";
155 compatible = "rockchip,rk-fixed-factor-clock";
156 clocks = <&clk_gates16 8>;
157 clock-output-names = "pclk_vio";
165 compatible = "rockchip,rk-pd-cons";
168 compatible = "rockchip,rk-pd-clock";
169 clock-output-names = "pd_gpu_0";
170 rockchip,pd-id = <CLK_PD_GPU_0>;
175 compatible = "rockchip,rk-pd-clock";
176 clocks = <&pd_gpu_0>;
177 clock-output-names = "pd_gpu_1";
178 rockchip,pd-id = <CLK_PD_GPU_1>;
183 compatible = "rockchip,rk-pd-clock";
184 clock-output-names = "pd_video";
185 rockchip,pd-id = <CLK_PD_VIDEO>;
190 compatible = "rockchip,rk-pd-clock";
191 clock-output-names = "pd_vio";
192 rockchip,pd-id = <CLK_PD_VIO>;
197 compatible = "rockchip,rk-pd-clock";
198 clocks = <&pd_video>;
199 clock-output-names = "pd_hevc";
200 rockchip,pd-id = <CLK_PD_VIRT>;
205 compatible = "rockchip,rk-pd-clock";
207 clock-output-names = "pd_vop";
208 rockchip,pd-id = <CLK_PD_VIRT>;
213 compatible = "rockchip,rk-pd-clock";
215 clock-output-names = "pd_isp";
216 rockchip,pd-id = <CLK_PD_VIRT>;
221 compatible = "rockchip,rk-pd-clock";
223 clock-output-names = "pd_iep";
224 rockchip,pd-id = <CLK_PD_VIRT>;
229 compatible = "rockchip,rk-pd-clock";
231 clock-output-names = "pd_rga";
232 rockchip,pd-id = <CLK_PD_VIRT>;
236 pd_mipicsi: pd_mipicsi {
237 compatible = "rockchip,rk-pd-clock";
239 clock-output-names = "pd_mipicsi";
240 rockchip,pd-id = <CLK_PD_VIRT>;
244 pd_mipidsi: pd_mipidsi {
245 compatible = "rockchip,rk-pd-clock";
247 clock-output-names = "pd_mipidsi";
248 rockchip,pd-id = <CLK_PD_VIRT>;
253 compatible = "rockchip,rk-pd-clock";
255 clock-output-names = "pd_lvds";
256 rockchip,pd-id = <CLK_PD_VIRT>;
261 compatible = "rockchip,rk-pd-clock";
263 clock-output-names = "pd_hdmi";
264 rockchip,pd-id = <CLK_PD_VIRT>;
269 compatible = "rockchip,rk-pd-clock";
271 clock-output-names = "pd_edp";
272 rockchip,pd-id = <CLK_PD_VIRT>;
278 compatible = "rockchip,rk-clock-regs";
279 #address-cells = <1>;
281 ranges = <0x0 0x0 0xff760000 0x1000>;
282 reg = <0x0 0xff760000 0x0 0x1000>;
284 /* PLL control regs */
286 compatible = "rockchip,rk-pll-cons";
287 #address-cells = <1>;
291 clk_apllb: pll-clk@0000 {
292 compatible = "rockchip,rk3188-pll-clk";
294 mode-reg = <0x000c 8>;
295 status-reg = <0x0480 1>;
297 clock-output-names = "clk_apllb";
298 rockchip,pll-type = <CLK_PLL_3368_APLLB>;
303 clk_aplll: pll-clk@0010 {
304 compatible = "rockchip,rk3188-pll-clk";
306 mode-reg = <0x001c 8>;
307 status-reg = <0x0480 0>;
309 clock-output-names = "clk_aplll";
310 rockchip,pll-type = <CLK_PLL_3368_APLLL>;
314 clk_dpll: pll-clk@0020 {
315 compatible = "rockchip,rk3188-pll-clk";
317 mode-reg = <0x002c 8>;
318 status-reg = <0x0480 2>;
320 clock-output-names = "clk_dpll";
321 rockchip,pll-type = <CLK_PLL_3188PLUS>;
326 clk_cpll: pll-clk@0030 {
327 compatible = "rockchip,rk3188-pll-clk";
329 mode-reg = <0x003c 8>;
330 status-reg = <0x0480 3>;
332 clock-output-names = "clk_cpll";
333 rockchip,pll-type = <CLK_PLL_3188PLUS>;
335 #clock-init-cells = <1>;
338 clk_gpll: pll-clk@0040 {
339 compatible = "rockchip,rk3188-pll-clk";
341 mode-reg = <0x004c 8>;
342 status-reg = <0x0480 4>;
344 clock-output-names = "clk_gpll";
345 rockchip,pll-type = <CLK_PLL_3188PLUS>;
347 #clock-init-cells = <1>;
350 clk_npll: pll-clk@0050 {
351 compatible = "rockchip,rk3188-pll-clk";
353 mode-reg = <0x005c 8>;
354 status-reg = <0x0480 5>;
356 clock-output-names = "clk_npll";
357 rockchip,pll-type = <CLK_PLL_3368_LOW_JITTER>;
359 #clock-init-cells = <1>;
363 /* Select control regs */
365 compatible = "rockchip,rk-sel-cons";
366 #address-cells = <1>;
370 clk_sel_con0: sel-con@0100 {
371 compatible = "rockchip,rk3188-selcon";
373 #address-cells = <1>;
376 clk_core_b_div: clk_core_b_div {
377 compatible = "rockchip,rk3188-div-con";
378 rockchip,bits = <0 5>;
379 clocks = <&clk_core_b>;
380 clock-output-names = "clk_core_b";
381 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
383 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
384 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
385 CLK_SET_RATE_NO_REPARENT)>;
390 clk_core_b: clk_core_b_mux {
391 compatible = "rockchip,rk3188-mux-con";
392 rockchip,bits = <7 1>;
393 clocks = <&clk_apllb>, <&clk_gpll>;
394 clock-output-names = "clk_core_b";
396 #clock-init-cells = <1>;
399 aclkm_core_b: aclkm_core_b_div {
400 compatible = "rockchip,rk3188-div-con";
401 rockchip,bits = <8 5>;
402 clocks = <&clk_core_b>;
403 clock-output-names = "aclkm_core_b";
404 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
406 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
412 clk_sel_con1: sel-con@0104 {
413 compatible = "rockchip,rk3188-selcon";
415 #address-cells = <1>;
418 atclk_core_b: atclk_core_b_div {
419 compatible = "rockchip,rk3188-div-con";
420 rockchip,bits = <0 5>;
421 clocks = <&clk_core_b>;
422 clock-output-names = "atclk_core_b";
423 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
425 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
430 pclk_dbg_b: pclk_dbg_b_div {
431 compatible = "rockchip,rk3188-div-con";
432 rockchip,bits = <8 5>;
433 clocks = <&clk_core_b>;
434 clock-output-names = "pclk_dbg_b";
435 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
437 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
441 clk_sel_con2: sel-con@0108 {
442 compatible = "rockchip,rk3188-selcon";
444 #address-cells = <1>;
447 clk_core_l_div: clk_core_l_div {
448 compatible = "rockchip,rk3188-div-con";
449 rockchip,bits = <0 5>;
450 clocks = <&clk_core_l>;
451 clock-output-names = "clk_core_l";
452 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
454 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
455 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
456 CLK_SET_RATE_NO_REPARENT)>;
461 clk_core_l: clk_core_l_mux {
462 compatible = "rockchip,rk3188-mux-con";
463 rockchip,bits = <7 1>;
464 clocks = <&clk_aplll>, <&clk_gpll>;
465 clock-output-names = "clk_core_l";
467 #clock-init-cells = <1>;
470 aclkm_core_l: aclkm_core_l_div {
471 compatible = "rockchip,rk3188-div-con";
472 rockchip,bits = <8 5>;
473 clocks = <&clk_core_l>;
474 clock-output-names = "aclkm_core_l";
475 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
477 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
483 clk_sel_con3: sel-con@010c {
484 compatible = "rockchip,rk3188-selcon";
486 #address-cells = <1>;
489 atclk_core_l: atclk_core_l_div {
490 compatible = "rockchip,rk3188-div-con";
491 rockchip,bits = <0 5>;
492 clocks = <&clk_core_l>;
493 clock-output-names = "atclk_core_l";
494 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
496 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
501 pclk_dbg_l: pclk_dbg_l_div {
502 compatible = "rockchip,rk3188-div-con";
503 rockchip,bits = <8 5>;
504 clocks = <&clk_core_l>;
505 clock-output-names = "pclk_dbg_l";
506 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
508 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
512 clk_sel_con4: sel-con@0110 {
513 compatible = "rockchip,rk3188-selcon";
515 #address-cells = <1>;
518 clk_cs_div: clk_cs_div {
519 compatible = "rockchip,rk3188-div-con";
520 rockchip,bits = <0 5>;
522 clock-output-names = "clk_cs";
523 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
525 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
526 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
532 compatible = "rockchip,rk3188-mux-con";
533 rockchip,bits = <6 2>;
534 clocks = <&clk_gates0 9>, <&clk_gates0 10>, <&clk_gates0 8>, <&dummy>;
535 clock-output-names = "clk_cs";
537 #clock-init-cells = <1>;
540 clkin_trace: clkin_trace_div {
541 compatible = "rockchip,rk3188-div-con";
542 rockchip,bits = <8 5>;
544 clock-output-names = "clkin_trace";
545 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
547 #clock-init-cells = <1>;
552 clk_sel_con5: sel-con@0114 {
553 compatible = "rockchip,rk3188-selcon";
555 #address-cells = <1>;
558 aclk_cci_div: aclk_cci_div {
559 compatible = "rockchip,rk3188-div-con";
560 rockchip,bits = <0 5>;
561 clocks = <&aclk_cci>;
562 clock-output-names = "aclk_cci";
563 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
565 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
570 aclk_cci: aclk_cci_mux {
571 compatible = "rockchip,rk3188-mux-con";
572 rockchip,bits = <6 2>;
573 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
574 clock-output-names = "aclk_cci";
576 #clock-init-cells = <1>;
580 /* sel[7:6] reserved */
582 clk_sel_con8: sel-con@0120 {
583 compatible = "rockchip,rk3188-selcon";
585 #address-cells = <1>;
588 aclk_bus_div: aclk_bus_div {
589 compatible = "rockchip,rk3188-div-con";
590 rockchip,bits = <0 5>;
591 clocks = <&aclk_bus>;
592 clock-output-names = "aclk_bus";
593 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
595 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
600 aclk_bus: aclk_bus_mux {
601 compatible = "rockchip,rk3188-mux-con";
602 rockchip,bits = <7 1>;
603 clocks = <&clk_gates1 11>, <&clk_gates1 10>;
604 clock-output-names = "aclk_bus";
606 #clock-init-cells = <1>;
609 hclk_bus: hclk_bus_div {
610 compatible = "rockchip,rk3188-div-con";
611 rockchip,bits = <8 2>;
612 clocks = <&aclk_bus>;
613 clock-output-names = "hclk_bus";
614 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
616 #clock-init-cells = <1>;
621 pclk_bus: pclk_bus_div {
622 compatible = "rockchip,rk3188-div-con";
623 rockchip,bits = <12 3>;
624 clocks = <&aclk_bus>;
625 clock-output-names = "pclk_bus";
626 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
628 #clock-init-cells = <1>;
632 clk_sel_con9: sel-con@0124 {
633 compatible = "rockchip,rk3188-selcon";
635 #address-cells = <1>;
638 aclk_peri_div: aclk_peri_div {
639 compatible = "rockchip,rk3188-div-con";
640 rockchip,bits = <0 5>;
641 clocks = <&aclk_peri>;
642 clock-output-names = "aclk_peri";
643 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
645 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
650 aclk_peri: aclk_peri_mux {
651 compatible = "rockchip,rk3188-mux-con";
652 rockchip,bits = <7 1>;
653 clocks = <&clk_cpll>, <&clk_gpll>;
654 clock-output-names = "aclk_peri";
656 #clock-init-cells = <1>;
659 hclk_peri: hclk_peri_div {
660 compatible = "rockchip,rk3188-div-con";
661 rockchip,bits = <8 2>;
662 clocks = <&aclk_peri>;
663 clock-output-names = "hclk_peri";
664 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
665 rockchip,div-relations =
670 #clock-init-cells = <1>;
675 pclk_peri: pclk_peri_div {
676 compatible = "rockchip,rk3188-div-con";
677 rockchip,bits = <12 2>;
678 clocks = <&aclk_peri>;
679 clock-output-names = "pclk_peri";
680 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
681 rockchip,div-relations =
687 #clock-init-cells = <1>;
691 clk_sel_con10: sel-con@0128 {
692 compatible = "rockchip,rk3188-selcon";
694 #address-cells = <1>;
697 pclk_pmu_pre: pclk_pmu_pre_div {
698 compatible = "rockchip,rk3188-div-con";
699 rockchip,bits = <0 5>;
700 clocks = <&clk_gpll>;
701 clock-output-names = "pclk_pmu_pre";
702 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
704 #clock-init-cells = <1>;
709 pclk_alive_pre: pclk_alive_pre_div {
710 compatible = "rockchip,rk3188-div-con";
711 rockchip,bits = <8 5>;
712 clocks = <&clk_gpll>;
713 clock-output-names = "pclk_alive_pre";
714 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
716 #clock-init-cells = <1>;
721 clk_crypto: clk_crypto_div {
722 compatible = "rockchip,rk3188-div-con";
723 rockchip,bits = <14 2>;
724 clocks = <&aclk_bus>;
725 clock-output-names = "clk_crypto";
726 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
728 #clock-init-cells = <1>;
732 /* sel[11]: reserved */
734 clk_sel_con12: sel-con@0130 {
735 compatible = "rockchip,rk3188-selcon";
737 #address-cells = <1>;
740 fclk_mcu_div: fclk_mcu_div {
741 compatible = "rockchip,rk3188-div-con";
742 rockchip,bits = <0 5>;
743 clocks = <&fclk_mcu>;
744 clock-output-names = "fclk_mcu";
745 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
747 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
752 fclk_mcu: fclk_mcu_mux {
753 compatible = "rockchip,rk3188-mux-con";
754 rockchip,bits = <7 1>;
755 clocks = <&clk_cpll>, <&clk_gpll>;
756 clock-output-names = "fclk_mcu";
758 #clock-init-cells = <1>;
761 stclk_mcu: stclk_mcu_div {
762 compatible = "rockchip,rk3188-div-con";
763 rockchip,bits = <8 3>;
764 clocks = <&fclk_mcu>;
765 clock-output-names = "stclk_mcu";
766 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
771 clk_sel_con13: sel-con@0134 {
772 compatible = "rockchip,rk3188-selcon";
774 #address-cells = <1>;
777 clk_ddr_div: clk_ddr_div {
778 compatible = "rockchip,rk3188-div-con";
779 rockchip,bits = <0 2>;
781 clock-output-names = "clk_ddr";
782 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
784 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
785 CLK_SET_RATE_NO_REPARENT)>;
786 rockchip,clkops-idx =
787 <CLKOPS_RATE_DDR_DIV4>;
792 clk_ddr: clk_ddr_mux {
793 compatible = "rockchip,rk3188-mux-con";
794 rockchip,bits = <4 1>;
795 clocks = <&clk_dpll>, <&clk_gpll>;
796 clock-output-names = "clk_ddr";
802 usbphy_480m: usbphy_480m_mux {
803 compatible = "rockchip,rk3188-mux-con";
804 rockchip,bits = <8 1>;
805 clocks = <&xin24m>, <&usbotg_480m_out>;
806 clock-output-names = "usbphy_480m";
808 rockchip,clkops-idx =
809 <CLKOPS_RATE_RK3288_USB480M>;
810 #clock-init-cells = <1>;
814 clk_sel_con14: sel-con@0138 {
815 compatible = "rockchip,rk3188-selcon";
817 #address-cells = <1>;
820 clk_gpu_core_div: clk_gpu_core_div {
821 compatible = "rockchip,rk3188-div-con";
822 rockchip,bits = <0 5>;
823 clocks = <&clk_gpu_core>;
824 clock-output-names = "clk_gpu";
825 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
827 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
828 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
833 clk_gpu_core: clk_gpu_core_mux {
834 compatible = "rockchip,rk3188-mux-con";
835 rockchip,bits = <6 2>;
836 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
837 clock-output-names = "clk_gpu";
839 #clock-init-cells = <1>;
842 aclk_gpu_mem: aclk_gpu_mem_div {
843 compatible = "rockchip,rk3188-div-con";
844 rockchip,bits = <8 5>;
845 clocks = <&aclk_gpu>;
846 clock-output-names = "aclk_gpu_mem";
847 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
849 #clock-init-cells = <1>;
854 aclk_gpu: aclk_gpu_mux {
855 compatible = "rockchip,rk3188-mux-con";
856 rockchip,bits = <14 1>;
857 clocks = <&clk_cpll>, <&clk_gpll>;
858 clock-output-names = "aclk_gpu";
860 #clock-init-cells = <1>;
864 clk_sel_con15: sel-con@013c {
865 compatible = "rockchip,rk3188-selcon";
867 #address-cells = <1>;
870 aclk_vepu_div: aclk_vepu_div {
871 compatible = "rockchip,rk3188-div-con";
872 rockchip,bits = <0 5>;
873 clocks = <&aclk_vepu>;
874 clock-output-names = "aclk_vepu";
875 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
877 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
882 aclk_vepu: aclk_vepu_mux {
883 compatible = "rockchip,rk3188-mux-con";
884 rockchip,bits = <6 2>;
885 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
886 clock-output-names = "aclk_vepu";
888 #clock-init-cells = <1>;
891 aclk_vdpu_div: aclk_vdpu_div {
892 compatible = "rockchip,rk3188-div-con";
893 rockchip,bits = <8 5>;
894 clocks = <&aclk_vdpu>;
895 clock-output-names = "aclk_vdpu";
896 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
898 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
903 aclk_vdpu: aclk_vdpu_mux {
904 compatible = "rockchip,rk3188-mux-con";
905 rockchip,bits = <14 2>;
906 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
907 clock-output-names = "aclk_vdpu";
909 #clock-init-cells = <1>;
913 clk_sel_con16: sel-con@0140 {
914 compatible = "rockchip,rk3188-selcon";
916 #address-cells = <1>;
919 aclk_gpu_cfg: aclk_gpu_cfg_div {
920 compatible = "rockchip,rk3188-div-con";
921 rockchip,bits = <8 5>;
922 clocks = <&aclk_gpu>;
923 clock-output-names = "aclk_gpu_cfg";
924 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
926 #clock-init-cells = <1>;
930 clk_sel_con17: sel-con@0144 {
931 compatible = "rockchip,rk3188-selcon";
933 #address-cells = <1>;
936 clk_hevc_cabac_div: clk_hevc_cabac_div {
937 compatible = "rockchip,rk3188-div-con";
938 rockchip,bits = <0 5>;
939 clocks = <&clk_hevc_cabac>;
940 clock-output-names = "clk_hevc_cabac";
941 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
943 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
948 clk_hevc_cabac: clk_hevc_cabac_mux {
949 compatible = "rockchip,rk3188-mux-con";
950 rockchip,bits = <6 2>;
951 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
952 clock-output-names = "clk_hevc_cabac";
954 #clock-init-cells = <1>;
957 clk_hevc_core_div: clk_hevc_core_div {
958 compatible = "rockchip,rk3188-div-con";
959 rockchip,bits = <8 5>;
960 clocks = <&clk_hevc_core>;
961 clock-output-names = "clk_hevc_core";
962 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
964 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
969 clk_hevc_core: clk_hevc_core_mux {
970 compatible = "rockchip,rk3188-mux-con";
971 rockchip,bits = <14 2>;
972 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
973 clock-output-names = "clk_hevc_core";
975 #clock-init-cells = <1>;
979 clk_sel_con18: sel-con@0148 {
980 compatible = "rockchip,rk3188-selcon";
982 #address-cells = <1>;
985 clk_rga_div: clk_rga_div {
986 compatible = "rockchip,rk3188-div-con";
987 rockchip,bits = <0 5>;
989 clock-output-names = "clk_rga";
990 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
992 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
997 clk_rga: clk_rga_mux {
998 compatible = "rockchip,rk3188-mux-con";
999 rockchip,bits = <6 2>;
1000 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
1001 clock-output-names = "clk_rga";
1003 #clock-init-cells = <1>;
1006 aclk_rga_div: aclk_rga_div {
1007 compatible = "rockchip,rk3188-div-con";
1008 rockchip,bits = <8 5>;
1009 clocks = <&aclk_rga_pre>;
1010 clock-output-names = "aclk_rga_pre";
1011 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1013 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1018 aclk_rga_pre: aclk_rga_mux {
1019 compatible = "rockchip,rk3188-mux-con";
1020 rockchip,bits = <14 2>;
1021 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
1022 clock-output-names = "aclk_rga_pre";
1024 #clock-init-cells = <1>;
1028 clk_sel_con19: sel-con@014c {
1029 compatible = "rockchip,rk3188-selcon";
1031 #address-cells = <1>;
1034 aclk_vio0_div: aclk_vio0_div {
1035 compatible = "rockchip,rk3188-div-con";
1036 rockchip,bits = <0 5>;
1037 clocks = <&aclk_vio0>;
1038 clock-output-names = "aclk_vio0";
1039 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1041 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1046 aclk_vio0: aclk_vio0_mux {
1047 compatible = "rockchip,rk3188-mux-con";
1048 rockchip,bits = <6 2>;
1049 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
1050 clock-output-names = "aclk_vio0";
1052 #clock-init-cells = <1>;
1056 clk_sel_con20: sel-con@0150 {
1057 compatible = "rockchip,rk3188-selcon";
1059 #address-cells = <1>;
1062 dclk_vop0_div: dclk_vop0_div {
1063 compatible = "rockchip,rk3188-div-con";
1064 rockchip,bits = <0 8>;
1065 clocks = <&dclk_vop0>;
1066 clock-output-names = "dclk_vop0";
1067 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1069 rockchip,clkops-idx =
1070 <CLKOPS_RATE_RK3368_DCLK_LCDC>;
1071 rockchip,flags = <CLK_SET_RATE_PARENT>;
1075 dclk_vop0: dclk_vop0_mux {
1076 compatible = "rockchip,rk3188-mux-con";
1077 rockchip,bits = <8 2>;
1078 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&dummy>;
1079 clock-output-names = "dclk_vop0";
1081 #clock-init-cells = <1>;
1084 /* 15:10 reserved */
1087 clk_sel_con21: sel-con@0154 {
1088 compatible = "rockchip,rk3188-selcon";
1090 #address-cells = <1>;
1093 hclk_vio: hclk_vio_div {
1094 compatible = "rockchip,rk3188-div-con";
1095 rockchip,bits = <0 5>;
1096 clocks = <&aclk_vio0>;
1097 clock-output-names = "hclk_vio";
1098 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1100 #clock-init-cells = <1>;
1105 pclk_isp: pclk_isp_mux {
1106 compatible = "rockchip,rk3188-mux-con";
1107 rockchip,bits = <6 1>;
1108 clocks = <&clk_gates17 2>, <&pclkin_isp_inv>;
1109 clock-output-names = "pclk_isp";
1115 clk_vip_div: clk_vip_div {
1116 compatible = "rockchip,rk3188-div-con";
1117 rockchip,bits = <8 5>;
1118 clocks = <&clk_vip>;
1119 clock-output-names = "clk_vip";
1120 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1122 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1125 pclk_vip: pclk_vip_mux {
1126 compatible = "rockchip,rk3188-mux-con";
1127 rockchip,bits = <13 1>;
1128 clocks = <&clk_gates16 13>, <&pclkin_vip_inv>;
1129 clock-output-names = "pclk_vip";
1133 clk_vip: clk_vip_mux {
1134 compatible = "rockchip,rk3188-mux-con";
1135 rockchip,bits = <14 1>;
1136 clocks = <&clk_vip_pll>, <&xin24m>;
1137 clock-output-names = "clk_vip";
1139 #clock-init-cells = <1>;
1142 clk_vip_pll: clk_vip_pll_mux {
1143 compatible = "rockchip,rk3188-mux-con";
1144 rockchip,bits = <15 1>;
1145 clocks = <&clk_cpll>, <&clk_gpll>;
1146 clock-output-names = "clk_vip_pll";
1148 #clock-init-cells = <1>;
1152 clk_sel_con22: sel-con@0158 {
1153 compatible = "rockchip,rk3188-selcon";
1155 #address-cells = <1>;
1158 clk_isp_div: clk_isp_div {
1159 compatible = "rockchip,rk3188-div-con";
1160 rockchip,bits = <0 6>;
1161 clocks = <&clk_isp>;
1162 clock-output-names = "clk_isp";
1163 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1165 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1168 clk_isp: clk_isp_mux {
1169 compatible = "rockchip,rk3188-mux-con";
1170 rockchip,bits = <6 2>;
1171 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1172 clock-output-names = "clk_isp";
1174 #clock-init-cells = <1>;
1178 clk_sel_con23: sel-con@015c {
1179 compatible = "rockchip,rk3188-selcon";
1181 #address-cells = <1>;
1184 clk_edp_div: clk_edp_div {
1185 compatible = "rockchip,rk3188-div-con";
1186 rockchip,bits = <0 6>;
1187 clocks = <&clk_edp>;
1188 clock-output-names = "clk_edp";
1189 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1191 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1194 clk_edp: clk_edp_mux {
1195 compatible = "rockchip,rk3188-mux-con";
1196 rockchip,bits = <6 2>;
1197 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1198 clock-output-names = "clk_edp";
1200 #clock-init-cells = <1>;
1203 clk_edp_24m: clk_edp_24m_mux {
1204 compatible = "rockchip,rk3188-mux-con";
1205 rockchip,bits = <8 1>;
1206 clocks = <&xin24m>, <&dummy>;
1207 clock-output-names = "clk_edp_24m";
1212 /* sel[24]: reserved */
1214 clk_sel_con25: sel-con@0164 {
1215 compatible = "rockchip,rk3188-selcon";
1217 #address-cells = <1>;
1220 clk_tsadc: clk_tsadc_div {
1221 compatible = "rockchip,rk3188-div-con";
1222 rockchip,bits = <0 6>;
1223 clocks = <&clk_32k_mux>;
1224 clock-output-names = "clk_tsadc";
1225 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1231 clk_saradc: clk_saradc_div {
1232 compatible = "rockchip,rk3188-div-con";
1233 rockchip,bits = <8 8>;
1235 clock-output-names = "clk_saradc";
1236 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1241 clk_sel_con26: sel-con@0168 {
1242 compatible = "rockchip,rk3188-selcon";
1244 #address-cells = <1>;
1249 hsic_usb_480m: hsic_usb_480m_mux {
1250 compatible = "rockchip,rk3188-mux-con";
1251 rockchip,bits = <8 1>;
1252 clocks = <&usbotg_480m_out>, <&dummy>;
1253 clock-output-names = "hsic_usb_480m";
1259 hsicphy_480m: hsicphy_480m_mux {
1260 compatible = "rockchip,rk3188-mux-con";
1261 rockchip,bits = <12 2>;
1262 clocks = <&clk_cpll>, <&clk_gpll>, <&hsic_usb_480m>, <&hsic_usb_480m>;
1263 clock-output-names = "hsicphy_480m";
1268 clk_sel_con27: sel-con@016c {
1269 compatible = "rockchip,rk3188-selcon";
1271 #address-cells = <1>;
1274 i2s_pll_div: i2s_pll_div {
1275 compatible = "rockchip,rk3188-div-con";
1276 rockchip,bits = <0 7>;
1277 clocks = <&i2s_pll>;
1278 clock-output-names = "i2s_pll";
1279 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1281 rockchip,clkops-idx =
1282 <CLKOPS_RATE_MUX_DIV>;
1283 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1288 clk_i2s: clk_i2s_mux {
1289 compatible = "rockchip,rk3188-mux-con";
1290 rockchip,bits = <8 2>;
1291 clocks = <&i2s_pll>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
1292 clock-output-names = "clk_i2s";
1294 rockchip,clkops-idx =
1295 <CLKOPS_RATE_RK3288_I2S>;
1296 rockchip,flags = <CLK_SET_RATE_PARENT>;
1299 /* 11:10 reserved */
1301 i2s_pll: i2s_pll_mux {
1302 compatible = "rockchip,rk3188-mux-con";
1303 rockchip,bits = <12 1>;
1304 clocks = <&clk_cpll>, <&clk_gpll>;
1305 clock-output-names = "i2s_pll";
1307 #clock-init-cells = <1>;
1310 /* 14:13 reserved */
1312 i2s_out: i2s_out_mux {
1313 compatible = "rockchip,rk3188-mux-con";
1314 rockchip,bits = <15 1>;
1315 clocks = <&clk_i2s>, <&xin12m>;
1316 clock-output-names = "i2s_out";
1321 clk_sel_con28: sel-con@0170 {
1322 compatible = "rockchip,rk3188-selcon";
1324 #address-cells = <1>;
1327 i2s_frac: i2s_frac {
1328 compatible = "rockchip,rk3188-frac-con";
1329 clocks = <&i2s_pll>;
1330 clock-output-names = "i2s_frac";
1331 /* numerator denominator */
1332 rockchip,bits = <0 32>;
1333 rockchip,clkops-idx =
1339 /* sel[30:29] reserved */
1341 clk_sel_con31: sel-con@017c {
1342 compatible = "rockchip,rk3188-selcon";
1344 #address-cells = <1>;
1348 spdif_8ch_pll_div: spdif_8ch_pll_div {
1349 compatible = "rockchip,rk3188-div-con";
1350 rockchip,bits = <0 7>;
1351 clocks = <&spdif_8ch_pll>;
1352 clock-output-names = "spdif_8ch_pll";
1353 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1355 rockchip,clkops-idx =
1356 <CLKOPS_RATE_MUX_DIV>;
1357 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1362 clk_spidf_8ch: clk_spidf_8ch_mux {
1363 compatible = "rockchip,rk3188-mux-con";
1364 rockchip,bits = <8 2>;
1365 clocks = <&spdif_8ch_pll>, <&spdif_8ch_frac>, <&i2s_clkin>, <&xin12m>;
1366 clock-output-names = "clk_spidf_8ch";
1368 rockchip,clkops-idx =
1369 <CLKOPS_RATE_RK3288_I2S>;
1370 rockchip,flags = <CLK_SET_RATE_PARENT>;
1373 /* 11:10 reserved */
1375 spdif_8ch_pll: spdif_8ch_pll_mux {
1376 compatible = "rockchip,rk3188-mux-con";
1377 rockchip,bits = <12 1>;
1378 clocks = <&clk_cpll>, <&clk_gpll>;
1379 clock-output-names = "spdif_8ch_pll";
1381 #clock-init-cells = <1>;
1384 /* 15:13 reserved */
1387 clk_sel_con32: sel-con@0180 {
1388 compatible = "rockchip,rk3188-selcon";
1390 #address-cells = <1>;
1393 spdif_8ch_frac: spdif_8ch_frac {
1394 compatible = "rockchip,rk3188-frac-con";
1395 clocks = <&spdif_8ch_pll>;
1396 clock-output-names = "spdif_8ch_frac";
1397 /* numerator denominator */
1398 rockchip,bits = <0 32>;
1399 rockchip,clkops-idx =
1405 clk_sel_con33: sel-con@0184 {
1406 compatible = "rockchip,rk3188-selcon";
1408 #address-cells = <1>;
1411 clk_uart0_pll_div: clk_uart0_pll_div {
1412 compatible = "rockchip,rk3188-div-con";
1413 rockchip,bits = <0 7>;
1414 clocks = <&clk_uart0_pll>;
1415 clock-output-names = "clk_uart0_pll";
1416 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1418 rockchip,clkops-idx =
1419 <CLKOPS_RATE_MUX_DIV>;
1424 clk_uart0: clk_uart0_mux {
1425 compatible = "rockchip,rk3188-mux-con";
1426 rockchip,bits = <8 2>;
1427 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>, <&xin24m>;
1428 clock-output-names = "clk_uart0";
1430 rockchip,clkops-idx =
1431 <CLKOPS_RATE_RK3288_I2S>;
1432 rockchip,flags = <CLK_SET_RATE_PARENT>;
1435 /* 11:10 reserved */
1437 clk_uart0_pll: clk_uart0_pll_mux {
1438 compatible = "rockchip,rk3188-mux-con";
1439 rockchip,bits = <12 2>;
1440 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
1441 clock-output-names = "clk_uart0_pll";
1446 clk_sel_con34: sel-con@0188 {
1447 compatible = "rockchip,rk3188-selcon";
1449 #address-cells = <1>;
1452 uart0_frac: uart0_frac {
1453 compatible = "rockchip,rk3188-frac-con";
1454 clocks = <&clk_uart0_pll>;
1455 clock-output-names = "uart0_frac";
1456 /* numerator denominator */
1457 rockchip,bits = <0 32>;
1458 rockchip,clkops-idx =
1464 clk_sel_con35: sel-con@018c {
1465 compatible = "rockchip,rk3188-selcon";
1467 #address-cells = <1>;
1470 uart1_div: uart1_div {
1471 compatible = "rockchip,rk3188-div-con";
1472 rockchip,bits = <0 7>;
1473 clocks = <&clk_uart_pll>;
1474 clock-output-names = "uart1_div";
1475 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1481 clk_uart1: clk_uart1_mux {
1482 compatible = "rockchip,rk3188-mux-con";
1483 rockchip,bits = <8 2>;
1484 clocks = <&uart1_div>, <&uart1_frac>, <&xin24m>, <&xin24m>;
1485 clock-output-names = "clk_uart1";
1487 rockchip,clkops-idx =
1488 <CLKOPS_RATE_RK3288_I2S>;
1489 rockchip,flags = <CLK_SET_RATE_PARENT>;
1492 /* 11:10 reserved */
1494 clk_uart_pll: clk_uart_pll_mux {
1495 compatible = "rockchip,rk3188-mux-con";
1496 rockchip,bits = <12 1>;
1497 clocks = <&clk_cpll>, <&clk_gpll>;
1498 clock-output-names = "clk_uart_pll";
1500 #clock-init-cells = <1>;
1504 clk_sel_con36: sel-con@0190 {
1505 compatible = "rockchip,rk3188-selcon";
1507 #address-cells = <1>;
1510 uart1_frac: uart1_frac {
1511 compatible = "rockchip,rk3188-frac-con";
1512 clocks = <&uart1_div>;
1513 clock-output-names = "uart1_frac";
1514 /* numerator denominator */
1515 rockchip,bits = <0 32>;
1516 rockchip,clkops-idx =
1522 clk_sel_con37: sel-con@0194 {
1523 compatible = "rockchip,rk3188-selcon";
1525 #address-cells = <1>;
1528 uart2_div: uart2_div {
1529 compatible = "rockchip,rk3188-div-con";
1530 rockchip,bits = <0 7>;
1531 clocks = <&clk_uart_pll>;
1532 clock-output-names = "uart2_div";
1533 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1539 clk_uart2: clk_uart2_mux {
1540 compatible = "rockchip,rk3188-mux-con";
1541 rockchip,bits = <8 1>;
1542 clocks = <&uart2_div>, <&xin24m>;
1543 clock-output-names = "clk_uart2";
1545 rockchip,flags = <CLK_SET_RATE_PARENT>;
1549 /* sel[38] reserved */
1551 clk_sel_con39: sel-con@019c {
1552 compatible = "rockchip,rk3188-selcon";
1554 #address-cells = <1>;
1557 uart3_div: uart3_div {
1558 compatible = "rockchip,rk3188-div-con";
1559 rockchip,bits = <0 7>;
1560 clocks = <&clk_uart_pll>;
1561 clock-output-names = "uart3_div";
1562 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1568 clk_uart3: clk_uart3_mux {
1569 compatible = "rockchip,rk3188-mux-con";
1570 rockchip,bits = <8 2>;
1571 clocks = <&uart3_div>, <&uart3_frac>, <&xin24m>, <&xin24m>;
1572 clock-output-names = "clk_uart3";
1574 rockchip,clkops-idx =
1575 <CLKOPS_RATE_RK3288_I2S>;
1576 rockchip,flags = <CLK_SET_RATE_PARENT>;
1580 clk_sel_con40: sel-con@01a0 {
1581 compatible = "rockchip,rk3188-selcon";
1583 #address-cells = <1>;
1586 uart3_frac: uart3_frac {
1587 compatible = "rockchip,rk3188-frac-con";
1588 clocks = <&uart3_div>;
1589 clock-output-names = "uart3_frac";
1590 /* numerator denominator */
1591 rockchip,bits = <0 32>;
1592 rockchip,clkops-idx =
1598 clk_sel_con41: sel-con@01a4 {
1599 compatible = "rockchip,rk3188-selcon";
1601 #address-cells = <1>;
1604 uart4_div: uart4_div {
1605 compatible = "rockchip,rk3188-div-con";
1606 rockchip,bits = <0 7>;
1607 clocks = <&clk_uart_pll>;
1608 clock-output-names = "uart4_div";
1609 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1615 clk_uart4: clk_uart4_mux {
1616 compatible = "rockchip,rk3188-mux-con";
1617 rockchip,bits = <8 2>;
1618 clocks = <&uart4_div>, <&uart4_frac>, <&xin24m>, <&xin24m>;
1619 clock-output-names = "clk_uart4";
1621 rockchip,clkops-idx =
1622 <CLKOPS_RATE_RK3288_I2S>;
1623 rockchip,flags = <CLK_SET_RATE_PARENT>;
1627 clk_sel_con42: sel-con@01a8 {
1628 compatible = "rockchip,rk3188-selcon";
1630 #address-cells = <1>;
1633 uart4_frac: uart4_frac {
1634 compatible = "rockchip,rk3188-frac-con";
1635 clocks = <&uart4_div>;
1636 clock-output-names = "uart4_frac";
1637 /* numerator denominator */
1638 rockchip,bits = <0 32>;
1639 rockchip,clkops-idx =
1645 clk_sel_con43: sel-con@01ac {
1646 compatible = "rockchip,rk3188-selcon";
1648 #address-cells = <1>;
1651 clk_mac_pll_div: clk_mac_pll_div {
1652 compatible = "rockchip,rk3188-div-con";
1653 rockchip,bits = <0 5>;
1654 clocks = <&clk_mac_pll>;
1655 clock-output-names = "clk_mac_pll";
1656 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1658 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1663 clk_mac_pll: clk_mac_pll_mux {
1664 compatible = "rockchip,rk3188-mux-con";
1665 rockchip,bits = <6 2>;
1666 clocks = <&clk_npll>, <&clk_cpll>, <&clk_gpll>, <&clk_gpll>;
1667 clock-output-names = "clk_mac_pll";
1671 clk_mac: clk_mac_mux {
1672 compatible = "rockchip,rk3188-mux-con";
1673 rockchip,bits = <8 1>;
1674 clocks = <&clk_mac_pll>, <&gmac_clkin>;
1675 clock-output-names = "clk_mac";
1677 rockchip,flags = <CLK_SET_RATE_PARENT>;
1678 #clock-init-cells = <1>;
1683 /* 12: test_clk: wifi_pll_sel */
1685 /* 15:13 reserved */
1688 clk_sel_con44: sel-con@01b0 {
1689 compatible = "rockchip,rk3188-selcon";
1691 #address-cells = <1>;
1694 /* test_clk: wifi_frac */
1697 clk_sel_con45: sel-con@01b4 {
1698 compatible = "rockchip,rk3188-selcon";
1700 #address-cells = <1>;
1703 clk_spi0_div: clk_spi0_div {
1704 compatible = "rockchip,rk3188-div-con";
1705 rockchip,bits = <0 7>;
1706 clocks = <&clk_spi0>;
1707 clock-output-names = "clk_spi0";
1708 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1710 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1713 clk_spi0: clk_spi0_mux {
1714 compatible = "rockchip,rk3188-mux-con";
1715 rockchip,bits = <7 1>;
1716 clocks = <&clk_cpll>, <&clk_gpll>;
1717 clock-output-names = "clk_spi0";
1721 clk_spi1_div: clk_spi1_div {
1722 compatible = "rockchip,rk3188-div-con";
1723 rockchip,bits = <8 7>;
1724 clocks = <&clk_spi1>;
1725 clock-output-names = "clk_spi1";
1726 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1728 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1731 clk_spi1: clk_spi1_mux {
1732 compatible = "rockchip,rk3188-mux-con";
1733 rockchip,bits = <15 1>;
1734 clocks = <&clk_cpll>, <&clk_gpll>;
1735 clock-output-names = "clk_spi1";
1740 clk_sel_con46: sel-con@01b8 {
1741 compatible = "rockchip,rk3188-selcon";
1743 #address-cells = <1>;
1746 clk_tsp_div: clk_tsp_div {
1747 compatible = "rockchip,rk3188-div-con";
1748 rockchip,bits = <0 5>;
1749 clocks = <&clk_tsp>;
1750 clock-output-names = "clk_tsp";
1751 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1753 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1758 clk_tsp: clk_tsp_mux {
1759 compatible = "rockchip,rk3188-mux-con";
1760 rockchip,bits = <6 2>;
1761 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1762 clock-output-names = "clk_tsp";
1766 clk_spi2_div: clk_spi2_div {
1767 compatible = "rockchip,rk3188-div-con";
1768 rockchip,bits = <8 7>;
1769 clocks = <&clk_spi2>;
1770 clock-output-names = "clk_spi2";
1771 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1773 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1776 clk_spi2: clk_spi2_mux {
1777 compatible = "rockchip,rk3188-mux-con";
1778 rockchip,bits = <15 1>;
1779 clocks = <&clk_cpll>, <&clk_gpll>;
1780 clock-output-names = "clk_spi2";
1785 clk_sel_con47: sel-con@01bc {
1786 compatible = "rockchip,rk3188-selcon";
1788 #address-cells = <1>;
1791 clk_nandc0_div: clk_nandc0_div {
1792 compatible = "rockchip,rk3188-div-con";
1793 rockchip,bits = <0 5>;
1794 clocks = <&clk_nandc0>;
1795 clock-output-names = "clk_nandc0";
1796 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1798 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1803 clk_nandc0: clk_nandc0_mux {
1804 compatible = "rockchip,rk3188-mux-con";
1805 rockchip,bits = <7 1>;
1806 clocks = <&clk_cpll>, <&clk_gpll>;
1807 clock-output-names = "clk_nandc0";
1813 /* 15:13 reserved */
1816 clk_sel_con48: sel-con@01c0 {
1817 compatible = "rockchip,rk3188-selcon";
1819 #address-cells = <1>;
1822 clk_sdio0_div: clk_sdio0_div {
1823 compatible = "rockchip,rk3188-div-con";
1824 rockchip,bits = <0 7>;
1825 clocks = <&clk_sdio0>;
1826 clock-output-names = "clk_sdio0";
1827 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1829 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1834 clk_sdio0: clk_sdio0_mux {
1835 compatible = "rockchip,rk3188-mux-con";
1836 rockchip,bits = <8 2>;
1837 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1838 clock-output-names = "clk_sdio0";
1842 /* 15:10 reserved */
1845 /* sel[49] reserved */
1847 clk_sel_con50: sel-con@01c8 {
1848 compatible = "rockchip,rk3188-selcon";
1850 #address-cells = <1>;
1853 clk_sdmmc0_div: clk_sdmmc0_div {
1854 compatible = "rockchip,rk3188-div-con";
1855 rockchip,bits = <0 7>;
1856 clocks = <&clk_sdmmc0>;
1857 clock-output-names = "clk_sdmmc0";
1858 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1860 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1865 clk_sdmmc0: clk_sdmmc0_mux {
1866 compatible = "rockchip,rk3188-mux-con";
1867 rockchip,bits = <8 2>;
1868 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1869 clock-output-names = "clk_sdmmc0";
1873 /* 15:10 reserved */
1876 clk_sel_con51: sel-con@01cc {
1877 compatible = "rockchip,rk3188-selcon";
1879 #address-cells = <1>;
1882 clk_emmc_div: clk_emmc_div {
1883 compatible = "rockchip,rk3188-div-con";
1884 rockchip,bits = <0 7>;
1885 clocks = <&clk_emmc>;
1886 clock-output-names = "clk_emmc";
1887 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1889 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1894 clk_emmc: clk_emmc_mux {
1895 compatible = "rockchip,rk3188-mux-con";
1896 rockchip,bits = <8 2>;
1897 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1898 clock-output-names = "clk_emmc";
1902 /* 15:10 reserved */
1905 clk_sel_con52: sel-con@01d0 {
1906 compatible = "rockchip,rk3188-selcon";
1908 #address-cells = <1>;
1911 clk_sfc_div: clk_sfc_div {
1912 compatible = "rockchip,rk3188-div-con";
1913 rockchip,bits = <0 5>;
1914 clocks = <&clk_sfc>;
1915 clock-output-names = "clk_sfc";
1916 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1918 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1923 clk_sfc: clk_sfc_mux {
1924 compatible = "rockchip,rk3188-mux-con";
1925 rockchip,bits = <7 1>;
1926 clocks = <&clk_cpll>, <&clk_gpll>;
1927 clock-output-names = "clk_sfc";
1934 clk_sel_con53: sel-con@01d4 {
1935 compatible = "rockchip,rk3188-selcon";
1937 #address-cells = <1>;
1940 i2s_2ch_pll_div: i2s_2ch_pll_div {
1941 compatible = "rockchip,rk3188-div-con";
1942 rockchip,bits = <0 7>;
1943 clocks = <&i2s_2ch_pll>;
1944 clock-output-names = "i2s_2ch_pll";
1945 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1947 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1948 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1953 clk_i2s_2ch: clk_i2s_2ch_mux {
1954 compatible = "rockchip,rk3188-mux-con";
1955 rockchip,bits = <8 2>;
1956 clocks = <&i2s_2ch_pll>, <&i2s_2ch_frac>, <&dummy>, <&xin12m>;
1957 clock-output-names = "clk_i2s_2ch";
1959 rockchip,clkops-idx =
1960 <CLKOPS_RATE_RK3288_I2S>;
1961 rockchip,flags = <CLK_SET_RATE_PARENT>;
1964 /* 11:10 reserved */
1966 i2s_2ch_pll: i2s_2ch_pll_mux {
1967 compatible = "rockchip,rk3188-mux-con";
1968 rockchip,bits = <12 1>;
1969 clocks = <&clk_cpll>, <&clk_gpll>;
1970 clock-output-names = "i2s_2ch_pll";
1972 #clock-init-cells = <1>;
1977 clk_sel_con54: sel-con@01d8 {
1978 compatible = "rockchip,rk3188-selcon";
1980 #address-cells = <1>;
1983 i2s_2ch_frac: i2s_2ch_frac {
1984 compatible = "rockchip,rk3188-frac-con";
1985 clocks = <&i2s_2ch_pll>;
1986 clock-output-names = "i2s_2ch_frac";
1987 /* numerator denominator */
1988 rockchip,bits = <0 32>;
1989 rockchip,clkops-idx =
1995 clk_sel_con55: sel-con@01dc {
1996 compatible = "rockchip,rk3188-selcon";
1998 #address-cells = <1>;
2001 clk_hdcp_div: clk_hdcp_div {
2002 compatible = "rockchip,rk3188-div-con";
2003 rockchip,bits = <0 6>;
2004 clocks = <&clk_hdcp>;
2005 clock-output-names = "clk_hdcp";
2006 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
2008 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
2011 clk_hdcp: clk_hdcp_mux {
2012 compatible = "rockchip,rk3188-mux-con";
2013 rockchip,bits = <6 2>;
2014 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
2015 clock-output-names = "clk_hdcp";
2021 /* Gate control regs */
2023 compatible = "rockchip,rk-gate-cons";
2024 #address-cells = <1>;
2028 clk_gates0: gate-clk@0200 {
2029 compatible = "rockchip,rk3188-gate-clk";
2038 <&clk_gpll>, <&clk_apllb>,
2039 <&clk_aplll>, <&dummy>,
2041 <&aclk_cci>, <&clkin_trace>,
2044 clock-output-names =
2045 "reserved", "reserved",/* core_b_apll core_b_gpll */
2046 "reserved", "reserved",
2048 "reserved", "reserved",/* core_l_apll core_l_gpll */
2049 "reserved", "reserved",
2051 "g_clk_cs_gpll", "g_clk_cs_apllb",
2052 "g_clk_cs_aplll", "reserved",
2054 "aclk_cci", "clkin_trace",
2055 "reserved", "reserved";
2060 clk_gates1: gate-clk@0204 {
2061 compatible = "rockchip,rk3188-gate-clk";
2064 <&aclk_bus>, <&hclk_bus>,
2065 <&pclk_bus>, <&fclk_mcu>,
2071 <&clk_gpll>, <&clk_cpll>,
2076 clock-output-names =
2077 "aclk_bus", "hclk_bus",
2078 "pclk_bus", "fclk_mcu",
2080 "reserved", "reserved",
2081 "reserved", "reserved",
2083 "reserved", "reserved",/* ddr_dpll ddr_gpll */
2084 "aclk_bus_gpll", "aclk_bus_cpll",
2086 "reserved", "reserved",
2087 "reserved", "reserved";
2092 clk_gates2: gate-clk@0208 {
2093 compatible = "rockchip,rk3188-gate-clk";
2096 <&clk_uart0_pll>, <&uart0_frac>,
2097 <&uart1_div>, <&uart1_frac>,
2099 <&uart2_div>, <&dummy>,
2100 <&uart3_div>, <&uart3_frac>,
2102 <&uart4_div>, <&uart4_frac>,
2108 clock-output-names =
2109 "clk_uart0_pll", "uart0_frac",
2110 "uart1_div", "uart1_frac",
2112 "uart2_div", "reserved",
2113 "uart3_div", "uart3_frac",
2115 "uart4_div", "uart4_frac",
2116 "reserved", "reserved",
2118 "reserved", "reserved",
2119 "reserved", "reserved";
2124 clk_gates3: gate-clk@020c {
2125 compatible = "rockchip,rk3188-gate-clk";
2128 <&aclk_peri>, <&dummy>,
2129 <&hclk_peri>, <&pclk_peri>,
2131 <&clk_mac_pll>, <&clk_tsadc>,
2132 <&clk_saradc>, <&clk_spi0>,
2134 <&clk_spi1>, <&clk_spi2>,
2140 clock-output-names =
2141 "aclk_peri", "reserved", /* bit1: aclk_peri */
2142 "hclk_peri", "pclk_peri",
2144 "clk_mac_pll", "clk_tsadc",
2145 "clk_saradc", "clk_spi0",
2147 "clk_spi1", "clk_spi2",
2148 "reserved", "reserved",
2150 "reserved", "reserved",
2151 "reserved", "reserved";
2156 clk_gates4: gate-clk@0210 {
2157 compatible = "rockchip,rk3188-gate-clk";
2160 <&aclk_vio0>, <&dclk_vop0>,
2161 <&xin24m>, <&aclk_rga_pre>,
2163 <&clk_rga>, <&clk_vip_pll>,
2164 <&aclk_vepu>, <&aclk_vdpu>,
2166 <&dummy>, <&clk_isp>,
2167 <&dummy>, <&clk_gpu_core>,
2169 <&xin32k>, <&xin24m>,
2170 <&xin24m>, <&dummy>;
2172 clock-output-names =
2173 "aclk_vio0", "dclk_vop0",
2174 "clk_vop0_pwm", "aclk_rga_pre",
2176 "clk_rga", "clk_vip_pll",
2177 "aclk_vepu", "aclk_vdpu",
2179 "reserved", "clk_isp", /* bit8: hclk_vpu */
2180 "reserved", "clk_gpu",
2182 "clk_hdmi_cec", "clk_hdmi_hdcp",
2183 "clk_dsiphy_24m", "reserved";
2188 clk_gates5: gate-clk@0214 {
2189 compatible = "rockchip,rk3188-gate-clk";
2192 <&dummy>, <&clk_hevc_cabac>,
2193 <&clk_hevc_core>, <&clk_edp>,
2195 <&clk_edp_24m>, <&clk_hdcp>,
2198 <&aclk_gpu_mem>, <&aclk_gpu_cfg>,
2201 <&dummy>, <&i2s_2ch_pll>,
2202 <&i2s_2ch_frac>, <&clk_i2s_2ch>;
2204 clock-output-names =
2205 "reserved", "clk_hevc_cabac",
2206 "clk_hevc_core", "clk_edp",
2208 "clk_edp_24m", "clk_hdcp",
2209 "reserved", "reserved",
2211 "aclk_gpu_mem", "aclk_gpu_cfg",
2212 "reserved", "reserved",
2214 "reserved", "i2s_2ch_pll",
2215 "i2s_2ch_frac", "clk_i2s_2ch";
2220 clk_gates6: gate-clk@0218 {
2221 compatible = "rockchip,rk3188-gate-clk";
2224 <&i2s_out>, <&i2s_pll>,
2225 <&i2s_frac>, <&clk_i2s>,
2227 <&spdif_8ch_pll>, <&spdif_8ch_frac>,
2228 <&clk_spidf_8ch>, <&clk_sfc>,
2233 <&clk_tsp>, <&dummy>,
2236 clock-output-names =
2237 "i2s_out", "i2s_pll",
2238 "i2s_frac", "clk_i2s",
2240 "spdif_8ch_pll", "spdif_8ch_frac",
2241 "clk_spidf_8ch", "clk_sfc",
2243 "reserved", "reserved",
2244 "reserved", "reserved",
2246 "clk_tsp", "reserved",
2247 "reserved", "reserved";/* clk_ddrphy_gate clk4x_ddrphy_gate */
2252 clk_gates7: gate-clk@021c {
2253 compatible = "rockchip,rk3188-gate-clk";
2256 <&jtag_clkin>, <&dummy>,
2257 <&clk_crypto>, <&xin24m>,
2260 <&clk_mac>, <&clk_mac>,
2262 <&clk_nandc0>, <&pclk_pmu_pre>,
2263 <&xin24m>, <&xin24m>,
2268 clock-output-names =
2269 "clk_jtag", "reserved",/* bit1: test_clk */
2270 "clk_crypto", "clk_pvtm_pmu",
2272 "clk_mac_rx", "clk_mac_tx",
2273 "clk_mac_ref", "clk_mac_refout",
2275 "clk_nandc0", "pclk_pmu_pre",
2276 "clk_pvtm_core", "clk_pvtm_gpu",
2278 "clk_sdmmc0", "clk_sdio0",
2279 "reserved", "clk_emmc";
2284 clk_gates8: gate-clk@0220 {
2285 compatible = "rockchip,rk3188-gate-clk";
2288 <&hsic_usb_480m>, <&xin24m>,
2291 <&clk_32k_mux>, <&dummy>,
2292 <&xin12m>, <&hsicphy_480m>,
2300 clock-output-names =
2301 "hsic_usb_480m", "clk_otgphy0",
2302 "reserved", "reserved",
2304 "g_clk_otg_adp", "reserved",/* bit4: clk_otg_adp */
2305 "hsicphy_12m", "hsicphy_480m",
2307 "reserved", "reserved",
2308 "reserved", "reserved",
2310 "reserved", "reserved",
2311 "reserved", "reserved";
2316 clk_gates9: gate-clk@0224 {
2317 compatible = "rockchip,rk3188-gate-clk";
2332 clock-output-names =
2333 "reserved", "reserved",
2334 "reserved", "reserved",
2336 "reserved", "reserved",
2337 "reserved", "reserved",
2339 "reserved", "reserved",
2340 "reserved", "reserved",
2342 "reserved", "reserved",
2343 "reserved", "reserved";
2348 clk_gates10: gate-clk@0228 {
2349 compatible = "rockchip,rk3188-gate-clk";
2364 clock-output-names =
2365 "reserved", "reserved",
2366 "reserved", "reserved",
2368 "reserved", "reserved",
2369 "reserved", "reserved",
2371 "reserved", "reserved",
2372 "reserved", "reserved",
2374 "reserved", "reserved",
2375 "reserved", "reserved";
2380 clk_gates11: gate-clk@022c {
2381 compatible = "rockchip,rk3188-gate-clk";
2396 clock-output-names =
2397 "reserved", "reserved",
2398 "reserved", "reserved",
2400 "reserved", "reserved",
2401 "reserved", "reserved",
2403 "reserved", "reserved",
2404 "reserved", "reserved",
2406 "reserved", "reserved",
2407 "reserved", "reserved";
2412 clk_gates12: gate-clk@0230 {
2413 compatible = "rockchip,rk3188-gate-clk";
2416 <&pclk_bus>, <&pclk_bus>,
2417 <&pclk_bus>, <&pclk_bus>,
2419 <&aclk_bus>, <&aclk_bus>,
2420 <&aclk_bus>, <&hclk_bus>,
2422 <&hclk_bus>, <&hclk_bus>,
2423 <&hclk_bus>, <&aclk_bus>,
2425 <&aclk_bus>, <&dummy>,
2428 clock-output-names =
2429 "g_pclk_pwm0", "g_p_mailbox",
2430 "g_p_i2cpmu", "g_p_i2caudio",
2432 "g_aclk_intmem", "g_clk_intmem0",
2433 "g_clk_intmem1", "g_h_i2s_8ch",
2435 "g_h_i2s_2ch", "g_hclk_rom",
2436 "g_hclk_spdif", "g_aclk_dmac",
2438 "g_a_strc_sys", "reserved",/* bit13: pclk_ddrupctl */
2439 "reserved", "reserved";/* bit14: pclk_ddrphy */
2444 clk_gates13: gate-clk@0234 {
2445 compatible = "rockchip,rk3188-gate-clk";
2448 <&pclk_bus>, <&pclk_bus>,
2449 <&dummy>, <&hclk_bus>,
2451 <&hclk_bus>, <&pclk_bus>,
2452 <&pclk_bus>, <&clkin_hsadc_tsp>,
2454 <&pclk_bus>, <&aclk_bus>,
2455 <&hclk_bus>, <&dummy>,
2460 clock-output-names =
2461 "g_p_efuse_1024", "g_p_efuse_256",
2462 "reserved", "g_mclk_crypto",/* bit2: nclk_ddrupctl */
2464 "g_sclk_crypto", "g_p_uartdbg",
2465 "g_pclk_pwm1", "clk_hsadc_tsp",
2467 "g_pclk_sim", "g_aclk_gic400",
2468 "g_hclk_tsp", "reserved",
2470 "reserved", "reserved",
2471 "reserved", "reserved";
2476 clk_gates14: gate-clk@0238 {
2477 compatible = "rockchip,rk3188-gate-clk";
2492 clock-output-names =
2493 "reserved", "reserved",
2494 "reserved", "reserved",
2496 "reserved", "reserved",
2497 "reserved", "reserved",
2499 "reserved", "reserved",
2500 "reserved", "reserved",
2502 "reserved", "reserved",
2503 "reserved", "reserved";
2508 clk_gates15: gate-clk@023c {
2509 compatible = "rockchip,rk3188-gate-clk";
2524 clock-output-names =
2525 "reserved", "reserved",/* aclk_video hclk_video */
2526 "reserved", "reserved",
2528 "reserved", "reserved",
2529 "reserved", "reserved",
2531 "reserved", "reserved",
2532 "reserved", "reserved",
2534 "reserved", "reserved",
2535 "reserved", "reserved";
2540 clk_gates16: gate-clk@0240 {
2541 compatible = "rockchip,rk3188-gate-clk";
2544 <&clk_gates16 10>, <&clk_gates16 8>,
2545 <&clk_gates16 9>, <&clk_gates16 8>,
2547 <&clk_gates16 9>, <&clk_gates16 9>,
2548 <&clk_gates16 8>, <&clk_gates17 8>,
2550 <&clk_gates16 7>, <&aclk_vio0>,
2551 <&aclk_rga_pre>, <&clk_gates16 9>,
2553 <&clk_gates16 8>, <&pclkin_vip>,
2554 <&clk_isp>, <&dummy>;
2556 clock-output-names =
2557 "g_aclk_rga", "g_hclk_rga",
2558 "g_aclk_iep", "g_hclk_iep",
2560 "g_aclk_vop_iep", "g_aclk_vop",
2561 "g_hclk_vop", "h_vio_ahb_arbi",
2563 "g_hclk_vio_noc", "g_aclk_vio0_noc",
2564 "g_aclk_vio1_noc", "g_aclk_vip",
2566 "g_hclk_vip", "g_pclkin_vip",
2567 "g_hclk_isp", "reserved";
2572 clk_gates17: gate-clk@0244 {
2573 compatible = "rockchip,rk3188-gate-clk";
2576 <&clk_isp>, <&dummy>,
2577 <&pclkin_isp>, <&pclk_vio>,
2579 <&pclk_vio>, <&dummy>,
2580 <&pclk_vio>, <&hclk_vio>,
2582 <&clk_gates17 7>, <&pclk_vio>,
2583 <&clk_gates16 10>, <&pclk_vio>,
2585 <&clk_gates16 8>, <&dummy>,
2588 clock-output-names =
2589 "g_aclk_isp", "reserved",
2590 "g_pclkin_isp", "g_p_mipi_dsi0",
2592 "g_p_mipi_csi", "reserved",
2593 "g_p_hdmi_ctrl", "g_hclk_vio_h2p",
2595 "g_pclk_vio_h2p", "g_p_edp_ctrl",
2596 "g_aclk_hdcp", "g_pclk_hdcp",
2598 "g_h_hdcpmmu", "reserved",
2599 "reserved", "reserved";
2604 clk_gates18: gate-clk@0248 {
2605 compatible = "rockchip,rk3188-gate-clk";
2620 clock-output-names =
2621 "reserved", "reserved",/* bit0-1: aclk_gpu_cfg aclk_gpu_mem */
2622 "reserved", "reserved",/* bit2: clk_gpu_core */
2624 "reserved", "reserved",
2625 "reserved", "reserved",
2627 "reserved", "reserved",
2628 "reserved", "reserved",
2630 "reserved", "reserved",
2631 "reserved", "reserved";
2636 clk_gates19: gate-clk@024c {
2637 compatible = "rockchip,rk3188-gate-clk";
2640 <&hclk_peri>, <&pclk_peri>,
2641 <&aclk_peri>, <&aclk_peri>,
2643 <&pclk_peri>, <&pclk_peri>,
2644 <&pclk_peri>, <&pclk_peri>,
2646 <&pclk_peri>, <&pclk_peri>,
2647 <&pclk_peri>, <&pclk_peri>,
2649 <&pclk_peri>, <&pclk_peri>,
2650 <&pclk_peri>, <&pclk_peri>;
2652 clock-output-names =
2653 "g_hp_axi_matrix", "g_pp_axi_matrix",
2654 "g_ap_axi_matrix", "g_a_dmac_peri",
2656 "g_pclk_spi0", "g_pclk_spi1",
2657 "g_pclk_spi2", "g_pclk_uart0",
2659 "g_pclk_uart1", "g_pclk_uart3",
2660 "g_pclk_uart4", "g_pclk_i2c2",
2662 "g_pclk_i2c3", "g_pclk_i2c4",
2663 "g_pclk_i2c5", "g_pclk_saradc";
2668 clk_gates20: gate-clk@0250 {
2669 compatible = "rockchip,rk3188-gate-clk";
2672 <&pclk_peri>, <&hclk_peri>,
2673 <&hclk_peri>, <&hclk_peri>,
2675 <&dummy>, <&hclk_peri>,
2676 <&hclk_peri>, <&hclk_peri>,
2678 <&aclk_peri>, <&hclk_peri>,
2679 <&hclk_peri>, <&hclk_peri>,
2681 <&dummy>, <&aclk_peri>,
2682 <&pclk_peri>, <&aclk_peri>;
2684 clock-output-names =
2685 "g_pclk_tsadc", "g_hclk_otg0",
2686 "g_h_pmu_otg0", "g_hclk_host0",
2688 "reserved", "g_hclk_hsic",
2689 "g_h_usb_peri", "g_h_p_ahb_arbi",
2691 "g_a_peri_niu", "g_h_emem_peri",
2692 "g_h_mmc_peri", "g_hclk_nand0",
2694 "reserved", "g_aclk_gmac",
2695 "g_pclk_gmac", "g_hclk_sfc";
2700 clk_gates21: gate-clk@0254 {
2701 compatible = "rockchip,rk3188-gate-clk";
2704 <&hclk_peri>, <&hclk_peri>,
2705 <&hclk_peri>, <&hclk_peri>,
2707 <&aclk_peri>, <&dummy>,
2716 clock-output-names =
2717 "g_hclk_sdmmc", "g_hclk_sdio0",
2718 "g_hclk_emmc", "g_hclk_hsadc",
2720 "g_aclk_peri_mmu", "reserved",
2721 "reserved", "reserved",
2723 "reserved", "reserved",
2724 "reserved", "reserved",
2726 "reserved", "reserved",
2727 "reserved", "reserved";
2732 clk_gates22: gate-clk@0258 {
2733 compatible = "rockchip,rk3188-gate-clk";
2736 <&dummy>, <&pclk_alive_pre>,
2737 <&pclk_alive_pre>, <&pclk_alive_pre>,
2742 <&pclk_alive_pre>, <&pclk_alive_pre>,
2743 <&pclk_vio>, <&pclk_vio>,
2745 <&pclk_alive_pre>, <&pclk_alive_pre>,
2748 clock-output-names =
2749 "reserved", "g_pclk_gpio1",
2750 "g_pclk_gpio2", "g_pclk_gpio3",
2752 "reserved", "reserved",
2753 "reserved", "reserved",
2755 "g_pclk_grf", "g_p_alive_niu",
2756 "g_pclk_dphytx0", "g_pclk_dphyrx",
2758 "g_pclk_timer0", "g_pclk_timer1",
2759 "reserved", "reserved";
2764 clk_gates23: gate-clk@025c {
2765 compatible = "rockchip,rk3188-gate-clk";
2768 <&pclk_pmu_pre>, <&pclk_pmu_pre>,
2769 <&pclk_pmu_pre>, <&pclk_pmu_pre>,
2771 <&pclk_pmu_pre>, <&pclk_pmu_pre>,
2780 clock-output-names =
2781 "g_pclk_pmu", "g_pclk_intmem1",
2782 "g_pclk_pmu_noc", "g_pclk_sgrf",
2784 "g_pclk_gpio0", "g_pclk_pmugrf",
2785 "reserved", "reserved",
2787 "reserved", "reserved",
2788 "reserved", "reserved",
2790 "reserved", "reserved",
2791 "reserved", "reserved";
2796 clk_gates24: gate-clk@0260 {
2797 compatible = "rockchip,rk3188-gate-clk";
2800 <&xin24m>, <&xin24m>,
2801 <&xin24m>, <&xin24m>,
2803 <&xin24m>, <&xin24m>,
2804 <&xin24m>, <&xin24m>,
2806 <&xin24m>, <&xin24m>,
2807 <&xin24m>, <&xin24m>,
2812 clock-output-names =
2813 "g_clk_timer0", "g_clk_timer1",
2814 "g_clk_timer2", "g_clk_timer3",
2816 "g_clk_timer4", "g_clk_timer5",
2817 "g_clk_timer10", "g_clk_timer11",
2819 "g_clk_timer12", "g_clk_timer13",
2820 "g_clk_timer14", "g_clk_timer15",
2822 "reserved", "reserved",
2823 "reserved", "reserved";
2831 compatible = "rockchip,rk-clock-special-regs";
2832 #address-cells = <2>;
2836 clk_32k_mux: clk_32k_mux {
2837 compatible = "rockchip,rk3188-mux-con";
2838 reg = <0x0 0xff738100 0x0 0x4>;
2839 rockchip,bits = <6 1>;
2840 clocks = <&xin32k>, <&pvtm_clkout>;
2841 clock-output-names = "clk_32k_mux";
2843 #clock-init-cells = <1>;