arch/arm64/boot/dts/rk3368-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014-2015 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk3368.h>
  15
  16 /{
  17         clocks {
  18                 compatible = "rockchip,rk-clocks";
  19                 rockchip,grf = <&grf>;
  20                 #address-cells = <2>;
  21                 #size-cells = <2>;
  22                 ranges;
  23
  24                 fixed_rate_cons {
  25                         compatible = "rockchip,rk-fixed-rate-cons";
  26
  27                         xin24m: xin24m {
  28                                 compatible = "rockchip,rk-fixed-clock";
  29                                 clock-output-names = "xin24m";
  30                                 clock-frequency = <24000000>;
  31                                 #clock-cells = <0>;
  32                         };
  33
  34                         xin12m: xin12m {
  35                                 compatible = "rockchip,rk-fixed-clock";
  36                                 clocks = <&xin24m>;
  37                                 clock-output-names = "xin12m";
  38                                 clock-frequency = <12000000>;
  39                                 #clock-cells = <0>;
  40                         };
  41
  42                         xin32k: xin32k {
  43                                 compatible = "rockchip,rk-fixed-clock";
  44                                 clock-output-names = "xin32k";
  45                                 clock-frequency = <32000>;
  46                                 #clock-cells = <0>;
  47                         };
  48
  49                         pvtm_clkout: pvtm_clkout {
  50                                 compatible = "rockchip,rk-fixed-clock";
  51                                 clock-output-names = "pvtm_clkout";
  52                                 clock-frequency = <32000>;
  53                                 #clock-cells = <0>;
  54                         };
  55
  56                         dummy: dummy {
  57                                 compatible = "rockchip,rk-fixed-clock";
  58                                 clock-output-names = "dummy";
  59                                 clock-frequency = <0>;
  60                                 #clock-cells = <0>;
  61                         };
  62
  63                         jtag_clkin: jtag_clkin {
  64                                 compatible = "rockchip,rk-fixed-clock";
  65                                 clock-output-names = "jtag_clkin";
  66                                 clock-frequency = <0>;
  67                                 #clock-cells = <0>;
  68                         };
  69
  70                         gmac_clkin: gmac_clkin {
  71                                 compatible = "rockchip,rk-fixed-clock";
  72                                 clock-output-names = "gmac_clkin";
  73                                 clock-frequency = <0>;
  74                                 #clock-cells = <0>;
  75                         };
  76
  77                         pclkin_isp: pclkin_isp {
  78                                 compatible = "rockchip,rk-fixed-clock";
  79                                 clock-output-names = "pclkin_isp";
  80                                 clock-frequency = <0>;
  81                                 #clock-cells = <0>;
  82                         };
  83
  84                         pclkin_vip: pclkin_vip {
  85                                 compatible = "rockchip,rk-fixed-clock";
  86                                 clock-output-names = "pclkin_vip";
  87                                 clock-frequency = <0>;
  88                                 #clock-cells = <0>;
  89                         };
  90
  91                         clkin_hsadc_tsp: clkin_hsadc_tsp {
  92                                 compatible = "rockchip,rk-fixed-clock";
  93                                 clock-output-names = "clkin_hsadc_tsp";
  94                                 clock-frequency = <0>;
  95                                 #clock-cells = <0>;
  96                         };
  97
  98                         i2s_clkin: i2s_clkin {
  99                                 compatible = "rockchip,rk-fixed-clock";
 100                                 clock-output-names = "i2s_clkin";
 101                                 clock-frequency = <0>;
 102                                 #clock-cells = <0>;
 103                         };
 104                 };
 105
 106                 fixed_factor_cons {
 107                         compatible = "rockchip,rk-fixed-factor-cons";
 108
 109                         hclk_vepu: hclk_vepu {
 110                                 compatible = "rockchip,rk-fixed-factor-clock";
 111                                 clocks = <&aclk_vepu>;
 112                                 clock-output-names = "hclk_vepu";
 113                                 clock-div = <4>;
 114                                 clock-mult = <1>;
 115                                 #clock-cells = <0>;
 116                         };
 117
 118                         hclk_vdpu: hclk_vdpu {
 119                                 compatible = "rockchip,rk-fixed-factor-clock";
 120                                 clocks = <&aclk_vdpu>;
 121                                 clock-output-names = "hclk_vdpu";
 122                                 clock-div = <4>;
 123                                 clock-mult = <1>;
 124                                 #clock-cells = <0>;
 125                         };
 126
 127                         usbotg_480m_out: usbotg_480m_out {
 128                                 compatible = "rockchip,rk-fixed-factor-clock";
 129                                 clocks = <&clk_gates8 1>;
 130                                 clock-output-names = "usbotg_480m_out";
 131                                 clock-div = <1>;
 132                                 clock-mult = <20>;
 133                                 #clock-cells = <0>;
 134                         };
 135
 136                         pclkin_isp_inv: pclkin_isp_inv {
 137                                 compatible = "rockchip,rk-fixed-factor-clock";
 138                                 clocks = <&clk_gates17 2>;
 139                                 clock-output-names = "pclkin_isp_inv";
 140                                 clock-div = <1>;
 141                                 clock-mult = <1>;
 142                                 #clock-cells = <0>;
 143                         };
 144
 145                         pclkin_vip_inv: pclkin_vip_inv {
 146                                 compatible = "rockchip,rk-fixed-factor-clock";
 147                                 clocks = <&clk_gates16 13>;
 148                                 clock-output-names = "pclkin_vip_inv";
 149                                 clock-div = <1>;
 150                                 clock-mult = <1>;
 151                                 #clock-cells = <0>;
 152                         };
 153
 154                         pclk_vio: pclk_vio {
 155                                 compatible = "rockchip,rk-fixed-factor-clock";
 156                                 clocks = <&clk_gates16 8>;
 157                                 clock-output-names = "pclk_vio";
 158                                 clock-div = <1>;
 159                                 clock-mult = <1>;
 160                                 #clock-cells = <0>;
 161                         };
 162                 };
 163
 164                 clock_regs {
 165                         compatible = "rockchip,rk-clock-regs";
 166                         #address-cells = <1>;
 167                         #size-cells = <1>;
 168                         ranges = <0x0 0x0 0xff760000 0x1000>;
 169                         reg = <0x0 0xff760000 0x0 0x1000>;
 170
 171                         /* PLL control regs */
 172                         pll_cons {
 173                                 compatible = "rockchip,rk-pll-cons";
 174                                 #address-cells = <1>;
 175                                 #size-cells = <1>;
 176                                 ranges;
 177
 178                                 clk_apllb: pll-clk@0000 {
 179                                         compatible = "rockchip,rk3188-pll-clk";
 180                                         reg = <0x0000 0x10>;
 181                                         mode-reg = <0x000c 8>;
 182                                         status-reg = <0x0480 1>;
 183                                         clocks = <&xin24m>;
 184                                         clock-output-names = "clk_apllb";
 185                                         rockchip,pll-type = <CLK_PLL_3368_APLLB>;
 186                                         #clock-cells = <0>;
 187                                 };
 188
 189
 190                                 clk_aplll: pll-clk@0010 {
 191                                         compatible = "rockchip,rk3188-pll-clk";
 192                                         reg = <0x0010 0x10>;
 193                                         mode-reg = <0x001c 8>;
 194                                         status-reg = <0x0480 0>;
 195                                         clocks = <&xin24m>;
 196                                         clock-output-names = "clk_aplll";
 197                                         rockchip,pll-type = <CLK_PLL_3368_APLLL>;
 198                                         #clock-cells = <0>;
 199                                 };
 200
 201                                 clk_dpll: pll-clk@0020 {
 202                                         compatible = "rockchip,rk3188-pll-clk";
 203                                         reg = <0x0020 0x10>;
 204                                         mode-reg = <0x002c 8>;
 205                                         status-reg = <0x0480 2>;
 206                                         clocks = <&xin24m>;
 207                                         clock-output-names = "clk_dpll";
 208                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 209                                         #clock-cells = <0>;
 210                                 };
 211
 212
 213                                 clk_cpll: pll-clk@0030 {
 214                                         compatible = "rockchip,rk3188-pll-clk";
 215                                         reg = <0x0030 0x10>;
 216                                         mode-reg = <0x003c 8>;
 217                                         status-reg = <0x0480 3>;
 218                                         clocks = <&xin24m>;
 219                                         clock-output-names = "clk_cpll";
 220                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 221                                         #clock-cells = <0>;
 222                                         #clock-init-cells = <1>;
 223                                 };
 224
 225                                 clk_gpll: pll-clk@0040 {
 226                                         compatible = "rockchip,rk3188-pll-clk";
 227                                         reg = <0x0040 0x10>;
 228                                         mode-reg = <0x004c 8>;
 229                                         status-reg = <0x0480 4>;
 230                                         clocks = <&xin24m>;
 231                                         clock-output-names = "clk_gpll";
 232                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 233                                         #clock-cells = <0>;
 234                                         #clock-init-cells = <1>;
 235                                 };
 236
 237                                 clk_npll: pll-clk@0050 {
 238                                         compatible = "rockchip,rk3188-pll-clk";
 239                                         reg = <0x0050 0x10>;
 240                                         mode-reg = <0x005c 8>;
 241                                         status-reg = <0x0480 5>;
 242                                         clocks = <&xin24m>;
 243                                         clock-output-names = "clk_npll";
 244                                         rockchip,pll-type = <CLK_PLL_3368_LOW_JITTER>;
 245                                         #clock-cells = <0>;
 246                                         #clock-init-cells = <1>;
 247                                 };
 248                         };
 249
 250                         /* Select control regs */
 251                         clk_sel_cons {
 252                                 compatible = "rockchip,rk-sel-cons";
 253                                 #address-cells = <1>;
 254                                 #size-cells = <1>;
 255                                 ranges;
 256
 257                                 clk_sel_con0: sel-con@0100 {
 258                                         compatible = "rockchip,rk3188-selcon";
 259                                         reg = <0x0100 0x4>;
 260                                         #address-cells = <1>;
 261                                         #size-cells = <1>;
 262
 263                                         clk_core_b_div: clk_core_b_div {
 264                                                 compatible = "rockchip,rk3188-div-con";
 265                                                 rockchip,bits = <0 5>;
 266                                                 clocks = <&clk_core_b>;
 267                                                 clock-output-names = "clk_core_b";
 268                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 269                                                 #clock-cells = <0>;
 270                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 271                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 272                                                                         CLK_SET_RATE_NO_REPARENT)>;
 273                                         };
 274
 275                                         /* 6:5 reserved */
 276
 277                                         clk_core_b: clk_core_b_mux {
 278                                                 compatible = "rockchip,rk3188-mux-con";
 279                                                 rockchip,bits = <7 1>;
 280                                                 clocks = <&clk_apllb>, <&clk_gpll>;
 281                                                 clock-output-names = "clk_core_b";
 282                                                 #clock-cells = <0>;
 283                                                 #clock-init-cells = <1>;
 284                                         };
 285
 286                                         aclkm_core_b: aclkm_core_b_div {
 287                                                 compatible = "rockchip,rk3188-div-con";
 288                                                 rockchip,bits = <8 5>;
 289                                                 clocks = <&clk_core_b>;
 290                                                 clock-output-names = "aclkm_core_b";
 291                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 292                                                 #clock-cells = <0>;
 293                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 294                                         };
 295
 296                                         /* 15:13 reserved */
 297                                 };
 298
 299                                 clk_sel_con1: sel-con@0104 {
 300                                         compatible = "rockchip,rk3188-selcon";
 301                                         reg = <0x0104 0x4>;
 302                                         #address-cells = <1>;
 303                                         #size-cells = <1>;
 304
 305                                         atclk_core_b: atclk_core_b_div {
 306                                                 compatible = "rockchip,rk3188-div-con";
 307                                                 rockchip,bits = <0 5>;
 308                                                 clocks = <&clk_core_b>;
 309                                                 clock-output-names = "atclk_core_b";
 310                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 311                                                 #clock-cells = <0>;
 312                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 313                                         };
 314
 315                                         /* 7:5 reserved */
 316
 317                                         pclk_dbg_b: pclk_dbg_b_div {
 318                                                 compatible = "rockchip,rk3188-div-con";
 319                                                 rockchip,bits = <8 5>;
 320                                                 clocks = <&clk_core_b>;
 321                                                 clock-output-names = "pclk_dbg_b";
 322                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 323                                                 #clock-cells = <0>;
 324                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 325                                         };
 326                                 };
 327
 328                                 clk_sel_con2: sel-con@0108 {
 329                                         compatible = "rockchip,rk3188-selcon";
 330                                         reg = <0x0108 0x4>;
 331                                         #address-cells = <1>;
 332                                         #size-cells = <1>;
 333
 334                                         clk_core_l_div: clk_core_l_div {
 335                                                 compatible = "rockchip,rk3188-div-con";
 336                                                 rockchip,bits = <0 5>;
 337                                                 clocks = <&clk_core_l>;
 338                                                 clock-output-names = "clk_core_l";
 339                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 340                                                 #clock-cells = <0>;
 341                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 342                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 343                                                                         CLK_SET_RATE_NO_REPARENT)>;
 344                                         };
 345
 346                                         /* 6:5 reserved */
 347
 348                                         clk_core_l: clk_core_l_mux {
 349                                                 compatible = "rockchip,rk3188-mux-con";
 350                                                 rockchip,bits = <7 1>;
 351                                                 clocks = <&clk_aplll>, <&clk_gpll>;
 352                                                 clock-output-names = "clk_core_l";
 353                                                 #clock-cells = <0>;
 354                                                 #clock-init-cells = <1>;
 355                                         };
 356
 357                                         aclkm_core_l: aclkm_core_l_div {
 358                                                 compatible = "rockchip,rk3188-div-con";
 359                                                 rockchip,bits = <8 5>;
 360                                                 clocks = <&clk_core_l>;
 361                                                 clock-output-names = "aclkm_core_l";
 362                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 363                                                 #clock-cells = <0>;
 364                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 365                                         };
 366
 367                                         /* 15:13 reserved */
 368                                 };
 369
 370                                 clk_sel_con3: sel-con@010c {
 371                                         compatible = "rockchip,rk3188-selcon";
 372                                         reg = <0x010c 0x4>;
 373                                         #address-cells = <1>;
 374                                         #size-cells = <1>;
 375
 376                                         atclk_core_l: atclk_core_l_div {
 377                                                 compatible = "rockchip,rk3188-div-con";
 378                                                 rockchip,bits = <0 5>;
 379                                                 clocks = <&clk_core_l>;
 380                                                 clock-output-names = "atclk_core_l";
 381                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 382                                                 #clock-cells = <0>;
 383                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 384                                         };
 385
 386                                         /* 7:5 reserved */
 387
 388                                         pclk_dbg_l: pclk_dbg_l_div {
 389                                                 compatible = "rockchip,rk3188-div-con";
 390                                                 rockchip,bits = <8 5>;
 391                                                 clocks = <&clk_core_l>;
 392                                                 clock-output-names = "pclk_dbg_l";
 393                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 394                                                 #clock-cells = <0>;
 395                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 396                                         };
 397                                 };
 398
 399                                 clk_sel_con4: sel-con@0110 {
 400                                         compatible = "rockchip,rk3188-selcon";
 401                                         reg = <0x0110 0x4>;
 402                                         #address-cells = <1>;
 403                                         #size-cells = <1>;
 404
 405                                         clk_cs_div: clk_cs_div {
 406                                                 compatible = "rockchip,rk3188-div-con";
 407                                                 rockchip,bits = <0 5>;
 408                                                 clocks = <&clk_cs>;
 409                                                 clock-output-names = "clk_cs";
 410                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 411                                                 #clock-cells = <0>;
 412                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 413                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 414                                         };
 415
 416                                         /* 5 reserved */
 417
 418                                         clk_cs: clk_cs_mux {
 419                                                 compatible = "rockchip,rk3188-mux-con";
 420                                                 rockchip,bits = <6 2>;
 421                                                 clocks = <&clk_gates0 9>, <&clk_gates0 10>, <&clk_gates0 8>, <&dummy>;
 422                                                 clock-output-names = "clk_cs";
 423                                                 #clock-cells = <0>;
 424                                                 #clock-init-cells = <1>;
 425                                         };
 426
 427                                         clkin_trace: clkin_trace_div {
 428                                                 compatible = "rockchip,rk3188-div-con";
 429                                                 rockchip,bits = <8 5>;
 430                                                 clocks = <&clk_cs>;
 431                                                 clock-output-names = "clkin_trace";
 432                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 433                                                 #clock-cells = <0>;
 434                                                 #clock-init-cells = <1>;
 435                                         };
 436
 437                                 };
 438
 439                                 clk_sel_con5: sel-con@0114 {
 440                                         compatible = "rockchip,rk3188-selcon";
 441                                         reg = <0x0114 0x4>;
 442                                         #address-cells = <1>;
 443                                         #size-cells = <1>;
 444
 445                                         aclk_cci_div: aclk_cci_div {
 446                                                 compatible = "rockchip,rk3188-div-con";
 447                                                 rockchip,bits = <0 5>;
 448                                                 clocks = <&aclk_cci>;
 449                                                 clock-output-names = "aclk_cci";
 450                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 451                                                 #clock-cells = <0>;
 452                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 453                                         };
 454
 455                                         /* 5 reserved */
 456
 457                                         aclk_cci: aclk_cci_mux {
 458                                                 compatible = "rockchip,rk3188-mux-con";
 459                                                 rockchip,bits = <6 2>;
 460                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
 461                                                 clock-output-names = "aclk_cci";
 462                                                 #clock-cells = <0>;
 463                                                 #clock-init-cells = <1>;
 464                                         };
 465                                 };
 466
 467                                 /* sel[7:6] reserved */
 468
 469                                 clk_sel_con8: sel-con@0120 {
 470                                         compatible = "rockchip,rk3188-selcon";
 471                                         reg = <0x0120 0x4>;
 472                                         #address-cells = <1>;
 473                                         #size-cells = <1>;
 474
 475                                         aclk_bus_div: aclk_bus_div {
 476                                                 compatible = "rockchip,rk3188-div-con";
 477                                                 rockchip,bits = <0 5>;
 478                                                 clocks = <&aclk_bus>;
 479                                                 clock-output-names = "aclk_bus";
 480                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 481                                                 #clock-cells = <0>;
 482                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 483                                         };
 484
 485                                         /* 6:5 reserved */
 486
 487                                         aclk_bus: aclk_bus_mux {
 488                                                 compatible = "rockchip,rk3188-mux-con";
 489                                                 rockchip,bits = <7 1>;
 490                                                 clocks = <&clk_gates1 11>, <&clk_gates1 10>;
 491                                                 clock-output-names = "aclk_bus";
 492                                                 #clock-cells = <0>;
 493                                                 #clock-init-cells = <1>;
 494                                         };
 495
 496                                         hclk_bus: hclk_bus_div {
 497                                                 compatible = "rockchip,rk3188-div-con";
 498                                                 rockchip,bits = <8 2>;
 499                                                 clocks = <&aclk_bus>;
 500                                                 clock-output-names = "hclk_bus";
 501                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 502                                                 #clock-cells = <0>;
 503                                                 #clock-init-cells = <1>;
 504                                         };
 505
 506                                         /* 11:10 reserved */
 507
 508                                         pclk_bus: pclk_bus_div {
 509                                                 compatible = "rockchip,rk3188-div-con";
 510                                                 rockchip,bits = <12 3>;
 511                                                 clocks = <&aclk_bus>;
 512                                                 clock-output-names = "pclk_bus";
 513                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 514                                                 #clock-cells = <0>;
 515                                                 #clock-init-cells = <1>;
 516                                         };
 517                                 };
 518
 519                                 clk_sel_con9: sel-con@0124 {
 520                                         compatible = "rockchip,rk3188-selcon";
 521                                         reg = <0x0124 0x4>;
 522                                         #address-cells = <1>;
 523                                         #size-cells = <1>;
 524
 525                                         aclk_peri_div: aclk_peri_div {
 526                                                 compatible = "rockchip,rk3188-div-con";
 527                                                 rockchip,bits = <0 5>;
 528                                                 clocks = <&aclk_peri>;
 529                                                 clock-output-names = "aclk_peri";
 530                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 531                                                 #clock-cells = <0>;
 532                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 533                                         };
 534
 535                                         /* 6:5 reserved */
 536
 537                                         aclk_peri: aclk_peri_mux {
 538                                                 compatible = "rockchip,rk3188-mux-con";
 539                                                 rockchip,bits = <7 1>;
 540                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 541                                                 clock-output-names = "aclk_peri";
 542                                                 #clock-cells = <0>;
 543                                                 #clock-init-cells = <1>;
 544                                         };
 545
 546                                         hclk_peri: hclk_peri_div {
 547                                                 compatible = "rockchip,rk3188-div-con";
 548                                                 rockchip,bits = <8 2>;
 549                                                 clocks = <&aclk_peri>;
 550                                                 clock-output-names = "hclk_peri";
 551                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 552                                                 rockchip,div-relations =
 553                                                                 <0x0 1
 554                                                                  0x1 2
 555                                                                  0x2 4>;
 556                                                 #clock-cells = <0>;
 557                                                 #clock-init-cells = <1>;
 558                                         };
 559
 560                                         /* 11:10 reserved */
 561
 562                                         pclk_peri: pclk_peri_div {
 563                                                 compatible = "rockchip,rk3188-div-con";
 564                                                 rockchip,bits = <12 2>;
 565                                                 clocks = <&aclk_peri>;
 566                                                 clock-output-names = "pclk_peri";
 567                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 568                                                 rockchip,div-relations =
 569                                                                 <0x0 1
 570                                                                  0x1 2
 571                                                                  0x2 4
 572                                                                  0x3 8>;
 573                                                 #clock-cells = <0>;
 574                                                 #clock-init-cells = <1>;
 575                                         };
 576                                 };
 577
 578                                 clk_sel_con10: sel-con@0128 {
 579                                         compatible = "rockchip,rk3188-selcon";
 580                                         reg = <0x0128 0x4>;
 581                                         #address-cells = <1>;
 582                                         #size-cells = <1>;
 583
 584                                         pclk_pmu_pre: pclk_pmu_pre_div {
 585                                                 compatible = "rockchip,rk3188-div-con";
 586                                                 rockchip,bits = <0 5>;
 587                                                 clocks = <&clk_gpll>;
 588                                                 clock-output-names = "pclk_pmu_pre";
 589                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 590                                                 #clock-cells = <0>;
 591                                                 #clock-init-cells = <1>;
 592                                         };
 593
 594                                         /* 7:5 reserved */
 595
 596                                         pclk_alive_pre: pclk_alive_pre_div {
 597                                                 compatible = "rockchip,rk3188-div-con";
 598                                                 rockchip,bits = <8 5>;
 599                                                 clocks = <&clk_gpll>;
 600                                                 clock-output-names = "pclk_alive_pre";
 601                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 602                                                 #clock-cells = <0>;
 603                                                 #clock-init-cells = <1>;
 604                                         };
 605
 606                                         /* 13 reserved */
 607
 608                                         clk_crypto: clk_crypto_div {
 609                                                 compatible = "rockchip,rk3188-div-con";
 610                                                 rockchip,bits = <14 2>;
 611                                                 clocks = <&aclk_bus>;
 612                                                 clock-output-names = "clk_crypto";
 613                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 614                                                 #clock-cells = <0>;
 615                                                 #clock-init-cells = <1>;
 616                                         };
 617                                 };
 618
 619                                 /* sel[11]: reserved */
 620
 621                                 clk_sel_con12: sel-con@0130 {
 622                                         compatible = "rockchip,rk3188-selcon";
 623                                         reg = <0x0130 0x4>;
 624                                         #address-cells = <1>;
 625                                         #size-cells = <1>;
 626
 627                                         fclk_mcu_div: fclk_mcu_div {
 628                                                 compatible = "rockchip,rk3188-div-con";
 629                                                 rockchip,bits = <0 5>;
 630                                                 clocks = <&fclk_mcu>;
 631                                                 clock-output-names = "fclk_mcu";
 632                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 633                                                 #clock-cells = <0>;
 634                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 635                                         };
 636
 637                                         /* 6:5 reserved */
 638
 639                                         fclk_mcu: fclk_mcu_mux {
 640                                                 compatible = "rockchip,rk3188-mux-con";
 641                                                 rockchip,bits = <7 1>;
 642                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 643                                                 clock-output-names = "fclk_mcu";
 644                                                 #clock-cells = <0>;
 645                                                 #clock-init-cells = <1>;
 646                                         };
 647
 648                                         stclk_mcu: stclk_mcu_div {
 649                                                 compatible = "rockchip,rk3188-div-con";
 650                                                 rockchip,bits = <8 3>;
 651                                                 clocks = <&fclk_mcu>;
 652                                                 clock-output-names = "stclk_mcu";
 653                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 654                                                 #clock-cells = <0>;
 655                                         };
 656                                 };
 657
 658                                 clk_sel_con13: sel-con@0134 {
 659                                         compatible = "rockchip,rk3188-selcon";
 660                                         reg = <0x0134 0x4>;
 661                                         #address-cells = <1>;
 662                                         #size-cells = <1>;
 663
 664                                         clk_ddr_div: clk_ddr_div {
 665                                                 compatible = "rockchip,rk3188-div-con";
 666                                                 rockchip,bits = <0 2>;
 667                                                 clocks = <&clk_ddr>;
 668                                                 clock-output-names = "clk_ddr";
 669                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 670                                                 #clock-cells = <0>;
 671                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 672                                                                         CLK_SET_RATE_NO_REPARENT)>;
 673                                                 rockchip,clkops-idx =
 674                                                         <CLKOPS_RATE_DDR_DIV4>;
 675                                         };
 676
 677                                         /* 3:2 reserved */
 678
 679                                         clk_ddr: clk_ddr_mux {
 680                                                 compatible = "rockchip,rk3188-mux-con";
 681                                                 rockchip,bits = <4 1>;
 682                                                 clocks = <&clk_dpll>, <&clk_gpll>;
 683                                                 clock-output-names = "clk_ddr";
 684                                                 #clock-cells = <0>;
 685                                         };
 686
 687                                         /* 7:5 reserved */
 688
 689                                         usbphy_480m: usbphy_480m_mux {
 690                                                 compatible = "rockchip,rk3188-mux-con";
 691                                                 rockchip,bits = <8 1>;
 692                                                 clocks = <&xin24m>, <&usbotg_480m_out>;
 693                                                 clock-output-names = "usbphy_480m";
 694                                                 #clock-cells = <0>;
 695                                                 rockchip,clkops-idx =
 696                                                         <CLKOPS_RATE_RK3288_USB480M>;
 697                                                 #clock-init-cells = <1>;
 698                                         };
 699                                 };
 700
 701                                 clk_sel_con14: sel-con@0138 {
 702                                         compatible = "rockchip,rk3188-selcon";
 703                                         reg = <0x0138 0x4>;
 704                                         #address-cells = <1>;
 705                                         #size-cells = <1>;
 706
 707                                         clk_gpu_core_div: clk_gpu_core_div {
 708                                                 compatible = "rockchip,rk3188-div-con";
 709                                                 rockchip,bits = <0 5>;
 710                                                 clocks = <&clk_gpu_core>;
 711                                                 clock-output-names = "clk_gpu";
 712                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 713                                                 #clock-cells = <0>;
 714                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 715                                                 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
 716                                         };
 717
 718                                         /* 5 reserved */
 719
 720                                         clk_gpu_core: clk_gpu_core_mux {
 721                                                 compatible = "rockchip,rk3188-mux-con";
 722                                                 rockchip,bits = <6 2>;
 723                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
 724                                                 clock-output-names = "clk_gpu";
 725                                                 #clock-cells = <0>;
 726                                                 #clock-init-cells = <1>;
 727                                         };
 728
 729                                         aclk_gpu_mem: aclk_gpu_mem_div {
 730                                                 compatible = "rockchip,rk3188-div-con";
 731                                                 rockchip,bits = <8 5>;
 732                                                 clocks = <&aclk_gpu>;
 733                                                 clock-output-names = "aclk_gpu_mem";
 734                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 735                                                 #clock-cells = <0>;
 736                                                 #clock-init-cells = <1>;
 737                                         };
 738
 739                                         /* 13 reserved */
 740
 741                                         aclk_gpu: aclk_gpu_mux {
 742                                                 compatible = "rockchip,rk3188-mux-con";
 743                                                 rockchip,bits = <14 1>;
 744                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 745                                                 clock-output-names = "aclk_gpu";
 746                                                 #clock-cells = <0>;
 747                                                 #clock-init-cells = <1>;
 748                                         };
 749                                 };
 750
 751                                 clk_sel_con15: sel-con@013c {
 752                                         compatible = "rockchip,rk3188-selcon";
 753                                         reg = <0x013c 0x4>;
 754                                         #address-cells = <1>;
 755                                         #size-cells = <1>;
 756
 757                                         aclk_vepu_div: aclk_vepu_div {
 758                                                 compatible = "rockchip,rk3188-div-con";
 759                                                 rockchip,bits = <0 5>;
 760                                                 clocks = <&aclk_vepu>;
 761                                                 clock-output-names = "aclk_vepu";
 762                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 763                                                 #clock-cells = <0>;
 764                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 765                                         };
 766
 767                                         /* 5 reserved */
 768
 769                                         aclk_vepu: aclk_vepu_mux {
 770                                                 compatible = "rockchip,rk3188-mux-con";
 771                                                 rockchip,bits = <6 2>;
 772                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 773                                                 clock-output-names = "aclk_vepu";
 774                                                 #clock-cells = <0>;
 775                                                 #clock-init-cells = <1>;
 776                                         };
 777
 778                                         aclk_vdpu_div: aclk_vdpu_div {
 779                                                 compatible = "rockchip,rk3188-div-con";
 780                                                 rockchip,bits = <8 5>;
 781                                                 clocks = <&aclk_vdpu>;
 782                                                 clock-output-names = "aclk_vdpu";
 783                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 784                                                 #clock-cells = <0>;
 785                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 786                                         };
 787
 788                                         /* 13 reserved */
 789
 790                                         aclk_vdpu: aclk_vdpu_mux {
 791                                                 compatible = "rockchip,rk3188-mux-con";
 792                                                 rockchip,bits = <14 2>;
 793                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 794                                                 clock-output-names = "aclk_vdpu";
 795                                                 #clock-cells = <0>;
 796                                                 #clock-init-cells = <1>;
 797                                         };
 798                                 };
 799
 800                                 clk_sel_con16: sel-con@0140 {
 801                                         compatible = "rockchip,rk3188-selcon";
 802                                         reg = <0x0140 0x4>;
 803                                         #address-cells = <1>;
 804                                         #size-cells = <1>;
 805
 806                                         aclk_gpu_cfg: aclk_gpu_cfg_div {
 807                                                 compatible = "rockchip,rk3188-div-con";
 808                                                 rockchip,bits = <8 5>;
 809                                                 clocks = <&aclk_gpu>;
 810                                                 clock-output-names = "aclk_gpu_cfg";
 811                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 812                                                 #clock-cells = <0>;
 813                                                 #clock-init-cells = <1>;
 814                                         };
 815                                 };
 816
 817                                 clk_sel_con17: sel-con@0144 {
 818                                         compatible = "rockchip,rk3188-selcon";
 819                                         reg = <0x0144 0x4>;
 820                                         #address-cells = <1>;
 821                                         #size-cells = <1>;
 822
 823                                         clk_hevc_cabac_div: clk_hevc_cabac_div {
 824                                                 compatible = "rockchip,rk3188-div-con";
 825                                                 rockchip,bits = <0 5>;
 826                                                 clocks = <&clk_hevc_cabac>;
 827                                                 clock-output-names = "clk_hevc_cabac";
 828                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 829                                                 #clock-cells = <0>;
 830                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 831                                         };
 832
 833                                         /* 5 reserved */
 834
 835                                         clk_hevc_cabac: clk_hevc_cabac_mux {
 836                                                 compatible = "rockchip,rk3188-mux-con";
 837                                                 rockchip,bits = <6 2>;
 838                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 839                                                 clock-output-names = "clk_hevc_cabac";
 840                                                 #clock-cells = <0>;
 841                                                 #clock-init-cells = <1>;
 842                                         };
 843
 844                                         clk_hevc_core_div: clk_hevc_core_div {
 845                                                 compatible = "rockchip,rk3188-div-con";
 846                                                 rockchip,bits = <8 5>;
 847                                                 clocks = <&clk_hevc_core>;
 848                                                 clock-output-names = "clk_hevc_core";
 849                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 850                                                 #clock-cells = <0>;
 851                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 852                                         };
 853
 854                                         /* 13 reserved */
 855
 856                                         clk_hevc_core: clk_hevc_core_mux {
 857                                                 compatible = "rockchip,rk3188-mux-con";
 858                                                 rockchip,bits = <14 2>;
 859                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 860                                                 clock-output-names = "clk_hevc_core";
 861                                                 #clock-cells = <0>;
 862                                                 #clock-init-cells = <1>;
 863                                         };
 864                                 };
 865
 866                                 clk_sel_con18: sel-con@0148 {
 867                                         compatible = "rockchip,rk3188-selcon";
 868                                         reg = <0x0148 0x4>;
 869                                         #address-cells = <1>;
 870                                         #size-cells = <1>;
 871
 872                                         clk_rga_div: clk_rga_div {
 873                                                 compatible = "rockchip,rk3188-div-con";
 874                                                 rockchip,bits = <0 5>;
 875                                                 clocks = <&clk_rga>;
 876                                                 clock-output-names = "clk_rga";
 877                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 878                                                 #clock-cells = <0>;
 879                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 880                                         };
 881
 882                                         /* 5 reserved */
 883
 884                                         clk_rga: clk_rga_mux {
 885                                                 compatible = "rockchip,rk3188-mux-con";
 886                                                 rockchip,bits = <6 2>;
 887                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
 888                                                 clock-output-names = "clk_rga";
 889                                                 #clock-cells = <0>;
 890                                                 #clock-init-cells = <1>;
 891                                         };
 892
 893                                         aclk_rga_div: aclk_rga_div {
 894                                                 compatible = "rockchip,rk3188-div-con";
 895                                                 rockchip,bits = <8 5>;
 896                                                 clocks = <&aclk_rga_pre>;
 897                                                 clock-output-names = "aclk_rga_pre";
 898                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 899                                                 #clock-cells = <0>;
 900                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 901                                         };
 902
 903                                         /* 13 reserved */
 904
 905                                         aclk_rga_pre: aclk_rga_mux {
 906                                                 compatible = "rockchip,rk3188-mux-con";
 907                                                 rockchip,bits = <14 2>;
 908                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
 909                                                 clock-output-names = "aclk_rga_pre";
 910                                                 #clock-cells = <0>;
 911                                                 #clock-init-cells = <1>;
 912                                         };
 913                                 };
 914
 915                                 clk_sel_con19: sel-con@014c {
 916                                         compatible = "rockchip,rk3188-selcon";
 917                                         reg = <0x014c 0x4>;
 918                                         #address-cells = <1>;
 919                                         #size-cells = <1>;
 920
 921                                         aclk_vio0_div: aclk_vio0_div {
 922                                                 compatible = "rockchip,rk3188-div-con";
 923                                                 rockchip,bits = <0 5>;
 924                                                 clocks = <&aclk_vio0>;
 925                                                 clock-output-names = "aclk_vio0";
 926                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 927                                                 #clock-cells = <0>;
 928                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 929                                         };
 930
 931                                         /* 5 reserved */
 932
 933                                         aclk_vio0: aclk_vio0_mux {
 934                                                 compatible = "rockchip,rk3188-mux-con";
 935                                                 rockchip,bits = <6 2>;
 936                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
 937                                                 clock-output-names = "aclk_vio0";
 938                                                 #clock-cells = <0>;
 939                                                 #clock-init-cells = <1>;
 940                                         };
 941                                 };
 942
 943                                 clk_sel_con20: sel-con@0150 {
 944                                         compatible = "rockchip,rk3188-selcon";
 945                                         reg = <0x0150 0x4>;
 946                                         #address-cells = <1>;
 947                                         #size-cells = <1>;
 948
 949                                         dclk_vop0_div: dclk_vop0_div {
 950                                                 compatible = "rockchip,rk3188-div-con";
 951                                                 rockchip,bits = <0 8>;
 952                                                 clocks = <&dclk_vop0>;
 953                                                 clock-output-names = "dclk_vop0";
 954                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 955                                                 #clock-cells = <0>;
 956                                                 rockchip,clkops-idx =
 957                                                         <CLKOPS_RATE_RK3368_DCLK_LCDC>;
 958                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 959
 960                                         };
 961
 962                                         dclk_vop0: dclk_vop0_mux {
 963                                                 compatible = "rockchip,rk3188-mux-con";
 964                                                 rockchip,bits = <8 2>;
 965                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&dummy>;
 966                                                 clock-output-names = "dclk_vop0";
 967                                                 #clock-cells = <0>;
 968                                                 #clock-init-cells = <1>;
 969                                         };
 970
 971                                         /* 15:10 reserved */
 972                                 };
 973
 974                                 clk_sel_con21: sel-con@0154 {
 975                                         compatible = "rockchip,rk3188-selcon";
 976                                         reg = <0x0154 0x4>;
 977                                         #address-cells = <1>;
 978                                         #size-cells = <1>;
 979
 980                                         hclk_vio: hclk_vio_div {
 981                                                 compatible = "rockchip,rk3188-div-con";
 982                                                 rockchip,bits = <0 5>;
 983                                                 clocks = <&aclk_vio0>;
 984                                                 clock-output-names = "hclk_vio";
 985                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 986                                                 #clock-cells = <0>;
 987                                                 #clock-init-cells = <1>;
 988                                         };
 989
 990                                         /* 5 reserved */
 991
 992                                         pclk_isp: pclk_isp_mux {
 993                                                 compatible = "rockchip,rk3188-mux-con";
 994                                                 rockchip,bits = <6 1>;
 995                                                 clocks = <&clk_gates17 2>, <&pclkin_isp_inv>;
 996                                                 clock-output-names = "pclk_isp";
 997                                                 #clock-cells = <0>;
 998                                         };
 999
1000                                         /* 7 reserved */
1001
1002                                         clk_vip_div: clk_vip_div {
1003                                                 compatible = "rockchip,rk3188-div-con";
1004                                                 rockchip,bits = <8 5>;
1005                                                 clocks = <&clk_vip>;
1006                                                 clock-output-names = "clk_vip";
1007                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1008                                                 #clock-cells = <0>;
1009                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1010                                         };
1011
1012                                         pclk_vip: pclk_vip_mux {
1013                                                 compatible = "rockchip,rk3188-mux-con";
1014                                                 rockchip,bits = <13 1>;
1015                                                 clocks = <&clk_gates16 13>, <&pclkin_vip_inv>;
1016                                                 clock-output-names = "pclk_vip";
1017                                                 #clock-cells = <0>;
1018                                         };
1019
1020                                         clk_vip: clk_vip_mux {
1021                                                 compatible = "rockchip,rk3188-mux-con";
1022                                                 rockchip,bits = <14 1>;
1023                                                 clocks = <&clk_vip_pll>, <&xin24m>;
1024                                                 clock-output-names = "clk_vip";
1025                                                 #clock-cells = <0>;
1026                                                 #clock-init-cells = <1>;
1027                                         };
1028
1029                                         clk_vip_pll: clk_vip_pll_mux {
1030                                                 compatible = "rockchip,rk3188-mux-con";
1031                                                 rockchip,bits = <15 1>;
1032                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1033                                                 clock-output-names = "clk_vip_pll";
1034                                                 #clock-cells = <0>;
1035                                                 #clock-init-cells = <1>;
1036                                         };
1037                                 };
1038
1039                                 clk_sel_con22: sel-con@0158 {
1040                                         compatible = "rockchip,rk3188-selcon";
1041                                         reg = <0x0158 0x4>;
1042                                         #address-cells = <1>;
1043                                         #size-cells = <1>;
1044
1045                                         clk_isp_div: clk_isp_div {
1046                                                 compatible = "rockchip,rk3188-div-con";
1047                                                 rockchip,bits = <0 6>;
1048                                                 clocks = <&clk_isp>;
1049                                                 clock-output-names = "clk_isp";
1050                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1051                                                 #clock-cells = <0>;
1052                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1053                                         };
1054
1055                                         clk_isp: clk_isp_mux {
1056                                                 compatible = "rockchip,rk3188-mux-con";
1057                                                 rockchip,bits = <6 2>;
1058                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1059                                                 clock-output-names = "clk_isp";
1060                                                 #clock-cells = <0>;
1061                                                 #clock-init-cells = <1>;
1062                                         };
1063                                 };
1064
1065                                 clk_sel_con23: sel-con@015c {
1066                                         compatible = "rockchip,rk3188-selcon";
1067                                         reg = <0x015c 0x4>;
1068                                         #address-cells = <1>;
1069                                         #size-cells = <1>;
1070
1071                                         clk_edp_div: clk_edp_div {
1072                                                 compatible = "rockchip,rk3188-div-con";
1073                                                 rockchip,bits = <0 6>;
1074                                                 clocks = <&clk_edp>;
1075                                                 clock-output-names = "clk_edp";
1076                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1077                                                 #clock-cells = <0>;
1078                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1079                                         };
1080
1081                                         clk_edp: clk_edp_mux {
1082                                                 compatible = "rockchip,rk3188-mux-con";
1083                                                 rockchip,bits = <6 2>;
1084                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1085                                                 clock-output-names = "clk_edp";
1086                                                 #clock-cells = <0>;
1087                                                 #clock-init-cells = <1>;
1088                                         };
1089
1090                                         clk_edp_24m: clk_edp_24m_mux {
1091                                                 compatible = "rockchip,rk3188-mux-con";
1092                                                 rockchip,bits = <8 1>;
1093                                                 clocks = <&xin24m>, <&dummy>;
1094                                                 clock-output-names = "clk_edp_24m";
1095                                                 #clock-cells = <0>;
1096                                         };
1097                                 };
1098
1099                                 /* sel[24]: reserved */
1100
1101                                 clk_sel_con25: sel-con@0164 {
1102                                         compatible = "rockchip,rk3188-selcon";
1103                                         reg = <0x0164 0x4>;
1104                                         #address-cells = <1>;
1105                                         #size-cells = <1>;
1106
1107                                         clk_tsadc: clk_tsadc_div {
1108                                                 compatible = "rockchip,rk3188-div-con";
1109                                                 rockchip,bits = <0 6>;
1110                                                 clocks = <&clk_32k_mux>;
1111                                                 clock-output-names = "clk_tsadc";
1112                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1113                                                 #clock-cells = <0>;
1114                                         };
1115
1116                                         /* 7:6 reserved */
1117
1118                                         clk_saradc: clk_saradc_div {
1119                                                 compatible = "rockchip,rk3188-div-con";
1120                                                 rockchip,bits = <8 8>;
1121                                                 clocks = <&xin24m>;
1122                                                 clock-output-names = "clk_saradc";
1123                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1124                                                 #clock-cells = <0>;
1125                                         };
1126                                 };
1127
1128                                 clk_sel_con26: sel-con@0168 {
1129                                         compatible = "rockchip,rk3188-selcon";
1130                                         reg = <0x0168 0x4>;
1131                                         #address-cells = <1>;
1132                                         #size-cells = <1>;
1133
1134                                         /* 7:0 reserved */
1135
1136                                         hsic_usb_480m: hsic_usb_480m_mux {
1137                                                 compatible = "rockchip,rk3188-mux-con";
1138                                                 rockchip,bits = <8 1>;
1139                                                 clocks = <&usbotg_480m_out>, <&dummy>;
1140                                                 clock-output-names = "hsic_usb_480m";
1141                                                 #clock-cells = <0>;
1142                                         };
1143
1144                                         /* 11:9 reserved */
1145
1146                                         hsicphy_480m: hsicphy_480m_mux {
1147                                                 compatible = "rockchip,rk3188-mux-con";
1148                                                 rockchip,bits = <12 2>;
1149                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&hsic_usb_480m>, <&hsic_usb_480m>;
1150                                                 clock-output-names = "hsicphy_480m";
1151                                                 #clock-cells = <0>;
1152                                         };
1153                                 };
1154
1155                                 clk_sel_con27: sel-con@016c {
1156                                         compatible = "rockchip,rk3188-selcon";
1157                                         reg = <0x016c 0x4>;
1158                                         #address-cells = <1>;
1159                                         #size-cells = <1>;
1160
1161                                         i2s_pll_div: i2s_pll_div {
1162                                                 compatible = "rockchip,rk3188-div-con";
1163                                                 rockchip,bits = <0 7>;
1164                                                 clocks = <&i2s_pll>;
1165                                                 clock-output-names = "i2s_pll";
1166                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1167                                                 #clock-cells = <0>;
1168                                                 rockchip,clkops-idx =
1169                                                         <CLKOPS_RATE_MUX_DIV>;
1170                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1171                                         };
1172
1173                                         /* 7 reserved */
1174
1175                                         clk_i2s: clk_i2s_mux {
1176                                                 compatible = "rockchip,rk3188-mux-con";
1177                                                 rockchip,bits = <8 2>;
1178                                                 clocks = <&i2s_pll>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
1179                                                 clock-output-names = "clk_i2s";
1180                                                 #clock-cells = <0>;
1181                                                 rockchip,clkops-idx =
1182                                                         <CLKOPS_RATE_RK3288_I2S>;
1183                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1184                                         };
1185
1186                                         /* 11:10 reserved */
1187
1188                                         i2s_pll: i2s_pll_mux {
1189                                                 compatible = "rockchip,rk3188-mux-con";
1190                                                 rockchip,bits = <12 1>;
1191                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1192                                                 clock-output-names = "i2s_pll";
1193                                                 #clock-cells = <0>;
1194                                                 #clock-init-cells = <1>;
1195                                         };
1196
1197                                         /* 14:13 reserved */
1198
1199                                         i2s_out: i2s_out_mux {
1200                                                 compatible = "rockchip,rk3188-mux-con";
1201                                                 rockchip,bits = <15 1>;
1202                                                 clocks = <&clk_i2s>, <&xin12m>;
1203                                                 clock-output-names = "i2s_out";
1204                                                 #clock-cells = <0>;
1205                                         };
1206                                 };
1207
1208                                 clk_sel_con28: sel-con@0170 {
1209                                         compatible = "rockchip,rk3188-selcon";
1210                                         reg = <0x0170 0x4>;
1211                                         #address-cells = <1>;
1212                                         #size-cells = <1>;
1213
1214                                         i2s_frac: i2s_frac {
1215                                                 compatible = "rockchip,rk3188-frac-con";
1216                                                 clocks = <&i2s_pll>;
1217                                                 clock-output-names = "i2s_frac";
1218                                                 /* numerator    denominator */
1219                                                 rockchip,bits = <0 32>;
1220                                                 rockchip,clkops-idx =
1221                                                         <CLKOPS_RATE_FRAC>;
1222                                                 #clock-cells = <0>;
1223                                         };
1224                                 };
1225
1226                                 /* sel[30:29] reserved */
1227
1228                                 clk_sel_con31: sel-con@017c {
1229                                         compatible = "rockchip,rk3188-selcon";
1230                                         reg = <0x017c 0x4>;
1231                                         #address-cells = <1>;
1232                                         #size-cells = <1>;
1233
1234
1235                                         spdif_8ch_pll_div: spdif_8ch_pll_div {
1236                                                 compatible = "rockchip,rk3188-div-con";
1237                                                 rockchip,bits = <0 7>;
1238                                                 clocks = <&spdif_8ch_pll>;
1239                                                 clock-output-names = "spdif_8ch_pll";
1240                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1241                                                 #clock-cells = <0>;
1242                                                 rockchip,clkops-idx =
1243                                                         <CLKOPS_RATE_MUX_DIV>;
1244                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1245                                         };
1246
1247                                         /* 7 reserved */
1248
1249                                         clk_spidf_8ch: clk_spidf_8ch_mux {
1250                                                 compatible = "rockchip,rk3188-mux-con";
1251                                                 rockchip,bits = <8 2>;
1252                                                 clocks = <&spdif_8ch_pll>, <&spdif_8ch_frac>, <&i2s_clkin>, <&xin12m>;
1253                                                 clock-output-names = "clk_spidf_8ch";
1254                                                 #clock-cells = <0>;
1255                                                 rockchip,clkops-idx =
1256                                                         <CLKOPS_RATE_RK3288_I2S>;
1257                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1258                                         };
1259
1260                                         /* 11:10 reserved */
1261
1262                                         spdif_8ch_pll: spdif_8ch_pll_mux {
1263                                                 compatible = "rockchip,rk3188-mux-con";
1264                                                 rockchip,bits = <12 1>;
1265                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1266                                                 clock-output-names = "spdif_8ch_pll";
1267                                                 #clock-cells = <0>;
1268                                                 #clock-init-cells = <1>;
1269                                         };
1270
1271                                         /* 15:13 reserved */
1272                                 };
1273
1274                                 clk_sel_con32: sel-con@0180 {
1275                                         compatible = "rockchip,rk3188-selcon";
1276                                         reg = <0x0180 0x4>;
1277                                         #address-cells = <1>;
1278                                         #size-cells = <1>;
1279
1280                                         spdif_8ch_frac: spdif_8ch_frac {
1281                                                 compatible = "rockchip,rk3188-frac-con";
1282                                                 clocks = <&spdif_8ch_pll>;
1283                                                 clock-output-names = "spdif_8ch_frac";
1284                                                 /* numerator    denominator */
1285                                                 rockchip,bits = <0 32>;
1286                                                 rockchip,clkops-idx =
1287                                                         <CLKOPS_RATE_FRAC>;
1288                                                 #clock-cells = <0>;
1289                                         };
1290                                 };
1291
1292                                 clk_sel_con33: sel-con@0184 {
1293                                         compatible = "rockchip,rk3188-selcon";
1294                                         reg = <0x0184 0x4>;
1295                                         #address-cells = <1>;
1296                                         #size-cells = <1>;
1297
1298                                         clk_uart0_pll_div: clk_uart0_pll_div {
1299                                                 compatible = "rockchip,rk3188-div-con";
1300                                                 rockchip,bits = <0 7>;
1301                                                 clocks = <&clk_uart0_pll>;
1302                                                 clock-output-names = "clk_uart0_pll";
1303                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1304                                                 #clock-cells = <0>;
1305                                                 rockchip,clkops-idx =
1306                                                         <CLKOPS_RATE_MUX_DIV>;
1307                                         };
1308
1309                                         /* 7: reserved */
1310
1311                                         clk_uart0: clk_uart0_mux {
1312                                                 compatible = "rockchip,rk3188-mux-con";
1313                                                 rockchip,bits = <8 2>;
1314                                                 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>, <&xin24m>;
1315                                                 clock-output-names = "clk_uart0";
1316                                                 #clock-cells = <0>;
1317                                                 rockchip,clkops-idx =
1318                                                         <CLKOPS_RATE_RK3288_I2S>;
1319                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1320                                         };
1321
1322                                         /* 11:10 reserved */
1323
1324                                         clk_uart0_pll: clk_uart0_pll_mux {
1325                                                 compatible = "rockchip,rk3188-mux-con";
1326                                                 rockchip,bits = <12 2>;
1327                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
1328                                                 clock-output-names = "clk_uart0_pll";
1329                                                 #clock-cells = <0>;
1330                                         };
1331                                 };
1332
1333                                 clk_sel_con34: sel-con@0188 {
1334                                         compatible = "rockchip,rk3188-selcon";
1335                                         reg = <0x0188 0x4>;
1336                                         #address-cells = <1>;
1337                                         #size-cells = <1>;
1338
1339                                         uart0_frac: uart0_frac {
1340                                                 compatible = "rockchip,rk3188-frac-con";
1341                                                 clocks = <&clk_uart0_pll>;
1342                                                 clock-output-names = "uart0_frac";
1343                                                 /* numerator    denominator */
1344                                                 rockchip,bits = <0 32>;
1345                                                 rockchip,clkops-idx =
1346                                                         <CLKOPS_RATE_FRAC>;
1347                                                 #clock-cells = <0>;
1348                                         };
1349                                 };
1350
1351                                 clk_sel_con35: sel-con@018c {
1352                                         compatible = "rockchip,rk3188-selcon";
1353                                         reg = <0x018c 0x4>;
1354                                         #address-cells = <1>;
1355                                         #size-cells = <1>;
1356
1357                                         uart1_div: uart1_div {
1358                                                 compatible = "rockchip,rk3188-div-con";
1359                                                 rockchip,bits = <0 7>;
1360                                                 clocks = <&clk_uart_pll>;
1361                                                 clock-output-names = "uart1_div";
1362                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1363                                                 #clock-cells = <0>;
1364                                         };
1365
1366                                         /* 7 reserved */
1367
1368                                         clk_uart1: clk_uart1_mux {
1369                                                 compatible = "rockchip,rk3188-mux-con";
1370                                                 rockchip,bits = <8 2>;
1371                                                 clocks = <&uart1_div>, <&uart1_frac>, <&xin24m>, <&xin24m>;
1372                                                 clock-output-names = "clk_uart1";
1373                                                 #clock-cells = <0>;
1374                                                 rockchip,clkops-idx =
1375                                                         <CLKOPS_RATE_RK3288_I2S>;
1376                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1377                                         };
1378
1379                                         /* 11:10 reserved */
1380
1381                                         clk_uart_pll: clk_uart_pll_mux {
1382                                                 compatible = "rockchip,rk3188-mux-con";
1383                                                 rockchip,bits = <12 1>;
1384                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1385                                                 clock-output-names = "clk_uart_pll";
1386                                                 #clock-cells = <0>;
1387                                                 #clock-init-cells = <1>;
1388                                         };
1389                                 };
1390
1391                                 clk_sel_con36: sel-con@0190 {
1392                                         compatible = "rockchip,rk3188-selcon";
1393                                         reg = <0x0190 0x4>;
1394                                         #address-cells = <1>;
1395                                         #size-cells = <1>;
1396
1397                                         uart1_frac: uart1_frac {
1398                                                 compatible = "rockchip,rk3188-frac-con";
1399                                                 clocks = <&uart1_div>;
1400                                                 clock-output-names = "uart1_frac";
1401                                                 /* numerator    denominator */
1402                                                 rockchip,bits = <0 32>;
1403                                                 rockchip,clkops-idx =
1404                                                         <CLKOPS_RATE_FRAC>;
1405                                                 #clock-cells = <0>;
1406                                         };
1407                                 };
1408
1409                                 clk_sel_con37: sel-con@0194 {
1410                                         compatible = "rockchip,rk3188-selcon";
1411                                         reg = <0x0194 0x4>;
1412                                         #address-cells = <1>;
1413                                         #size-cells = <1>;
1414
1415                                         uart2_div: uart2_div {
1416                                                 compatible = "rockchip,rk3188-div-con";
1417                                                 rockchip,bits = <0 7>;
1418                                                 clocks = <&clk_uart_pll>;
1419                                                 clock-output-names = "uart2_div";
1420                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1421                                                 #clock-cells = <0>;
1422                                         };
1423
1424                                         /* 7 reserved */
1425
1426                                         clk_uart2: clk_uart2_mux {
1427                                                 compatible = "rockchip,rk3188-mux-con";
1428                                                 rockchip,bits = <8 1>;
1429                                                 clocks = <&uart2_div>, <&xin24m>;
1430                                                 clock-output-names = "clk_uart2";
1431                                                 #clock-cells = <0>;
1432                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1433                                         };
1434                                 };
1435
1436                                 /* sel[38] reserved */
1437
1438                                 clk_sel_con39: sel-con@019c {
1439                                         compatible = "rockchip,rk3188-selcon";
1440                                         reg = <0x019c 0x4>;
1441                                         #address-cells = <1>;
1442                                         #size-cells = <1>;
1443
1444                                         uart3_div: uart3_div {
1445                                                 compatible = "rockchip,rk3188-div-con";
1446                                                 rockchip,bits = <0 7>;
1447                                                 clocks = <&clk_uart_pll>;
1448                                                 clock-output-names = "uart3_div";
1449                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1450                                                 #clock-cells = <0>;
1451                                         };
1452
1453                                         /* 7 reserved */
1454
1455                                         clk_uart3: clk_uart3_mux {
1456                                                 compatible = "rockchip,rk3188-mux-con";
1457                                                 rockchip,bits = <8 2>;
1458                                                 clocks = <&uart3_div>, <&uart3_frac>, <&xin24m>, <&xin24m>;
1459                                                 clock-output-names = "clk_uart3";
1460                                                 #clock-cells = <0>;
1461                                                 rockchip,clkops-idx =
1462                                                         <CLKOPS_RATE_RK3288_I2S>;
1463                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1464                                         };
1465                                 };
1466
1467                                 clk_sel_con40: sel-con@01a0 {
1468                                         compatible = "rockchip,rk3188-selcon";
1469                                         reg = <0x01a0 0x4>;
1470                                         #address-cells = <1>;
1471                                         #size-cells = <1>;
1472
1473                                         uart3_frac: uart3_frac {
1474                                                 compatible = "rockchip,rk3188-frac-con";
1475                                                 clocks = <&uart3_div>;
1476                                                 clock-output-names = "uart3_frac";
1477                                                 /* numerator    denominator */
1478                                                 rockchip,bits = <0 32>;
1479                                                 rockchip,clkops-idx =
1480                                                         <CLKOPS_RATE_FRAC>;
1481                                                 #clock-cells = <0>;
1482                                         };
1483                                 };
1484
1485                                 clk_sel_con41: sel-con@01a4 {
1486                                         compatible = "rockchip,rk3188-selcon";
1487                                         reg = <0x01a4 0x4>;
1488                                         #address-cells = <1>;
1489                                         #size-cells = <1>;
1490
1491                                         uart4_div: uart4_div {
1492                                                 compatible = "rockchip,rk3188-div-con";
1493                                                 rockchip,bits = <0 7>;
1494                                                 clocks = <&clk_uart_pll>;
1495                                                 clock-output-names = "uart4_div";
1496                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1497                                                 #clock-cells = <0>;
1498                                         };
1499
1500                                         /* 7 reserved */
1501
1502                                         clk_uart4: clk_uart4_mux {
1503                                                 compatible = "rockchip,rk3188-mux-con";
1504                                                 rockchip,bits = <8 2>;
1505                                                 clocks = <&uart4_div>, <&uart4_frac>, <&xin24m>, <&xin24m>;
1506                                                 clock-output-names = "clk_uart4";
1507                                                 #clock-cells = <0>;
1508                                                 rockchip,clkops-idx =
1509                                                         <CLKOPS_RATE_RK3288_I2S>;
1510                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1511                                         };
1512                                 };
1513
1514                                 clk_sel_con42: sel-con@01a8 {
1515                                         compatible = "rockchip,rk3188-selcon";
1516                                         reg = <0x01a8 0x4>;
1517                                         #address-cells = <1>;
1518                                         #size-cells = <1>;
1519
1520                                         uart4_frac: uart4_frac {
1521                                                 compatible = "rockchip,rk3188-frac-con";
1522                                                 clocks = <&uart4_div>;
1523                                                 clock-output-names = "uart4_frac";
1524                                                 /* numerator    denominator */
1525                                                 rockchip,bits = <0 32>;
1526                                                 rockchip,clkops-idx =
1527                                                         <CLKOPS_RATE_FRAC>;
1528                                                 #clock-cells = <0>;
1529                                         };
1530                                 };
1531
1532                                 clk_sel_con43: sel-con@01ac {
1533                                         compatible = "rockchip,rk3188-selcon";
1534                                         reg = <0x01ac 0x4>;
1535                                         #address-cells = <1>;
1536                                         #size-cells = <1>;
1537
1538                                         clk_mac_pll_div: clk_mac_pll_div {
1539                                                 compatible = "rockchip,rk3188-div-con";
1540                                                 rockchip,bits = <0 5>;
1541                                                 clocks = <&clk_mac_pll>;
1542                                                 clock-output-names = "clk_mac_pll";
1543                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1544                                                 #clock-cells = <0>;
1545                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1546                                         };
1547
1548                                         /* 5 reserved */
1549
1550                                         clk_mac_pll: clk_mac_pll_mux {
1551                                                 compatible = "rockchip,rk3188-mux-con";
1552                                                 rockchip,bits = <6 2>;
1553                                                 clocks = <&clk_npll>, <&clk_cpll>, <&clk_gpll>, <&clk_gpll>;
1554                                                 clock-output-names = "clk_mac_pll";
1555                                                 #clock-cells = <0>;
1556                                         };
1557
1558                                         clk_mac: clk_mac_mux {
1559                                                 compatible = "rockchip,rk3188-mux-con";
1560                                                 rockchip,bits = <8 1>;
1561                                                 clocks = <&clk_mac_pll>, <&gmac_clkin>;
1562                                                 clock-output-names = "clk_mac";
1563                                                 #clock-cells = <0>;
1564                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1565                                                 #clock-init-cells = <1>;
1566                                         };
1567
1568                                         /* 11:9 reserved */
1569
1570                                         /* 12: test_clk: wifi_pll_sel */
1571
1572                                         /* 15:13 reserved */
1573                                 };
1574
1575                                 clk_sel_con44: sel-con@01b0 {
1576                                         compatible = "rockchip,rk3188-selcon";
1577                                         reg = <0x01b0 0x4>;
1578                                         #address-cells = <1>;
1579                                         #size-cells = <1>;
1580
1581                                         /* test_clk: wifi_frac */
1582                                 };
1583
1584                                 clk_sel_con45: sel-con@01b4 {
1585                                         compatible = "rockchip,rk3188-selcon";
1586                                         reg = <0x01b4 0x4>;
1587                                         #address-cells = <1>;
1588                                         #size-cells = <1>;
1589
1590                                         clk_spi0_div: clk_spi0_div {
1591                                                 compatible = "rockchip,rk3188-div-con";
1592                                                 rockchip,bits = <0 7>;
1593                                                 clocks = <&clk_spi0>;
1594                                                 clock-output-names = "clk_spi0";
1595                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1596                                                 #clock-cells = <0>;
1597                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1598                                         };
1599
1600                                         clk_spi0: clk_spi0_mux {
1601                                                 compatible = "rockchip,rk3188-mux-con";
1602                                                 rockchip,bits = <7 1>;
1603                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1604                                                 clock-output-names = "clk_spi0";
1605                                                 #clock-cells = <0>;
1606                                         };
1607
1608                                         clk_spi1_div: clk_spi1_div {
1609                                                 compatible = "rockchip,rk3188-div-con";
1610                                                 rockchip,bits = <8 7>;
1611                                                 clocks = <&clk_spi1>;
1612                                                 clock-output-names = "clk_spi1";
1613                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1614                                                 #clock-cells = <0>;
1615                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1616                                         };
1617
1618                                         clk_spi1: clk_spi1_mux {
1619                                                 compatible = "rockchip,rk3188-mux-con";
1620                                                 rockchip,bits = <15 1>;
1621                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1622                                                 clock-output-names = "clk_spi1";
1623                                                 #clock-cells = <0>;
1624                                         };
1625                                 };
1626
1627                                 clk_sel_con46: sel-con@01b8 {
1628                                         compatible = "rockchip,rk3188-selcon";
1629                                         reg = <0x01b8 0x4>;
1630                                         #address-cells = <1>;
1631                                         #size-cells = <1>;
1632
1633                                         clk_tsp_div: clk_tsp_div {
1634                                                 compatible = "rockchip,rk3188-div-con";
1635                                                 rockchip,bits = <0 5>;
1636                                                 clocks = <&clk_tsp>;
1637                                                 clock-output-names = "clk_tsp";
1638                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1639                                                 #clock-cells = <0>;
1640                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1641                                         };
1642
1643                                         /* 5 reserved */
1644
1645                                         clk_tsp: clk_tsp_mux {
1646                                                 compatible = "rockchip,rk3188-mux-con";
1647                                                 rockchip,bits = <6 2>;
1648                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1649                                                 clock-output-names = "clk_tsp";
1650                                                 #clock-cells = <0>;
1651                                         };
1652
1653                                         clk_spi2_div: clk_spi2_div {
1654                                                 compatible = "rockchip,rk3188-div-con";
1655                                                 rockchip,bits = <8 7>;
1656                                                 clocks = <&clk_spi2>;
1657                                                 clock-output-names = "clk_spi2";
1658                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1659                                                 #clock-cells = <0>;
1660                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1661                                         };
1662
1663                                         clk_spi2: clk_spi2_mux {
1664                                                 compatible = "rockchip,rk3188-mux-con";
1665                                                 rockchip,bits = <15 1>;
1666                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1667                                                 clock-output-names = "clk_spi2";
1668                                                 #clock-cells = <0>;
1669                                         };
1670                                 };
1671
1672                                 clk_sel_con47: sel-con@01bc {
1673                                         compatible = "rockchip,rk3188-selcon";
1674                                         reg = <0x01bc 0x4>;
1675                                         #address-cells = <1>;
1676                                         #size-cells = <1>;
1677
1678                                         clk_nandc0_div: clk_nandc0_div {
1679                                                 compatible = "rockchip,rk3188-div-con";
1680                                                 rockchip,bits = <0 5>;
1681                                                 clocks = <&clk_nandc0>;
1682                                                 clock-output-names = "clk_nandc0";
1683                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1684                                                 #clock-cells = <0>;
1685                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1686                                         };
1687
1688                                         /* 6:5 reserved */
1689
1690                                         clk_nandc0: clk_nandc0_mux {
1691                                                 compatible = "rockchip,rk3188-mux-con";
1692                                                 rockchip,bits = <7 1>;
1693                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1694                                                 clock-output-names = "clk_nandc0";
1695                                                 #clock-cells = <0>;
1696                                         };
1697
1698                                         /* 12:8 test_div */
1699
1700                                         /* 15:13 reserved */
1701                                 };
1702
1703                                 clk_sel_con48: sel-con@01c0 {
1704                                         compatible = "rockchip,rk3188-selcon";
1705                                         reg = <0x01c0 0x4>;
1706                                         #address-cells = <1>;
1707                                         #size-cells = <1>;
1708
1709                                         clk_sdio0_div: clk_sdio0_div {
1710                                                 compatible = "rockchip,rk3188-div-con";
1711                                                 rockchip,bits = <0 7>;
1712                                                 clocks = <&clk_sdio0>;
1713                                                 clock-output-names = "clk_sdio0";
1714                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1715                                                 #clock-cells = <0>;
1716                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1717                                         };
1718
1719                                         /* 7 reserved */
1720
1721                                         clk_sdio0: clk_sdio0_mux {
1722                                                 compatible = "rockchip,rk3188-mux-con";
1723                                                 rockchip,bits = <8 2>;
1724                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1725                                                 clock-output-names = "clk_sdio0";
1726                                                 #clock-cells = <0>;
1727                                         };
1728
1729                                         /* 15:10 reserved */
1730                                 };
1731
1732                                 /* sel[49] reserved */
1733
1734                                 clk_sel_con50: sel-con@01c8 {
1735                                         compatible = "rockchip,rk3188-selcon";
1736                                         reg = <0x01c8 0x4>;
1737                                         #address-cells = <1>;
1738                                         #size-cells = <1>;
1739
1740                                         clk_sdmmc0_div: clk_sdmmc0_div {
1741                                                 compatible = "rockchip,rk3188-div-con";
1742                                                 rockchip,bits = <0 7>;
1743                                                 clocks = <&clk_sdmmc0>;
1744                                                 clock-output-names = "clk_sdmmc0";
1745                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1746                                                 #clock-cells = <0>;
1747                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1748                                         };
1749
1750                                         /* 7 reserved */
1751
1752                                         clk_sdmmc0: clk_sdmmc0_mux {
1753                                                 compatible = "rockchip,rk3188-mux-con";
1754                                                 rockchip,bits = <8 2>;
1755                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1756                                                 clock-output-names = "clk_sdmmc0";
1757                                                 #clock-cells = <0>;
1758                                         };
1759
1760                                         /* 15:10 reserved */
1761                                 };
1762
1763                                 clk_sel_con51: sel-con@01cc {
1764                                         compatible = "rockchip,rk3188-selcon";
1765                                         reg = <0x01cc 0x4>;
1766                                         #address-cells = <1>;
1767                                         #size-cells = <1>;
1768
1769                                         clk_emmc_div: clk_emmc_div {
1770                                                 compatible = "rockchip,rk3188-div-con";
1771                                                 rockchip,bits = <0 7>;
1772                                                 clocks = <&clk_emmc>;
1773                                                 clock-output-names = "clk_emmc";
1774                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1775                                                 #clock-cells = <0>;
1776                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1777                                         };
1778
1779                                         /* 7 reserved */
1780
1781                                         clk_emmc: clk_emmc_mux {
1782                                                 compatible = "rockchip,rk3188-mux-con";
1783                                                 rockchip,bits = <8 2>;
1784                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1785                                                 clock-output-names = "clk_emmc";
1786                                                 #clock-cells = <0>;
1787                                         };
1788
1789                                         /* 15:10 reserved */
1790                                 };
1791
1792                                 clk_sel_con52: sel-con@01d0 {
1793                                         compatible = "rockchip,rk3188-selcon";
1794                                         reg = <0x01d0 0x4>;
1795                                         #address-cells = <1>;
1796                                         #size-cells = <1>;
1797
1798                                         clk_sfc_div: clk_sfc_div {
1799                                                 compatible = "rockchip,rk3188-div-con";
1800                                                 rockchip,bits = <0 5>;
1801                                                 clocks = <&clk_sfc>;
1802                                                 clock-output-names = "clk_sfc";
1803                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1804                                                 #clock-cells = <0>;
1805                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1806                                         };
1807
1808                                         /* 6:5 reserved */
1809
1810                                         clk_sfc: clk_sfc_mux {
1811                                                 compatible = "rockchip,rk3188-mux-con";
1812                                                 rockchip,bits = <7 1>;
1813                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1814                                                 clock-output-names = "clk_sfc";
1815                                                 #clock-cells = <0>;
1816                                         };
1817
1818                                         /* 15:8 reserved */
1819                                 };
1820
1821                                 clk_sel_con53: sel-con@01d4 {
1822                                         compatible = "rockchip,rk3188-selcon";
1823                                         reg = <0x01d4 0x4>;
1824                                         #address-cells = <1>;
1825                                         #size-cells = <1>;
1826
1827                                         i2s_2ch_pll_div: i2s_2ch_pll_div {
1828                                                 compatible = "rockchip,rk3188-div-con";
1829                                                 rockchip,bits = <0 7>;
1830                                                 clocks = <&i2s_2ch_pll>;
1831                                                 clock-output-names = "i2s_2ch_pll";
1832                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1833                                                 #clock-cells = <0>;
1834                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1835                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1836                                         };
1837
1838                                         /* 7 reserved */
1839
1840                                         clk_i2s_2ch: clk_i2s_2ch_mux {
1841                                                 compatible = "rockchip,rk3188-mux-con";
1842                                                 rockchip,bits = <8 2>;
1843                                                 clocks = <&i2s_2ch_pll>, <&i2s_2ch_frac>, <&dummy>, <&xin12m>;
1844                                                 clock-output-names = "clk_i2s_2ch";
1845                                                 #clock-cells = <0>;
1846                                                 rockchip,clkops-idx =
1847                                                         <CLKOPS_RATE_RK3288_I2S>;
1848                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1849                                         };
1850
1851                                         /* 11:10 reserved */
1852
1853                                         i2s_2ch_pll: i2s_2ch_pll_mux {
1854                                                 compatible = "rockchip,rk3188-mux-con";
1855                                                 rockchip,bits = <12 1>;
1856                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1857                                                 clock-output-names = "i2s_2ch_pll";
1858                                                 #clock-cells = <0>;
1859                                                 #clock-init-cells = <1>;
1860                                         };
1861
1862                                 };
1863
1864                                 clk_sel_con54: sel-con@01d8 {
1865                                         compatible = "rockchip,rk3188-selcon";
1866                                         reg = <0x01d8 0x4>;
1867                                         #address-cells = <1>;
1868                                         #size-cells = <1>;
1869
1870                                         i2s_2ch_frac: i2s_2ch_frac {
1871                                                 compatible = "rockchip,rk3188-frac-con";
1872                                                 clocks = <&i2s_2ch_pll>;
1873                                                 clock-output-names = "i2s_2ch_frac";
1874                                                 /* numerator    denominator */
1875                                                 rockchip,bits = <0 32>;
1876                                                 rockchip,clkops-idx =
1877                                                         <CLKOPS_RATE_FRAC>;
1878                                                 #clock-cells = <0>;
1879                                         };
1880                                 };
1881
1882                                 clk_sel_con55: sel-con@01dc {
1883                                         compatible = "rockchip,rk3188-selcon";
1884                                         reg = <0x01dc 0x4>;
1885                                         #address-cells = <1>;
1886                                         #size-cells = <1>;
1887
1888                                         clk_hdcp_div: clk_hdcp_div {
1889                                                 compatible = "rockchip,rk3188-div-con";
1890                                                 rockchip,bits = <0 6>;
1891                                                 clocks = <&clk_hdcp>;
1892                                                 clock-output-names = "clk_hdcp";
1893                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1894                                                 #clock-cells = <0>;
1895                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1896                                         };
1897
1898                                         clk_hdcp: clk_hdcp_mux {
1899                                                 compatible = "rockchip,rk3188-mux-con";
1900                                                 rockchip,bits = <6 2>;
1901                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1902                                                 clock-output-names = "clk_hdcp";
1903                                                 #clock-cells = <0>;
1904                                         };
1905                                 };
1906                         };
1907
1908                         /* Gate control regs */
1909                         clk_gate_cons {
1910                                 compatible = "rockchip,rk-gate-cons";
1911                                 #address-cells = <1>;
1912                                 #size-cells = <1>;
1913                                 ranges;
1914
1915                                 clk_gates0: gate-clk@0200 {
1916                                         compatible = "rockchip,rk3188-gate-clk";
1917                                         reg = <0x0200 0x4>;
1918                                         clocks =
1919                                                 <&dummy>,       <&dummy>,
1920                                                 <&dummy>,       <&dummy>,
1921
1922                                                 <&dummy>,       <&dummy>,
1923                                                 <&dummy>,       <&dummy>,
1924
1925                                                 <&clk_gpll>,    <&clk_apllb>,
1926                                                 <&clk_aplll>,   <&dummy>,
1927
1928                                                 <&aclk_cci>,    <&clkin_trace>,
1929                                                 <&dummy>,       <&dummy>;
1930
1931                                         clock-output-names =
1932                                                 "reserved",     "reserved",/* core_b_apll core_b_gpll */
1933                                                 "reserved",     "reserved",
1934
1935                                                 "reserved",     "reserved",/* core_l_apll core_l_gpll */
1936                                                 "reserved",     "reserved",
1937
1938                                                 "g_clk_cs_gpll",        "g_clk_cs_apllb",
1939                                                 "g_clk_cs_aplll",       "reserved",
1940
1941                                                 "aclk_cci",     "clkin_trace",
1942                                                 "reserved",     "reserved";
1943
1944                                         #clock-cells = <1>;
1945                                 };
1946
1947                                 clk_gates1: gate-clk@0204 {
1948                                         compatible = "rockchip,rk3188-gate-clk";
1949                                         reg = <0x0204 0x4>;
1950                                         clocks =
1951                                                 <&aclk_bus>,    <&hclk_bus>,
1952                                                 <&pclk_bus>,    <&fclk_mcu>,
1953
1954                                                 <&dummy>,       <&dummy>,
1955                                                 <&dummy>,       <&dummy>,
1956
1957                                                 <&dummy>,       <&dummy>,
1958                                                 <&clk_gpll>,    <&clk_cpll>,
1959
1960                                                 <&dummy>,       <&dummy>,
1961                                                 <&dummy>,       <&dummy>;
1962
1963                                         clock-output-names =
1964                                                 "aclk_bus",     "hclk_bus",
1965                                                 "pclk_bus",     "fclk_mcu",
1966
1967                                                 "reserved",     "reserved",
1968                                                 "reserved",     "reserved",
1969
1970                                                 "reserved",     "reserved",/* ddr_dpll  ddr_gpll */
1971                                                 "aclk_bus_gpll",        "aclk_bus_cpll",
1972
1973                                                 "reserved",     "reserved",
1974                                                 "reserved",     "reserved";
1975
1976                                         #clock-cells = <1>;
1977                                 };
1978
1979                                 clk_gates2: gate-clk@0208 {
1980                                         compatible = "rockchip,rk3188-gate-clk";
1981                                         reg = <0x0208 0x4>;
1982                                         clocks =
1983                                                 <&clk_uart0_pll>,       <&uart0_frac>,
1984                                                 <&uart1_div>,   <&uart1_frac>,
1985
1986                                                 <&uart2_div>,   <&dummy>,
1987                                                 <&uart3_div>,   <&uart3_frac>,
1988
1989                                                 <&uart4_div>,   <&uart4_frac>,
1990                                                 <&dummy>,       <&dummy>,
1991
1992                                                 <&dummy>,       <&dummy>,
1993                                                 <&dummy>,       <&dummy>;
1994
1995                                         clock-output-names =
1996                                                 "clk_uart0_pll",        "uart0_frac",
1997                                                 "uart1_div",    "uart1_frac",
1998
1999                                                 "uart2_div",    "reserved",
2000                                                 "uart3_div",    "uart3_frac",
2001
2002                                                 "uart4_div",    "uart4_frac",
2003                                                 "reserved",     "reserved",
2004
2005                                                 "reserved",     "reserved",
2006                                                 "reserved",     "reserved";
2007
2008                                         #clock-cells = <1>;
2009                                 };
2010
2011                                 clk_gates3: gate-clk@020c {
2012                                         compatible = "rockchip,rk3188-gate-clk";
2013                                         reg = <0x020c 0x4>;
2014                                         clocks =
2015                                                 <&aclk_peri>,   <&dummy>,
2016                                                 <&hclk_peri>,   <&pclk_peri>,
2017
2018                                                 <&clk_mac_pll>, <&clk_tsadc>,
2019                                                 <&clk_saradc>,  <&clk_spi0>,
2020
2021                                                 <&clk_spi1>,    <&clk_spi2>,
2022                                                 <&dummy>,       <&dummy>,
2023
2024                                                 <&dummy>,       <&dummy>,
2025                                                 <&dummy>,       <&dummy>;
2026
2027                                         clock-output-names =
2028                                                 "aclk_peri",    "reserved", /* bit1: aclk_peri */
2029                                                 "hclk_peri",    "pclk_peri",
2030
2031                                                 "clk_mac_pll",  "clk_tsadc",
2032                                                 "clk_saradc",   "clk_spi0",
2033
2034                                                 "clk_spi1",     "clk_spi2",
2035                                                 "reserved",     "reserved",
2036
2037                                                 "reserved",     "reserved",
2038                                                 "reserved",     "reserved";
2039
2040                                         #clock-cells = <1>;
2041                                 };
2042
2043                                 clk_gates4: gate-clk@0210 {
2044                                         compatible = "rockchip,rk3188-gate-clk";
2045                                         reg = <0x0210 0x4>;
2046                                         clocks =
2047                                                 <&aclk_vio0>,   <&dclk_vop0>,
2048                                                 <&xin24m>,      <&aclk_rga_pre>,
2049
2050                                                 <&clk_rga>,     <&clk_vip_pll>,
2051                                                 <&aclk_vepu>,   <&aclk_vdpu>,
2052
2053                                                 <&dummy>,       <&clk_isp>,
2054                                                 <&dummy>,       <&clk_gpu_core>,
2055
2056                                                 <&xin32k>,      <&xin24m>,
2057                                                 <&xin24m>,      <&dummy>;
2058
2059                                         clock-output-names =
2060                                                 "aclk_vio0",    "dclk_vop0",
2061                                                 "clk_vop0_pwm", "aclk_rga_pre",
2062
2063                                                 "clk_rga",      "clk_vip_pll",
2064                                                 "aclk_vepu",    "aclk_vdpu",
2065
2066                                                 "reserved",     "clk_isp", /* bit8: hclk_vpu */
2067                                                 "reserved",     "clk_gpu",
2068
2069                                                 "clk_hdmi_cec", "clk_hdmi_hdcp",
2070                                                 "clk_dsiphy_24m",       "reserved";
2071
2072                                         #clock-cells = <1>;
2073                                 };
2074
2075                                 clk_gates5: gate-clk@0214 {
2076                                         compatible = "rockchip,rk3188-gate-clk";
2077                                         reg = <0x0214 0x4>;
2078                                         clocks =
2079                                                 <&dummy>,       <&clk_hevc_cabac>,
2080                                                 <&clk_hevc_core>,       <&clk_edp>,
2081
2082                                                 <&clk_edp_24m>, <&clk_hdcp>,
2083                                                 <&dummy>,       <&dummy>,
2084
2085                                                 <&aclk_gpu_mem>,        <&aclk_gpu_cfg>,
2086                                                 <&dummy>,       <&dummy>,
2087
2088                                                 <&dummy>,       <&i2s_2ch_pll>,
2089                                                 <&i2s_2ch_frac>,        <&clk_i2s_2ch>;
2090
2091                                         clock-output-names =
2092                                                 "reserved",     "clk_hevc_cabac",
2093                                                 "clk_hevc_core",        "clk_edp",
2094
2095                                                 "clk_edp_24m",  "clk_hdcp",
2096                                                 "reserved",     "reserved",
2097
2098                                                 "aclk_gpu_mem", "aclk_gpu_cfg",
2099                                                 "reserved",     "reserved",
2100
2101                                                 "reserved",     "i2s_2ch_pll",
2102                                                 "i2s_2ch_frac", "clk_i2s_2ch";
2103
2104                                         #clock-cells = <1>;
2105                                 };
2106
2107                                 clk_gates6: gate-clk@0218 {
2108                                         compatible = "rockchip,rk3188-gate-clk";
2109                                         reg = <0x0218 0x4>;
2110                                         clocks =
2111                                                 <&i2s_out>,     <&i2s_pll>,
2112                                                 <&i2s_frac>,    <&clk_i2s>,
2113
2114                                                 <&spdif_8ch_pll>,       <&spdif_8ch_frac>,
2115                                                 <&clk_spidf_8ch>,       <&clk_sfc>,
2116
2117                                                 <&dummy>,       <&dummy>,
2118                                                 <&dummy>,       <&dummy>,
2119
2120                                                 <&clk_tsp>,     <&dummy>,
2121                                                 <&dummy>,       <&dummy>;
2122
2123                                         clock-output-names =
2124                                                 "i2s_out",      "i2s_pll",
2125                                                 "i2s_frac",     "clk_i2s",
2126
2127                                                 "spdif_8ch_pll",        "spdif_8ch_frac",
2128                                                 "clk_spidf_8ch",        "clk_sfc",
2129
2130                                                 "reserved",     "reserved",
2131                                                 "reserved",     "reserved",
2132
2133                                                 "clk_tsp",      "reserved",
2134                                                 "reserved",     "reserved";/* clk_ddrphy_gate   clk4x_ddrphy_gate */
2135
2136                                         #clock-cells = <1>;
2137                                 };
2138
2139                                 clk_gates7: gate-clk@021c {
2140                                         compatible = "rockchip,rk3188-gate-clk";
2141                                         reg = <0x021c 0x4>;
2142                                         clocks =
2143                                                 <&jtag_clkin>,  <&dummy>,
2144                                                 <&clk_crypto>,  <&xin24m>,
2145
2146                                                 <&dummy>,       <&dummy>,
2147                                                 <&clk_mac>,     <&clk_mac>,
2148
2149                                                 <&clk_nandc0>,  <&pclk_pmu_pre>,
2150                                                 <&xin24m>,      <&xin24m>,
2151
2152                                                 <&dummy>,       <&dummy>,
2153                                                 <&dummy>,       <&dummy>;
2154
2155                                         clock-output-names =
2156                                                 "clk_jtag",     "reserved",/* bit1: test_clk */
2157                                                 "clk_crypto",   "clk_pvtm_pmu",
2158
2159                                                 "clk_mac_rx",   "clk_mac_tx",
2160                                                 "clk_mac_ref",  "clk_mac_refout",
2161
2162                                                 "clk_nandc0",   "pclk_pmu_pre",
2163                                                 "clk_pvtm_core",        "clk_pvtm_gpu",
2164
2165                                                 "clk_sdmmc0",   "clk_sdio0",
2166                                                 "reserved",     "clk_emmc";
2167
2168                                         #clock-cells = <1>;
2169                                 };
2170
2171                                 clk_gates8: gate-clk@0220 {
2172                                         compatible = "rockchip,rk3188-gate-clk";
2173                                         reg = <0x0220 0x4>;
2174                                         clocks =
2175                                                 <&hsic_usb_480m>,       <&xin24m>,
2176                                                 <&dummy>,       <&dummy>,
2177
2178                                                 <&clk_32k_mux>, <&dummy>,
2179                                                 <&xin12m>,      <&hsicphy_480m>,
2180
2181                                                 <&dummy>,       <&dummy>,
2182                                                 <&dummy>,       <&dummy>,
2183
2184                                                 <&dummy>,       <&dummy>,
2185                                                 <&dummy>,       <&dummy>;
2186
2187                                         clock-output-names =
2188                                                 "hsic_usb_480m",        "clk_otgphy0",
2189                                                 "reserved",     "reserved",
2190
2191                                                 "g_clk_otg_adp",        "reserved",/* bit4: clk_otg_adp */
2192                                                 "hsicphy_12m",  "hsicphy_480m",
2193
2194                                                 "reserved",     "reserved",
2195                                                 "reserved",     "reserved",
2196
2197                                                 "reserved",     "reserved",
2198                                                 "reserved",     "reserved";
2199
2200                                         #clock-cells = <1>;
2201                                 };
2202
2203                                 clk_gates9: gate-clk@0224 {
2204                                         compatible = "rockchip,rk3188-gate-clk";
2205                                         reg = <0x0224 0x4>;
2206                                         clocks =
2207                                                 <&dummy>,       <&dummy>,
2208                                                 <&dummy>,       <&dummy>,
2209
2210                                                 <&dummy>,       <&dummy>,
2211                                                 <&dummy>,       <&dummy>,
2212
2213                                                 <&dummy>,       <&dummy>,
2214                                                 <&dummy>,       <&dummy>,
2215
2216                                                 <&dummy>,       <&dummy>,
2217                                                 <&dummy>,       <&dummy>;
2218
2219                                         clock-output-names =
2220                                                 "reserved",     "reserved",
2221                                                 "reserved",     "reserved",
2222
2223                                                 "reserved",     "reserved",
2224                                                 "reserved",     "reserved",
2225
2226                                                 "reserved",     "reserved",
2227                                                 "reserved",     "reserved",
2228
2229                                                 "reserved",     "reserved",
2230                                                 "reserved",     "reserved";
2231
2232                                         #clock-cells = <1>;
2233                                 };
2234
2235                                 clk_gates10: gate-clk@0228 {
2236                                         compatible = "rockchip,rk3188-gate-clk";
2237                                         reg = <0x0228 0x4>;
2238                                         clocks =
2239                                                 <&dummy>,       <&dummy>,
2240                                                 <&dummy>,       <&dummy>,
2241
2242                                                 <&dummy>,       <&dummy>,
2243                                                 <&dummy>,       <&dummy>,
2244
2245                                                 <&dummy>,       <&dummy>,
2246                                                 <&dummy>,       <&dummy>,
2247
2248                                                 <&dummy>,       <&dummy>,
2249                                                 <&dummy>,       <&dummy>;
2250
2251                                         clock-output-names =
2252                                                 "reserved",     "reserved",
2253                                                 "reserved",     "reserved",
2254
2255                                                 "reserved",     "reserved",
2256                                                 "reserved",     "reserved",
2257
2258                                                 "reserved",     "reserved",
2259                                                 "reserved",     "reserved",
2260
2261                                                 "reserved",     "reserved",
2262                                                 "reserved",     "reserved";
2263
2264                                         #clock-cells = <1>;
2265                                 };
2266
2267                                 clk_gates11: gate-clk@022c {
2268                                         compatible = "rockchip,rk3188-gate-clk";
2269                                         reg = <0x022c 0x4>;
2270                                         clocks =
2271                                                 <&dummy>,       <&dummy>,
2272                                                 <&dummy>,       <&dummy>,
2273
2274                                                 <&dummy>,       <&dummy>,
2275                                                 <&dummy>,       <&dummy>,
2276
2277                                                 <&dummy>,       <&dummy>,
2278                                                 <&dummy>,       <&dummy>,
2279
2280                                                 <&dummy>,       <&dummy>,
2281                                                 <&dummy>,       <&dummy>;
2282
2283                                         clock-output-names =
2284                                                 "reserved",     "reserved",
2285                                                 "reserved",     "reserved",
2286
2287                                                 "reserved",     "reserved",
2288                                                 "reserved",     "reserved",
2289
2290                                                 "reserved",     "reserved",
2291                                                 "reserved",     "reserved",
2292
2293                                                 "reserved",     "reserved",
2294                                                 "reserved",     "reserved";
2295
2296                                         #clock-cells = <1>;
2297                                 };
2298
2299                                 clk_gates12: gate-clk@0230 {
2300                                         compatible = "rockchip,rk3188-gate-clk";
2301                                         reg = <0x0230 0x4>;
2302                                         clocks =
2303                                                 <&pclk_bus>,    <&pclk_bus>,
2304                                                 <&pclk_bus>,    <&pclk_bus>,
2305
2306                                                 <&aclk_bus>,    <&aclk_bus>,
2307                                                 <&aclk_bus>,    <&hclk_bus>,
2308
2309                                                 <&hclk_bus>,    <&hclk_bus>,
2310                                                 <&hclk_bus>,    <&aclk_bus>,
2311
2312                                                 <&aclk_bus>,    <&dummy>,
2313                                                 <&dummy>,       <&dummy>;
2314
2315                                         clock-output-names =
2316                                                 "g_pclk_pwm0",  "g_p_mailbox",
2317                                                 "g_p_i2cpmu",   "g_p_i2caudio",
2318
2319                                                 "g_aclk_intmem",        "g_clk_intmem0",
2320                                                 "g_clk_intmem1",        "g_h_i2s_8ch",
2321
2322                                                 "g_h_i2s_2ch",  "g_hclk_rom",
2323                                                 "g_hclk_spdif", "g_aclk_dmac",
2324
2325                                                 "g_a_strc_sys", "reserved",/* bit13: pclk_ddrupctl */
2326                                                 "reserved",     "reserved";/* bit14: pclk_ddrphy */
2327
2328                                         #clock-cells = <1>;
2329                                 };
2330
2331                                 clk_gates13: gate-clk@0234 {
2332                                         compatible = "rockchip,rk3188-gate-clk";
2333                                         reg = <0x0234 0x4>;
2334                                         clocks =
2335                                                 <&pclk_bus>,    <&pclk_bus>,
2336                                                 <&dummy>,       <&hclk_bus>,
2337
2338                                                 <&hclk_bus>,    <&pclk_bus>,
2339                                                 <&pclk_bus>,    <&clkin_hsadc_tsp>,
2340
2341                                                 <&pclk_bus>,    <&aclk_bus>,
2342                                                 <&hclk_bus>,    <&dummy>,
2343
2344                                                 <&dummy>,       <&dummy>,
2345                                                 <&dummy>,       <&dummy>;
2346
2347                                         clock-output-names =
2348                                                 "g_p_efuse_1024",       "g_p_efuse_256",
2349                                                 "reserved",     "g_mclk_crypto",/* bit2: nclk_ddrupctl */
2350
2351                                                 "g_sclk_crypto",        "g_p_uartdbg",
2352                                                 "g_pclk_pwm1",  "clk_hsadc_tsp",
2353
2354                                                 "g_pclk_sim",   "g_aclk_gic400",
2355                                                 "g_hclk_tsp",   "reserved",
2356
2357                                                 "reserved",     "reserved",
2358                                                 "reserved",     "reserved";
2359
2360                                         #clock-cells = <1>;
2361                                 };
2362
2363                                 clk_gates14: gate-clk@0238 {
2364                                         compatible = "rockchip,rk3188-gate-clk";
2365                                         reg = <0x0238 0x4>;
2366                                         clocks =
2367                                                 <&dummy>,       <&dummy>,
2368                                                 <&dummy>,       <&dummy>,
2369
2370                                                 <&dummy>,       <&dummy>,
2371                                                 <&dummy>,       <&dummy>,
2372
2373                                                 <&dummy>,       <&dummy>,
2374                                                 <&dummy>,       <&dummy>,
2375
2376                                                 <&dummy>,       <&dummy>,
2377                                                 <&dummy>,       <&dummy>;
2378
2379                                         clock-output-names =
2380                                                 "reserved",     "reserved",
2381                                                 "reserved",     "reserved",
2382
2383                                                 "reserved",     "reserved",
2384                                                 "reserved",     "reserved",
2385
2386                                                 "reserved",     "reserved",
2387                                                 "reserved",     "reserved",
2388
2389                                                 "reserved",     "reserved",
2390                                                 "reserved",     "reserved";
2391
2392                                         #clock-cells = <1>;
2393                                 };
2394
2395                                 clk_gates15: gate-clk@023c {
2396                                         compatible = "rockchip,rk3188-gate-clk";
2397                                         reg = <0x023c 0x4>;
2398                                         clocks =
2399                                                 <&dummy>,       <&dummy>,
2400                                                 <&dummy>,       <&dummy>,
2401
2402                                                 <&dummy>,       <&dummy>,
2403                                                 <&dummy>,       <&dummy>,
2404
2405                                                 <&dummy>,       <&dummy>,
2406                                                 <&dummy>,       <&dummy>,
2407
2408                                                 <&dummy>,       <&dummy>,
2409                                                 <&dummy>,       <&dummy>;
2410
2411                                         clock-output-names =
2412                                                 "reserved",     "reserved",/* aclk_video hclk_video */
2413                                                 "reserved",     "reserved",
2414
2415                                                 "reserved",     "reserved",
2416                                                 "reserved",     "reserved",
2417
2418                                                 "reserved",     "reserved",
2419                                                 "reserved",     "reserved",
2420
2421                                                 "reserved",     "reserved",
2422                                                 "reserved",     "reserved";
2423
2424                                         #clock-cells = <1>;
2425                                 };
2426
2427                                 clk_gates16: gate-clk@0240 {
2428                                         compatible = "rockchip,rk3188-gate-clk";
2429                                         reg = <0x0240 0x4>;
2430                                         clocks =
2431                                                 <&clk_gates16 10>,      <&clk_gates16 8>,
2432                                                 <&clk_gates16 9>,       <&clk_gates16 8>,
2433
2434                                                 <&clk_gates16 9>,       <&clk_gates16 9>,
2435                                                 <&clk_gates16 8>,       <&clk_gates17 8>,
2436
2437                                                 <&clk_gates16 7>,       <&aclk_vio0>,
2438                                                 <&aclk_rga_pre>,        <&clk_gates16 9>,
2439
2440                                                 <&clk_gates16 8>,       <&pclkin_vip>,
2441                                                 <&clk_isp>,     <&dummy>;
2442
2443                                         clock-output-names =
2444                                                 "g_aclk_rga",   "g_hclk_rga",
2445                                                 "g_aclk_iep",   "g_hclk_iep",
2446
2447                                                 "g_aclk_vop_iep",       "g_aclk_vop",
2448                                                 "g_hclk_vop",   "h_vio_ahb_arbi",
2449
2450                                                 "g_hclk_vio_noc",       "g_aclk_vio0_noc",
2451                                                 "g_aclk_vio1_noc",      "g_aclk_vip",
2452
2453                                                 "g_hclk_vip",   "g_pclkin_vip",
2454                                                 "g_hclk_isp",   "reserved";
2455
2456                                         #clock-cells = <1>;
2457                                 };
2458
2459                                 clk_gates17: gate-clk@0244 {
2460                                         compatible = "rockchip,rk3188-gate-clk";
2461                                         reg = <0x0244 0x4>;
2462                                         clocks =
2463                                                 <&clk_isp>,     <&dummy>,
2464                                                 <&pclkin_isp>,  <&pclk_vio>,
2465
2466                                                 <&pclk_vio>,    <&dummy>,
2467                                                 <&pclk_vio>,    <&hclk_vio>,
2468
2469                                                 <&clk_gates17 7>,       <&pclk_vio>,
2470                                                 <&clk_gates16 10>,      <&pclk_vio>,
2471
2472                                                 <&clk_gates16 8>,       <&dummy>,
2473                                                 <&dummy>,       <&dummy>;
2474
2475                                         clock-output-names =
2476                                                 "g_aclk_isp",   "reserved",
2477                                                 "g_pclkin_isp", "g_p_mipi_dsi0",
2478
2479                                                 "g_p_mipi_csi", "reserved",
2480                                                 "g_p_hdmi_ctrl",        "g_hclk_vio_h2p",
2481
2482                                                 "g_pclk_vio_h2p",       "g_p_edp_ctrl",
2483                                                 "g_aclk_hdcp",  "g_pclk_hdcp",
2484
2485                                                 "g_h_hdcpmmu",  "reserved",
2486                                                 "reserved",     "reserved";
2487
2488                                         #clock-cells = <1>;
2489                                 };
2490
2491                                 clk_gates18: gate-clk@0248 {
2492                                         compatible = "rockchip,rk3188-gate-clk";
2493                                         reg = <0x0248 0x4>;
2494                                         clocks =
2495                                                 <&dummy>,       <&dummy>,
2496                                                 <&dummy>,       <&dummy>,
2497
2498                                                 <&dummy>,       <&dummy>,
2499                                                 <&dummy>,       <&dummy>,
2500
2501                                                 <&dummy>,       <&dummy>,
2502                                                 <&dummy>,       <&dummy>,
2503
2504                                                 <&dummy>,       <&dummy>,
2505                                                 <&dummy>,       <&dummy>;
2506
2507                                         clock-output-names =
2508                                                 "reserved",     "reserved",/* bit0-1: aclk_gpu_cfg aclk_gpu_mem */
2509                                                 "reserved",     "reserved",/* bit2: clk_gpu_core */
2510
2511                                                 "reserved",     "reserved",
2512                                                 "reserved",     "reserved",
2513
2514                                                 "reserved",     "reserved",
2515                                                 "reserved",     "reserved",
2516
2517                                                 "reserved",     "reserved",
2518                                                 "reserved",     "reserved";
2519
2520                                         #clock-cells = <1>;
2521                                 };
2522
2523                                 clk_gates19: gate-clk@024c {
2524                                         compatible = "rockchip,rk3188-gate-clk";
2525                                         reg = <0x024c 0x4>;
2526                                         clocks =
2527                                                 <&hclk_peri>,   <&pclk_peri>,
2528                                                 <&aclk_peri>,   <&aclk_peri>,
2529
2530                                                 <&pclk_peri>,   <&pclk_peri>,
2531                                                 <&pclk_peri>,   <&pclk_peri>,
2532
2533                                                 <&pclk_peri>,   <&pclk_peri>,
2534                                                 <&pclk_peri>,   <&pclk_peri>,
2535
2536                                                 <&pclk_peri>,   <&pclk_peri>,
2537                                                 <&pclk_peri>,   <&pclk_peri>;
2538
2539                                         clock-output-names =
2540                                                 "g_hp_axi_matrix",      "g_pp_axi_matrix",
2541                                                 "g_ap_axi_matrix",      "g_a_dmac_peri",
2542
2543                                                 "g_pclk_spi0",  "g_pclk_spi1",
2544                                                 "g_pclk_spi2",  "g_pclk_uart0",
2545
2546                                                 "g_pclk_uart1", "g_pclk_uart3",
2547                                                 "g_pclk_uart4", "g_pclk_i2c2",
2548
2549                                                 "g_pclk_i2c3",  "g_pclk_i2c4",
2550                                                 "g_pclk_i2c5",  "g_pclk_saradc";
2551
2552                                         #clock-cells = <1>;
2553                                 };
2554
2555                                 clk_gates20: gate-clk@0250 {
2556                                         compatible = "rockchip,rk3188-gate-clk";
2557                                         reg = <0x0250 0x4>;
2558                                         clocks =
2559                                                 <&pclk_peri>,   <&hclk_peri>,
2560                                                 <&hclk_peri>,   <&hclk_peri>,
2561
2562                                                 <&dummy>,       <&hclk_peri>,
2563                                                 <&hclk_peri>,   <&hclk_peri>,
2564
2565                                                 <&aclk_peri>,   <&hclk_peri>,
2566                                                 <&hclk_peri>,   <&hclk_peri>,
2567
2568                                                 <&dummy>,       <&aclk_peri>,
2569                                                 <&pclk_peri>,   <&aclk_peri>;
2570
2571                                         clock-output-names =
2572                                                 "g_pclk_tsadc", "g_hclk_otg0",
2573                                                 "g_h_pmu_otg0", "g_hclk_host0",
2574
2575                                                 "reserved",     "g_hclk_hsic",
2576                                                 "g_h_usb_peri", "g_h_p_ahb_arbi",
2577
2578                                                 "g_a_peri_niu", "g_h_emem_peri",
2579                                                 "g_h_mmc_peri", "g_hclk_nand0",
2580
2581                                                 "reserved",     "g_aclk_gmac",
2582                                                 "g_pclk_gmac",  "g_hclk_sfc";
2583
2584                                         #clock-cells = <1>;
2585                                 };
2586
2587                                 clk_gates21: gate-clk@0254 {
2588                                         compatible = "rockchip,rk3188-gate-clk";
2589                                         reg = <0x0254 0x4>;
2590                                         clocks =
2591                                                 <&hclk_peri>,   <&hclk_peri>,
2592                                                 <&hclk_peri>,   <&hclk_peri>,
2593
2594                                                 <&aclk_peri>,   <&dummy>,
2595                                                 <&dummy>,       <&dummy>,
2596
2597                                                 <&dummy>,       <&dummy>,
2598                                                 <&dummy>,       <&dummy>,
2599
2600                                                 <&dummy>,       <&dummy>,
2601                                                 <&dummy>,       <&dummy>;
2602
2603                                         clock-output-names =
2604                                                 "g_hclk_sdmmc", "g_hclk_sdio0",
2605                                                 "g_hclk_emmc",  "g_hclk_hsadc",
2606
2607                                                 "g_aclk_peri_mmu",      "reserved",
2608                                                 "reserved",     "reserved",
2609
2610                                                 "reserved",     "reserved",
2611                                                 "reserved",     "reserved",
2612
2613                                                 "reserved",     "reserved",
2614                                                 "reserved",     "reserved";
2615
2616                                         #clock-cells = <1>;
2617                                 };
2618
2619                                 clk_gates22: gate-clk@0258 {
2620                                         compatible = "rockchip,rk3188-gate-clk";
2621                                         reg = <0x0258 0x4>;
2622                                         clocks =
2623                                                 <&dummy>,       <&pclk_alive_pre>,
2624                                                 <&pclk_alive_pre>,      <&pclk_alive_pre>,
2625
2626                                                 <&dummy>,       <&dummy>,
2627                                                 <&dummy>,       <&dummy>,
2628
2629                                                 <&pclk_alive_pre>,      <&pclk_alive_pre>,
2630                                                 <&pclk_vio>,    <&pclk_vio>,
2631
2632                                                 <&pclk_alive_pre>,      <&pclk_alive_pre>,
2633                                                 <&dummy>,       <&dummy>;
2634
2635                                         clock-output-names =
2636                                                 "reserved",     "g_pclk_gpio1",
2637                                                 "g_pclk_gpio2", "g_pclk_gpio3",
2638
2639                                                 "reserved",     "reserved",
2640                                                 "reserved",     "reserved",
2641
2642                                                 "g_pclk_grf",   "g_p_alive_niu",
2643                                                 "g_pclk_dphytx0",       "g_pclk_dphyrx",
2644
2645                                                 "g_pclk_timer0",        "g_pclk_timer1",
2646                                                 "reserved",     "reserved";
2647
2648                                         #clock-cells = <1>;
2649                                 };
2650
2651                                 clk_gates23: gate-clk@025c {
2652                                         compatible = "rockchip,rk3188-gate-clk";
2653                                         reg = <0x025c 0x4>;
2654                                         clocks =
2655                                                 <&pclk_pmu_pre>,        <&pclk_pmu_pre>,
2656                                                 <&pclk_pmu_pre>,        <&pclk_pmu_pre>,
2657
2658                                                 <&pclk_pmu_pre>,        <&pclk_pmu_pre>,
2659                                                 <&dummy>,       <&dummy>,
2660
2661                                                 <&dummy>,       <&dummy>,
2662                                                 <&dummy>,       <&dummy>,
2663
2664                                                 <&dummy>,       <&dummy>,
2665                                                 <&dummy>,       <&dummy>;
2666
2667                                         clock-output-names =
2668                                                 "g_pclk_pmu",   "g_pclk_intmem1",
2669                                                 "g_pclk_pmu_noc",       "g_pclk_sgrf",
2670
2671                                                 "g_pclk_gpio0", "g_pclk_pmugrf",
2672                                                 "reserved",     "reserved",
2673
2674                                                 "reserved",     "reserved",
2675                                                 "reserved",     "reserved",
2676
2677                                                 "reserved",     "reserved",
2678                                                 "reserved",     "reserved";
2679
2680                                         #clock-cells = <1>;
2681                                 };
2682
2683                                 clk_gates24: gate-clk@0260 {
2684                                         compatible = "rockchip,rk3188-gate-clk";
2685                                         reg = <0x0260 0x4>;
2686                                         clocks =
2687                                                 <&xin24m>,      <&xin24m>,
2688                                                 <&xin24m>,      <&xin24m>,
2689
2690                                                 <&xin24m>,      <&xin24m>,
2691                                                 <&xin24m>,      <&xin24m>,
2692
2693                                                 <&xin24m>,      <&xin24m>,
2694                                                 <&xin24m>,      <&xin24m>,
2695
2696                                                 <&dummy>,       <&dummy>,
2697                                                 <&dummy>,       <&dummy>;
2698
2699                                         clock-output-names =
2700                                                 "g_clk_timer0", "g_clk_timer1",
2701                                                 "g_clk_timer2", "g_clk_timer3",
2702
2703                                                 "g_clk_timer4", "g_clk_timer5",
2704                                                 "g_clk_timer10",        "g_clk_timer11",
2705
2706                                                 "g_clk_timer12",        "g_clk_timer13",
2707                                                 "g_clk_timer14",        "g_clk_timer15",
2708
2709                                                 "reserved",     "reserved",
2710                                                 "reserved",     "reserved";
2711
2712                                         #clock-cells = <1>;
2713                                 };
2714                         };
2715                 };
2716
2717                 special_regs {
2718                         compatible = "rockchip,rk-clock-special-regs";
2719                         #address-cells = <2>;
2720                         #size-cells = <2>;
2721                         ranges;
2722
2723                         clk_32k_mux: clk_32k_mux {
2724                                 compatible = "rockchip,rk3188-mux-con";
2725                                 reg = <0x0 0xff738100 0x0 0x4>;
2726                                 rockchip,bits = <6 1>;
2727                                 clocks = <&xin32k>, <&pvtm_clkout>;
2728                                 clock-output-names = "clk_32k_mux";
2729                                 #clock-cells = <0>;
2730                                 #clock-init-cells = <1>;
2731                         };
2732                 };
2733         };
2734 };