2 * Copyright (C) 2014-2015 ROCKCHIP, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #include <dt-bindings/clock/rockchip,rk3368.h>
18 compatible = "rockchip,rk-clocks";
19 rockchip,grf = <&grf>;
25 compatible = "rockchip,rk-fixed-rate-cons";
28 compatible = "rockchip,rk-fixed-clock";
29 clock-output-names = "xin24m";
30 clock-frequency = <24000000>;
35 compatible = "rockchip,rk-fixed-clock";
37 clock-output-names = "xin12m";
38 clock-frequency = <12000000>;
43 compatible = "rockchip,rk-fixed-clock";
44 clock-output-names = "xin32k";
45 clock-frequency = <32000>;
49 pvtm_clkout: pvtm_clkout {
50 compatible = "rockchip,rk-fixed-clock";
51 clock-output-names = "pvtm_clkout";
52 clock-frequency = <32000>;
57 compatible = "rockchip,rk-fixed-clock";
58 clock-output-names = "dummy";
59 clock-frequency = <0>;
63 jtag_clkin: jtag_clkin {
64 compatible = "rockchip,rk-fixed-clock";
65 clock-output-names = "jtag_clkin";
66 clock-frequency = <0>;
70 gmac_clkin: gmac_clkin {
71 compatible = "rockchip,rk-fixed-clock";
72 clock-output-names = "gmac_clkin";
73 clock-frequency = <0>;
77 pclkin_isp: pclkin_isp {
78 compatible = "rockchip,rk-fixed-clock";
79 clock-output-names = "pclkin_isp";
80 clock-frequency = <0>;
84 pclkin_vip: pclkin_vip {
85 compatible = "rockchip,rk-fixed-clock";
86 clock-output-names = "pclkin_vip";
87 clock-frequency = <0>;
91 clkin_hsadc_tsp: clkin_hsadc_tsp {
92 compatible = "rockchip,rk-fixed-clock";
93 clock-output-names = "clkin_hsadc_tsp";
94 clock-frequency = <0>;
98 i2s_clkin: i2s_clkin {
99 compatible = "rockchip,rk-fixed-clock";
100 clock-output-names = "i2s_clkin";
101 clock-frequency = <0>;
107 compatible = "rockchip,rk-fixed-factor-cons";
109 hclk_vepu: hclk_vepu {
110 compatible = "rockchip,rk-fixed-factor-clock";
111 clocks = <&aclk_vepu>;
112 clock-output-names = "hclk_vepu";
118 hclk_vdpu: hclk_vdpu {
119 compatible = "rockchip,rk-fixed-factor-clock";
120 clocks = <&aclk_vdpu>;
121 clock-output-names = "hclk_vdpu";
127 usbotg_480m_out: usbotg_480m_out {
128 compatible = "rockchip,rk-fixed-factor-clock";
129 clocks = <&clk_gates8 1>;
130 clock-output-names = "usbotg_480m_out";
136 pclkin_isp_inv: pclkin_isp_inv {
137 compatible = "rockchip,rk-fixed-factor-clock";
138 clocks = <&clk_gates17 2>;
139 clock-output-names = "pclkin_isp_inv";
145 pclkin_vip_inv: pclkin_vip_inv {
146 compatible = "rockchip,rk-fixed-factor-clock";
147 clocks = <&clk_gates16 13>;
148 clock-output-names = "pclkin_vip_inv";
155 compatible = "rockchip,rk-fixed-factor-clock";
156 clocks = <&clk_gates16 8>;
157 clock-output-names = "pclk_vio";
165 compatible = "rockchip,rk-clock-regs";
166 #address-cells = <1>;
168 ranges = <0x0 0x0 0xff760000 0x1000>;
169 reg = <0x0 0xff760000 0x0 0x1000>;
171 /* PLL control regs */
173 compatible = "rockchip,rk-pll-cons";
174 #address-cells = <1>;
178 clk_apllb: pll-clk@0000 {
179 compatible = "rockchip,rk3188-pll-clk";
181 mode-reg = <0x000c 8>;
182 status-reg = <0x0480 1>;
184 clock-output-names = "clk_apllb";
185 rockchip,pll-type = <CLK_PLL_3368_APLLB>;
190 clk_aplll: pll-clk@0010 {
191 compatible = "rockchip,rk3188-pll-clk";
193 mode-reg = <0x001c 8>;
194 status-reg = <0x0480 0>;
196 clock-output-names = "clk_aplll";
197 rockchip,pll-type = <CLK_PLL_3368_APLLL>;
201 clk_dpll: pll-clk@0020 {
202 compatible = "rockchip,rk3188-pll-clk";
204 mode-reg = <0x002c 8>;
205 status-reg = <0x0480 2>;
207 clock-output-names = "clk_dpll";
208 rockchip,pll-type = <CLK_PLL_3188PLUS>;
213 clk_cpll: pll-clk@0030 {
214 compatible = "rockchip,rk3188-pll-clk";
216 mode-reg = <0x003c 8>;
217 status-reg = <0x0480 3>;
219 clock-output-names = "clk_cpll";
220 rockchip,pll-type = <CLK_PLL_3188PLUS>;
222 #clock-init-cells = <1>;
225 clk_gpll: pll-clk@0040 {
226 compatible = "rockchip,rk3188-pll-clk";
228 mode-reg = <0x004c 8>;
229 status-reg = <0x0480 4>;
231 clock-output-names = "clk_gpll";
232 rockchip,pll-type = <CLK_PLL_3188PLUS>;
234 #clock-init-cells = <1>;
237 clk_npll: pll-clk@0050 {
238 compatible = "rockchip,rk3188-pll-clk";
240 mode-reg = <0x005c 8>;
241 status-reg = <0x0480 5>;
243 clock-output-names = "clk_npll";
244 rockchip,pll-type = <CLK_PLL_3368_LOW_JITTER>;
246 #clock-init-cells = <1>;
250 /* Select control regs */
252 compatible = "rockchip,rk-sel-cons";
253 #address-cells = <1>;
257 clk_sel_con0: sel-con@0100 {
258 compatible = "rockchip,rk3188-selcon";
260 #address-cells = <1>;
263 clk_core_b_div: clk_core_b_div {
264 compatible = "rockchip,rk3188-div-con";
265 rockchip,bits = <0 5>;
266 clocks = <&clk_core_b>;
267 clock-output-names = "clk_core_b";
268 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
270 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
271 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
272 CLK_SET_RATE_NO_REPARENT)>;
277 clk_core_b: clk_core_b_mux {
278 compatible = "rockchip,rk3188-mux-con";
279 rockchip,bits = <7 1>;
280 clocks = <&clk_apllb>, <&clk_gpll>;
281 clock-output-names = "clk_core_b";
283 #clock-init-cells = <1>;
286 aclkm_core_b: aclkm_core_b_div {
287 compatible = "rockchip,rk3188-div-con";
288 rockchip,bits = <8 5>;
289 clocks = <&clk_core_b>;
290 clock-output-names = "aclkm_core_b";
291 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
293 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
299 clk_sel_con1: sel-con@0104 {
300 compatible = "rockchip,rk3188-selcon";
302 #address-cells = <1>;
305 atclk_core_b: atclk_core_b_div {
306 compatible = "rockchip,rk3188-div-con";
307 rockchip,bits = <0 5>;
308 clocks = <&clk_core_b>;
309 clock-output-names = "atclk_core_b";
310 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
312 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
317 pclk_dbg_b: pclk_dbg_b_div {
318 compatible = "rockchip,rk3188-div-con";
319 rockchip,bits = <8 5>;
320 clocks = <&clk_core_b>;
321 clock-output-names = "pclk_dbg_b";
322 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
324 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
328 clk_sel_con2: sel-con@0108 {
329 compatible = "rockchip,rk3188-selcon";
331 #address-cells = <1>;
334 clk_core_l_div: clk_core_l_div {
335 compatible = "rockchip,rk3188-div-con";
336 rockchip,bits = <0 5>;
337 clocks = <&clk_core_l>;
338 clock-output-names = "clk_core_l";
339 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
341 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
342 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
343 CLK_SET_RATE_NO_REPARENT)>;
348 clk_core_l: clk_core_l_mux {
349 compatible = "rockchip,rk3188-mux-con";
350 rockchip,bits = <7 1>;
351 clocks = <&clk_aplll>, <&clk_gpll>;
352 clock-output-names = "clk_core_l";
354 #clock-init-cells = <1>;
357 aclkm_core_l: aclkm_core_l_div {
358 compatible = "rockchip,rk3188-div-con";
359 rockchip,bits = <8 5>;
360 clocks = <&clk_core_l>;
361 clock-output-names = "aclkm_core_l";
362 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
364 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
370 clk_sel_con3: sel-con@010c {
371 compatible = "rockchip,rk3188-selcon";
373 #address-cells = <1>;
376 atclk_core_l: atclk_core_l_div {
377 compatible = "rockchip,rk3188-div-con";
378 rockchip,bits = <0 5>;
379 clocks = <&clk_core_l>;
380 clock-output-names = "atclk_core_l";
381 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
383 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
388 pclk_dbg_l: pclk_dbg_l_div {
389 compatible = "rockchip,rk3188-div-con";
390 rockchip,bits = <8 5>;
391 clocks = <&clk_core_l>;
392 clock-output-names = "pclk_dbg_l";
393 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
395 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
399 clk_sel_con4: sel-con@0110 {
400 compatible = "rockchip,rk3188-selcon";
402 #address-cells = <1>;
405 clk_cs_div: clk_cs_div {
406 compatible = "rockchip,rk3188-div-con";
407 rockchip,bits = <0 5>;
409 clock-output-names = "clk_cs";
410 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
412 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
413 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
419 compatible = "rockchip,rk3188-mux-con";
420 rockchip,bits = <6 2>;
421 clocks = <&clk_gates0 9>, <&clk_gates0 10>, <&clk_gates0 8>, <&dummy>;
422 clock-output-names = "clk_cs";
424 #clock-init-cells = <1>;
427 clkin_trace: clkin_trace_div {
428 compatible = "rockchip,rk3188-div-con";
429 rockchip,bits = <8 5>;
431 clock-output-names = "clkin_trace";
432 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
434 #clock-init-cells = <1>;
439 clk_sel_con5: sel-con@0114 {
440 compatible = "rockchip,rk3188-selcon";
442 #address-cells = <1>;
445 aclk_cci_div: aclk_cci_div {
446 compatible = "rockchip,rk3188-div-con";
447 rockchip,bits = <0 5>;
448 clocks = <&aclk_cci>;
449 clock-output-names = "aclk_cci";
450 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
452 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
457 aclk_cci: aclk_cci_mux {
458 compatible = "rockchip,rk3188-mux-con";
459 rockchip,bits = <6 2>;
460 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
461 clock-output-names = "aclk_cci";
463 #clock-init-cells = <1>;
467 /* sel[7:6] reserved */
469 clk_sel_con8: sel-con@0120 {
470 compatible = "rockchip,rk3188-selcon";
472 #address-cells = <1>;
475 aclk_bus_div: aclk_bus_div {
476 compatible = "rockchip,rk3188-div-con";
477 rockchip,bits = <0 5>;
478 clocks = <&aclk_bus>;
479 clock-output-names = "aclk_bus";
480 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
482 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
487 aclk_bus: aclk_bus_mux {
488 compatible = "rockchip,rk3188-mux-con";
489 rockchip,bits = <7 1>;
490 clocks = <&clk_gates1 11>, <&clk_gates1 10>;
491 clock-output-names = "aclk_bus";
493 #clock-init-cells = <1>;
496 hclk_bus: hclk_bus_div {
497 compatible = "rockchip,rk3188-div-con";
498 rockchip,bits = <8 2>;
499 clocks = <&aclk_bus>;
500 clock-output-names = "hclk_bus";
501 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
503 #clock-init-cells = <1>;
508 pclk_bus: pclk_bus_div {
509 compatible = "rockchip,rk3188-div-con";
510 rockchip,bits = <12 3>;
511 clocks = <&aclk_bus>;
512 clock-output-names = "pclk_bus";
513 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
515 #clock-init-cells = <1>;
519 clk_sel_con9: sel-con@0124 {
520 compatible = "rockchip,rk3188-selcon";
522 #address-cells = <1>;
525 aclk_peri_div: aclk_peri_div {
526 compatible = "rockchip,rk3188-div-con";
527 rockchip,bits = <0 5>;
528 clocks = <&aclk_peri>;
529 clock-output-names = "aclk_peri";
530 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
532 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
537 aclk_peri: aclk_peri_mux {
538 compatible = "rockchip,rk3188-mux-con";
539 rockchip,bits = <7 1>;
540 clocks = <&clk_cpll>, <&clk_gpll>;
541 clock-output-names = "aclk_peri";
543 #clock-init-cells = <1>;
546 hclk_peri: hclk_peri_div {
547 compatible = "rockchip,rk3188-div-con";
548 rockchip,bits = <8 2>;
549 clocks = <&aclk_peri>;
550 clock-output-names = "hclk_peri";
551 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
552 rockchip,div-relations =
557 #clock-init-cells = <1>;
562 pclk_peri: pclk_peri_div {
563 compatible = "rockchip,rk3188-div-con";
564 rockchip,bits = <12 2>;
565 clocks = <&aclk_peri>;
566 clock-output-names = "pclk_peri";
567 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
568 rockchip,div-relations =
574 #clock-init-cells = <1>;
578 clk_sel_con10: sel-con@0128 {
579 compatible = "rockchip,rk3188-selcon";
581 #address-cells = <1>;
584 pclk_pmu_pre: pclk_pmu_pre_div {
585 compatible = "rockchip,rk3188-div-con";
586 rockchip,bits = <0 5>;
587 clocks = <&clk_gpll>;
588 clock-output-names = "pclk_pmu_pre";
589 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
591 #clock-init-cells = <1>;
596 pclk_alive_pre: pclk_alive_pre_div {
597 compatible = "rockchip,rk3188-div-con";
598 rockchip,bits = <8 5>;
599 clocks = <&clk_gpll>;
600 clock-output-names = "pclk_alive_pre";
601 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
603 #clock-init-cells = <1>;
608 clk_crypto: clk_crypto_div {
609 compatible = "rockchip,rk3188-div-con";
610 rockchip,bits = <14 2>;
611 clocks = <&aclk_bus>;
612 clock-output-names = "clk_crypto";
613 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
615 #clock-init-cells = <1>;
619 /* sel[11]: reserved */
621 clk_sel_con12: sel-con@0130 {
622 compatible = "rockchip,rk3188-selcon";
624 #address-cells = <1>;
627 fclk_mcu_div: fclk_mcu_div {
628 compatible = "rockchip,rk3188-div-con";
629 rockchip,bits = <0 5>;
630 clocks = <&fclk_mcu>;
631 clock-output-names = "fclk_mcu";
632 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
634 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
639 fclk_mcu: fclk_mcu_mux {
640 compatible = "rockchip,rk3188-mux-con";
641 rockchip,bits = <7 1>;
642 clocks = <&clk_cpll>, <&clk_gpll>;
643 clock-output-names = "fclk_mcu";
645 #clock-init-cells = <1>;
648 stclk_mcu: stclk_mcu_div {
649 compatible = "rockchip,rk3188-div-con";
650 rockchip,bits = <8 3>;
651 clocks = <&fclk_mcu>;
652 clock-output-names = "stclk_mcu";
653 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
658 clk_sel_con13: sel-con@0134 {
659 compatible = "rockchip,rk3188-selcon";
661 #address-cells = <1>;
664 clk_ddr_div: clk_ddr_div {
665 compatible = "rockchip,rk3188-div-con";
666 rockchip,bits = <0 2>;
668 clock-output-names = "clk_ddr";
669 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
671 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
672 CLK_SET_RATE_NO_REPARENT)>;
673 rockchip,clkops-idx =
674 <CLKOPS_RATE_DDR_DIV4>;
679 clk_ddr: clk_ddr_mux {
680 compatible = "rockchip,rk3188-mux-con";
681 rockchip,bits = <4 1>;
682 clocks = <&clk_dpll>, <&clk_gpll>;
683 clock-output-names = "clk_ddr";
689 usbphy_480m: usbphy_480m_mux {
690 compatible = "rockchip,rk3188-mux-con";
691 rockchip,bits = <8 1>;
692 clocks = <&xin24m>, <&usbotg_480m_out>;
693 clock-output-names = "usbphy_480m";
695 rockchip,clkops-idx =
696 <CLKOPS_RATE_RK3288_USB480M>;
697 #clock-init-cells = <1>;
701 clk_sel_con14: sel-con@0138 {
702 compatible = "rockchip,rk3188-selcon";
704 #address-cells = <1>;
707 clk_gpu_core_div: clk_gpu_core_div {
708 compatible = "rockchip,rk3188-div-con";
709 rockchip,bits = <0 5>;
710 clocks = <&clk_gpu_core>;
711 clock-output-names = "clk_gpu";
712 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
714 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
715 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
720 clk_gpu_core: clk_gpu_core_mux {
721 compatible = "rockchip,rk3188-mux-con";
722 rockchip,bits = <6 2>;
723 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
724 clock-output-names = "clk_gpu";
726 #clock-init-cells = <1>;
729 aclk_gpu_mem: aclk_gpu_mem_div {
730 compatible = "rockchip,rk3188-div-con";
731 rockchip,bits = <8 5>;
732 clocks = <&aclk_gpu>;
733 clock-output-names = "aclk_gpu_mem";
734 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
736 #clock-init-cells = <1>;
741 aclk_gpu: aclk_gpu_mux {
742 compatible = "rockchip,rk3188-mux-con";
743 rockchip,bits = <14 1>;
744 clocks = <&clk_cpll>, <&clk_gpll>;
745 clock-output-names = "aclk_gpu";
747 #clock-init-cells = <1>;
751 clk_sel_con15: sel-con@013c {
752 compatible = "rockchip,rk3188-selcon";
754 #address-cells = <1>;
757 aclk_vepu_div: aclk_vepu_div {
758 compatible = "rockchip,rk3188-div-con";
759 rockchip,bits = <0 5>;
760 clocks = <&aclk_vepu>;
761 clock-output-names = "aclk_vepu";
762 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
764 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
769 aclk_vepu: aclk_vepu_mux {
770 compatible = "rockchip,rk3188-mux-con";
771 rockchip,bits = <6 2>;
772 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
773 clock-output-names = "aclk_vepu";
775 #clock-init-cells = <1>;
778 aclk_vdpu_div: aclk_vdpu_div {
779 compatible = "rockchip,rk3188-div-con";
780 rockchip,bits = <8 5>;
781 clocks = <&aclk_vdpu>;
782 clock-output-names = "aclk_vdpu";
783 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
785 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
790 aclk_vdpu: aclk_vdpu_mux {
791 compatible = "rockchip,rk3188-mux-con";
792 rockchip,bits = <14 2>;
793 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
794 clock-output-names = "aclk_vdpu";
796 #clock-init-cells = <1>;
800 clk_sel_con16: sel-con@0140 {
801 compatible = "rockchip,rk3188-selcon";
803 #address-cells = <1>;
806 aclk_gpu_cfg: aclk_gpu_cfg_div {
807 compatible = "rockchip,rk3188-div-con";
808 rockchip,bits = <8 5>;
809 clocks = <&aclk_gpu>;
810 clock-output-names = "aclk_gpu_cfg";
811 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
813 #clock-init-cells = <1>;
817 clk_sel_con17: sel-con@0144 {
818 compatible = "rockchip,rk3188-selcon";
820 #address-cells = <1>;
823 clk_hevc_cabac_div: clk_hevc_cabac_div {
824 compatible = "rockchip,rk3188-div-con";
825 rockchip,bits = <0 5>;
826 clocks = <&clk_hevc_cabac>;
827 clock-output-names = "clk_hevc_cabac";
828 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
830 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
835 clk_hevc_cabac: clk_hevc_cabac_mux {
836 compatible = "rockchip,rk3188-mux-con";
837 rockchip,bits = <6 2>;
838 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
839 clock-output-names = "clk_hevc_cabac";
841 #clock-init-cells = <1>;
844 clk_hevc_core_div: clk_hevc_core_div {
845 compatible = "rockchip,rk3188-div-con";
846 rockchip,bits = <8 5>;
847 clocks = <&clk_hevc_core>;
848 clock-output-names = "clk_hevc_core";
849 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
851 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
856 clk_hevc_core: clk_hevc_core_mux {
857 compatible = "rockchip,rk3188-mux-con";
858 rockchip,bits = <14 2>;
859 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
860 clock-output-names = "clk_hevc_core";
862 #clock-init-cells = <1>;
866 clk_sel_con18: sel-con@0148 {
867 compatible = "rockchip,rk3188-selcon";
869 #address-cells = <1>;
872 clk_rga_div: clk_rga_div {
873 compatible = "rockchip,rk3188-div-con";
874 rockchip,bits = <0 5>;
876 clock-output-names = "clk_rga";
877 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
879 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
884 clk_rga: clk_rga_mux {
885 compatible = "rockchip,rk3188-mux-con";
886 rockchip,bits = <6 2>;
887 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
888 clock-output-names = "clk_rga";
890 #clock-init-cells = <1>;
893 aclk_rga_div: aclk_rga_div {
894 compatible = "rockchip,rk3188-div-con";
895 rockchip,bits = <8 5>;
896 clocks = <&aclk_rga_pre>;
897 clock-output-names = "aclk_rga_pre";
898 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
900 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
905 aclk_rga_pre: aclk_rga_mux {
906 compatible = "rockchip,rk3188-mux-con";
907 rockchip,bits = <14 2>;
908 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
909 clock-output-names = "aclk_rga_pre";
911 #clock-init-cells = <1>;
915 clk_sel_con19: sel-con@014c {
916 compatible = "rockchip,rk3188-selcon";
918 #address-cells = <1>;
921 aclk_vio0_div: aclk_vio0_div {
922 compatible = "rockchip,rk3188-div-con";
923 rockchip,bits = <0 5>;
924 clocks = <&aclk_vio0>;
925 clock-output-names = "aclk_vio0";
926 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
928 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
933 aclk_vio0: aclk_vio0_mux {
934 compatible = "rockchip,rk3188-mux-con";
935 rockchip,bits = <6 2>;
936 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
937 clock-output-names = "aclk_vio0";
939 #clock-init-cells = <1>;
943 clk_sel_con20: sel-con@0150 {
944 compatible = "rockchip,rk3188-selcon";
946 #address-cells = <1>;
949 dclk_vop0_div: dclk_vop0_div {
950 compatible = "rockchip,rk3188-div-con";
951 rockchip,bits = <0 8>;
952 clocks = <&dclk_vop0>;
953 clock-output-names = "dclk_vop0";
954 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
956 rockchip,clkops-idx =
957 <CLKOPS_RATE_RK3368_DCLK_LCDC>;
958 rockchip,flags = <CLK_SET_RATE_PARENT>;
962 dclk_vop0: dclk_vop0_mux {
963 compatible = "rockchip,rk3188-mux-con";
964 rockchip,bits = <8 2>;
965 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&dummy>;
966 clock-output-names = "dclk_vop0";
968 #clock-init-cells = <1>;
974 clk_sel_con21: sel-con@0154 {
975 compatible = "rockchip,rk3188-selcon";
977 #address-cells = <1>;
980 hclk_vio: hclk_vio_div {
981 compatible = "rockchip,rk3188-div-con";
982 rockchip,bits = <0 5>;
983 clocks = <&aclk_vio0>;
984 clock-output-names = "hclk_vio";
985 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
987 #clock-init-cells = <1>;
992 pclk_isp: pclk_isp_mux {
993 compatible = "rockchip,rk3188-mux-con";
994 rockchip,bits = <6 1>;
995 clocks = <&clk_gates17 2>, <&pclkin_isp_inv>;
996 clock-output-names = "pclk_isp";
1002 clk_vip_div: clk_vip_div {
1003 compatible = "rockchip,rk3188-div-con";
1004 rockchip,bits = <8 5>;
1005 clocks = <&clk_vip>;
1006 clock-output-names = "clk_vip";
1007 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1009 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1012 pclk_vip: pclk_vip_mux {
1013 compatible = "rockchip,rk3188-mux-con";
1014 rockchip,bits = <13 1>;
1015 clocks = <&clk_gates16 13>, <&pclkin_vip_inv>;
1016 clock-output-names = "pclk_vip";
1020 clk_vip: clk_vip_mux {
1021 compatible = "rockchip,rk3188-mux-con";
1022 rockchip,bits = <14 1>;
1023 clocks = <&clk_vip_pll>, <&xin24m>;
1024 clock-output-names = "clk_vip";
1026 #clock-init-cells = <1>;
1029 clk_vip_pll: clk_vip_pll_mux {
1030 compatible = "rockchip,rk3188-mux-con";
1031 rockchip,bits = <15 1>;
1032 clocks = <&clk_cpll>, <&clk_gpll>;
1033 clock-output-names = "clk_vip_pll";
1035 #clock-init-cells = <1>;
1039 clk_sel_con22: sel-con@0158 {
1040 compatible = "rockchip,rk3188-selcon";
1042 #address-cells = <1>;
1045 clk_isp_div: clk_isp_div {
1046 compatible = "rockchip,rk3188-div-con";
1047 rockchip,bits = <0 6>;
1048 clocks = <&clk_isp>;
1049 clock-output-names = "clk_isp";
1050 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1052 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1055 clk_isp: clk_isp_mux {
1056 compatible = "rockchip,rk3188-mux-con";
1057 rockchip,bits = <6 2>;
1058 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1059 clock-output-names = "clk_isp";
1061 #clock-init-cells = <1>;
1065 clk_sel_con23: sel-con@015c {
1066 compatible = "rockchip,rk3188-selcon";
1068 #address-cells = <1>;
1071 clk_edp_div: clk_edp_div {
1072 compatible = "rockchip,rk3188-div-con";
1073 rockchip,bits = <0 6>;
1074 clocks = <&clk_edp>;
1075 clock-output-names = "clk_edp";
1076 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1078 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1081 clk_edp: clk_edp_mux {
1082 compatible = "rockchip,rk3188-mux-con";
1083 rockchip,bits = <6 2>;
1084 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1085 clock-output-names = "clk_edp";
1087 #clock-init-cells = <1>;
1090 clk_edp_24m: clk_edp_24m_mux {
1091 compatible = "rockchip,rk3188-mux-con";
1092 rockchip,bits = <8 1>;
1093 clocks = <&xin24m>, <&dummy>;
1094 clock-output-names = "clk_edp_24m";
1099 /* sel[24]: reserved */
1101 clk_sel_con25: sel-con@0164 {
1102 compatible = "rockchip,rk3188-selcon";
1104 #address-cells = <1>;
1107 clk_tsadc: clk_tsadc_div {
1108 compatible = "rockchip,rk3188-div-con";
1109 rockchip,bits = <0 6>;
1110 clocks = <&clk_32k_mux>;
1111 clock-output-names = "clk_tsadc";
1112 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1118 clk_saradc: clk_saradc_div {
1119 compatible = "rockchip,rk3188-div-con";
1120 rockchip,bits = <8 8>;
1122 clock-output-names = "clk_saradc";
1123 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1128 clk_sel_con26: sel-con@0168 {
1129 compatible = "rockchip,rk3188-selcon";
1131 #address-cells = <1>;
1136 hsic_usb_480m: hsic_usb_480m_mux {
1137 compatible = "rockchip,rk3188-mux-con";
1138 rockchip,bits = <8 1>;
1139 clocks = <&usbotg_480m_out>, <&dummy>;
1140 clock-output-names = "hsic_usb_480m";
1146 hsicphy_480m: hsicphy_480m_mux {
1147 compatible = "rockchip,rk3188-mux-con";
1148 rockchip,bits = <12 2>;
1149 clocks = <&clk_cpll>, <&clk_gpll>, <&hsic_usb_480m>, <&hsic_usb_480m>;
1150 clock-output-names = "hsicphy_480m";
1155 clk_sel_con27: sel-con@016c {
1156 compatible = "rockchip,rk3188-selcon";
1158 #address-cells = <1>;
1161 i2s_pll_div: i2s_pll_div {
1162 compatible = "rockchip,rk3188-div-con";
1163 rockchip,bits = <0 7>;
1164 clocks = <&i2s_pll>;
1165 clock-output-names = "i2s_pll";
1166 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1168 rockchip,clkops-idx =
1169 <CLKOPS_RATE_MUX_DIV>;
1170 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1175 clk_i2s: clk_i2s_mux {
1176 compatible = "rockchip,rk3188-mux-con";
1177 rockchip,bits = <8 2>;
1178 clocks = <&i2s_pll>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
1179 clock-output-names = "clk_i2s";
1181 rockchip,clkops-idx =
1182 <CLKOPS_RATE_RK3288_I2S>;
1183 rockchip,flags = <CLK_SET_RATE_PARENT>;
1186 /* 11:10 reserved */
1188 i2s_pll: i2s_pll_mux {
1189 compatible = "rockchip,rk3188-mux-con";
1190 rockchip,bits = <12 1>;
1191 clocks = <&clk_cpll>, <&clk_gpll>;
1192 clock-output-names = "i2s_pll";
1194 #clock-init-cells = <1>;
1197 /* 14:13 reserved */
1199 i2s_out: i2s_out_mux {
1200 compatible = "rockchip,rk3188-mux-con";
1201 rockchip,bits = <15 1>;
1202 clocks = <&clk_i2s>, <&xin12m>;
1203 clock-output-names = "i2s_out";
1208 clk_sel_con28: sel-con@0170 {
1209 compatible = "rockchip,rk3188-selcon";
1211 #address-cells = <1>;
1214 i2s_frac: i2s_frac {
1215 compatible = "rockchip,rk3188-frac-con";
1216 clocks = <&i2s_pll>;
1217 clock-output-names = "i2s_frac";
1218 /* numerator denominator */
1219 rockchip,bits = <0 32>;
1220 rockchip,clkops-idx =
1226 /* sel[30:29] reserved */
1228 clk_sel_con31: sel-con@017c {
1229 compatible = "rockchip,rk3188-selcon";
1231 #address-cells = <1>;
1235 spdif_8ch_pll_div: spdif_8ch_pll_div {
1236 compatible = "rockchip,rk3188-div-con";
1237 rockchip,bits = <0 7>;
1238 clocks = <&spdif_8ch_pll>;
1239 clock-output-names = "spdif_8ch_pll";
1240 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1242 rockchip,clkops-idx =
1243 <CLKOPS_RATE_MUX_DIV>;
1244 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1249 clk_spidf_8ch: clk_spidf_8ch_mux {
1250 compatible = "rockchip,rk3188-mux-con";
1251 rockchip,bits = <8 2>;
1252 clocks = <&spdif_8ch_pll>, <&spdif_8ch_frac>, <&i2s_clkin>, <&xin12m>;
1253 clock-output-names = "clk_spidf_8ch";
1255 rockchip,clkops-idx =
1256 <CLKOPS_RATE_RK3288_I2S>;
1257 rockchip,flags = <CLK_SET_RATE_PARENT>;
1260 /* 11:10 reserved */
1262 spdif_8ch_pll: spdif_8ch_pll_mux {
1263 compatible = "rockchip,rk3188-mux-con";
1264 rockchip,bits = <12 1>;
1265 clocks = <&clk_cpll>, <&clk_gpll>;
1266 clock-output-names = "spdif_8ch_pll";
1268 #clock-init-cells = <1>;
1271 /* 15:13 reserved */
1274 clk_sel_con32: sel-con@0180 {
1275 compatible = "rockchip,rk3188-selcon";
1277 #address-cells = <1>;
1280 spdif_8ch_frac: spdif_8ch_frac {
1281 compatible = "rockchip,rk3188-frac-con";
1282 clocks = <&spdif_8ch_pll>;
1283 clock-output-names = "spdif_8ch_frac";
1284 /* numerator denominator */
1285 rockchip,bits = <0 32>;
1286 rockchip,clkops-idx =
1292 clk_sel_con33: sel-con@0184 {
1293 compatible = "rockchip,rk3188-selcon";
1295 #address-cells = <1>;
1298 clk_uart0_pll_div: clk_uart0_pll_div {
1299 compatible = "rockchip,rk3188-div-con";
1300 rockchip,bits = <0 7>;
1301 clocks = <&clk_uart0_pll>;
1302 clock-output-names = "clk_uart0_pll";
1303 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1305 rockchip,clkops-idx =
1306 <CLKOPS_RATE_MUX_DIV>;
1311 clk_uart0: clk_uart0_mux {
1312 compatible = "rockchip,rk3188-mux-con";
1313 rockchip,bits = <8 2>;
1314 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>, <&xin24m>;
1315 clock-output-names = "clk_uart0";
1317 rockchip,clkops-idx =
1318 <CLKOPS_RATE_RK3288_I2S>;
1319 rockchip,flags = <CLK_SET_RATE_PARENT>;
1322 /* 11:10 reserved */
1324 clk_uart0_pll: clk_uart0_pll_mux {
1325 compatible = "rockchip,rk3188-mux-con";
1326 rockchip,bits = <12 2>;
1327 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
1328 clock-output-names = "clk_uart0_pll";
1333 clk_sel_con34: sel-con@0188 {
1334 compatible = "rockchip,rk3188-selcon";
1336 #address-cells = <1>;
1339 uart0_frac: uart0_frac {
1340 compatible = "rockchip,rk3188-frac-con";
1341 clocks = <&clk_uart0_pll>;
1342 clock-output-names = "uart0_frac";
1343 /* numerator denominator */
1344 rockchip,bits = <0 32>;
1345 rockchip,clkops-idx =
1351 clk_sel_con35: sel-con@018c {
1352 compatible = "rockchip,rk3188-selcon";
1354 #address-cells = <1>;
1357 uart1_div: uart1_div {
1358 compatible = "rockchip,rk3188-div-con";
1359 rockchip,bits = <0 7>;
1360 clocks = <&clk_uart_pll>;
1361 clock-output-names = "uart1_div";
1362 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1368 clk_uart1: clk_uart1_mux {
1369 compatible = "rockchip,rk3188-mux-con";
1370 rockchip,bits = <8 2>;
1371 clocks = <&uart1_div>, <&uart1_frac>, <&xin24m>, <&xin24m>;
1372 clock-output-names = "clk_uart1";
1374 rockchip,clkops-idx =
1375 <CLKOPS_RATE_RK3288_I2S>;
1376 rockchip,flags = <CLK_SET_RATE_PARENT>;
1379 /* 11:10 reserved */
1381 clk_uart_pll: clk_uart_pll_mux {
1382 compatible = "rockchip,rk3188-mux-con";
1383 rockchip,bits = <12 1>;
1384 clocks = <&clk_cpll>, <&clk_gpll>;
1385 clock-output-names = "clk_uart_pll";
1387 #clock-init-cells = <1>;
1391 clk_sel_con36: sel-con@0190 {
1392 compatible = "rockchip,rk3188-selcon";
1394 #address-cells = <1>;
1397 uart1_frac: uart1_frac {
1398 compatible = "rockchip,rk3188-frac-con";
1399 clocks = <&uart1_div>;
1400 clock-output-names = "uart1_frac";
1401 /* numerator denominator */
1402 rockchip,bits = <0 32>;
1403 rockchip,clkops-idx =
1409 clk_sel_con37: sel-con@0194 {
1410 compatible = "rockchip,rk3188-selcon";
1412 #address-cells = <1>;
1415 uart2_div: uart2_div {
1416 compatible = "rockchip,rk3188-div-con";
1417 rockchip,bits = <0 7>;
1418 clocks = <&clk_uart_pll>;
1419 clock-output-names = "uart2_div";
1420 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1426 clk_uart2: clk_uart2_mux {
1427 compatible = "rockchip,rk3188-mux-con";
1428 rockchip,bits = <8 1>;
1429 clocks = <&uart2_div>, <&xin24m>;
1430 clock-output-names = "clk_uart2";
1432 rockchip,flags = <CLK_SET_RATE_PARENT>;
1436 /* sel[38] reserved */
1438 clk_sel_con39: sel-con@019c {
1439 compatible = "rockchip,rk3188-selcon";
1441 #address-cells = <1>;
1444 uart3_div: uart3_div {
1445 compatible = "rockchip,rk3188-div-con";
1446 rockchip,bits = <0 7>;
1447 clocks = <&clk_uart_pll>;
1448 clock-output-names = "uart3_div";
1449 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1455 clk_uart3: clk_uart3_mux {
1456 compatible = "rockchip,rk3188-mux-con";
1457 rockchip,bits = <8 2>;
1458 clocks = <&uart3_div>, <&uart3_frac>, <&xin24m>, <&xin24m>;
1459 clock-output-names = "clk_uart3";
1461 rockchip,clkops-idx =
1462 <CLKOPS_RATE_RK3288_I2S>;
1463 rockchip,flags = <CLK_SET_RATE_PARENT>;
1467 clk_sel_con40: sel-con@01a0 {
1468 compatible = "rockchip,rk3188-selcon";
1470 #address-cells = <1>;
1473 uart3_frac: uart3_frac {
1474 compatible = "rockchip,rk3188-frac-con";
1475 clocks = <&uart3_div>;
1476 clock-output-names = "uart3_frac";
1477 /* numerator denominator */
1478 rockchip,bits = <0 32>;
1479 rockchip,clkops-idx =
1485 clk_sel_con41: sel-con@01a4 {
1486 compatible = "rockchip,rk3188-selcon";
1488 #address-cells = <1>;
1491 uart4_div: uart4_div {
1492 compatible = "rockchip,rk3188-div-con";
1493 rockchip,bits = <0 7>;
1494 clocks = <&clk_uart_pll>;
1495 clock-output-names = "uart4_div";
1496 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1502 clk_uart4: clk_uart4_mux {
1503 compatible = "rockchip,rk3188-mux-con";
1504 rockchip,bits = <8 2>;
1505 clocks = <&uart4_div>, <&uart4_frac>, <&xin24m>, <&xin24m>;
1506 clock-output-names = "clk_uart4";
1508 rockchip,clkops-idx =
1509 <CLKOPS_RATE_RK3288_I2S>;
1510 rockchip,flags = <CLK_SET_RATE_PARENT>;
1514 clk_sel_con42: sel-con@01a8 {
1515 compatible = "rockchip,rk3188-selcon";
1517 #address-cells = <1>;
1520 uart4_frac: uart4_frac {
1521 compatible = "rockchip,rk3188-frac-con";
1522 clocks = <&uart4_div>;
1523 clock-output-names = "uart4_frac";
1524 /* numerator denominator */
1525 rockchip,bits = <0 32>;
1526 rockchip,clkops-idx =
1532 clk_sel_con43: sel-con@01ac {
1533 compatible = "rockchip,rk3188-selcon";
1535 #address-cells = <1>;
1538 clk_mac_pll_div: clk_mac_pll_div {
1539 compatible = "rockchip,rk3188-div-con";
1540 rockchip,bits = <0 5>;
1541 clocks = <&clk_mac_pll>;
1542 clock-output-names = "clk_mac_pll";
1543 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1545 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1550 clk_mac_pll: clk_mac_pll_mux {
1551 compatible = "rockchip,rk3188-mux-con";
1552 rockchip,bits = <6 2>;
1553 clocks = <&clk_npll>, <&clk_cpll>, <&clk_gpll>, <&clk_gpll>;
1554 clock-output-names = "clk_mac_pll";
1558 clk_mac: clk_mac_mux {
1559 compatible = "rockchip,rk3188-mux-con";
1560 rockchip,bits = <8 1>;
1561 clocks = <&clk_mac_pll>, <&gmac_clkin>;
1562 clock-output-names = "clk_mac";
1564 rockchip,flags = <CLK_SET_RATE_PARENT>;
1565 #clock-init-cells = <1>;
1570 /* 12: test_clk: wifi_pll_sel */
1572 /* 15:13 reserved */
1575 clk_sel_con44: sel-con@01b0 {
1576 compatible = "rockchip,rk3188-selcon";
1578 #address-cells = <1>;
1581 /* test_clk: wifi_frac */
1584 clk_sel_con45: sel-con@01b4 {
1585 compatible = "rockchip,rk3188-selcon";
1587 #address-cells = <1>;
1590 clk_spi0_div: clk_spi0_div {
1591 compatible = "rockchip,rk3188-div-con";
1592 rockchip,bits = <0 7>;
1593 clocks = <&clk_spi0>;
1594 clock-output-names = "clk_spi0";
1595 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1597 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1600 clk_spi0: clk_spi0_mux {
1601 compatible = "rockchip,rk3188-mux-con";
1602 rockchip,bits = <7 1>;
1603 clocks = <&clk_cpll>, <&clk_gpll>;
1604 clock-output-names = "clk_spi0";
1608 clk_spi1_div: clk_spi1_div {
1609 compatible = "rockchip,rk3188-div-con";
1610 rockchip,bits = <8 7>;
1611 clocks = <&clk_spi1>;
1612 clock-output-names = "clk_spi1";
1613 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1615 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1618 clk_spi1: clk_spi1_mux {
1619 compatible = "rockchip,rk3188-mux-con";
1620 rockchip,bits = <15 1>;
1621 clocks = <&clk_cpll>, <&clk_gpll>;
1622 clock-output-names = "clk_spi1";
1627 clk_sel_con46: sel-con@01b8 {
1628 compatible = "rockchip,rk3188-selcon";
1630 #address-cells = <1>;
1633 clk_tsp_div: clk_tsp_div {
1634 compatible = "rockchip,rk3188-div-con";
1635 rockchip,bits = <0 5>;
1636 clocks = <&clk_tsp>;
1637 clock-output-names = "clk_tsp";
1638 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1640 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1645 clk_tsp: clk_tsp_mux {
1646 compatible = "rockchip,rk3188-mux-con";
1647 rockchip,bits = <6 2>;
1648 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1649 clock-output-names = "clk_tsp";
1653 clk_spi2_div: clk_spi2_div {
1654 compatible = "rockchip,rk3188-div-con";
1655 rockchip,bits = <8 7>;
1656 clocks = <&clk_spi2>;
1657 clock-output-names = "clk_spi2";
1658 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1660 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1663 clk_spi2: clk_spi2_mux {
1664 compatible = "rockchip,rk3188-mux-con";
1665 rockchip,bits = <15 1>;
1666 clocks = <&clk_cpll>, <&clk_gpll>;
1667 clock-output-names = "clk_spi2";
1672 clk_sel_con47: sel-con@01bc {
1673 compatible = "rockchip,rk3188-selcon";
1675 #address-cells = <1>;
1678 clk_nandc0_div: clk_nandc0_div {
1679 compatible = "rockchip,rk3188-div-con";
1680 rockchip,bits = <0 5>;
1681 clocks = <&clk_nandc0>;
1682 clock-output-names = "clk_nandc0";
1683 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1685 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1690 clk_nandc0: clk_nandc0_mux {
1691 compatible = "rockchip,rk3188-mux-con";
1692 rockchip,bits = <7 1>;
1693 clocks = <&clk_cpll>, <&clk_gpll>;
1694 clock-output-names = "clk_nandc0";
1700 /* 15:13 reserved */
1703 clk_sel_con48: sel-con@01c0 {
1704 compatible = "rockchip,rk3188-selcon";
1706 #address-cells = <1>;
1709 clk_sdio0_div: clk_sdio0_div {
1710 compatible = "rockchip,rk3188-div-con";
1711 rockchip,bits = <0 7>;
1712 clocks = <&clk_sdio0>;
1713 clock-output-names = "clk_sdio0";
1714 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1716 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1721 clk_sdio0: clk_sdio0_mux {
1722 compatible = "rockchip,rk3188-mux-con";
1723 rockchip,bits = <8 2>;
1724 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1725 clock-output-names = "clk_sdio0";
1729 /* 15:10 reserved */
1732 /* sel[49] reserved */
1734 clk_sel_con50: sel-con@01c8 {
1735 compatible = "rockchip,rk3188-selcon";
1737 #address-cells = <1>;
1740 clk_sdmmc0_div: clk_sdmmc0_div {
1741 compatible = "rockchip,rk3188-div-con";
1742 rockchip,bits = <0 7>;
1743 clocks = <&clk_sdmmc0>;
1744 clock-output-names = "clk_sdmmc0";
1745 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1747 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1752 clk_sdmmc0: clk_sdmmc0_mux {
1753 compatible = "rockchip,rk3188-mux-con";
1754 rockchip,bits = <8 2>;
1755 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1756 clock-output-names = "clk_sdmmc0";
1760 /* 15:10 reserved */
1763 clk_sel_con51: sel-con@01cc {
1764 compatible = "rockchip,rk3188-selcon";
1766 #address-cells = <1>;
1769 clk_emmc_div: clk_emmc_div {
1770 compatible = "rockchip,rk3188-div-con";
1771 rockchip,bits = <0 7>;
1772 clocks = <&clk_emmc>;
1773 clock-output-names = "clk_emmc";
1774 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1776 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1781 clk_emmc: clk_emmc_mux {
1782 compatible = "rockchip,rk3188-mux-con";
1783 rockchip,bits = <8 2>;
1784 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1785 clock-output-names = "clk_emmc";
1789 /* 15:10 reserved */
1792 clk_sel_con52: sel-con@01d0 {
1793 compatible = "rockchip,rk3188-selcon";
1795 #address-cells = <1>;
1798 clk_sfc_div: clk_sfc_div {
1799 compatible = "rockchip,rk3188-div-con";
1800 rockchip,bits = <0 5>;
1801 clocks = <&clk_sfc>;
1802 clock-output-names = "clk_sfc";
1803 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1805 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1810 clk_sfc: clk_sfc_mux {
1811 compatible = "rockchip,rk3188-mux-con";
1812 rockchip,bits = <7 1>;
1813 clocks = <&clk_cpll>, <&clk_gpll>;
1814 clock-output-names = "clk_sfc";
1821 clk_sel_con53: sel-con@01d4 {
1822 compatible = "rockchip,rk3188-selcon";
1824 #address-cells = <1>;
1827 i2s_2ch_pll_div: i2s_2ch_pll_div {
1828 compatible = "rockchip,rk3188-div-con";
1829 rockchip,bits = <0 7>;
1830 clocks = <&i2s_2ch_pll>;
1831 clock-output-names = "i2s_2ch_pll";
1832 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1834 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1835 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1840 clk_i2s_2ch: clk_i2s_2ch_mux {
1841 compatible = "rockchip,rk3188-mux-con";
1842 rockchip,bits = <8 2>;
1843 clocks = <&i2s_2ch_pll>, <&i2s_2ch_frac>, <&dummy>, <&xin12m>;
1844 clock-output-names = "clk_i2s_2ch";
1846 rockchip,clkops-idx =
1847 <CLKOPS_RATE_RK3288_I2S>;
1848 rockchip,flags = <CLK_SET_RATE_PARENT>;
1851 /* 11:10 reserved */
1853 i2s_2ch_pll: i2s_2ch_pll_mux {
1854 compatible = "rockchip,rk3188-mux-con";
1855 rockchip,bits = <12 1>;
1856 clocks = <&clk_cpll>, <&clk_gpll>;
1857 clock-output-names = "i2s_2ch_pll";
1859 #clock-init-cells = <1>;
1864 clk_sel_con54: sel-con@01d8 {
1865 compatible = "rockchip,rk3188-selcon";
1867 #address-cells = <1>;
1870 i2s_2ch_frac: i2s_2ch_frac {
1871 compatible = "rockchip,rk3188-frac-con";
1872 clocks = <&i2s_2ch_pll>;
1873 clock-output-names = "i2s_2ch_frac";
1874 /* numerator denominator */
1875 rockchip,bits = <0 32>;
1876 rockchip,clkops-idx =
1882 clk_sel_con55: sel-con@01dc {
1883 compatible = "rockchip,rk3188-selcon";
1885 #address-cells = <1>;
1888 clk_hdcp_div: clk_hdcp_div {
1889 compatible = "rockchip,rk3188-div-con";
1890 rockchip,bits = <0 6>;
1891 clocks = <&clk_hdcp>;
1892 clock-output-names = "clk_hdcp";
1893 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1895 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1898 clk_hdcp: clk_hdcp_mux {
1899 compatible = "rockchip,rk3188-mux-con";
1900 rockchip,bits = <6 2>;
1901 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1902 clock-output-names = "clk_hdcp";
1908 /* Gate control regs */
1910 compatible = "rockchip,rk-gate-cons";
1911 #address-cells = <1>;
1915 clk_gates0: gate-clk@0200 {
1916 compatible = "rockchip,rk3188-gate-clk";
1925 <&clk_gpll>, <&clk_apllb>,
1926 <&clk_aplll>, <&dummy>,
1928 <&aclk_cci>, <&clkin_trace>,
1931 clock-output-names =
1932 "reserved", "reserved",/* core_b_apll core_b_gpll */
1933 "reserved", "reserved",
1935 "reserved", "reserved",/* core_l_apll core_l_gpll */
1936 "reserved", "reserved",
1938 "g_clk_cs_gpll", "g_clk_cs_apllb",
1939 "g_clk_cs_aplll", "reserved",
1941 "aclk_cci", "clkin_trace",
1942 "reserved", "reserved";
1947 clk_gates1: gate-clk@0204 {
1948 compatible = "rockchip,rk3188-gate-clk";
1951 <&aclk_bus>, <&hclk_bus>,
1952 <&pclk_bus>, <&fclk_mcu>,
1958 <&clk_gpll>, <&clk_cpll>,
1963 clock-output-names =
1964 "aclk_bus", "hclk_bus",
1965 "pclk_bus", "fclk_mcu",
1967 "reserved", "reserved",
1968 "reserved", "reserved",
1970 "reserved", "reserved",/* ddr_dpll ddr_gpll */
1971 "aclk_bus_gpll", "aclk_bus_cpll",
1973 "reserved", "reserved",
1974 "reserved", "reserved";
1979 clk_gates2: gate-clk@0208 {
1980 compatible = "rockchip,rk3188-gate-clk";
1983 <&clk_uart0_pll>, <&uart0_frac>,
1984 <&uart1_div>, <&uart1_frac>,
1986 <&uart2_div>, <&dummy>,
1987 <&uart3_div>, <&uart3_frac>,
1989 <&uart4_div>, <&uart4_frac>,
1995 clock-output-names =
1996 "clk_uart0_pll", "uart0_frac",
1997 "uart1_div", "uart1_frac",
1999 "uart2_div", "reserved",
2000 "uart3_div", "uart3_frac",
2002 "uart4_div", "uart4_frac",
2003 "reserved", "reserved",
2005 "reserved", "reserved",
2006 "reserved", "reserved";
2011 clk_gates3: gate-clk@020c {
2012 compatible = "rockchip,rk3188-gate-clk";
2015 <&aclk_peri>, <&dummy>,
2016 <&hclk_peri>, <&pclk_peri>,
2018 <&clk_mac_pll>, <&clk_tsadc>,
2019 <&clk_saradc>, <&clk_spi0>,
2021 <&clk_spi1>, <&clk_spi2>,
2027 clock-output-names =
2028 "aclk_peri", "reserved", /* bit1: aclk_peri */
2029 "hclk_peri", "pclk_peri",
2031 "clk_mac_pll", "clk_tsadc",
2032 "clk_saradc", "clk_spi0",
2034 "clk_spi1", "clk_spi2",
2035 "reserved", "reserved",
2037 "reserved", "reserved",
2038 "reserved", "reserved";
2043 clk_gates4: gate-clk@0210 {
2044 compatible = "rockchip,rk3188-gate-clk";
2047 <&aclk_vio0>, <&dclk_vop0>,
2048 <&xin24m>, <&aclk_rga_pre>,
2050 <&clk_rga>, <&clk_vip_pll>,
2051 <&aclk_vepu>, <&aclk_vdpu>,
2053 <&dummy>, <&clk_isp>,
2054 <&dummy>, <&clk_gpu_core>,
2056 <&xin32k>, <&xin24m>,
2057 <&xin24m>, <&dummy>;
2059 clock-output-names =
2060 "aclk_vio0", "dclk_vop0",
2061 "clk_vop0_pwm", "aclk_rga_pre",
2063 "clk_rga", "clk_vip_pll",
2064 "aclk_vepu", "aclk_vdpu",
2066 "reserved", "clk_isp", /* bit8: hclk_vpu */
2067 "reserved", "clk_gpu",
2069 "clk_hdmi_cec", "clk_hdmi_hdcp",
2070 "clk_dsiphy_24m", "reserved";
2075 clk_gates5: gate-clk@0214 {
2076 compatible = "rockchip,rk3188-gate-clk";
2079 <&dummy>, <&clk_hevc_cabac>,
2080 <&clk_hevc_core>, <&clk_edp>,
2082 <&clk_edp_24m>, <&clk_hdcp>,
2085 <&aclk_gpu_mem>, <&aclk_gpu_cfg>,
2088 <&dummy>, <&i2s_2ch_pll>,
2089 <&i2s_2ch_frac>, <&clk_i2s_2ch>;
2091 clock-output-names =
2092 "reserved", "clk_hevc_cabac",
2093 "clk_hevc_core", "clk_edp",
2095 "clk_edp_24m", "clk_hdcp",
2096 "reserved", "reserved",
2098 "aclk_gpu_mem", "aclk_gpu_cfg",
2099 "reserved", "reserved",
2101 "reserved", "i2s_2ch_pll",
2102 "i2s_2ch_frac", "clk_i2s_2ch";
2107 clk_gates6: gate-clk@0218 {
2108 compatible = "rockchip,rk3188-gate-clk";
2111 <&i2s_out>, <&i2s_pll>,
2112 <&i2s_frac>, <&clk_i2s>,
2114 <&spdif_8ch_pll>, <&spdif_8ch_frac>,
2115 <&clk_spidf_8ch>, <&clk_sfc>,
2120 <&clk_tsp>, <&dummy>,
2123 clock-output-names =
2124 "i2s_out", "i2s_pll",
2125 "i2s_frac", "clk_i2s",
2127 "spdif_8ch_pll", "spdif_8ch_frac",
2128 "clk_spidf_8ch", "clk_sfc",
2130 "reserved", "reserved",
2131 "reserved", "reserved",
2133 "clk_tsp", "reserved",
2134 "reserved", "reserved";/* clk_ddrphy_gate clk4x_ddrphy_gate */
2139 clk_gates7: gate-clk@021c {
2140 compatible = "rockchip,rk3188-gate-clk";
2143 <&jtag_clkin>, <&dummy>,
2144 <&clk_crypto>, <&xin24m>,
2147 <&clk_mac>, <&clk_mac>,
2149 <&clk_nandc0>, <&pclk_pmu_pre>,
2150 <&xin24m>, <&xin24m>,
2155 clock-output-names =
2156 "clk_jtag", "reserved",/* bit1: test_clk */
2157 "clk_crypto", "clk_pvtm_pmu",
2159 "clk_mac_rx", "clk_mac_tx",
2160 "clk_mac_ref", "clk_mac_refout",
2162 "clk_nandc0", "pclk_pmu_pre",
2163 "clk_pvtm_core", "clk_pvtm_gpu",
2165 "clk_sdmmc0", "clk_sdio0",
2166 "reserved", "clk_emmc";
2171 clk_gates8: gate-clk@0220 {
2172 compatible = "rockchip,rk3188-gate-clk";
2175 <&hsic_usb_480m>, <&xin24m>,
2178 <&clk_32k_mux>, <&dummy>,
2179 <&xin12m>, <&hsicphy_480m>,
2187 clock-output-names =
2188 "hsic_usb_480m", "clk_otgphy0",
2189 "reserved", "reserved",
2191 "g_clk_otg_adp", "reserved",/* bit4: clk_otg_adp */
2192 "hsicphy_12m", "hsicphy_480m",
2194 "reserved", "reserved",
2195 "reserved", "reserved",
2197 "reserved", "reserved",
2198 "reserved", "reserved";
2203 clk_gates9: gate-clk@0224 {
2204 compatible = "rockchip,rk3188-gate-clk";
2219 clock-output-names =
2220 "reserved", "reserved",
2221 "reserved", "reserved",
2223 "reserved", "reserved",
2224 "reserved", "reserved",
2226 "reserved", "reserved",
2227 "reserved", "reserved",
2229 "reserved", "reserved",
2230 "reserved", "reserved";
2235 clk_gates10: gate-clk@0228 {
2236 compatible = "rockchip,rk3188-gate-clk";
2251 clock-output-names =
2252 "reserved", "reserved",
2253 "reserved", "reserved",
2255 "reserved", "reserved",
2256 "reserved", "reserved",
2258 "reserved", "reserved",
2259 "reserved", "reserved",
2261 "reserved", "reserved",
2262 "reserved", "reserved";
2267 clk_gates11: gate-clk@022c {
2268 compatible = "rockchip,rk3188-gate-clk";
2283 clock-output-names =
2284 "reserved", "reserved",
2285 "reserved", "reserved",
2287 "reserved", "reserved",
2288 "reserved", "reserved",
2290 "reserved", "reserved",
2291 "reserved", "reserved",
2293 "reserved", "reserved",
2294 "reserved", "reserved";
2299 clk_gates12: gate-clk@0230 {
2300 compatible = "rockchip,rk3188-gate-clk";
2303 <&pclk_bus>, <&pclk_bus>,
2304 <&pclk_bus>, <&pclk_bus>,
2306 <&aclk_bus>, <&aclk_bus>,
2307 <&aclk_bus>, <&hclk_bus>,
2309 <&hclk_bus>, <&hclk_bus>,
2310 <&hclk_bus>, <&aclk_bus>,
2312 <&aclk_bus>, <&dummy>,
2315 clock-output-names =
2316 "g_pclk_pwm0", "g_p_mailbox",
2317 "g_p_i2cpmu", "g_p_i2caudio",
2319 "g_aclk_intmem", "g_clk_intmem0",
2320 "g_clk_intmem1", "g_h_i2s_8ch",
2322 "g_h_i2s_2ch", "g_hclk_rom",
2323 "g_hclk_spdif", "g_aclk_dmac",
2325 "g_a_strc_sys", "reserved",/* bit13: pclk_ddrupctl */
2326 "reserved", "reserved";/* bit14: pclk_ddrphy */
2331 clk_gates13: gate-clk@0234 {
2332 compatible = "rockchip,rk3188-gate-clk";
2335 <&pclk_bus>, <&pclk_bus>,
2336 <&dummy>, <&hclk_bus>,
2338 <&hclk_bus>, <&pclk_bus>,
2339 <&pclk_bus>, <&clkin_hsadc_tsp>,
2341 <&pclk_bus>, <&aclk_bus>,
2342 <&hclk_bus>, <&dummy>,
2347 clock-output-names =
2348 "g_p_efuse_1024", "g_p_efuse_256",
2349 "reserved", "g_mclk_crypto",/* bit2: nclk_ddrupctl */
2351 "g_sclk_crypto", "g_p_uartdbg",
2352 "g_pclk_pwm1", "clk_hsadc_tsp",
2354 "g_pclk_sim", "g_aclk_gic400",
2355 "g_hclk_tsp", "reserved",
2357 "reserved", "reserved",
2358 "reserved", "reserved";
2363 clk_gates14: gate-clk@0238 {
2364 compatible = "rockchip,rk3188-gate-clk";
2379 clock-output-names =
2380 "reserved", "reserved",
2381 "reserved", "reserved",
2383 "reserved", "reserved",
2384 "reserved", "reserved",
2386 "reserved", "reserved",
2387 "reserved", "reserved",
2389 "reserved", "reserved",
2390 "reserved", "reserved";
2395 clk_gates15: gate-clk@023c {
2396 compatible = "rockchip,rk3188-gate-clk";
2411 clock-output-names =
2412 "reserved", "reserved",/* aclk_video hclk_video */
2413 "reserved", "reserved",
2415 "reserved", "reserved",
2416 "reserved", "reserved",
2418 "reserved", "reserved",
2419 "reserved", "reserved",
2421 "reserved", "reserved",
2422 "reserved", "reserved";
2427 clk_gates16: gate-clk@0240 {
2428 compatible = "rockchip,rk3188-gate-clk";
2431 <&clk_gates16 10>, <&clk_gates16 8>,
2432 <&clk_gates16 9>, <&clk_gates16 8>,
2434 <&clk_gates16 9>, <&clk_gates16 9>,
2435 <&clk_gates16 8>, <&clk_gates17 8>,
2437 <&clk_gates16 7>, <&aclk_vio0>,
2438 <&aclk_rga_pre>, <&clk_gates16 9>,
2440 <&clk_gates16 8>, <&pclkin_vip>,
2441 <&clk_isp>, <&dummy>;
2443 clock-output-names =
2444 "g_aclk_rga", "g_hclk_rga",
2445 "g_aclk_iep", "g_hclk_iep",
2447 "g_aclk_vop_iep", "g_aclk_vop",
2448 "g_hclk_vop", "h_vio_ahb_arbi",
2450 "g_hclk_vio_noc", "g_aclk_vio0_noc",
2451 "g_aclk_vio1_noc", "g_aclk_vip",
2453 "g_hclk_vip", "g_pclkin_vip",
2454 "g_hclk_isp", "reserved";
2459 clk_gates17: gate-clk@0244 {
2460 compatible = "rockchip,rk3188-gate-clk";
2463 <&clk_isp>, <&dummy>,
2464 <&pclkin_isp>, <&pclk_vio>,
2466 <&pclk_vio>, <&dummy>,
2467 <&pclk_vio>, <&hclk_vio>,
2469 <&clk_gates17 7>, <&pclk_vio>,
2470 <&clk_gates16 10>, <&pclk_vio>,
2472 <&clk_gates16 8>, <&dummy>,
2475 clock-output-names =
2476 "g_aclk_isp", "reserved",
2477 "g_pclkin_isp", "g_p_mipi_dsi0",
2479 "g_p_mipi_csi", "reserved",
2480 "g_p_hdmi_ctrl", "g_hclk_vio_h2p",
2482 "g_pclk_vio_h2p", "g_p_edp_ctrl",
2483 "g_aclk_hdcp", "g_pclk_hdcp",
2485 "g_h_hdcpmmu", "reserved",
2486 "reserved", "reserved";
2491 clk_gates18: gate-clk@0248 {
2492 compatible = "rockchip,rk3188-gate-clk";
2507 clock-output-names =
2508 "reserved", "reserved",/* bit0-1: aclk_gpu_cfg aclk_gpu_mem */
2509 "reserved", "reserved",/* bit2: clk_gpu_core */
2511 "reserved", "reserved",
2512 "reserved", "reserved",
2514 "reserved", "reserved",
2515 "reserved", "reserved",
2517 "reserved", "reserved",
2518 "reserved", "reserved";
2523 clk_gates19: gate-clk@024c {
2524 compatible = "rockchip,rk3188-gate-clk";
2527 <&hclk_peri>, <&pclk_peri>,
2528 <&aclk_peri>, <&aclk_peri>,
2530 <&pclk_peri>, <&pclk_peri>,
2531 <&pclk_peri>, <&pclk_peri>,
2533 <&pclk_peri>, <&pclk_peri>,
2534 <&pclk_peri>, <&pclk_peri>,
2536 <&pclk_peri>, <&pclk_peri>,
2537 <&pclk_peri>, <&pclk_peri>;
2539 clock-output-names =
2540 "g_hp_axi_matrix", "g_pp_axi_matrix",
2541 "g_ap_axi_matrix", "g_a_dmac_peri",
2543 "g_pclk_spi0", "g_pclk_spi1",
2544 "g_pclk_spi2", "g_pclk_uart0",
2546 "g_pclk_uart1", "g_pclk_uart3",
2547 "g_pclk_uart4", "g_pclk_i2c2",
2549 "g_pclk_i2c3", "g_pclk_i2c4",
2550 "g_pclk_i2c5", "g_pclk_saradc";
2555 clk_gates20: gate-clk@0250 {
2556 compatible = "rockchip,rk3188-gate-clk";
2559 <&pclk_peri>, <&hclk_peri>,
2560 <&hclk_peri>, <&hclk_peri>,
2562 <&dummy>, <&hclk_peri>,
2563 <&hclk_peri>, <&hclk_peri>,
2565 <&aclk_peri>, <&hclk_peri>,
2566 <&hclk_peri>, <&hclk_peri>,
2568 <&dummy>, <&aclk_peri>,
2569 <&pclk_peri>, <&aclk_peri>;
2571 clock-output-names =
2572 "g_pclk_tsadc", "g_hclk_otg0",
2573 "g_h_pmu_otg0", "g_hclk_host0",
2575 "reserved", "g_hclk_hsic",
2576 "g_h_usb_peri", "g_h_p_ahb_arbi",
2578 "g_a_peri_niu", "g_h_emem_peri",
2579 "g_h_mmc_peri", "g_hclk_nand0",
2581 "reserved", "g_aclk_gmac",
2582 "g_pclk_gmac", "g_hclk_sfc";
2587 clk_gates21: gate-clk@0254 {
2588 compatible = "rockchip,rk3188-gate-clk";
2591 <&hclk_peri>, <&hclk_peri>,
2592 <&hclk_peri>, <&hclk_peri>,
2594 <&aclk_peri>, <&dummy>,
2603 clock-output-names =
2604 "g_hclk_sdmmc", "g_hclk_sdio0",
2605 "g_hclk_emmc", "g_hclk_hsadc",
2607 "g_aclk_peri_mmu", "reserved",
2608 "reserved", "reserved",
2610 "reserved", "reserved",
2611 "reserved", "reserved",
2613 "reserved", "reserved",
2614 "reserved", "reserved";
2619 clk_gates22: gate-clk@0258 {
2620 compatible = "rockchip,rk3188-gate-clk";
2623 <&dummy>, <&pclk_alive_pre>,
2624 <&pclk_alive_pre>, <&pclk_alive_pre>,
2629 <&pclk_alive_pre>, <&pclk_alive_pre>,
2630 <&pclk_vio>, <&pclk_vio>,
2632 <&pclk_alive_pre>, <&pclk_alive_pre>,
2635 clock-output-names =
2636 "reserved", "g_pclk_gpio1",
2637 "g_pclk_gpio2", "g_pclk_gpio3",
2639 "reserved", "reserved",
2640 "reserved", "reserved",
2642 "g_pclk_grf", "g_p_alive_niu",
2643 "g_pclk_dphytx0", "g_pclk_dphyrx",
2645 "g_pclk_timer0", "g_pclk_timer1",
2646 "reserved", "reserved";
2651 clk_gates23: gate-clk@025c {
2652 compatible = "rockchip,rk3188-gate-clk";
2655 <&pclk_pmu_pre>, <&pclk_pmu_pre>,
2656 <&pclk_pmu_pre>, <&pclk_pmu_pre>,
2658 <&pclk_pmu_pre>, <&pclk_pmu_pre>,
2667 clock-output-names =
2668 "g_pclk_pmu", "g_pclk_intmem1",
2669 "g_pclk_pmu_noc", "g_pclk_sgrf",
2671 "g_pclk_gpio0", "g_pclk_pmugrf",
2672 "reserved", "reserved",
2674 "reserved", "reserved",
2675 "reserved", "reserved",
2677 "reserved", "reserved",
2678 "reserved", "reserved";
2683 clk_gates24: gate-clk@0260 {
2684 compatible = "rockchip,rk3188-gate-clk";
2687 <&xin24m>, <&xin24m>,
2688 <&xin24m>, <&xin24m>,
2690 <&xin24m>, <&xin24m>,
2691 <&xin24m>, <&xin24m>,
2693 <&xin24m>, <&xin24m>,
2694 <&xin24m>, <&xin24m>,
2699 clock-output-names =
2700 "g_clk_timer0", "g_clk_timer1",
2701 "g_clk_timer2", "g_clk_timer3",
2703 "g_clk_timer4", "g_clk_timer5",
2704 "g_clk_timer10", "g_clk_timer11",
2706 "g_clk_timer12", "g_clk_timer13",
2707 "g_clk_timer14", "g_clk_timer15",
2709 "reserved", "reserved",
2710 "reserved", "reserved";
2718 compatible = "rockchip,rk-clock-special-regs";
2719 #address-cells = <2>;
2723 clk_32k_mux: clk_32k_mux {
2724 compatible = "rockchip,rk3188-mux-con";
2725 reg = <0x0 0xff738100 0x0 0x4>;
2726 rockchip,bits = <6 1>;
2727 clocks = <&xin32k>, <&pvtm_clkout>;
2728 clock-output-names = "clk_32k_mux";
2730 #clock-init-cells = <1>;