arch/arm64/boot/dts/rk3368-box-r88.dts

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/arm-gic.h>
   4 #include <dt-bindings/rkfb/rk_fb.h>
   5 #include <dt-bindings/input/input.h>
   6 #include "rk3368.dtsi"
   7 #include "../../../arm/boot/dts/vtl_ts_sdk8846.dtsi"
   8 //#include "../../../arm/boot/dts/lcd-b101ew05.dtsi"
   9 #include "../../../arm/boot/dts/lcd-box.dtsi"
  10
  11
  12 / {
  13         chosen {
  14                 bootargs = "earlyprintk=uart8250-32bit,0xff690000";
  15         };
  16
  17         wireless-wlan {
  18                 compatible = "wlan-platdata";
  19                 rockchip,grf = <&grf>;
  20
  21                 /* wifi_chip_type - wifi chip define
  22                  * ap6210, ap6330, ap6335
  23                  * rtl8188eu, rtl8723bs, rtl8723bu
  24                  * esp8089
  25                 */
  26                 wifi_chip_type = "ap6335";
  27
  28                 sdio_vref = <1800>; //1800mv or 3300mv
  29
  30                 //keep_wifi_power_on;
  31
  32                 //power_ctrl_by_pmu;
  33                 power_pmu_regulator = "act_ldo3";
  34                 power_pmu_enable_level = <1>; //1->HIGH, 0->LOW
  35
  36                 //vref_ctrl_enable;
  37                 //vref_ctrl_gpio = <&gpio0 GPIO_A2 GPIO_ACTIVE_HIGH>;
  38                 vref_pmu_regulator = "act_ldo3";
  39                 vref_pmu_enable_level = <1>; //1->HIGH, 0->LOW
  40
  41                 WIFI,poweren_gpio = <&gpio3 GPIO_A4 GPIO_ACTIVE_HIGH>;
  42                 WIFI,host_wake_irq = <&gpio3 GPIO_A6 GPIO_ACTIVE_HIGH>;
  43                 //WIFI,reset_gpio = <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
  44
  45                 status = "okay";
  46         };
  47
  48         wireless-bluetooth {
  49                 compatible = "bluetooth-platdata";
  50
  51                 //wifi-bt-power-toggle;
  52
  53                 uart_rts_gpios = <&gpio2 GPIO_D3 GPIO_ACTIVE_LOW>;
  54                 pinctrl-names = "default","rts_gpio";
  55                 pinctrl-0 = <&uart0_rts>;
  56                 pinctrl-1 = <&uart0_rts_gpio>;
  57
  58                 BT,power_gpio = <&gpio3 GPIO_A3 GPIO_ACTIVE_HIGH>;
  59                 BT,reset_gpio = <&gpio3 GPIO_A5 GPIO_ACTIVE_HIGH>;
  60                 BT,wake_gpio = <&gpio3 GPIO_A2 GPIO_ACTIVE_HIGH>;
  61                 BT,wake_host_irq = <&gpio3 GPIO_A7 GPIO_ACTIVE_HIGH>;
  62                 status = "okay";
  63         };
  64
  65         hallsensor {
  66                compatible = "hall_och165t";
  67                type = <SENSOR_TYPE_HALL>;
  68                irq-gpio = <&gpio0 GPIO_C0 IRQ_TYPE_EDGE_BOTH>;
  69         };
  70
  71         backlight {
  72                 compatible = "pwm-backlight";
  73                 pwms = <&pwm0 0 25000>;
  74                 brightness-levels = <255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240
  75                      239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220
  76                      219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200
  77                      199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180
  78                      179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160
  79                      159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140
  80                      139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120
  81                      119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
  82                      99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70
  83                      69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40
  84                      39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
  85                      9 8 7 6 5 4 3 2 1 0>;
  86                 default-brightness-level = <200>;
  87                 enable-gpios = <&gpio0 GPIO_C4 GPIO_ACTIVE_HIGH>;
  88                 status = "disabled";
  89         };
  90
  91         pwm_regulator {
  92                 compatible = "rockchip_pwm_regulator";
  93                 pwms = <&pwm1 0 2000>;
  94                 rockchip,pwm_id= <1>;
  95                 rockchip,pwm_voltage_map= <900000 925000 950000 975000 1000000 1025000 1050000 1075000 1100000 1125000 1150000 1175000 1200000 1225000 1250000 1275000 1300000 1325000 1350000 1375000>;
  96                 rockchip,pwm_voltage= <1000000>;
  97                 rockchip,pwm_min_voltage= <900000>;
  98                 rockchip,pwm_max_voltage= <1375000>;
  99                 rockchip,pwm_suspend_voltage= <950000>;
 100                 rockchip,pwm_coefficient= <555>;
 101                 regulators {
 102                         #address-cells = <1>;
 103                         #size-cells = <0>;
 104                         pwm_reg0: regulator@0 {
 105                                 regulator-compatible = "pwm_dcdc1";
 106                                 regulator-name= "vdd_logic";
 107                                 regulator-min-microvolt = <900000>;
 108                                 regulator-max-microvolt = <1375000>;
 109                                 regulator-always-on;
 110                                 regulator-boot-on;
 111                         };
 112                 };
 113                 test-power{
 114                         status = "okay";
 115                 };
 116         };
 117
 118         codec_hdmi_i2s: codec-hdmi-i2s {
 119                 compatible = "hdmi-i2s";
 120         };
 121
 122         codec_hdmi_spdif: codec-hdmi-spdif {
 123                 compatible = "hdmi-spdif";
 124         };
 125
 126         rockchip-hdmi-i2s {
 127                 status = "disabled";
 128                 compatible = "rockchip-hdmi-i2s";
 129                 dais {
 130                         dai0 {
 131                                 audio-codec = <&codec_hdmi_i2s>;
 132                                 audio-controller = <&i2s0>;
 133                                 format = "i2s";
 134                                 //continuous-clock;
 135                                 //bitclock-inversion;
 136                                 //frame-inversion;
 137                                 //bitclock-master;
 138                                 //frame-master;
 139                         };
 140                 };
 141         };
 142
 143
 144
 145         rockchip-spdif-card {
 146                         compatible = "rockchip-spdif-card";
 147                         dais {
 148                                 dai0 {
 149                                         audio-codec = <&codec_hdmi_spdif>;
 150                                         audio-controller = <&spdif>;
 151                                 };
 152                         };
 153                 };
 154         rockchip-rk1000 {
 155                 compatible = "rockchip-rk1000";
 156                 dais {
 157                         dai0 {
 158                                 audio-codec = <&rk1000_codec>;
 159                                 audio-controller = <&i2s0>;
 160                                 format = "i2s";
 161                         };
 162                 };
 163         };
 164         rockchip-rt5631 {
 165                 compatible = "rockchip-rt5631";
 166                 dais {
 167                         dai0 {
 168                                 audio-codec = <&rt5631>;
 169                                 audio-controller = <&i2s0>;
 170                                 format = "i2s";
 171                                 //continuous-clock;
 172                                 //bitclock-inversion;
 173                                 //frame-inversion;
 174                                 //bitclock-master;
 175                                 //frame-master;
 176                         };
 177                 };
 178         };
 179
 180         rockchip-rt3224 {
 181                 compatible = "rockchip-rt3261";
 182                 dais {
 183                         dai0 {
 184                                 audio-codec = <&rt3261>;
 185                                 audio-controller = <&i2s0>;
 186                                 format = "i2s";
 187                                 //continuous-clock;
 188                                 //bitclock-inversion;
 189                                 //frame-inversion;
 190                                 //bitclock-master;
 191                                 //frame-master;
 192                         };
 193                         dai1 {
 194                                 audio-codec = <&rt3261>;
 195                                 audio-controller = <&i2s0>;
 196                                 format = "dsp_a";
 197                                 //continuous-clock;
 198                                 bitclock-inversion;
 199                                 //frame-inversion;
 200                                 //bitclock-master;
 201                                 //frame-master;
 202                         };
 203                 };
 204         };
 205         power-led {
 206                 compatible = "gpio-leds";
 207                 green {
 208                         gpios = <&gpio3 GPIO_D5 GPIO_ACTIVE_LOW>;
 209                         default-state = "on";
 210                 };
 211         };
 212         io-domains {
 213                 compatible = "rockchip,rk3368-io-voltage-domain";
 214                 rockchip,grf = <&grf>;
 215                 rockchip,pmugrf = <&pmugrf>;
 216
 217                 /*GRF_IO_VSEL*/
 218                 dvp-supply = <&ldo7_reg>;      /*DVPIO_VDD*/
 219                 flash0-supply = <&dcdc2_reg>;  /*FLASH0_VDD*/
 220                 wifi-supply = <&ldo7_reg>;     /*APIO2_VDD*/
 221                 audio-supply = <&dcdc2_reg>;   /*APIO3_VDD*/
 222                 sdcard-supply = <&ldo1_reg>;   /*SDMMC0_VDD*/
 223                 gpio30-supply = <&dcdc2_reg>;  /*APIO1_VDD*/
 224                 gpio1830-supply = <&dcdc2_reg>;/*ADIO4_VDD*/
 225
 226                 /*PMU_GRF_IO_VSEL*/
 227                 pmu-supply = <&ldo5_reg>;      /*PMUIO_VDD*/
 228                 vop-supply = <&ldo5_reg>;      /*LCDC_VDD*/
 229         };
 230 };
 231
 232 &gmac_clkin {
 233         clock-frequency = <50000000>;
 234 };
 235
 236 &gmac {
 237         //power_ctl_by = "gpio";        //"gpio" "pmu"
 238         //power-gpio = <&gpio0 GPIO_A6 GPIO_ACTIVE_HIGH>;
 239         //power-pmu = "act_ldo"
 240         reset-gpio = <&gpio3 GPIO_B4 GPIO_ACTIVE_LOW>;
 241         phy-mode = "rmii";
 242         pinctrl-names = "default";
 243         pinctrl-0 = <&rmii_pins>;
 244         clock_in_out = "output";
 245         tx_delay = <0x28>;
 246         rx_delay = <0x10>;
 247         status = "okay"; //if want to use gmac, please set "okay"
 248 };
 249
 250 &pinctrl {
 251         //used for init some gpio
 252         init-gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_HIGH
 253         &gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 254
 255         gpio0_gpio {
 256                 gpio0_c7: gpio0-c7 {
 257                 rockchip,pins = <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_down>;
 258         };
 259         gpio0_a3: gpio0-a3 {
 260                 rockchip,pins = <0 GPIO_A3 RK_FUNC_3 &pcfg_pull_none>;
 261         };
 262         gpio0_c2: gpio0-c2 {
 263                 rockchip,pins = <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_down>;
 264         };
 265
 266         //to add
 267         };
 268
 269 };
 270
 271 &nandc0 {
 272         status = "disabled"; // used nand set "disabled" ,used emmc set "okay"
 273 };
 274
 275 &nandc0reg {
 276         status = "okay"; // used nand set "disabled" ,used emmc set "okay"
 277 };
 278
 279 &emmc {
 280         clock-frequency = <150000000>;
 281         clock-freq-min-max = <400000 150000000>;
 282
 283         supports-highspeed;
 284         supports-emmc;
 285         bootpart-no-access;
 286
 287         //supports-sd;
 288         supports-DDR_MODE; //you should set the two value in your project. only close in RK3288-SDK board.
 289         caps2-mmc-hs200;
 290
 291         ignore-pm-notify;
 292         keep-power-in-suspend;
 293
 294         //poll-hw-reset
 295         status = "okay";
 296 };
 297
 298 &sdmmc {
 299         clock-frequency = <50000000>;
 300         clock-freq-min-max = <400000 50000000>;
 301         supports-highspeed;
 302         supports-sd;
 303         broken-cd;
 304         card-detect-delay = <200>;
 305
 306         ignore-pm-notify;
 307         keep-power-in-suspend;
 308
 309         vmmc-supply = <&ldo1_reg>;
 310         status = "okay";
 311 };
 312
 313 &edp{
 314         status = "disabled";
 315 };
 316
 317 &sdio {
 318         clock-frequency = <50000000>;
 319         clock-freq-min-max = <200000 50000000>;
 320         supports-highspeed;
 321         supports-sdio;
 322         ignore-pm-notify;
 323         keep-power-in-suspend;
 324         //cap-sdio-irq;
 325         status = "okay";
 326 };
 327
 328 &spi0 {
 329         status = "disabled";
 330         max-freq = <48000000>;
 331         /*
 332         spi_test@00 {
 333                 compatible = "rockchip,spi_test_bus0_cs0";
 334                 reg = <0>;
 335                 spi-max-frequency = <24000000>;
 336                 //spi-cpha;
 337                 //spi-cpol;
 338                 poll_mode = <0>;
 339                 type = <0>;
 340                 enable_dma = <0>;
 341
 342         };
 343
 344         spi_test@01 {
 345                 compatible = "rockchip,spi_test_bus0_cs1";
 346                 reg = <1>;
 347                 spi-max-frequency = <24000000>;
 348                 spi-cpha;
 349                 spi-cpol;
 350                 poll_mode = <0>;
 351                 type = <0>;
 352                 enable_dma = <0>;
 353         };
 354         */
 355 };
 356
 357 &spi1 {
 358         status = "disabled";
 359         max-freq = <48000000>;
 360         /*
 361         spi_test@10 {
 362                 compatible = "rockchip,spi_test_bus1_cs0";
 363                 reg = <0>;
 364                 spi-max-frequency = <24000000>;
 365                 //spi-cpha;
 366                 //spi-cpol;
 367                 poll_mode = <0>;
 368                 type = <0>;
 369                 enable_dma = <0>;
 370         };
 371         */
 372 };
 373
 374 &spi2 {
 375         status = "disabled";
 376         max-freq = <48000000>;
 377         /*
 378         spi_test@20 {
 379                 compatible = "rockchip,spi_test_bus2_cs0";
 380                 reg = <0>;
 381                 spi-max-frequency = <24000000>;
 382                 //spi-cpha;
 383                 //spi-cpol;
 384                 poll_mode = <0>;
 385                 type = <0>;
 386                 enable_dma = <0>;
 387         };
 388
 389         spi_test@21 {
 390                 compatible = "rockchip,spi_test_bus2_cs1";
 391                 reg = <1>;
 392                 spi-max-frequency = <24000000>;
 393                 //spi-cpha;
 394                 //spi-cpol;
 395                 poll_mode = <0>;
 396                 type = <0>;
 397                 enable_dma = <0>;
 398         };
 399         */
 400 };
 401
 402 &uart_dbg {
 403         status = "okay";
 404 };
 405
 406 &uart_bt {
 407         status = "okay";
 408         dma-names = "!tx", "!rx";
 409         pinctrl-0 = <&uart0_xfer &uart0_cts>;
 410 };
 411
 412 &tsadc {
 413        tsadc-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
 414        //tsadc-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
 415        status = "okay";
 416 };
 417
 418 &i2c0 {
 419         status = "okay";
 420         syr827: syr827@40 {
 421                 compatible = "silergy,syr82x";
 422                 reg = <0x40>;
 423                 status = "okay";
 424                 regulators {
 425                         #address-cells = <1>;
 426                         #size-cells = <0>;
 427                         syr827_dc1: regulator@0 {
 428                         reg = <0>;
 429                         regulator-compatible = "syr82x_dcdc1";
 430                         regulator-name = "vdd_arm";
 431                         regulator-min-microvolt = <712500>;
 432                         regulator-max-microvolt = <1500000>;
 433                         regulator-always-on;
 434                         regulator-boot-on;
 435                         regulator-initial-mode = <0x1>;
 436                         regulator-initial-state = <3>;
 437                         regulator-state-mem {
 438                                 regulator-state-mode = <0x2>;
 439                                 regulator-state-disabled;
 440                                 regulator-state-uv = <900000>;
 441                         };
 442                 };
 443            };
 444         };
 445         syr828: syr828@41 {
 446                 compatible = "silergy,syr82x";
 447                 reg = <0x41>;
 448                 status = "disabled";
 449                 regulators {
 450                         #address-cells = <1>;
 451                         #size-cells = <0>;
 452                         syr828_dc1: regulator@0 {
 453                         reg = <0>;
 454                         regulator-compatible = "syr82x_dcdc1";
 455                         regulator-name = "vdd_gpu";
 456                         regulator-min-microvolt = <712500>;
 457                         regulator-max-microvolt = <1500000>;
 458                         regulator-always-on;
 459                         regulator-boot-on;
 460                         regulator-initial-mode = <0x1>;
 461                         regulator-initial-state = <3>;
 462                         regulator-state-mem {
 463                                 regulator-state-mode = <0x2>;
 464                                 regulator-state-enabled;
 465                                 regulator-state-uv = <900000>;
 466                         };
 467                 };
 468            };
 469         };
 470
 471         xz3216: xz3216@60 {
 472                 compatible = "xz3216";
 473                 reg = <0x60>;
 474                 status = "okay";
 475                 regulators {
 476                         #address-cells = <1>;
 477                         #size-cells = <0>;
 478                         xz3216_dc1: regulator@0 {
 479                         reg = <0>;
 480                         regulator-compatible = "xz_dcdc1";
 481                         regulator-name = "vdd_arm";
 482                         regulator-min-microvolt = <902500>;
 483                         regulator-max-microvolt = <1400000>;
 484                         regulator-always-on;
 485                         regulator-boot-on;
 486                         regulator-initial-mode = <0x1>;
 487                         regulator-initial-state = <3>;
 488                         regulator-state-mem {
 489                                 regulator-state-mode = <0x2>;
 490                                 regulator-state-enabled;
 491                                 regulator-state-uv = <1000000>;
 492                         };
 493                 };
 494            };
 495         };
 496
 497         act8846: act8846@5a {
 498                 reg = <0x5a>;
 499                 status = "diasbled";
 500         };
 501
 502         CW2015@62 {
 503                 compatible = "cw201x";
 504                 reg = <0x62>;
 505                 dc_det_gpio = <&gpio0 GPIO_C1 GPIO_ACTIVE_LOW>;
 506                 bat_low_gpio = <&gpio0 GPIO_C2 GPIO_ACTIVE_LOW>;
 507                 chg_ok_gpio = <&gpio0 GPIO_D3 GPIO_ACTIVE_HIGH>;
 508                 bat_config_info = <0x15 0x42 0x60 0x59 0x52 0x58 0x4D 0x48 0x48 0x44 0x44 0x46 0x49 0x48 0x32
 509                         0x24 0x20 0x17 0x13 0x0F 0x19 0x3E 0x51 0x45 0x08 0x76 0x0B 0x85 0x0E 0x1C 0x2E 0x3E 0x4D 0x52 0x52
 510                         0x57 0x3D 0x1B 0x6A 0x2D 0x25 0x43 0x52 0x87 0x8F 0x91 0x94 0x52 0x82 0x8C 0x92 0x96 0xFF 0x7B 0xBB
 511                         0xCB 0x2F 0x7D 0x72 0xA5 0xB5 0xC1 0x46 0xAE>;
 512                 is_dc_charge = <1>;
 513                 is_usb_charge = <0>;
 514                 status = "diasbled";
 515         };
 516         rtc@51 {
 517                 compatible = "rtc,hym8563";
 518                 reg = <0x51>;
 519                 /*box not used rtc irq,and this pin used as rk1000 spk ctrl*/
 520                 #irq_gpio = <&gpio0 GPIO_A1 IRQ_TYPE_EDGE_FALLING>;
 521         };
 522
 523 };
 524
 525 &i2c1 {
 526         status = "okay";
 527         rk1000_control@40 {
 528                 compatible = "rockchip,rk1000_control";
 529                 reg = <0x40>;
 530                 gpio-reset = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>;
 531                 #clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 532                 #clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 533                 #pinctrl-names = "default";
 534                 #pinctrl-0 = <&i2s_mclk>;
 535                 status = "okay";
 536         };
 537         rk1000_tve@42 {
 538                 compatible = "rockchip,rk1000_tve";
 539                 reg = <0x42>;
 540                 rockchip,source = <0>; //0: LCDC0; 1: LCDC1
 541                 rockchip,prop = <PRMRY>;//<EXTEND>
 542                 status = "okay";
 543         };
 544         rk1000_codec: rk1000_codec@60 {
 545                 compatible = "rockchip,rk1000_codec";
 546                 reg = <0x60>;
 547                 spk_ctl_io = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>;
 548                 boot_depop = <1>;
 549                 pa_enable_time = <5000>;
 550                 status = "okay";
 551         };
 552         mpu6050:mpu@68{
 553                 compatible = "mpu6050";
 554                 reg = <0x68>;
 555                 mpu-int_config = <0x10>;
 556                 mpu-level_shifter = <0>;
 557                 mpu-orientation = <0 1 0 1 0 0 0 0 1>;
 558                 orientation-x= <0>;
 559                 orientation-y= <1>;
 560                 orientation-z= <1>;
 561                 irq-gpio = <&gpio3 GPIO_B6 IRQ_TYPE_LEVEL_LOW>;
 562                 mpu-debug = <0>;
 563                 status = "disabled";
 564         };
 565         ak8963:compass@0d{
 566                 compatible = "mpu_ak8963";
 567                 reg = <0x0d>;
 568                 compass-bus = <0>;
 569                 compass-adapt_num = <0>;
 570                 compass-orientation = <1 0 0 0 1 0 0 0 1>;
 571                 orientation-x= <0>;
 572                 orientation-y= <0>;
 573                 orientation-z= <1>;
 574                 compass-debug = <1>;
 575                 status = "disabled";
 576         };
 577         rt3261: rt3261@1c {
 578                 compatible = "rt3261";
 579                 reg = <0x1c>;
 580                 spk-num= <2>;
 581                 modem-input-mode = <1>;
 582                 lout-to-modem_mode = <1>;
 583                 spk-amplify = <2>;
 584                 status = "disabled";
 585         };
 586 };
 587
 588 &i2c2 {
 589         status = "disabled";
 590         rt5631: rt5631@1a {
 591                 compatible = "rt5631";
 592                 reg = <0x1a>;
 593         };
 594         ts@01 {
 595                 compatible = "ct,vtl_ts";
 596                 reg = <0x01>;
 597                 screen_max_x = <1536>;
 598                 screen_max_y = <2048>;
 599                 xy_swap = <1>;
 600                 x_reverse = <0>;
 601                 y_reverse = <0>;
 602                 x_mul = <2>;
 603                 y_mul = <2>;
 604                 bin_ver = <0>;
 605                 irq_gpio_number = <&gpio0 GPIO_B4 IRQ_TYPE_LEVEL_LOW>;
 606                 rst_gpio_number = <&gpio0 GPIO_B3 GPIO_ACTIVE_HIGH>;
 607         };
 608 };
 609
 610 &i2c3 {
 611         status = "disabled";
 612 };
 613
 614 &i2c4 {
 615         status = "disabled";
 616 };
 617
 618 &i2c5 {
 619         status = "disabled";
 620 };
 621
 622 &CPU_SLEEP_0 {
 623         arm,psci-suspend-param = <0x1010000>;
 624 };
 625
 626 &fb {
 627         rockchip,disp-mode = <NO_DUAL>;
 628         rockchip,uboot-logo-on = <1>;
 629         rockchip,disp-policy = <DISPLAY_POLICY_BOX_TEMP>;
 630 };
 631
 632 &disp_timings {
 633         native-mode = <&timing1>;
 634 };
 635
 636 &rk_screen {
 637         display-timings = <&disp_timings>;
 638 };
 639
 640
 641 &lvds {
 642         status = "okay";
 643         //pinctrl-names = "lcdc", "sleep";
 644         //pinctrl-0 = <&lcdc_lcdc>;
 645         //pinctrl-1 = <&lcdc_gpio>;
 646 };
 647
 648 &lcdc {
 649         status = "okay";
 650         rockchip,mirror = <NO_MIRROR>;
 651         rockchip,cabc_mode = <0>;
 652         rockchip,fb-win-map = <FB_DEFAULT_ORDER>;
 653         pinctrl-names = "default", "gpio";
 654         pinctrl-0 = <&lcdc_lcdc>;
 655         pinctrl-1 = <&lcdc_gpio>;
 656
 657         power_ctr: power_ctr {
 658                 rockchip,debug = <0>;
 659                 /*lcd_en:lcd_en {
 660                         rockchip,power_type = <GPIO>;
 661                         gpios = <&gpio0 GPIO_C6 GPIO_ACTIVE_HIGH>;
 662                         rockchip,delay = <10>;
 663                 };
 664
 665                 lcd_cs:lcd_cs {
 666                         rockchip,power_type = <GPIO>;
 667                         gpios = <&gpio0 GPIO_C5 GPIO_ACTIVE_HIGH>;
 668                         rockchip,delay = <10>;
 669                 };
 670
 671                 lcd_rst:lcd_rst {
 672                         rockchip,power_type = <GPIO>;
 673                         gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
 674                         rockchip,delay = <5>;
 675                 };*/
 676         };
 677 };
 678
 679
 680
 681
 682 &hdmi {
 683         status = "okay";
 684 };
 685
 686 &adc {
 687         status = "disabled";
 688
 689         rockchip_headset {
 690                 compatible = "rockchip_headset";
 691                 headset_gpio = <&gpio0 GPIO_C7 GPIO_ACTIVE_LOW>;
 692                 pinctrl-names = "default";
 693                 pinctrl-0 = <&gpio0_c7>;//gpio0_c7
 694                 io-channels = <&adc 2>;
 695                 /*
 696                 hook_gpio = ;
 697                 hook_down_type = ; //interrupt hook key down status
 698                 */
 699        };
 700
 701         key {
 702                 compatible = "rockchip,key";
 703                 io-channels = <&adc 1>;
 704
 705                 vol-up-key {
 706                         linux,code = <115>;
 707                         label = "volume up";
 708                         rockchip,adc_value = <1>;
 709                 };
 710
 711                 vol-down-key {
 712                         linux,code = <114>;
 713                         label = "volume down";
 714                         rockchip,adc_value = <170>;
 715                 };
 716
 717                 power-key {
 718                         gpios = <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
 719                         linux,code = <116>;
 720                         label = "power";
 721                         gpio-key,wakeup;
 722                 };
 723
 724                 menu-key {
 725                         linux,code = <59>;
 726                         label = "menu";
 727                         rockchip,adc_value = <355>;
 728                 };
 729
 730                 home-key {
 731                         linux,code = <102>;
 732                         label = "home";
 733                         rockchip,adc_value = <746>;
 734                 };
 735
 736                 back-key {
 737                         linux,code = <158>;
 738                         label = "back";
 739                         rockchip,adc_value = <560>;
 740                 };
 741
 742                 camera-key {
 743                         linux,code = <212>;
 744                         label = "camera";
 745                         rockchip,adc_value = <450>;
 746                 };
 747         };
 748 };
 749
 750 &pwm0 {
 751         status = "disabled";
 752 };
 753
 754 &pwm1 {
 755         status = "okay";
 756 };
 757
 758 &clk_core_b_dvfs_table {
 759         operating-points = <
 760                 /* KHz    uV */
 761                 //216000 950000
 762                 312000 950000
 763                 408000 950000
 764                 600000 975000
 765                 696000 975000
 766                 816000 1000000
 767                 1008000 1100000
 768                 1200000 1175000
 769                 1416000 1300000
 770                 1488000 1325000
 771                 1512000 1350000
 772                 >;
 773         status = "okay";
 774 };
 775
 776 &clk_core_l_dvfs_table {
 777         operating-points = <
 778                 /* KHz    uV */
 779                 //216000 950000
 780                 312000 950000
 781                 408000 950000
 782                 600000 950000
 783                 696000 975000
 784                 816000 1050000
 785                 1008000 1100000
 786                 1200000 1250000
 787                 //1300000 1300000
 788                 >;
 789         status = "okay";
 790 };
 791
 792 &clk_gpu_dvfs_table {
 793         operating-points = <
 794                 /* KHz    uV */
 795                 //200000 1200000
 796                 300000 1200000
 797                 400000 1200000
 798                 600000 1200000
 799                 >;
 800 };
 801
 802 &clk_ddr_dvfs_table {
 803         operating-points = <
 804                 /* KHz    uV */
 805                 200000 1050000
 806                 300000 1050000
 807                 400000 1100000
 808                 533000 1150000
 809                 800000 1200000
 810                 >;
 811
 812         freq-table = <
 813                 /*status                freq(KHz)*/
 814                 SYS_STATUS_NORMAL       800000
 815                 /*SYS_STATUS_SUSPEND    200000
 816                 SYS_STATUS_VIDEO_1080P  240000
 817                 SYS_STATUS_VIDEO_4K     400000
 818                 SYS_STATUS_PERFORMANCE  528000
 819                 SYS_STATUS_DUALVIEW     400000
 820                 SYS_STATUS_BOOST        324000
 821                 SYS_STATUS_ISP          400000*/
 822                 >;
 823         auto-freq-table = <
 824                 240000
 825                 324000
 826                 396000
 827                 528000
 828                 >;
 829         auto-freq=<0>;
 830         status="okay";
 831 };
 832
 833 &dwc_control_usb {
 834                 host_drv_gpio = <&gpio0 GPIO_A4 GPIO_ACTIVE_LOW>;
 835                 otg_drv_gpio = <&gpio0 GPIO_A5 GPIO_ACTIVE_LOW>;
 836
 837                 rockchip,remote_wakeup;
 838                 rockchip,usb_irq_wakeup;
 839         };
 840
 841 &usb0 {
 842         /*0 - Normal, 1 - Force Host, 2 - Force Device*/
 843         rockchip,usb-mode = <0>;
 844 };
 845
 846 /include/ "../../../arm/boot/dts/act8846.dtsi"
 847 &act8846 {
 848         gpios =<&gpio0 GPIO_B0 GPIO_ACTIVE_LOW>,<&gpio0 GPIO_A3 GPIO_ACTIVE_HIGH>;
 849         act8846,system-power-controller;
 850
 851         regulators {
 852
 853                 dcdc1_reg: regulator@0{
 854                         regulator-name= "act_dcdc1";
 855                         regulator-min-microvolt = <1200000>;
 856                         regulator-max-microvolt = <1200000>;
 857                         regulator-always-on;
 858                         regulator-boot-on;
 859                 };
 860
 861                 dcdc2_reg: regulator@1 {
 862                         regulator-name= "vccio";
 863                         regulator-min-microvolt = <3300000>;
 864                         regulator-max-microvolt = <3300000>;
 865                         regulator-initial-state = <3>;
 866                         regulator-state-mem {
 867                                 regulator-state-enabled;
 868                                 regulator-state-uv = <3300000>;
 869                         };
 870                 };
 871
 872                 dcdc3_reg: regulator@2 {
 873                         regulator-name= "vdd_logic";
 874                         regulator-min-microvolt = <700000>;
 875                         regulator-max-microvolt = <1500000>;
 876                         regulator-initial-state = <3>;
 877                         regulator-state-mem {
 878                                 regulator-state-enabled;
 879                                 regulator-state-uv = <1000000>;
 880                         };
 881
 882                 };
 883
 884                 dcdc4_reg: regulator@3 {
 885                         regulator-name= "act_dcdc4";
 886                         regulator-min-microvolt = <2000000>;
 887                         regulator-max-microvolt = <2000000>;
 888                                 regulator-initial-state = <3>;
 889                         regulator-state-mem {
 890                                 regulator-state-enabled;
 891                                 regulator-state-uv = <2000000>;
 892                         };
 893                 };
 894
 895                 ldo1_reg: regulator@4 {
 896                         regulator-name= "vccio_sd";
 897                         regulator-min-microvolt = <1800000>;
 898                         regulator-max-microvolt = <3300000>;
 899
 900                 };
 901
 902                 ldo2_reg: regulator@5 {
 903                         regulator-name= "act_ldo2";
 904                         regulator-min-microvolt = <1000000>;
 905                         regulator-max-microvolt = <1000000>;
 906
 907                 };
 908
 909                 ldo3_reg: regulator@6 {
 910                         regulator-name= "act_ldo3";
 911                         regulator-min-microvolt = <3300000>;
 912                         regulator-max-microvolt = <3300000>;
 913
 914                 };
 915
 916                 ldo4_reg:regulator@7 {
 917                         regulator-name= "act_ldo4";
 918                         regulator-min-microvolt = <3300000>;
 919                         regulator-max-microvolt = <3300000>;
 920
 921                 };
 922
 923                 ldo5_reg: regulator@8 {
 924                         regulator-name= "act_ldo5";
 925                         regulator-min-microvolt = <3300000>;
 926                         regulator-max-microvolt = <3300000>;
 927
 928                 };
 929
 930                 ldo6_reg: regulator@9 {
 931                         regulator-name= "act_ldo6";
 932                         regulator-min-microvolt = <1000000>;
 933                         regulator-max-microvolt = <1000000>;
 934                         regulator-initial-state = <3>;
 935                         regulator-state-mem {
 936                                 regulator-state-enabled;
 937                         };
 938
 939                 };
 940
 941                 ldo7_reg: regulator@10 {
 942                         regulator-name= "vcc_18";
 943                         regulator-min-microvolt = <1800000>;
 944                         regulator-max-microvolt = <1800000>;
 945                         regulator-initial-state = <3>;
 946                         regulator-state-mem {
 947                                 regulator-state-enabled;
 948                         };
 949
 950                 };
 951
 952                 ldo8_reg: regulator@11 {
 953                         regulator-name= "act_ldo8";
 954                         regulator-min-microvolt = <1800000>;
 955                         regulator-max-microvolt = <1800000>;
 956
 957                 };
 958         };
 959 };
 960
 961 &ion_cma {
 962        reg = <0x00000000 0x00000000>; /* 0MB */
 963 };
 964
 965 /*
 966 &dwc_control_usb {
 967         usb_uart {
 968                 status = "disabled";
 969         };
 970 };
 971
 972 &rk3288_cif_sensor{
 973         status = "okay";
 974 };
 975 */
 976
 977 &remotectl {
 978         handle_cpu_id = <1>;
 979         status = "okay";
 980         ir_key1{
 981                 rockchip,usercode = <0x4040>;
 982                 rockchip,key_table =
 983                         <0xf2   KEY_REPLY>,
 984                         <0xba   KEY_BACK>,
 985                         <0xf4   KEY_UP>,
 986                         <0xf1   KEY_DOWN>,
 987                         <0xef   KEY_LEFT>,
 988                         <0xee   KEY_RIGHT>,
 989                         <0xbd   KEY_HOME>,
 990                         <0xea   KEY_VOLUMEUP>,
 991                         <0xe3   KEY_VOLUMEDOWN>,
 992                         <0xe2   KEY_SEARCH>,
 993                         <0xb2   KEY_POWER>,
 994                         <0xbc   KEY_MUTE>,
 995                         <0xec   KEY_MENU>,
 996                         <0xbf   0x190>,
 997                         <0xe0   0x191>,
 998                         <0xe1   0x192>,
 999                         <0xe9   183>,
1000                         <0xe6   248>,
1001                         <0xe8   185>,
1002                         <0xe7   186>,
1003                         <0xf0   388>,
1004                         <0xbe   0x175>;
1005         };
1006         ir_key2{
1007                 rockchip,usercode = <0xff00>;
1008                 rockchip,key_table =
1009                         <0xf9   KEY_HOME>,
1010                         <0xbf   KEY_BACK>,
1011                         <0xfb   KEY_MENU>,
1012                         <0xaa   KEY_REPLY>,
1013                         <0xb9   KEY_UP>,
1014                         <0xe9   KEY_DOWN>,
1015                         <0xb8   KEY_LEFT>,
1016                         <0xea   KEY_RIGHT>,
1017                         <0xeb   KEY_VOLUMEDOWN>,
1018                         <0xef   KEY_VOLUMEUP>,
1019                         <0xf7   KEY_MUTE>,
1020                         <0xe7   KEY_POWER>,
1021                         <0xfc   KEY_POWER>,
1022                         <0xa9   KEY_VOLUMEDOWN>,
1023                         <0xa8   KEY_VOLUMEDOWN>,
1024                         <0xe0   KEY_VOLUMEDOWN>,
1025                         <0xa5   KEY_VOLUMEDOWN>,
1026                         <0xab   183>,
1027                         <0xb7   388>,
1028                         <0xf8   184>,
1029                         <0xaf   185>,
1030                         <0xed   KEY_VOLUMEDOWN>,
1031                         <0xee   186>,
1032                         <0xb3   KEY_VOLUMEDOWN>,
1033                         <0xf1   KEY_VOLUMEDOWN>,
1034                         <0xf2   KEY_VOLUMEDOWN>,
1035                         <0xf3   KEY_SEARCH>,
1036                         <0xb4   KEY_VOLUMEDOWN>,
1037                         <0xbe   KEY_SEARCH>;
1038         };
1039         ir_key3{
1040                 rockchip,usercode = <0x1dcc>;
1041                 rockchip,key_table =
1042                         <0xee   KEY_REPLY>,
1043                         <0xf0   KEY_BACK>,
1044                         <0xf8   KEY_UP>,
1045                         <0xbb   KEY_DOWN>,
1046                         <0xef   KEY_LEFT>,
1047                         <0xed   KEY_RIGHT>,
1048                         <0xfc   KEY_HOME>,
1049                         <0xf1   KEY_VOLUMEUP>,
1050                         <0xfd   KEY_VOLUMEDOWN>,
1051                         <0xb7   KEY_SEARCH>,
1052                         <0xff   KEY_POWER>,
1053                         <0xf3   KEY_MUTE>,
1054                         <0xbf   KEY_MENU>,
1055                         <0xf9   0x191>,
1056                         <0xf5   0x192>,
1057                         <0xb3   388>,
1058                         <0xbe   KEY_1>,
1059                         <0xba   KEY_2>,
1060                         <0xb2   KEY_3>,
1061                         <0xbd   KEY_4>,
1062                         <0xf9   KEY_5>,
1063                         <0xb1   KEY_6>,
1064                         <0xfc   KEY_7>,
1065                         <0xf8   KEY_8>,
1066                         <0xb0   KEY_9>,
1067                         <0xb6   KEY_0>,
1068                         <0xb5   KEY_BACKSPACE>;
1069         };
1070 };