2 * ARM Ltd. Juno Plaform
4 * Fast Models FVP v2 support
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 compatible = "arm,juno", "arm,vexpress";
14 interrupt-parent = <&gic>;
28 compatible = "arm,cortex-a53","arm,armv8";
30 enable-method = "psci";
35 compatible = "arm,cortex-a53","arm,armv8";
37 enable-method = "psci";
42 compatible = "arm,cortex-a53","arm,armv8";
44 enable-method = "psci";
49 compatible = "arm,cortex-a53","arm,armv8";
51 enable-method = "psci";
56 compatible = "arm,cortex-a57","arm,armv8";
58 enable-method = "psci";
63 compatible = "arm,cortex-a57","arm,armv8";
65 enable-method = "psci";
70 device_type = "memory";
71 reg = <0x00000000 0x80000000 0x0 0x80000000>,
72 <0x00000008 0x80000000 0x1 0x80000000>;
76 device_type = "memory";
77 reg = <0x00000000 0x14000000 0x0 0x02000000>;
80 gic: interrupt-controller@2c001000 {
81 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
82 #interrupt-cells = <3>;
85 reg = <0x0 0x2c010000 0 0x1000>,
86 <0x0 0x2c02f000 0 0x1000>,
87 <0x0 0x2c04f000 0 0x2000>,
88 <0x0 0x2c06f000 0 0x2000>;
89 interrupts = <GIC_PPI 9 0xf04>;
93 compatible = "arm,gic-msi";
94 reg = <0x0 0x2c1c0000 0 0x10000
95 0x0 0x2c1d0000 0 0x10000
96 0x0 0x2c1e0000 0 0x10000
97 0x0 0x2c1f0000 0 0x10000>;
101 compatible = "arm,armv8-timer";
102 interrupts = <GIC_PPI 13 0xff01>,
109 compatible = "arm,armv8-pmuv3";
110 interrupts = <GIC_SPI 60 4>,
117 compatible = "arm,psci";
119 cpu_suspend = <0xC4000001>;
120 cpu_off = <0x84000002>;
121 cpu_on = <0xC4000003>;
122 migrate = <0xC4000005>;
126 compatible = "arm,pcie-xr3";
128 reg = <0 0x7ff30000 0 0x1000
129 0 0x7ff20000 0 0x10000
130 0 0x40000000 0 0x10000000>;
132 #address-cells = <3>;
134 ranges = <0x01000000 0x0 0x00000000 0x00 0x5ff00000 0x0 0x00100000
135 0x02000000 0x0 0x00000000 0x40 0x00000000 0x0 0x80000000
136 0x42000000 0x0 0x80000000 0x40 0x80000000 0x0 0x80000000>;
137 #interrupt-cells = <1>;
138 interrupt-map-mask = <0 0 0 7>;
139 interrupt-map = <0 0 0 1 &gic 0 136 4
142 0 0 0 4 &gic 0 139 4>;
145 scpi: scpi@2b1f0000 {
146 compatible = "arm,scpi-mhu";
147 reg = <0x0 0x2b1f0000 0x0 0x10000>, /* MHU registers */
148 <0x0 0x2e000000 0x0 0x10000>; /* Payload area */
149 interrupts = <0 36 4>, /* low priority interrupt */
150 <0 35 4>, /* high priority interrupt */
151 <0 37 4>; /* secure channel interrupt */
153 clock-output-names = "a57", "a53", "gpu", "hdlcd0", "hdlcd1";
156 hdlcd0_osc: scpi_osc@3 {
157 compatible = "arm,scpi-osc";
160 frequency-range = <23000000 210000000>;
161 clock-output-names = "pxlclk0";
164 hdlcd1_osc: scpi_osc@4 {
165 compatible = "arm,scpi-osc";
168 frequency-range = <23000000 210000000>;
169 clock-output-names = "pxlclk1";
172 soc_uartclk: refclk72738khz {
173 compatible = "fixed-clock";
175 clock-frequency = <7273800>;
176 clock-output-names = "juno:uartclk";
179 soc_refclk24mhz: clk24mhz {
180 compatible = "fixed-clock";
182 clock-frequency = <24000000>;
183 clock-output-names = "juno:clk24mhz";
186 mb_eth25mhz: clk25mhz {
187 compatible = "fixed-clock";
189 clock-frequency = <25000000>;
190 clock-output-names = "ethclk25mhz";
193 soc_usb48mhz: clk48mhz {
194 compatible = "fixed-clock";
196 clock-frequency = <48000000>;
197 clock-output-names = "clk48mhz";
200 soc_smc50mhz: clk50mhz {
201 compatible = "fixed-clock";
203 clock-frequency = <50000000>;
204 clock-output-names = "smc_clk";
207 soc_refclk100mhz: refclk100mhz {
208 compatible = "fixed-clock";
210 clock-frequency = <100000000>;
211 clock-output-names = "apb_pclk";
214 soc_faxiclk: refclk533mhz {
215 compatible = "fixed-clock";
217 clock-frequency = <533000000>;
218 clock-output-names = "faxi_clk";
221 soc_fixed_3v3: fixedregulator@0 {
222 compatible = "regulator-fixed";
223 regulator-name = "3V3";
224 regulator-min-microvolt = <3300000>;
225 regulator-max-microvolt = <3300000>;
229 memory-controller@7ffd0000 {
230 compatible = "arm,pl354", "arm,primecell";
231 reg = <0 0x7ffd0000 0 0x1000>;
232 interrupts = <0 86 4>,
234 clocks = <&soc_smc50mhz>;
235 clock-names = "apb_pclk";
236 chip5-memwidth = <16>;
239 dma0: dma@0x7ff00000 {
240 compatible = "arm,pl330", "arm,primecell";
241 reg = <0x0 0x7ff00000 0 0x1000>;
242 interrupts = <0 95 4>,
253 #dma-requests = <32>;
254 clocks = <&soc_faxiclk>;
255 clock-names = "apb_pclk";
258 soc_uart0: uart@7ff80000 {
259 compatible = "arm,pl011", "arm,primecell";
260 reg = <0x0 0x7ff80000 0x0 0x1000>;
261 interrupts = <0 83 4>;
262 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
263 clock-names = "uartclk", "apb_pclk";
266 dma-names = "rx", "tx";
269 /* this UART is reserved for secure software.
270 soc_uart1: uart@7ff70000 {
271 compatible = "arm,pl011", "arm,primecell";
272 reg = <0x0 0x7ff70000 0x0 0x1000>;
273 interrupts = <0 84 4>;
274 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
275 clock-names = "uartclk", "apb_pclk";
279 compatible = "phy-ulpi-generic";
280 reg = <0x0 0x94 0x0 0x4>;
285 compatible = "snps,ehci-h20ahb";
286 /* compatible = "arm,h20ahb-ehci"; */
287 reg = <0x0 0x7ffc0000 0x0 0x10000>;
288 interrupts = <0 117 4>;
289 clocks = <&soc_usb48mhz>;
295 compatible = "generic-ohci";
296 reg = <0x0 0x7ffb0000 0x0 0x10000>;
297 interrupts = <0 116 4>;
298 clocks = <&soc_usb48mhz>;
303 #address-cells = <1>;
305 compatible = "snps,designware-i2c";
306 reg = <0x0 0x7ffa0000 0x0 0x1000>;
307 interrupts = <0 104 4>;
308 clock-frequency = <400000>;
309 i2c-sda-hold-time-ns = <500>;
310 clocks = <&soc_smc50mhz>;
312 dvi0: dvi-transmitter@70 {
313 compatible = "nxp,tda998x";
317 dvi1: dvi-transmitter@71 {
318 compatible = "nxp,tda998x";
324 compatible = "arm,pl180", "arm,primecell";
325 reg = <0x0 0x1c050000 0x0 0x1000>;
326 interrupts = <0 73 4>,
328 max-frequency = <12000000>;
329 vmmc-supply = <&soc_fixed_3v3>;
330 clocks = <&soc_refclk24mhz>, <&soc_refclk100mhz>;
331 clock-names = "mclk", "apb_pclk";
335 compatible = "arm,hdlcd";
336 reg = <0 0x7ff60000 0 0x1000>;
337 interrupts = <0 85 4>;
338 clocks = <&hdlcd0_osc>;
339 clock-names = "pxlclk";
343 native-mode = <&timing0>;
345 /* 1024 x 768 framebufer, standard VGA timings * /
346 clock-frequency = <65000>;
360 compatible = "arm,hdlcd";
361 reg = <0 0x7ff50000 0 0x1000>;
362 interrupts = <0 93 4>;
363 clocks = <&hdlcd1_osc>;
364 clock-names = "pxlclk";
368 native-mode = <&timing1>;
370 /* 1024 x 768 framebufer, standard VGA timings */
371 clock-frequency = <65000>;
385 compatible = "simple-bus";
386 #address-cells = <2>;
388 ranges = <0 0 0 0x08000000 0x04000000>,
389 <1 0 0 0x14000000 0x04000000>,
390 <2 0 0 0x18000000 0x04000000>,
391 <3 0 0 0x1c000000 0x04000000>,
392 <4 0 0 0x0c000000 0x04000000>,
393 <5 0 0 0x10000000 0x04000000>;
395 #interrupt-cells = <1>;
396 interrupt-map-mask = <0 0 15>;
397 interrupt-map = <0 0 0 &gic 0 68 4>,
400 <0 0 3 &gic 0 160 4>,
401 <0 0 4 &gic 0 161 4>,
402 <0 0 5 &gic 0 162 4>,
403 <0 0 6 &gic 0 163 4>,
404 <0 0 7 &gic 0 164 4>,
405 <0 0 8 &gic 0 165 4>,
406 <0 0 9 &gic 0 166 4>,
407 <0 0 10 &gic 0 167 4>,
408 <0 0 11 &gic 0 168 4>,
409 <0 0 12 &gic 0 169 4>;
414 arm,vexpress,site = <0>;
415 arm,v2m-memory-map = "rs1";
416 compatible = "arm,vexpress,v2p-p1", "simple-bus";
417 #address-cells = <2>; /* SMB chipselect number and offset */
419 #interrupt-cells = <1>;
423 compatible = "nxp,usb-isp1763";
424 reg = <5 0x00000000 0x20000>;
429 ethernet@2,00000000 {
430 compatible = "smsc,lan9118", "smsc,lan9115";
431 reg = <2 0x00000000 0x10000>;
435 smsc,irq-active-high;
437 clocks = <&mb_eth25mhz>;
438 vdd33a-supply = <&soc_fixed_3v3>; /* change this */
439 vddvario-supply = <&soc_fixed_3v3>; /* and this */
443 compatible = "arm,amba-bus", "simple-bus";
444 #address-cells = <1>;
446 ranges = <0 3 0 0x200000>;
449 compatible = "arm,pl050", "arm,primecell";
450 reg = <0x060000 0x1000>;
452 clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
453 clock-names = "KMIREFCLK", "apb_pclk";
457 compatible = "arm,pl050", "arm,primecell";
458 reg = <0x070000 0x1000>;
460 clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
461 clock-names = "KMIREFCLK", "apb_pclk";
465 compatible = "arm,sp805", "arm,primecell";
466 reg = <0x0f0000 0x10000>;
468 clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
469 clock-names = "wdogclk", "apb_pclk";
472 v2m_timer01: timer@110000 {
473 compatible = "arm,sp804", "arm,primecell";
474 reg = <0x110000 0x10000>;
476 clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
477 clock-names = "timclken1", "apb_pclk";
480 v2m_timer23: timer@120000 {
481 compatible = "arm,sp804", "arm,primecell";
482 reg = <0x120000 0x10000>;
484 clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
485 clock-names = "timclken1", "apb_pclk";
489 compatible = "arm,pl031", "arm,primecell";
490 reg = <0x170000 0x10000>;
492 clocks = <&soc_smc50mhz>;
493 clock-names = "apb_pclk";