2 * dts file for Hisilicon D02 Development Board
4 * Copyright (C) 2014,2015 Hisilicon Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "hisilicon,hip05-d02";
16 interrupt-parent = <&gic>;
21 compatible = "arm,psci-0.2";
90 compatible = "arm,cortex-a57", "arm,armv8";
92 enable-method = "psci";
97 compatible = "arm,cortex-a57", "arm,armv8";
99 enable-method = "psci";
104 compatible = "arm,cortex-a57", "arm,armv8";
106 enable-method = "psci";
111 compatible = "arm,cortex-a57", "arm,armv8";
113 enable-method = "psci";
118 compatible = "arm,cortex-a57", "arm,armv8";
120 enable-method = "psci";
125 compatible = "arm,cortex-a57", "arm,armv8";
127 enable-method = "psci";
132 compatible = "arm,cortex-a57", "arm,armv8";
134 enable-method = "psci";
139 compatible = "arm,cortex-a57", "arm,armv8";
141 enable-method = "psci";
146 compatible = "arm,cortex-a57", "arm,armv8";
148 enable-method = "psci";
153 compatible = "arm,cortex-a57", "arm,armv8";
155 enable-method = "psci";
160 compatible = "arm,cortex-a57", "arm,armv8";
162 enable-method = "psci";
167 compatible = "arm,cortex-a57", "arm,armv8";
169 enable-method = "psci";
174 compatible = "arm,cortex-a57", "arm,armv8";
176 enable-method = "psci";
181 compatible = "arm,cortex-a57", "arm,armv8";
183 enable-method = "psci";
188 compatible = "arm,cortex-a57", "arm,armv8";
190 enable-method = "psci";
195 compatible = "arm,cortex-a57", "arm,armv8";
197 enable-method = "psci";
201 gic: interrupt-controller@8d000000 {
202 compatible = "arm,gic-v3";
203 #interrupt-cells = <3>;
204 #address-cells = <2>;
207 interrupt-controller;
208 #redistributor-regions = <1>;
209 redistributor-stride = <0x0 0x30000>;
210 reg = <0x0 0x8d000000 0 0x10000>, /* GICD */
211 <0x0 0x8d100000 0 0x300000>, /* GICR */
212 <0x0 0xfe000000 0 0x10000>, /* GICC */
213 <0x0 0xfe010000 0 0x10000>, /* GICH */
214 <0x0 0xfe020000 0 0x10000>; /* GICV */
215 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
217 its_totems: interrupt-controller@8c000000 {
218 compatible = "arm,gic-v3-its";
220 reg = <0x0 0x8c000000 0x0 0x40000>;
225 compatible = "arm,armv8-timer";
226 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
227 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
228 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
229 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
233 compatible = "arm,armv8-pmuv3";
234 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
238 compatible = "simple-bus";
239 #address-cells = <2>;
243 refclk200mhz: refclk200mhz {
244 compatible = "fixed-clock";
246 clock-frequency = <200000000>;
249 uart0: uart@80300000 {
250 compatible = "snps,dw-apb-uart";
251 reg = <0x0 0x80300000 0x0 0x10000>;
252 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&refclk200mhz>;
254 clock-names = "apb_pclk";
260 uart1: uart@80310000 {
261 compatible = "snps,dw-apb-uart";
262 reg = <0x0 0x80310000 0x0 0x10000>;
263 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&refclk200mhz>;
265 clock-names = "apb_pclk";