arch/arm64/boot/dts/hisilicon/hi6220.dtsi

   1 /*
   2  * dts file for Hisilicon Hi6220 SoC
   3  *
   4  * Copyright (C) 2015, Hisilicon Ltd.
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8
   9 / {
  10         compatible = "hisilicon,hi6220";
  11         interrupt-parent = <&gic>;
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         psci {
  16                 compatible = "arm,psci-0.2";
  17                 method = "smc";
  18         };
  19
  20         cpus {
  21                 #address-cells = <2>;
  22                 #size-cells = <0>;
  23
  24                 cpu-map {
  25                         cluster0 {
  26                                 core0 {
  27                                         cpu = <&cpu0>;
  28                                 };
  29                                 core1 {
  30                                         cpu = <&cpu1>;
  31                                 };
  32                                 core2 {
  33                                         cpu = <&cpu2>;
  34                                 };
  35                                 core3 {
  36                                         cpu = <&cpu3>;
  37                                 };
  38                         };
  39                         cluster1 {
  40                                 core0 {
  41                                         cpu = <&cpu4>;
  42                                 };
  43                                 core1 {
  44                                         cpu = <&cpu5>;
  45                                 };
  46                                 core2 {
  47                                         cpu = <&cpu6>;
  48                                 };
  49                                 core3 {
  50                                         cpu = <&cpu7>;
  51                                 };
  52                         };
  53                 };
  54
  55                 cpu0: cpu@0 {
  56                         compatible = "arm,cortex-a53", "arm,armv8";
  57                         device_type = "cpu";
  58                         reg = <0x0 0x0>;
  59                         enable-method = "psci";
  60                 };
  61
  62                 cpu1: cpu@1 {
  63                         compatible = "arm,cortex-a53", "arm,armv8";
  64                         device_type = "cpu";
  65                         reg = <0x0 0x1>;
  66                         enable-method = "psci";
  67                 };
  68
  69                 cpu2: cpu@2 {
  70                         compatible = "arm,cortex-a53", "arm,armv8";
  71                         device_type = "cpu";
  72                         reg = <0x0 0x2>;
  73                         enable-method = "psci";
  74                 };
  75
  76                 cpu3: cpu@3 {
  77                         compatible = "arm,cortex-a53", "arm,armv8";
  78                         device_type = "cpu";
  79                         reg = <0x0 0x3>;
  80                         enable-method = "psci";
  81                 };
  82
  83                 cpu4: cpu@100 {
  84                         compatible = "arm,cortex-a53", "arm,armv8";
  85                         device_type = "cpu";
  86                         reg = <0x0 0x100>;
  87                         enable-method = "psci";
  88                 };
  89
  90                 cpu5: cpu@101 {
  91                         compatible = "arm,cortex-a53", "arm,armv8";
  92                         device_type = "cpu";
  93                         reg = <0x0 0x101>;
  94                         enable-method = "psci";
  95                 };
  96
  97                 cpu6: cpu@102 {
  98                         compatible = "arm,cortex-a53", "arm,armv8";
  99                         device_type = "cpu";
 100                         reg = <0x0 0x102>;
 101                         enable-method = "psci";
 102                 };
 103
 104                 cpu7: cpu@103 {
 105                         compatible = "arm,cortex-a53", "arm,armv8";
 106                         device_type = "cpu";
 107                         reg = <0x0 0x103>;
 108                         enable-method = "psci";
 109                 };
 110         };
 111
 112         gic: interrupt-controller@f6801000 {
 113                 compatible = "arm,gic-400";
 114                 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
 115                       <0x0 0xf6802000 0 0x2000>, /* GICC */
 116                       <0x0 0xf6804000 0 0x2000>, /* GICH */
 117                       <0x0 0xf6806000 0 0x2000>; /* GICV */
 118                 #address-cells = <0>;
 119                 #interrupt-cells = <3>;
 120                 interrupt-controller;
 121                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 122         };
 123
 124         timer {
 125                 compatible = "arm,armv8-timer";
 126                 interrupt-parent = <&gic>;
 127                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 128                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 129                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 130                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 131         };
 132
 133         soc {
 134                 compatible = "simple-bus";
 135                 #address-cells = <2>;
 136                 #size-cells = <2>;
 137                 ranges;
 138
 139                 ao_ctrl: ao_ctrl@f7800000 {
 140                         compatible = "hisilicon,hi6220-aoctrl", "syscon";
 141                         reg = <0x0 0xf7800000 0x0 0x2000>;
 142                         #clock-cells = <1>;
 143                 };
 144
 145                 sys_ctrl: sys_ctrl@f7030000 {
 146                         compatible = "hisilicon,hi6220-sysctrl", "syscon";
 147                         reg = <0x0 0xf7030000 0x0 0x2000>;
 148                         #clock-cells = <1>;
 149                 };
 150
 151                 media_ctrl: media_ctrl@f4410000 {
 152                         compatible = "hisilicon,hi6220-mediactrl", "syscon";
 153                         reg = <0x0 0xf4410000 0x0 0x1000>;
 154                         #clock-cells = <1>;
 155                 };
 156
 157                 pm_ctrl: pm_ctrl@f7032000 {
 158                         compatible = "hisilicon,hi6220-pmctrl", "syscon";
 159                         reg = <0x0 0xf7032000 0x0 0x1000>;
 160                         #clock-cells = <1>;
 161                 };
 162
 163                 uart0: uart@f8015000 {  /* console */
 164                         compatible = "arm,pl011", "arm,primecell";
 165                         reg = <0x0 0xf8015000 0x0 0x1000>;
 166                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 167                         clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
 168                         clock-names = "uartclk", "apb_pclk";
 169                 };
 170         };
 171 };