arch/arm64/boot/dts/fvp-base-gicv2-psci.dts

   1 /*
   2  * Copyright (c) 2013, ARM Limited. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions are met:
   6  *
   7  * Redistributions of source code must retain the above copyright notice, this
   8  * list of conditions and the following disclaimer.
   9  *
  10  * Redistributions in binary form must reproduce the above copyright notice,
  11  * this list of conditions and the following disclaimer in the documentation
  12  * and/or other materials provided with the distribution.
  13  *
  14  * Neither the name of ARM nor the names of its contributors may be used
  15  * to endorse or promote products derived from this software without specific
  16  * prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  22  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  28  * POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 /dts-v1/;
  32
  33 /memreserve/ 0x80000000 0x00010000;
  34
  35 / {
  36 };
  37
  38 / {
  39         model = "FVP Base";
  40         compatible = "arm,vfp-base", "arm,vexpress";
  41         interrupt-parent = <&gic>;
  42         #address-cells = <2>;
  43         #size-cells = <2>;
  44
  45         chosen { };
  46
  47         aliases {
  48                 serial0 = &v2m_serial0;
  49                 serial1 = &v2m_serial1;
  50                 serial2 = &v2m_serial2;
  51                 serial3 = &v2m_serial3;
  52         };
  53
  54         psci {
  55                 compatible = "arm,psci";
  56                 method = "smc";
  57                 cpu_suspend = <0x84000001>;
  58                 cpu_off = <0x84000002>;
  59                 cpu_on = <0xc4000003>;
  60         };
  61
  62         cpus {
  63                 #address-cells = <2>;
  64                 #size-cells = <0>;
  65
  66                 idle-states {
  67                         entry-method = "arm,psci";
  68
  69                         CPU_SLEEP_0: cpu-sleep-0 {
  70                                 compatible = "arm,idle-state";
  71                                 entry-method-param = <0x0010000>;
  72                                 entry-latency-us = <40>;
  73                                 exit-latency-us = <100>;
  74                                 min-residency-us = <150>;
  75                         };
  76
  77                         CLUSTER_SLEEP_0: cluster-sleep-0 {
  78                                 compatible = "arm,idle-state";
  79                                 entry-method-param = <0x1010000>;
  80                                 entry-latency-us = <500>;
  81                                 exit-latency-us = <1000>;
  82                                 min-residency-us = <2500>;
  83                         };
  84                 };
  85
  86                 big0: cpu@0 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a57", "arm,armv8";
  89                         reg = <0x0 0x0>;
  90                         enable-method = "psci";
  91                         clock-frequency = <1000000>;
  92                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  93                 };
  94                 big1: cpu@1 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a57", "arm,armv8";
  97                         reg = <0x0 0x1>;
  98                         enable-method = "psci";
  99                         clock-frequency = <1000000>;
 100                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 101                 };
 102                 big2: cpu@2 {
 103                         device_type = "cpu";
 104                         compatible = "arm,cortex-a57", "arm,armv8";
 105                         reg = <0x0 0x2>;
 106                         enable-method = "psci";
 107                         clock-frequency = <1000000>;
 108                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 109                 };
 110                 big3: cpu@3 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a57", "arm,armv8";
 113                         reg = <0x0 0x3>;
 114                         enable-method = "psci";
 115                         clock-frequency = <1000000>;
 116                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 117                 };
 118                 little0: cpu@100 {
 119                         device_type = "cpu";
 120                         compatible = "arm,cortex-a53", "arm,armv8";
 121                         reg = <0x0 0x100>;
 122                         enable-method = "psci";
 123                         clock-frequency = <1000000>;
 124                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 125                 };
 126                 little1: cpu@101 {
 127                         device_type = "cpu";
 128                         compatible = "arm,cortex-a53", "arm,armv8";
 129                         reg = <0x0 0x101>;
 130                         enable-method = "psci";
 131                         clock-frequency = <1000000>;
 132                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 133                 };
 134                 little2: cpu@102 {
 135                         device_type = "cpu";
 136                         compatible = "arm,cortex-a53", "arm,armv8";
 137                         reg = <0x0 0x102>;
 138                         enable-method = "psci";
 139                         clock-frequency = <1000000>;
 140                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 141                 };
 142                 little3: cpu@103 {
 143                         device_type = "cpu";
 144                         compatible = "arm,cortex-a53", "arm,armv8";
 145                         reg = <0x0 0x103>;
 146                         enable-method = "psci";
 147                         clock-frequency = <1000000>;
 148                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 149                 };
 150
 151                 cpu-map {
 152                         cluster0 {
 153                                 core0 {
 154                                         cpu = <&big0>;
 155                                 };
 156                                 core1 {
 157                                         cpu = <&big1>;
 158                                 };
 159                                 core2 {
 160                                         cpu = <&big2>;
 161                                 };
 162                                 core3 {
 163                                         cpu = <&big3>;
 164                                 };
 165                         };
 166                         cluster1 {
 167                                 core0 {
 168                                         cpu = <&little0>;
 169                                 };
 170                                 core1 {
 171                                         cpu = <&little1>;
 172                                 };
 173                                 core2 {
 174                                         cpu = <&little2>;
 175                                 };
 176                                 core3 {
 177                                         cpu = <&little3>;
 178                                 };
 179                         };
 180                 };
 181         };
 182
 183         memory@80000000 {
 184                 device_type = "memory";
 185                 reg = <0x00000000 0x80000000 0 0x80000000>,
 186                       <0x00000008 0x80000000 0 0x80000000>;
 187         };
 188
 189         gic: interrupt-controller@2f000000 {
 190                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 191                 #interrupt-cells = <3>;
 192                 #address-cells = <0>;
 193                 interrupt-controller;
 194                 reg = <0x0 0x2f000000 0 0x10000>,
 195                       <0x0 0x2c000000 0 0x2000>,
 196                       <0x0 0x2c010000 0 0x2000>,
 197                       <0x0 0x2c02F000 0 0x2000>;
 198                 interrupts = <1 9 0xf04>;
 199         };
 200
 201         timer {
 202                 compatible = "arm,armv8-timer";
 203                 interrupts = <1 13 0xff01>,
 204                              <1 14 0xff01>,
 205                              <1 11 0xff01>,
 206                              <1 10 0xff01>;
 207                 clock-frequency = <100000000>;
 208         };
 209
 210         timer@2a810000 {
 211                         compatible = "arm,armv7-timer-mem";
 212                         reg = <0x0 0x2a810000 0x0 0x10000>;
 213                         clock-frequency = <100000000>;
 214                         #address-cells = <2>;
 215                         #size-cells = <2>;
 216                         ranges;
 217                         frame@2a820000 {
 218                                 frame-number = <0>;
 219                                 interrupts = <0 25 4>;
 220                                 reg = <0x0 0x2a820000 0x0 0x10000>;
 221                         };
 222         };
 223
 224         pmu {
 225                 compatible = "arm,armv8-pmuv3";
 226                 interrupts = <0 60 4>,
 227                              <0 61 4>,
 228                              <0 62 4>,
 229                              <0 63 4>;
 230         };
 231
 232         smb {
 233                 compatible = "simple-bus";
 234
 235                 #address-cells = <2>;
 236                 #size-cells = <1>;
 237                 ranges = <0 0 0 0x08000000 0x04000000>,
 238                          <1 0 0 0x14000000 0x04000000>,
 239                          <2 0 0 0x18000000 0x04000000>,
 240                          <3 0 0 0x1c000000 0x04000000>,
 241                          <4 0 0 0x0c000000 0x04000000>,
 242                          <5 0 0 0x10000000 0x04000000>;
 243
 244                 #interrupt-cells = <1>;
 245                 interrupt-map-mask = <0 0 63>;
 246                 interrupt-map = <0 0  0 &gic 0  0 4>,
 247                                 <0 0  1 &gic 0  1 4>,
 248                                 <0 0  2 &gic 0  2 4>,
 249                                 <0 0  3 &gic 0  3 4>,
 250                                 <0 0  4 &gic 0  4 4>,
 251                                 <0 0  5 &gic 0  5 4>,
 252                                 <0 0  6 &gic 0  6 4>,
 253                                 <0 0  7 &gic 0  7 4>,
 254                                 <0 0  8 &gic 0  8 4>,
 255                                 <0 0  9 &gic 0  9 4>,
 256                                 <0 0 10 &gic 0 10 4>,
 257                                 <0 0 11 &gic 0 11 4>,
 258                                 <0 0 12 &gic 0 12 4>,
 259                                 <0 0 13 &gic 0 13 4>,
 260                                 <0 0 14 &gic 0 14 4>,
 261                                 <0 0 15 &gic 0 15 4>,
 262                                 <0 0 16 &gic 0 16 4>,
 263                                 <0 0 17 &gic 0 17 4>,
 264                                 <0 0 18 &gic 0 18 4>,
 265                                 <0 0 19 &gic 0 19 4>,
 266                                 <0 0 20 &gic 0 20 4>,
 267                                 <0 0 21 &gic 0 21 4>,
 268                                 <0 0 22 &gic 0 22 4>,
 269                                 <0 0 23 &gic 0 23 4>,
 270                                 <0 0 24 &gic 0 24 4>,
 271                                 <0 0 25 &gic 0 25 4>,
 272                                 <0 0 26 &gic 0 26 4>,
 273                                 <0 0 27 &gic 0 27 4>,
 274                                 <0 0 28 &gic 0 28 4>,
 275                                 <0 0 29 &gic 0 29 4>,
 276                                 <0 0 30 &gic 0 30 4>,
 277                                 <0 0 31 &gic 0 31 4>,
 278                                 <0 0 32 &gic 0 32 4>,
 279                                 <0 0 33 &gic 0 33 4>,
 280                                 <0 0 34 &gic 0 34 4>,
 281                                 <0 0 35 &gic 0 35 4>,
 282                                 <0 0 36 &gic 0 36 4>,
 283                                 <0 0 37 &gic 0 37 4>,
 284                                 <0 0 38 &gic 0 38 4>,
 285                                 <0 0 39 &gic 0 39 4>,
 286                                 <0 0 40 &gic 0 40 4>,
 287                                 <0 0 41 &gic 0 41 4>,
 288                                 <0 0 42 &gic 0 42 4>;
 289
 290                 /include/ "rtsm_ve-motherboard.dtsi"
 291         };
 292 };
 293
 294 /include/ "clcd-panels.dtsi"