arch/arm64/boot/dts/fvp-base-gicv2-psci.dts

   1 /*
   2  * Copyright (c) 2013, ARM Limited. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions are met:
   6  *
   7  * Redistributions of source code must retain the above copyright notice, this
   8  * list of conditions and the following disclaimer.
   9  *
  10  * Redistributions in binary form must reproduce the above copyright notice,
  11  * this list of conditions and the following disclaimer in the documentation
  12  * and/or other materials provided with the distribution.
  13  *
  14  * Neither the name of ARM nor the names of its contributors may be used
  15  * to endorse or promote products derived from this software without specific
  16  * prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  22  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  28  * POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 /dts-v1/;
  32
  33 /memreserve/ 0x80000000 0x00010000;
  34
  35 / {
  36 };
  37
  38 / {
  39         model = "FVP Base";
  40         compatible = "arm,vfp-base", "arm,vexpress";
  41         interrupt-parent = <&gic>;
  42         #address-cells = <2>;
  43         #size-cells = <2>;
  44
  45         chosen { };
  46
  47         aliases {
  48                 serial0 = &v2m_serial0;
  49                 serial1 = &v2m_serial1;
  50                 serial2 = &v2m_serial2;
  51                 serial3 = &v2m_serial3;
  52         };
  53
  54         psci {
  55                 compatible = "arm,psci";
  56                 method = "smc";
  57                 cpu_suspend = <0xc4000001>;
  58                 cpu_off = <0x84000002>;
  59                 cpu_on = <0xc4000003>;
  60         };
  61
  62         cpus {
  63                 #address-cells = <2>;
  64                 #size-cells = <0>;
  65
  66                 big0: cpu@0 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a57", "arm,armv8";
  69                         reg = <0x0 0x0>;
  70                         enable-method = "psci";
  71                         clock-frequency = <1000000>;
  72                 };
  73                 big1: cpu@1 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a57", "arm,armv8";
  76                         reg = <0x0 0x1>;
  77                         enable-method = "psci";
  78                         clock-frequency = <1000000>;
  79                 };
  80                 big2: cpu@2 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a57", "arm,armv8";
  83                         reg = <0x0 0x2>;
  84                         enable-method = "psci";
  85                         clock-frequency = <1000000>;
  86                 };
  87                 big3: cpu@3 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a57", "arm,armv8";
  90                         reg = <0x0 0x3>;
  91                         enable-method = "psci";
  92                         clock-frequency = <1000000>;
  93                 };
  94                 little0: cpu@100 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a53", "arm,armv8";
  97                         reg = <0x0 0x100>;
  98                         enable-method = "psci";
  99                         clock-frequency = <1000000>;
 100                 };
 101                 little1: cpu@101 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a53", "arm,armv8";
 104                         reg = <0x0 0x101>;
 105                         enable-method = "psci";
 106                         clock-frequency = <1000000>;
 107                 };
 108                 little2: cpu@102 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a53", "arm,armv8";
 111                         reg = <0x0 0x102>;
 112                         enable-method = "psci";
 113                         clock-frequency = <1000000>;
 114                 };
 115                 little3: cpu@103 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a53", "arm,armv8";
 118                         reg = <0x0 0x103>;
 119                         enable-method = "psci";
 120                         clock-frequency = <1000000>;
 121                 };
 122
 123                 cpu-map {
 124                         cluster0 {
 125                                 core0 {
 126                                         cpu = <&big0>;
 127                                 };
 128                                 core1 {
 129                                         cpu = <&big1>;
 130                                 };
 131                                 core2 {
 132                                         cpu = <&big2>;
 133                                 };
 134                                 core3 {
 135                                         cpu = <&big3>;
 136                                 };
 137                         };
 138                         cluster1 {
 139                                 core0 {
 140                                         cpu = <&little0>;
 141                                 };
 142                                 core1 {
 143                                         cpu = <&little1>;
 144                                 };
 145                                 core2 {
 146                                         cpu = <&little2>;
 147                                 };
 148                                 core3 {
 149                                         cpu = <&little3>;
 150                                 };
 151                         };
 152                 };
 153         };
 154
 155         memory@80000000 {
 156                 device_type = "memory";
 157                 reg = <0x00000000 0x80000000 0 0x80000000>,
 158                       <0x00000008 0x80000000 0 0x80000000>;
 159         };
 160
 161         gic: interrupt-controller@2f000000 {
 162                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 163                 #interrupt-cells = <3>;
 164                 #address-cells = <0>;
 165                 interrupt-controller;
 166                 reg = <0x0 0x2f000000 0 0x10000>,
 167                       <0x0 0x2c000000 0 0x2000>,
 168                       <0x0 0x2c010000 0 0x2000>,
 169                       <0x0 0x2c02F000 0 0x2000>;
 170                 interrupts = <1 9 0xf04>;
 171         };
 172
 173         timer {
 174                 compatible = "arm,armv8-timer";
 175                 interrupts = <1 13 0xff01>,
 176                              <1 14 0xff01>,
 177                              <1 11 0xff01>,
 178                              <1 10 0xff01>;
 179                 clock-frequency = <100000000>;
 180         };
 181
 182         timer@2a810000 {
 183                         compatible = "arm,armv7-timer-mem";
 184                         reg = <0x0 0x2a810000 0x0 0x10000>;
 185                         clock-frequency = <100000000>;
 186                         #address-cells = <2>;
 187                         #size-cells = <2>;
 188                         ranges;
 189                         frame@2a820000 {
 190                                 frame-number = <0>;
 191                                 interrupts = <0 25 4>;
 192                                 reg = <0x0 0x2a820000 0x0 0x10000>;
 193                         };
 194         };
 195
 196         pmu {
 197                 compatible = "arm,armv8-pmuv3";
 198                 interrupts = <0 60 4>,
 199                              <0 61 4>,
 200                              <0 62 4>,
 201                              <0 63 4>;
 202         };
 203
 204         smb {
 205                 compatible = "simple-bus";
 206
 207                 #address-cells = <2>;
 208                 #size-cells = <1>;
 209                 ranges = <0 0 0 0x08000000 0x04000000>,
 210                          <1 0 0 0x14000000 0x04000000>,
 211                          <2 0 0 0x18000000 0x04000000>,
 212                          <3 0 0 0x1c000000 0x04000000>,
 213                          <4 0 0 0x0c000000 0x04000000>,
 214                          <5 0 0 0x10000000 0x04000000>;
 215
 216                 #interrupt-cells = <1>;
 217                 interrupt-map-mask = <0 0 63>;
 218                 interrupt-map = <0 0  0 &gic 0  0 4>,
 219                                 <0 0  1 &gic 0  1 4>,
 220                                 <0 0  2 &gic 0  2 4>,
 221                                 <0 0  3 &gic 0  3 4>,
 222                                 <0 0  4 &gic 0  4 4>,
 223                                 <0 0  5 &gic 0  5 4>,
 224                                 <0 0  6 &gic 0  6 4>,
 225                                 <0 0  7 &gic 0  7 4>,
 226                                 <0 0  8 &gic 0  8 4>,
 227                                 <0 0  9 &gic 0  9 4>,
 228                                 <0 0 10 &gic 0 10 4>,
 229                                 <0 0 11 &gic 0 11 4>,
 230                                 <0 0 12 &gic 0 12 4>,
 231                                 <0 0 13 &gic 0 13 4>,
 232                                 <0 0 14 &gic 0 14 4>,
 233                                 <0 0 15 &gic 0 15 4>,
 234                                 <0 0 16 &gic 0 16 4>,
 235                                 <0 0 17 &gic 0 17 4>,
 236                                 <0 0 18 &gic 0 18 4>,
 237                                 <0 0 19 &gic 0 19 4>,
 238                                 <0 0 20 &gic 0 20 4>,
 239                                 <0 0 21 &gic 0 21 4>,
 240                                 <0 0 22 &gic 0 22 4>,
 241                                 <0 0 23 &gic 0 23 4>,
 242                                 <0 0 24 &gic 0 24 4>,
 243                                 <0 0 25 &gic 0 25 4>,
 244                                 <0 0 26 &gic 0 26 4>,
 245                                 <0 0 27 &gic 0 27 4>,
 246                                 <0 0 28 &gic 0 28 4>,
 247                                 <0 0 29 &gic 0 29 4>,
 248                                 <0 0 30 &gic 0 30 4>,
 249                                 <0 0 31 &gic 0 31 4>,
 250                                 <0 0 32 &gic 0 32 4>,
 251                                 <0 0 33 &gic 0 33 4>,
 252                                 <0 0 34 &gic 0 34 4>,
 253                                 <0 0 35 &gic 0 35 4>,
 254                                 <0 0 36 &gic 0 36 4>,
 255                                 <0 0 37 &gic 0 37 4>,
 256                                 <0 0 38 &gic 0 38 4>,
 257                                 <0 0 39 &gic 0 39 4>,
 258                                 <0 0 40 &gic 0 40 4>,
 259                                 <0 0 41 &gic 0 41 4>,
 260                                 <0 0 42 &gic 0 42 4>;
 261
 262                 /include/ "rtsm_ve-motherboard.dtsi"
 263         };
 264
 265         panels {
 266                 panel@0 {
 267                         compatible      = "panel";
 268                         mode            = "XVGA";
 269                         refresh         = <60>;
 270                         xres            = <1024>;
 271                         yres            = <768>;
 272                         pixclock        = <15748>;
 273                         left_margin     = <152>;
 274                         right_margin    = <48>;
 275                         upper_margin    = <23>;
 276                         lower_margin    = <3>;
 277                         hsync_len       = <104>;
 278                         vsync_len       = <4>;
 279                         sync            = <0>;
 280                         vmode           = "FB_VMODE_NONINTERLACED";
 281                         tim2            = "TIM2_BCD", "TIM2_IPC";
 282                         cntl            = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
 283                         caps            = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
 284                         bpp             = <16>;
 285                 };
 286         };
 287 };