arch/arm64/boot/dts/arm/juno.dts

   1 /*
   2  * ARM Ltd. Juno Platform
   3  *
   4  * Copyright (c) 2013-2014 ARM Ltd.
   5  *
   6  * This file is licensed under a dual GPLv2 or BSD license.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12
  13 / {
  14         model = "ARM Juno development board (r0)";
  15         compatible = "arm,juno", "arm,vexpress";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 serial0 = &soc_uart0;
  22         };
  23
  24         chosen {
  25                 stdout-path = "serial0:115200n8";
  26         };
  27
  28         psci {
  29                 compatible = "arm,psci-0.2";
  30                 method = "smc";
  31         };
  32
  33         cpus {
  34                 #address-cells = <2>;
  35                 #size-cells = <0>;
  36
  37                 cpu-map {
  38                         cluster0 {
  39                                 core0 {
  40                                         cpu = <&A57_0>;
  41                                 };
  42                                 core1 {
  43                                         cpu = <&A57_1>;
  44                                 };
  45                         };
  46
  47                         cluster1 {
  48                                 core0 {
  49                                         cpu = <&A53_0>;
  50                                 };
  51                                 core1 {
  52                                         cpu = <&A53_1>;
  53                                 };
  54                                 core2 {
  55                                         cpu = <&A53_2>;
  56                                 };
  57                                 core3 {
  58                                         cpu = <&A53_3>;
  59                                 };
  60                         };
  61                 };
  62
  63                 A57_0: cpu@0 {
  64                         compatible = "arm,cortex-a57","arm,armv8";
  65                         reg = <0x0 0x0>;
  66                         device_type = "cpu";
  67                         enable-method = "psci";
  68                         next-level-cache = <&A57_L2>;
  69                         clocks = <&scpi_dvfs 0>;
  70                 };
  71
  72                 A57_1: cpu@1 {
  73                         compatible = "arm,cortex-a57","arm,armv8";
  74                         reg = <0x0 0x1>;
  75                         device_type = "cpu";
  76                         enable-method = "psci";
  77                         next-level-cache = <&A57_L2>;
  78                         clocks = <&scpi_dvfs 0>;
  79                 };
  80
  81                 A53_0: cpu@100 {
  82                         compatible = "arm,cortex-a53","arm,armv8";
  83                         reg = <0x0 0x100>;
  84                         device_type = "cpu";
  85                         enable-method = "psci";
  86                         next-level-cache = <&A53_L2>;
  87                         clocks = <&scpi_dvfs 1>;
  88                 };
  89
  90                 A53_1: cpu@101 {
  91                         compatible = "arm,cortex-a53","arm,armv8";
  92                         reg = <0x0 0x101>;
  93                         device_type = "cpu";
  94                         enable-method = "psci";
  95                         next-level-cache = <&A53_L2>;
  96                         clocks = <&scpi_dvfs 1>;
  97                 };
  98
  99                 A53_2: cpu@102 {
 100                         compatible = "arm,cortex-a53","arm,armv8";
 101                         reg = <0x0 0x102>;
 102                         device_type = "cpu";
 103                         enable-method = "psci";
 104                         next-level-cache = <&A53_L2>;
 105                         clocks = <&scpi_dvfs 1>;
 106                 };
 107
 108                 A53_3: cpu@103 {
 109                         compatible = "arm,cortex-a53","arm,armv8";
 110                         reg = <0x0 0x103>;
 111                         device_type = "cpu";
 112                         enable-method = "psci";
 113                         next-level-cache = <&A53_L2>;
 114                         clocks = <&scpi_dvfs 1>;
 115                 };
 116
 117                 A57_L2: l2-cache0 {
 118                         compatible = "cache";
 119                 };
 120
 121                 A53_L2: l2-cache1 {
 122                         compatible = "cache";
 123                 };
 124         };
 125
 126         pmu_a57 {
 127                 compatible = "arm,cortex-a57-pmu";
 128                 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
 129                              <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
 130                 interrupt-affinity = <&A57_0>,
 131                                      <&A57_1>;
 132         };
 133
 134         pmu_a53 {
 135                 compatible = "arm,cortex-a53-pmu";
 136                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 137                              <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 138                              <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 139                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 140                 interrupt-affinity = <&A53_0>,
 141                                      <&A53_1>,
 142                                      <&A53_2>,
 143                                      <&A53_3>;
 144         };
 145
 146         etr@20070000 {
 147                 compatible = "arm,coresight-tmc", "arm,primecell";
 148                 reg = <0 0x20070000 0 0x1000>;
 149
 150                 clocks = <&soc_smc50mhz>;
 151                 clock-names = "apb_pclk";
 152                 port {
 153                         etr_in_port: endpoint {
 154                                 slave-mode;
 155                                 remote-endpoint = <&replicator_out_port1>;
 156                         };
 157                 };
 158         };
 159
 160         tpiu@20030000 {
 161                 compatible = "arm,coresight-tpiu", "arm,primecell";
 162                 reg = <0 0x20030000 0 0x1000>;
 163
 164                 clocks = <&soc_smc50mhz>;
 165                 clock-names = "apb_pclk";
 166                 port {
 167                         tpiu_in_port: endpoint {
 168                                 slave-mode;
 169                                 remote-endpoint = <&replicator_out_port0>;
 170                         };
 171                 };
 172         };
 173
 174         replicator@20020000 {
 175                 /* non-configurable replicators don't show up on the
 176                  * AMBA bus.  As such no need to add "arm,primecell".
 177                  */
 178                 compatible = "arm,coresight-replicator";
 179
 180                 ports {
 181                         #address-cells = <1>;
 182                         #size-cells = <0>;
 183
 184                         /* replicator output ports */
 185                         port@0 {
 186                                 reg = <0>;
 187                                 replicator_out_port0: endpoint {
 188                                         remote-endpoint = <&tpiu_in_port>;
 189                                 };
 190                         };
 191
 192                         port@1 {
 193                                 reg = <1>;
 194                                 replicator_out_port1: endpoint {
 195                                         remote-endpoint = <&etr_in_port>;
 196                                 };
 197                         };
 198
 199                         /* replicator input port */
 200                         port@2 {
 201                                 reg = <0>;
 202                                 replicator_in_port0: endpoint {
 203                                         slave-mode;
 204                                         remote-endpoint = <&etf_out_port>;
 205                                 };
 206                         };
 207                 };
 208         };
 209
 210         etf@20010000 {
 211                 compatible = "arm,coresight-tmc", "arm,primecell";
 212                 reg = <0 0x20010000 0 0x1000>;
 213
 214                 clocks = <&soc_smc50mhz>;
 215                 clock-names = "apb_pclk";
 216                 ports {
 217                         #address-cells = <1>;
 218                         #size-cells = <0>;
 219
 220                         /* input port */
 221                         port@0 {
 222                                 reg = <0>;
 223                                 etf_in_port: endpoint {
 224                                         slave-mode;
 225                                         remote-endpoint =
 226                                                 <&main_funnel_out_port>;
 227                                 };
 228                         };
 229
 230                         /* output port */
 231                         port@1 {
 232                                 reg = <0>;
 233                                 etf_out_port: endpoint {
 234                                         remote-endpoint =
 235                                                 <&replicator_in_port0>;
 236                                 };
 237                         };
 238                 };
 239         };
 240
 241         main_funnel@20040000 {
 242                 compatible = "arm,coresight-funnel", "arm,primecell";
 243                 reg = <0 0x20040000 0 0x1000>;
 244
 245                 clocks = <&soc_smc50mhz>;
 246                 clock-names = "apb_pclk";
 247                 ports {
 248                         #address-cells = <1>;
 249                         #size-cells = <0>;
 250
 251                         port@0 {
 252                                 reg = <0>;
 253                                 main_funnel_out_port: endpoint {
 254                                         remote-endpoint =
 255                                                 <&etf_in_port>;
 256                                 };
 257                         };
 258
 259                         port@1 {
 260                                 reg = <0>;
 261                                 main_funnel_in_port0: endpoint {
 262                                         slave-mode;
 263                                         remote-endpoint =
 264                                                 <&A72_57_funnel_out_port>;
 265                                 };
 266                         };
 267
 268                         port@2 {
 269                                 reg = <1>;
 270                                 main_funnel_in_port1: endpoint {
 271                                         slave-mode;
 272                                         remote-endpoint = <&A53_funnel_out_port>;
 273                                 };
 274                         };
 275
 276                 };
 277         };
 278
 279         A72_57_funnel@220c0000 {
 280                 compatible = "arm,coresight-funnel", "arm,primecell";
 281                 reg = <0 0x220c0000 0 0x1000>;
 282
 283                 clocks = <&soc_smc50mhz>;
 284                 clock-names = "apb_pclk";
 285                 ports {
 286                         #address-cells = <1>;
 287                         #size-cells = <0>;
 288
 289                         port@0 {
 290                                 reg = <0>;
 291                                 A72_57_funnel_out_port: endpoint {
 292                                         remote-endpoint =
 293                                                 <&main_funnel_in_port0>;
 294                                 };
 295                         };
 296
 297                         port@1 {
 298                                 reg = <0>;
 299                                 A72_57_funnel_in_port0: endpoint {
 300                                         slave-mode;
 301                                         remote-endpoint =
 302                                                         <&A72_57_etm0_out_port>;
 303                                 };
 304                         };
 305
 306                         port@2 {
 307                                 reg = <1>;
 308                                 A72_57_funnel_in_port1: endpoint {
 309                                         slave-mode;
 310                                         remote-endpoint =
 311                                                         <&A72_57_etm1_out_port>;
 312                                 };
 313                         };
 314                 };
 315         };
 316
 317         A53_funnel@220c0000 {
 318                 compatible = "arm,coresight-funnel", "arm,primecell";
 319                 reg = <0 0x230c0000 0 0x1000>;
 320
 321                 clocks = <&soc_smc50mhz>;
 322                 clock-names = "apb_pclk";
 323                 ports {
 324                         #address-cells = <1>;
 325                         #size-cells = <0>;
 326
 327                         port@0 {
 328                                 reg = <0>;
 329                                 A53_funnel_out_port: endpoint {
 330                                         remote-endpoint =
 331                                                 <&main_funnel_in_port1>;
 332                                 };
 333                         };
 334
 335                         port@1 {
 336                                 reg = <0>;
 337                                 A53_funnel_in_port0: endpoint {
 338                                         slave-mode;
 339                                         remote-endpoint = <&A53_etm0_out_port>;
 340                                 };
 341                         };
 342
 343                         port@2 {
 344                                 reg = <1>;
 345                                 A53_funnel_in_port1: endpoint {
 346                                         slave-mode;
 347                                         remote-endpoint = <&A53_etm1_out_port>;
 348                                 };
 349                         };
 350                         port@3 {
 351                                 reg = <2>;
 352                                 A53_funnel_in_port2: endpoint {
 353                                         slave-mode;
 354                                         remote-endpoint = <&A53_etm2_out_port>;
 355                                 };
 356                         };
 357                         port@4 {
 358                                 reg = <3>;
 359                                 A53_funnel_in_port3: endpoint {
 360                                         slave-mode;
 361                                         remote-endpoint = <&A53_etm3_out_port>;
 362                                 };
 363                         };
 364                 };
 365         };
 366
 367         etm@22040000 {
 368                 compatible = "arm,coresight-etm4x", "arm,primecell";
 369                 reg = <0 0x22040000 0 0x1000>;
 370
 371                 cpu = <&A57_0>;
 372                 clocks = <&soc_smc50mhz>;
 373                 clock-names = "apb_pclk";
 374                 port {
 375                         A72_57_etm0_out_port: endpoint {
 376                                 remote-endpoint = <&A72_57_funnel_in_port0>;
 377                         };
 378                 };
 379         };
 380
 381         etm@22140000 {
 382                 compatible = "arm,coresight-etm4x", "arm,primecell";
 383                 reg = <0 0x22140000 0 0x1000>;
 384
 385                 cpu = <&A57_1>;
 386                 clocks = <&soc_smc50mhz>;
 387                 clock-names = "apb_pclk";
 388                 port {
 389                         A72_57_etm1_out_port: endpoint {
 390                                 remote-endpoint = <&A72_57_funnel_in_port1>;
 391                         };
 392                 };
 393         };
 394
 395         etm@23040000 {
 396                 compatible = "arm,coresight-etm4x", "arm,primecell";
 397                 reg = <0 0x23040000 0 0x1000>;
 398
 399                 cpu = <&A53_0>;
 400                 clocks = <&soc_smc50mhz>;
 401                 clock-names = "apb_pclk";
 402                 port {
 403                         A53_etm0_out_port: endpoint {
 404                                 remote-endpoint = <&A53_funnel_in_port0>;
 405                         };
 406                 };
 407         };
 408
 409         etm@23140000 {
 410                 compatible = "arm,coresight-etm4x", "arm,primecell";
 411                 reg = <0 0x23140000 0 0x1000>;
 412
 413                 cpu = <&A53_1>;
 414                 clocks = <&soc_smc50mhz>;
 415                 clock-names = "apb_pclk";
 416                 port {
 417                         A53_etm1_out_port: endpoint {
 418                                 remote-endpoint = <&A53_funnel_in_port1>;
 419                         };
 420                 };
 421         };
 422
 423         etm@23240000 {
 424                 compatible = "arm,coresight-etm4x", "arm,primecell";
 425                 reg = <0 0x23240000 0 0x1000>;
 426
 427                 cpu = <&A53_2>;
 428                 clocks = <&soc_smc50mhz>;
 429                 clock-names = "apb_pclk";
 430                 port {
 431                         A53_etm2_out_port: endpoint {
 432                                 remote-endpoint = <&A53_funnel_in_port2>;
 433                         };
 434                 };
 435         };
 436
 437         etm@23340000 {
 438                 compatible = "arm,coresight-etm4x", "arm,primecell";
 439                 reg = <0 0x23340000 0 0x1000>;
 440
 441                 cpu = <&A53_3>;
 442                 clocks = <&soc_smc50mhz>;
 443                 clock-names = "apb_pclk";
 444                 port {
 445                         A53_etm3_out_port: endpoint {
 446                                 remote-endpoint = <&A53_funnel_in_port3>;
 447                         };
 448                 };
 449         };
 450
 451         #include "juno-base.dtsi"
 452 };