2 * ARM Juno Platform motherboard peripherals
4 * Copyright (c) 2013-2014 ARM Ltd
6 * This file is licensed under a dual GPLv2 or BSD license.
10 mb_clk24mhz: clk24mhz {
11 compatible = "fixed-clock";
13 clock-frequency = <24000000>;
14 clock-output-names = "juno_mb:clk24mhz";
17 mb_clk25mhz: clk25mhz {
18 compatible = "fixed-clock";
20 clock-frequency = <25000000>;
21 clock-output-names = "juno_mb:clk25mhz";
24 v2m_refclk1mhz: refclk1mhz {
25 compatible = "fixed-clock";
27 clock-frequency = <1000000>;
28 clock-output-names = "juno_mb:refclk1mhz";
31 v2m_refclk32khz: refclk32khz {
32 compatible = "fixed-clock";
34 clock-frequency = <32768>;
35 clock-output-names = "juno_mb:refclk32khz";
39 compatible = "arm,vexpress,v2p-p1", "simple-bus";
40 #address-cells = <2>; /* SMB chipselect number and offset */
42 #interrupt-cells = <1>;
46 arm,vexpress,site = <0>;
47 arm,v2m-memory-map = "rs1";
49 mb_fixed_3v3: fixedregulator@0 {
50 compatible = "regulator-fixed";
51 regulator-name = "MCC_SB_3V3";
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
58 compatible = "gpio-keys";
63 debounce_interval = <50>;
67 gpios = <&iofpga_gpio0 0 0x4>;
70 debounce_interval = <50>;
74 gpios = <&iofpga_gpio0 1 0x4>;
77 debounce_interval = <50>;
81 gpios = <&iofpga_gpio0 2 0x4>;
84 debounce_interval = <50>;
88 gpios = <&iofpga_gpio0 3 0x4>;
91 debounce_interval = <50>;
95 gpios = <&iofpga_gpio0 4 0x4>;
98 debounce_interval = <50>;
102 gpios = <&iofpga_gpio0 5 0x4>;
106 ethernet@2,00000000 {
107 compatible = "smsc,lan9118", "smsc,lan9115";
108 reg = <2 0x00000000 0x10000>;
112 smsc,irq-active-high;
114 clocks = <&mb_clk25mhz>;
115 vdd33a-supply = <&mb_fixed_3v3>;
116 vddvario-supply = <&mb_fixed_3v3>;
120 compatible = "nxp,usb-isp1763";
121 reg = <5 0x00000000 0x20000>;
127 compatible = "arm,amba-bus", "simple-bus";
128 #address-cells = <1>;
130 ranges = <0 3 0 0x200000>;
132 v2m_sysctl: sysctl@020000 {
133 compatible = "arm,sp810", "arm,primecell";
134 reg = <0x020000 0x1000>;
135 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
136 clock-names = "refclk", "timclk", "apb_pclk";
138 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
142 compatible = "syscon", "simple-mfd";
143 reg = <0x010000 0x1000>;
146 compatible = "register-bit-led";
149 label = "vexpress:0";
150 linux,default-trigger = "heartbeat";
151 default-state = "on";
154 compatible = "register-bit-led";
157 label = "vexpress:1";
158 linux,default-trigger = "mmc0";
159 default-state = "off";
162 compatible = "register-bit-led";
165 label = "vexpress:2";
166 linux,default-trigger = "cpu0";
167 default-state = "off";
170 compatible = "register-bit-led";
173 label = "vexpress:3";
174 linux,default-trigger = "cpu1";
175 default-state = "off";
178 compatible = "register-bit-led";
181 label = "vexpress:4";
182 linux,default-trigger = "cpu2";
183 default-state = "off";
186 compatible = "register-bit-led";
189 label = "vexpress:5";
190 linux,default-trigger = "cpu3";
191 default-state = "off";
194 compatible = "register-bit-led";
197 label = "vexpress:6";
198 default-state = "off";
201 compatible = "register-bit-led";
204 label = "vexpress:7";
205 default-state = "off";
210 compatible = "arm,pl180", "arm,primecell";
211 reg = <0x050000 0x1000>;
213 /* cd-gpios = <&v2m_mmc_gpios 0 0>;
214 wp-gpios = <&v2m_mmc_gpios 1 0>; */
215 max-frequency = <12000000>;
216 vmmc-supply = <&mb_fixed_3v3>;
217 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
218 clock-names = "mclk", "apb_pclk";
222 compatible = "arm,pl050", "arm,primecell";
223 reg = <0x060000 0x1000>;
225 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
226 clock-names = "KMIREFCLK", "apb_pclk";
230 compatible = "arm,pl050", "arm,primecell";
231 reg = <0x070000 0x1000>;
233 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
234 clock-names = "KMIREFCLK", "apb_pclk";
238 compatible = "arm,sp805", "arm,primecell";
239 reg = <0x0f0000 0x10000>;
241 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
242 clock-names = "wdogclk", "apb_pclk";
245 v2m_timer01: timer@110000 {
246 compatible = "arm,sp804", "arm,primecell";
247 reg = <0x110000 0x10000>;
249 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
250 clock-names = "timclken1", "timclken2", "apb_pclk";
253 v2m_timer23: timer@120000 {
254 compatible = "arm,sp804", "arm,primecell";
255 reg = <0x120000 0x10000>;
257 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
258 clock-names = "timclken1", "timclken2", "apb_pclk";
262 compatible = "arm,pl031", "arm,primecell";
263 reg = <0x170000 0x10000>;
265 clocks = <&soc_smc50mhz>;
266 clock-names = "apb_pclk";
269 iofpga_gpio0: gpio@1d0000 {
270 compatible = "arm,pl061", "arm,primecell";
271 reg = <0x1d0000 0x1000>;
273 clocks = <&soc_smc50mhz>;
274 clock-names = "apb_pclk";
277 interrupt-controller;
278 #interrupt-cells = <2>;