2 * dts file for AppliedMicro (APM) X-Gene Storm SOC
4 * Copyright (C) 2013, Applied Micro Circuits Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
13 compatible = "apm,xgene-storm";
14 interrupt-parent = <&gic>;
24 compatible = "apm,potenza", "arm,armv8";
26 enable-method = "spin-table";
27 cpu-release-addr = <0x1 0x0000fff8>;
31 compatible = "apm,potenza", "arm,armv8";
33 enable-method = "spin-table";
34 cpu-release-addr = <0x1 0x0000fff8>;
38 compatible = "apm,potenza", "arm,armv8";
40 enable-method = "spin-table";
41 cpu-release-addr = <0x1 0x0000fff8>;
45 compatible = "apm,potenza", "arm,armv8";
47 enable-method = "spin-table";
48 cpu-release-addr = <0x1 0x0000fff8>;
52 compatible = "apm,potenza", "arm,armv8";
54 enable-method = "spin-table";
55 cpu-release-addr = <0x1 0x0000fff8>;
59 compatible = "apm,potenza", "arm,armv8";
61 enable-method = "spin-table";
62 cpu-release-addr = <0x1 0x0000fff8>;
66 compatible = "apm,potenza", "arm,armv8";
68 enable-method = "spin-table";
69 cpu-release-addr = <0x1 0x0000fff8>;
73 compatible = "apm,potenza", "arm,armv8";
75 enable-method = "spin-table";
76 cpu-release-addr = <0x1 0x0000fff8>;
80 gic: interrupt-controller@78010000 {
81 compatible = "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
84 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
85 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
86 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
87 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
88 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
92 compatible = "arm,armv8-timer";
93 interrupts = <1 0 0xff01>, /* Secure Phys IRQ */
94 <1 13 0xff01>, /* Non-secure Phys IRQ */
95 <1 14 0xff01>, /* Virt IRQ */
96 <1 15 0xff01>; /* Hyp IRQ */
97 clock-frequency = <50000000>;
101 compatible = "simple-bus";
102 #address-cells = <2>;
107 #address-cells = <2>;
111 compatible = "fixed-clock";
113 clock-frequency = <100000000>;
114 clock-output-names = "refclk";
117 pcppll: pcppll@17000100 {
118 compatible = "apm,xgene-pcppll-clock";
120 clocks = <&refclk 0>;
121 clock-names = "pcppll";
122 reg = <0x0 0x17000100 0x0 0x1000>;
123 clock-output-names = "pcppll";
127 socpll: socpll@17000120 {
128 compatible = "apm,xgene-socpll-clock";
130 clocks = <&refclk 0>;
131 clock-names = "socpll";
132 reg = <0x0 0x17000120 0x0 0x1000>;
133 clock-output-names = "socpll";
137 socplldiv2: socplldiv2 {
138 compatible = "fixed-factor-clock";
140 clocks = <&socpll 0>;
141 clock-names = "socplldiv2";
144 clock-output-names = "socplldiv2";
148 compatible = "apm,xgene-device-clock";
150 clocks = <&socplldiv2 0>;
151 clock-names = "qmlclk";
152 reg = <0x0 0x1703C000 0x0 0x1000>;
153 reg-names = "csr-reg";
154 clock-output-names = "qmlclk";
158 compatible = "apm,xgene-device-clock";
160 clocks = <&socplldiv2 0>;
161 clock-names = "ethclk";
162 reg = <0x0 0x17000000 0x0 0x1000>;
163 reg-names = "div-reg";
164 divider-offset = <0x238>;
165 divider-width = <0x9>;
166 divider-shift = <0x0>;
167 clock-output-names = "ethclk";
171 compatible = "apm,xgene-device-clock";
173 clocks = <ðclk 0>;
174 reg = <0x0 0x1702C000 0x0 0x1000>;
175 reg-names = "csr-reg";
176 clock-output-names = "menetclk";
179 sataphy1clk: sataphy1clk@1f21c000 {
180 compatible = "apm,xgene-device-clock";
182 clocks = <&socplldiv2 0>;
183 reg = <0x0 0x1f21c000 0x0 0x1000>;
184 reg-names = "csr-reg";
185 clock-output-names = "sataphy1clk";
189 enable-offset = <0x0>;
190 enable-mask = <0x06>;
193 sataphy2clk: sataphy1clk@1f22c000 {
194 compatible = "apm,xgene-device-clock";
196 clocks = <&socplldiv2 0>;
197 reg = <0x0 0x1f22c000 0x0 0x1000>;
198 reg-names = "csr-reg";
199 clock-output-names = "sataphy2clk";
203 enable-offset = <0x0>;
204 enable-mask = <0x06>;
207 sataphy3clk: sataphy1clk@1f23c000 {
208 compatible = "apm,xgene-device-clock";
210 clocks = <&socplldiv2 0>;
211 reg = <0x0 0x1f23c000 0x0 0x1000>;
212 reg-names = "csr-reg";
213 clock-output-names = "sataphy3clk";
217 enable-offset = <0x0>;
218 enable-mask = <0x06>;
221 sata01clk: sata01clk@1f21c000 {
222 compatible = "apm,xgene-device-clock";
224 clocks = <&socplldiv2 0>;
225 reg = <0x0 0x1f21c000 0x0 0x1000>;
226 reg-names = "csr-reg";
227 clock-output-names = "sata01clk";
230 enable-offset = <0x0>;
231 enable-mask = <0x39>;
234 sata23clk: sata23clk@1f22c000 {
235 compatible = "apm,xgene-device-clock";
237 clocks = <&socplldiv2 0>;
238 reg = <0x0 0x1f22c000 0x0 0x1000>;
239 reg-names = "csr-reg";
240 clock-output-names = "sata23clk";
243 enable-offset = <0x0>;
244 enable-mask = <0x39>;
247 sata45clk: sata45clk@1f23c000 {
248 compatible = "apm,xgene-device-clock";
250 clocks = <&socplldiv2 0>;
251 reg = <0x0 0x1f23c000 0x0 0x1000>;
252 reg-names = "csr-reg";
253 clock-output-names = "sata45clk";
256 enable-offset = <0x0>;
257 enable-mask = <0x39>;
260 rtcclk: rtcclk@17000000 {
261 compatible = "apm,xgene-device-clock";
263 clocks = <&socplldiv2 0>;
264 reg = <0x0 0x17000000 0x0 0x2000>;
265 reg-names = "csr-reg";
268 enable-offset = <0x10>;
270 clock-output-names = "rtcclk";
274 serial0: serial@1c020000 {
276 device_type = "serial";
277 compatible = "ns16550a";
278 reg = <0 0x1c020000 0x0 0x1000>;
280 clock-frequency = <10000000>; /* Updated by bootloader */
281 interrupt-parent = <&gic>;
282 interrupts = <0x0 0x4c 0x4>;
285 serial1: serial@1c021000 {
287 device_type = "serial";
288 compatible = "ns16550a";
289 reg = <0 0x1c021000 0x0 0x1000>;
291 clock-frequency = <10000000>; /* Updated by bootloader */
292 interrupt-parent = <&gic>;
293 interrupts = <0x0 0x4d 0x4>;
296 serial2: serial@1c022000 {
298 device_type = "serial";
299 compatible = "ns16550a";
300 reg = <0 0x1c022000 0x0 0x1000>;
302 clock-frequency = <10000000>; /* Updated by bootloader */
303 interrupt-parent = <&gic>;
304 interrupts = <0x0 0x4e 0x4>;
307 serial3: serial@1c023000 {
309 device_type = "serial";
310 compatible = "ns16550a";
311 reg = <0 0x1c023000 0x0 0x1000>;
313 clock-frequency = <10000000>; /* Updated by bootloader */
314 interrupt-parent = <&gic>;
315 interrupts = <0x0 0x4f 0x4>;
319 compatible = "apm,xgene-phy";
320 reg = <0x0 0x1f21a000 0x0 0x100>;
322 clocks = <&sataphy1clk 0>;
324 apm,tx-boost-gain = <30 30 30 30 30 30>;
325 apm,tx-eye-tuning = <2 10 10 2 10 10>;
329 compatible = "apm,xgene-phy";
330 reg = <0x0 0x1f22a000 0x0 0x100>;
332 clocks = <&sataphy2clk 0>;
334 apm,tx-boost-gain = <30 30 30 30 30 30>;
335 apm,tx-eye-tuning = <1 10 10 2 10 10>;
339 compatible = "apm,xgene-phy";
340 reg = <0x0 0x1f23a000 0x0 0x100>;
342 clocks = <&sataphy3clk 0>;
344 apm,tx-boost-gain = <31 31 31 31 31 31>;
345 apm,tx-eye-tuning = <2 10 10 2 10 10>;
348 sata1: sata@1a000000 {
349 compatible = "apm,xgene-ahci";
350 reg = <0x0 0x1a000000 0x0 0x1000>,
351 <0x0 0x1f210000 0x0 0x1000>,
352 <0x0 0x1f21d000 0x0 0x1000>,
353 <0x0 0x1f21e000 0x0 0x1000>,
354 <0x0 0x1f217000 0x0 0x1000>;
355 interrupts = <0x0 0x86 0x4>;
358 clocks = <&sata01clk 0>;
360 phy-names = "sata-phy";
363 sata2: sata@1a400000 {
364 compatible = "apm,xgene-ahci";
365 reg = <0x0 0x1a400000 0x0 0x1000>,
366 <0x0 0x1f220000 0x0 0x1000>,
367 <0x0 0x1f22d000 0x0 0x1000>,
368 <0x0 0x1f22e000 0x0 0x1000>,
369 <0x0 0x1f227000 0x0 0x1000>;
370 interrupts = <0x0 0x87 0x4>;
373 clocks = <&sata23clk 0>;
375 phy-names = "sata-phy";
378 sata3: sata@1a800000 {
379 compatible = "apm,xgene-ahci";
380 reg = <0x0 0x1a800000 0x0 0x1000>,
381 <0x0 0x1f230000 0x0 0x1000>,
382 <0x0 0x1f23d000 0x0 0x1000>,
383 <0x0 0x1f23e000 0x0 0x1000>;
384 interrupts = <0x0 0x88 0x4>;
387 clocks = <&sata45clk 0>;
389 phy-names = "sata-phy";
393 compatible = "apm,xgene-rtc";
394 reg = <0x0 0x10510000 0x0 0x400>;
395 interrupts = <0x0 0x46 0x4>;
397 clocks = <&rtcclk 0>;
400 menet: ethernet@17020000 {
401 compatible = "apm,xgene-enet";
403 reg = <0x0 0x17020000 0x0 0xd100>,
404 <0x0 0X17030000 0x0 0X400>,
405 <0x0 0X10000000 0x0 0X200>;
406 reg-names = "enet_csr", "ring_csr", "ring_cmd";
407 interrupts = <0x0 0x3c 0x4>;
409 clocks = <&menetclk 0>;
410 local-mac-address = [00 01 73 00 00 01];
411 phy-connection-type = "rgmii";
412 phy-handle = <&menetphy>;
414 compatible = "apm,xgene-mdio";
415 #address-cells = <1>;
417 menetphy: menetphy@3 {
418 compatible = "ethernet-phy-id001c.c915";