3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
16 select ARCH_HAS_UBSAN_SANITIZE_ALL
20 select AUDIT_ARCH_COMPAT_GENERIC
21 select ARM_GIC_V2M if PCI_MSI
23 select ARM_GIC_V3_ITS if PCI_MSI
25 select BUILDTIME_EXTABLE_SORT
26 select CLONE_BACKWARDS
28 select CPU_PM if (SUSPEND || CPU_IDLE)
29 select DCACHE_WORD_ACCESS
32 select GENERIC_ALLOCATOR
33 select GENERIC_CLOCKEVENTS
34 select GENERIC_CLOCKEVENTS_BROADCAST
35 select GENERIC_CPU_AUTOPROBE
36 select GENERIC_EARLY_IOREMAP
37 select GENERIC_IDLE_POLL_SETUP
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_SHOW_LEVEL
41 select GENERIC_PCI_IOMAP
42 select GENERIC_SCHED_CLOCK
43 select GENERIC_SMP_IDLE_THREAD
44 select GENERIC_STRNCPY_FROM_USER
45 select GENERIC_STRNLEN_USER
46 select GENERIC_TIME_VSYSCALL
47 select HANDLE_DOMAIN_IRQ
48 select HARDIRQS_SW_RESEND
49 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
50 select HAVE_ARCH_AUDITSYSCALL
51 select HAVE_ARCH_BITREVERSE
52 select HAVE_ARCH_HUGE_VMAP
53 select HAVE_ARCH_JUMP_LABEL
54 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
56 select HAVE_ARCH_SECCOMP_FILTER
57 select HAVE_ARCH_TRACEHOOK
59 select HAVE_C_RECORDMCOUNT
60 select HAVE_CC_STACKPROTECTOR
61 select HAVE_CMPXCHG_DOUBLE
62 select HAVE_CMPXCHG_LOCAL
63 select HAVE_DEBUG_BUGVERBOSE
64 select HAVE_DEBUG_KMEMLEAK
65 select HAVE_DMA_API_DEBUG
67 select HAVE_DMA_CONTIGUOUS
68 select HAVE_DYNAMIC_FTRACE
69 select HAVE_EFFICIENT_UNALIGNED_ACCESS
70 select HAVE_FTRACE_MCOUNT_RECORD
71 select HAVE_FUNCTION_TRACER
72 select HAVE_FUNCTION_GRAPH_TRACER
73 select HAVE_GENERIC_DMA_COHERENT
74 select HAVE_HW_BREAKPOINT if PERF_EVENTS
75 select HAVE_IRQ_TIME_ACCOUNTING
77 select HAVE_PATA_PLATFORM
78 select HAVE_PERF_EVENTS
80 select HAVE_PERF_USER_STACK_DUMP
81 select HAVE_RCU_TABLE_FREE
82 select HAVE_SYSCALL_TRACEPOINTS
83 select IOMMU_DMA if IOMMU_SUPPORT
85 select IRQ_FORCED_THREADING
86 select MODULES_USE_ELF_RELA
89 select OF_EARLY_FLATTREE
90 select OF_RESERVED_MEM
91 select PERF_USE_VMALLOC
96 select SYSCTL_EXCEPTION_TRACE
97 select HAVE_CONTEXT_TRACKING
99 ARM 64-bit (AArch64) Linux support.
104 config ARCH_PHYS_ADDR_T_64BIT
113 config STACKTRACE_SUPPORT
116 config ILLEGAL_POINTER_VALUE
118 default 0xdead000000000000
120 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
126 config RWSEM_XCHGADD_ALGORITHM
133 config GENERIC_BUG_RELATIVE_POINTERS
135 depends on GENERIC_BUG
137 config GENERIC_HWEIGHT
143 config GENERIC_CALIBRATE_DELAY
149 config HAVE_GENERIC_RCU_GUP
152 config ARCH_DMA_ADDR_T_64BIT
155 config NEED_DMA_MAP_STATE
158 config NEED_SG_DMA_LENGTH
170 config KERNEL_MODE_NEON
173 config FIX_EARLYCON_MEM
176 config PGTABLE_LEVELS
178 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
179 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
180 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
181 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
182 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
183 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
185 source "init/Kconfig"
187 source "kernel/Kconfig.freezer"
189 source "arch/arm64/Kconfig.platforms"
196 This feature enables support for PCI bus system. If you say Y
197 here, the kernel will include drivers and infrastructure code
198 to support PCI bus devices.
203 config PCI_DOMAINS_GENERIC
209 source "drivers/pci/Kconfig"
210 source "drivers/pci/pcie/Kconfig"
211 source "drivers/pci/hotplug/Kconfig"
215 menu "Kernel Features"
217 menu "ARM errata workarounds via the alternatives framework"
219 config ARM64_ERRATUM_826319
220 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
223 This option adds an alternative code sequence to work around ARM
224 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
225 AXI master interface and an L2 cache.
227 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
228 and is unable to accept a certain write via this interface, it will
229 not progress on read data presented on the read data channel and the
232 The workaround promotes data cache clean instructions to
233 data cache clean-and-invalidate.
234 Please note that this does not necessarily enable the workaround,
235 as it depends on the alternative framework, which will only patch
236 the kernel if an affected CPU is detected.
240 config ARM64_ERRATUM_827319
241 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
244 This option adds an alternative code sequence to work around ARM
245 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
246 master interface and an L2 cache.
248 Under certain conditions this erratum can cause a clean line eviction
249 to occur at the same time as another transaction to the same address
250 on the AMBA 5 CHI interface, which can cause data corruption if the
251 interconnect reorders the two transactions.
253 The workaround promotes data cache clean instructions to
254 data cache clean-and-invalidate.
255 Please note that this does not necessarily enable the workaround,
256 as it depends on the alternative framework, which will only patch
257 the kernel if an affected CPU is detected.
261 config ARM64_ERRATUM_824069
262 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
265 This option adds an alternative code sequence to work around ARM
266 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
267 to a coherent interconnect.
269 If a Cortex-A53 processor is executing a store or prefetch for
270 write instruction at the same time as a processor in another
271 cluster is executing a cache maintenance operation to the same
272 address, then this erratum might cause a clean cache line to be
273 incorrectly marked as dirty.
275 The workaround promotes data cache clean instructions to
276 data cache clean-and-invalidate.
277 Please note that this option does not necessarily enable the
278 workaround, as it depends on the alternative framework, which will
279 only patch the kernel if an affected CPU is detected.
283 config ARM64_ERRATUM_819472
284 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
287 This option adds an alternative code sequence to work around ARM
288 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
289 present when it is connected to a coherent interconnect.
291 If the processor is executing a load and store exclusive sequence at
292 the same time as a processor in another cluster is executing a cache
293 maintenance operation to the same address, then this erratum might
294 cause data corruption.
296 The workaround promotes data cache clean instructions to
297 data cache clean-and-invalidate.
298 Please note that this does not necessarily enable the workaround,
299 as it depends on the alternative framework, which will only patch
300 the kernel if an affected CPU is detected.
304 config ARM64_ERRATUM_832075
305 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
308 This option adds an alternative code sequence to work around ARM
309 erratum 832075 on Cortex-A57 parts up to r1p2.
311 Affected Cortex-A57 parts might deadlock when exclusive load/store
312 instructions to Write-Back memory are mixed with Device loads.
314 The workaround is to promote device loads to use Load-Acquire
316 Please note that this does not necessarily enable the workaround,
317 as it depends on the alternative framework, which will only patch
318 the kernel if an affected CPU is detected.
322 config ARM64_ERRATUM_834220
323 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
327 This option adds an alternative code sequence to work around ARM
328 erratum 834220 on Cortex-A57 parts up to r1p2.
330 Affected Cortex-A57 parts might report a Stage 2 translation
331 fault as the result of a Stage 1 fault for load crossing a
332 page boundary when there is a permission or device memory
333 alignment fault at Stage 1 and a translation fault at Stage 2.
335 The workaround is to verify that the Stage 1 translation
336 doesn't generate a fault before handling the Stage 2 fault.
337 Please note that this does not necessarily enable the workaround,
338 as it depends on the alternative framework, which will only patch
339 the kernel if an affected CPU is detected.
343 config ARM64_ERRATUM_845719
344 bool "Cortex-A53: 845719: a load might read incorrect data"
348 This option adds an alternative code sequence to work around ARM
349 erratum 845719 on Cortex-A53 parts up to r0p4.
351 When running a compat (AArch32) userspace on an affected Cortex-A53
352 part, a load at EL0 from a virtual address that matches the bottom 32
353 bits of the virtual address used by a recent load at (AArch64) EL1
354 might return incorrect data.
356 The workaround is to write the contextidr_el1 register on exception
357 return to a 32-bit task.
358 Please note that this does not necessarily enable the workaround,
359 as it depends on the alternative framework, which will only patch
360 the kernel if an affected CPU is detected.
364 config ARM64_ERRATUM_843419
365 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
369 This option builds kernel modules using the large memory model in
370 order to avoid the use of the ADRP instruction, which can cause
371 a subsequent memory access to use an incorrect address on Cortex-A53
374 Note that the kernel itself must be linked with a version of ld
375 which fixes potentially affected ADRP instructions through the
380 config CAVIUM_ERRATUM_22375
381 bool "Cavium erratum 22375, 24313"
384 Enable workaround for erratum 22375, 24313.
386 This implements two gicv3-its errata workarounds for ThunderX. Both
387 with small impact affecting only ITS table allocation.
389 erratum 22375: only alloc 8MB table size
390 erratum 24313: ignore memory access type
392 The fixes are in ITS initialization and basically ignore memory access
393 type and table size provided by the TYPER and BASER registers.
397 config CAVIUM_ERRATUM_23154
398 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
401 The gicv3 of ThunderX requires a modified version for
402 reading the IAR status to ensure data synchronization
403 (access to icc_iar1_el1 is not sync'ed before and after).
412 default ARM64_4K_PAGES
414 Page size (translation granule) configuration.
416 config ARM64_4K_PAGES
419 This feature enables 4KB pages support.
421 config ARM64_16K_PAGES
424 The system will use 16KB pages support. AArch32 emulation
425 requires applications compiled with 16K (or a multiple of 16K)
428 config ARM64_64K_PAGES
431 This feature enables 64KB pages support (4KB by default)
432 allowing only two levels of page tables and faster TLB
433 look-up. AArch32 emulation requires applications compiled
434 with 64K aligned segments.
439 prompt "Virtual address space size"
440 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
441 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
442 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
444 Allows choosing one of multiple possible virtual address
445 space sizes. The level of translation table is determined by
446 a combination of page size and virtual address space size.
448 config ARM64_VA_BITS_36
449 bool "36-bit" if EXPERT
450 depends on ARM64_16K_PAGES
452 config ARM64_VA_BITS_39
454 depends on ARM64_4K_PAGES
456 config ARM64_VA_BITS_42
458 depends on ARM64_64K_PAGES
460 config ARM64_VA_BITS_47
462 depends on ARM64_16K_PAGES
464 config ARM64_VA_BITS_48
471 default 36 if ARM64_VA_BITS_36
472 default 39 if ARM64_VA_BITS_39
473 default 42 if ARM64_VA_BITS_42
474 default 47 if ARM64_VA_BITS_47
475 default 48 if ARM64_VA_BITS_48
477 config CPU_BIG_ENDIAN
478 bool "Build big-endian kernel"
480 Say Y if you plan on running a kernel in big-endian mode.
483 bool "Multi-core scheduler support"
485 Multi-core scheduler support improves the CPU scheduler's decision
486 making when dealing with multi-core CPU chips at a cost of slightly
487 increased overhead in some places. If unsure say N here.
490 bool "SMT scheduler support"
492 Improves the CPU scheduler's decision making when dealing with
493 MultiThreading at a cost of slightly increased overhead in some
494 places. If unsure say N here.
497 int "Maximum number of CPUs (2-4096)"
499 # These have to remain sorted largest to smallest
503 bool "Support for hot-pluggable CPUs"
504 select GENERIC_IRQ_MIGRATION
506 Say Y here to experiment with turning CPUs off and on. CPUs
507 can be controlled through /sys/devices/system/cpu.
509 source kernel/Kconfig.preempt
510 source kernel/Kconfig.hz
512 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
515 config ARCH_HAS_HOLES_MEMORYMODEL
516 def_bool y if SPARSEMEM
518 config ARCH_SPARSEMEM_ENABLE
520 select SPARSEMEM_VMEMMAP_ENABLE
522 config ARCH_SPARSEMEM_DEFAULT
523 def_bool ARCH_SPARSEMEM_ENABLE
525 config ARCH_SELECT_MEMORY_MODEL
526 def_bool ARCH_SPARSEMEM_ENABLE
528 config HAVE_ARCH_PFN_VALID
529 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
531 config HW_PERF_EVENTS
535 config SYS_SUPPORTS_HUGETLBFS
538 config ARCH_WANT_HUGE_PMD_SHARE
539 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
541 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
544 config ARCH_HAS_CACHE_LINE_SIZE
550 bool "Enable seccomp to safely compute untrusted bytecode"
552 This kernel feature is useful for number crunching applications
553 that may need to compute untrusted bytecode during their
554 execution. By using pipes or other transports made available to
555 the process as file descriptors supporting the read/write
556 syscalls, it's possible to isolate those applications in
557 their own address space using seccomp. Once seccomp is
558 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
559 and the task is only allowed to execute a few safe syscalls
560 defined by each seccomp mode.
567 bool "Xen guest support on ARM64"
568 depends on ARM64 && OF
571 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
573 config FORCE_MAX_ZONEORDER
575 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
576 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
579 The kernel memory allocator divides physically contiguous memory
580 blocks into "zones", where each zone is a power of two number of
581 pages. This option selects the largest power of two that the kernel
582 keeps in the memory allocator. If you need to allocate very large
583 blocks of physically contiguous memory, then you may need to
586 This config option is actually maximum order plus one. For example,
587 a value of 11 means that the largest free memory block is 2^10 pages.
589 We make sure that we can allocate upto a HugePage size for each configuration.
591 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
593 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
594 4M allocations matching the default size used by generic code.
596 menuconfig ARMV8_DEPRECATED
597 bool "Emulate deprecated/obsolete ARMv8 instructions"
600 Legacy software support may require certain instructions
601 that have been deprecated or obsoleted in the architecture.
603 Enable this config to enable selective emulation of these
611 bool "Emulate SWP/SWPB instructions"
613 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
614 they are always undefined. Say Y here to enable software
615 emulation of these instructions for userspace using LDXR/STXR.
617 In some older versions of glibc [<=2.8] SWP is used during futex
618 trylock() operations with the assumption that the code will not
619 be preempted. This invalid assumption may be more likely to fail
620 with SWP emulation enabled, leading to deadlock of the user
623 NOTE: when accessing uncached shared regions, LDXR/STXR rely
624 on an external transaction monitoring block called a global
625 monitor to maintain update atomicity. If your system does not
626 implement a global monitor, this option can cause programs that
627 perform SWP operations to uncached memory to deadlock.
631 config CP15_BARRIER_EMULATION
632 bool "Emulate CP15 Barrier instructions"
634 The CP15 barrier instructions - CP15ISB, CP15DSB, and
635 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
636 strongly recommended to use the ISB, DSB, and DMB
637 instructions instead.
639 Say Y here to enable software emulation of these
640 instructions for AArch32 userspace code. When this option is
641 enabled, CP15 barrier usage is traced which can help
642 identify software that needs updating.
646 config SETEND_EMULATION
647 bool "Emulate SETEND instruction"
649 The SETEND instruction alters the data-endianness of the
650 AArch32 EL0, and is deprecated in ARMv8.
652 Say Y here to enable software emulation of the instruction
653 for AArch32 userspace code.
655 Note: All the cpus on the system must have mixed endian support at EL0
656 for this feature to be enabled. If a new CPU - which doesn't support mixed
657 endian - is hotplugged in after this feature has been enabled, there could
658 be unexpected results in the applications.
663 menu "ARMv8.1 architectural features"
665 config ARM64_HW_AFDBM
666 bool "Support for hardware updates of the Access and Dirty page flags"
669 The ARMv8.1 architecture extensions introduce support for
670 hardware updates of the access and dirty information in page
671 table entries. When enabled in TCR_EL1 (HA and HD bits) on
672 capable processors, accesses to pages with PTE_AF cleared will
673 set this bit instead of raising an access flag fault.
674 Similarly, writes to read-only pages with the DBM bit set will
675 clear the read-only bit (AP[2]) instead of raising a
678 Kernels built with this configuration option enabled continue
679 to work on pre-ARMv8.1 hardware and the performance impact is
680 minimal. If unsure, say Y.
683 bool "Enable support for Privileged Access Never (PAN)"
686 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
687 prevents the kernel or hypervisor from accessing user-space (EL0)
690 Choosing this option will cause any unprotected (not using
691 copy_to_user et al) memory access to fail with a permission fault.
693 The feature is detected at runtime, and will remain as a 'nop'
694 instruction if the cpu does not implement the feature.
696 config ARM64_LSE_ATOMICS
697 bool "Atomic instructions"
699 As part of the Large System Extensions, ARMv8.1 introduces new
700 atomic instructions that are designed specifically to scale in
703 Say Y here to make use of these instructions for the in-kernel
704 atomic routines. This incurs a small overhead on CPUs that do
705 not support these instructions and requires the kernel to be
706 built with binutils >= 2.25.
711 bool "Enable support for User Access Override (UAO)"
714 User Access Override (UAO; part of the ARMv8.2 Extensions)
715 causes the 'unprivileged' variant of the load/store instructions to
716 be overriden to be privileged.
718 This option changes get_user() and friends to use the 'unprivileged'
719 variant of the load/store instructions. This ensures that user-space
720 really did have access to the supplied memory. When addr_limit is
721 set to kernel memory the UAO bit will be set, allowing privileged
722 access to kernel memory.
724 Choosing this option will cause copy_to_user() et al to use user-space
727 The feature is detected at runtime, the kernel will use the
728 regular load/store instructions if the cpu does not implement the
735 config ARM64_ACPI_PARKING_PROTOCOL
736 bool "Enable support for the ARM64 ACPI parking protocol"
739 Enable support for the ARM64 ACPI parking protocol. If disabled
740 the kernel will not allow booting through the ARM64 ACPI parking
741 protocol even if the corresponding data is present in the ACPI
745 string "Default kernel command string"
748 Provide a set of default command-line options at build time by
749 entering them here. As a minimum, you should specify the the
750 root device (e.g. root=/dev/nfs).
753 bool "Always use the default kernel command string"
755 Always use the default kernel command string, even if the boot
756 loader passes other arguments to the kernel.
757 This is useful if you cannot or don't want to change the
758 command-line options your boot loader passes to the kernel.
764 bool "UEFI runtime support"
765 depends on OF && !CPU_BIG_ENDIAN
768 select EFI_PARAMS_FROM_FDT
769 select EFI_RUNTIME_WRAPPERS
774 This option provides support for runtime services provided
775 by UEFI firmware (such as non-volatile variables, realtime
776 clock, and platform reset). A UEFI stub is also provided to
777 allow the kernel to be booted as an EFI application. This
778 is only useful on systems that have UEFI firmware.
781 bool "Enable support for SMBIOS (DMI) tables"
785 This enables SMBIOS/DMI feature for systems.
787 This option is only useful on systems that have UEFI firmware.
788 However, even with this option, the resultant kernel should
789 continue to boot on existing non-UEFI platforms.
793 menu "Userspace binary formats"
795 source "fs/Kconfig.binfmt"
798 bool "Kernel support for 32-bit EL0"
799 depends on ARM64_4K_PAGES || EXPERT
800 select COMPAT_BINFMT_ELF
802 select OLD_SIGSUSPEND3
803 select COMPAT_OLD_SIGACTION
805 This option enables support for a 32-bit EL0 running under a 64-bit
806 kernel at EL1. AArch32-specific components such as system calls,
807 the user helper functions, VFP support and the ptrace interface are
808 handled appropriately by the kernel.
810 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
811 that you will only be able to execute AArch32 binaries that were compiled
812 with page size aligned segments.
814 If you want to execute 32-bit userspace applications, say Y.
816 config SYSVIPC_COMPAT
818 depends on COMPAT && SYSVIPC
822 menu "Power management options"
824 source "kernel/power/Kconfig"
826 config ARCH_SUSPEND_POSSIBLE
831 menu "CPU Power Management"
833 source "drivers/cpuidle/Kconfig"
835 source "drivers/cpufreq/Kconfig"
841 source "drivers/Kconfig"
843 source "drivers/firmware/Kconfig"
845 source "drivers/acpi/Kconfig"
849 source "arch/arm64/kvm/Kconfig"
851 source "arch/arm64/Kconfig.debug"
853 source "security/Kconfig"
855 source "crypto/Kconfig"
857 source "arch/arm64/crypto/Kconfig"