3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
16 select ARCH_HAS_UBSAN_SANITIZE_ALL
20 select AUDIT_ARCH_COMPAT_GENERIC
21 select ARM_GIC_V2M if PCI_MSI
23 select ARM_GIC_V3_ITS if PCI_MSI
25 select BUILDTIME_EXTABLE_SORT
26 select CLONE_BACKWARDS
28 select CPU_PM if (SUSPEND || CPU_IDLE)
29 select DCACHE_WORD_ACCESS
32 select GENERIC_ALLOCATOR
33 select GENERIC_CLOCKEVENTS
34 select GENERIC_CLOCKEVENTS_BROADCAST
35 select GENERIC_CPU_AUTOPROBE
36 select GENERIC_EARLY_IOREMAP
37 select GENERIC_IDLE_POLL_SETUP
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_SHOW_LEVEL
41 select GENERIC_PCI_IOMAP
42 select GENERIC_SCHED_CLOCK
43 select GENERIC_SMP_IDLE_THREAD
44 select GENERIC_STRNCPY_FROM_USER
45 select GENERIC_STRNLEN_USER
46 select GENERIC_TIME_VSYSCALL
47 select HANDLE_DOMAIN_IRQ
48 select HARDIRQS_SW_RESEND
49 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
50 select HAVE_ARCH_AUDITSYSCALL
51 select HAVE_ARCH_BITREVERSE
52 select HAVE_ARCH_HUGE_VMAP
53 select HAVE_ARCH_JUMP_LABEL
54 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
56 select HAVE_ARCH_MMAP_RND_BITS
57 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
58 select HAVE_ARCH_SECCOMP_FILTER
59 select HAVE_ARCH_TRACEHOOK
61 select HAVE_C_RECORDMCOUNT
62 select HAVE_CC_STACKPROTECTOR
63 select HAVE_CMPXCHG_DOUBLE
64 select HAVE_CMPXCHG_LOCAL
65 select HAVE_DEBUG_BUGVERBOSE
66 select HAVE_DEBUG_KMEMLEAK
67 select HAVE_DMA_API_DEBUG
69 select HAVE_DMA_CONTIGUOUS
70 select HAVE_DYNAMIC_FTRACE
71 select HAVE_EFFICIENT_UNALIGNED_ACCESS
72 select HAVE_FTRACE_MCOUNT_RECORD
73 select HAVE_FUNCTION_TRACER
74 select HAVE_FUNCTION_GRAPH_TRACER
75 select HAVE_GENERIC_DMA_COHERENT
76 select HAVE_HW_BREAKPOINT if PERF_EVENTS
77 select HAVE_IRQ_TIME_ACCOUNTING
79 select HAVE_PATA_PLATFORM
80 select HAVE_PERF_EVENTS
82 select HAVE_PERF_USER_STACK_DUMP
83 select HAVE_RCU_TABLE_FREE
84 select HAVE_SYSCALL_TRACEPOINTS
85 select IOMMU_DMA if IOMMU_SUPPORT
87 select IRQ_FORCED_THREADING
88 select MODULES_USE_ELF_RELA
91 select OF_EARLY_FLATTREE
92 select OF_RESERVED_MEM
93 select PERF_USE_VMALLOC
98 select SYSCTL_EXCEPTION_TRACE
99 select HAVE_CONTEXT_TRACKING
101 ARM 64-bit (AArch64) Linux support.
106 config ARCH_PHYS_ADDR_T_64BIT
112 config ARCH_MMAP_RND_BITS_MIN
113 default 14 if ARM64_64K_PAGES
114 default 16 if ARM64_16K_PAGES
117 # max bits determined by the following formula:
118 # VA_BITS - PAGE_SHIFT - 3
119 config ARCH_MMAP_RND_BITS_MAX
120 default 19 if ARM64_VA_BITS=36
121 default 24 if ARM64_VA_BITS=39
122 default 27 if ARM64_VA_BITS=42
123 default 30 if ARM64_VA_BITS=47
124 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
125 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
126 default 33 if ARM64_VA_BITS=48
127 default 14 if ARM64_64K_PAGES
128 default 16 if ARM64_16K_PAGES
131 config ARCH_MMAP_RND_COMPAT_BITS_MIN
132 default 7 if ARM64_64K_PAGES
133 default 9 if ARM64_16K_PAGES
136 config ARCH_MMAP_RND_COMPAT_BITS_MAX
142 config ILLEGAL_POINTER_VALUE
144 default 0xdead000000000000
146 config STACKTRACE_SUPPORT
149 config ILLEGAL_POINTER_VALUE
151 default 0xdead000000000000
153 config LOCKDEP_SUPPORT
156 config TRACE_IRQFLAGS_SUPPORT
159 config RWSEM_XCHGADD_ALGORITHM
166 config GENERIC_BUG_RELATIVE_POINTERS
168 depends on GENERIC_BUG
170 config GENERIC_HWEIGHT
176 config GENERIC_CALIBRATE_DELAY
182 config HAVE_GENERIC_RCU_GUP
185 config ARCH_DMA_ADDR_T_64BIT
188 config NEED_DMA_MAP_STATE
191 config NEED_SG_DMA_LENGTH
203 config KERNEL_MODE_NEON
206 config FIX_EARLYCON_MEM
209 config PGTABLE_LEVELS
211 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
212 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
213 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
214 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
215 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
216 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
218 source "init/Kconfig"
220 source "kernel/Kconfig.freezer"
222 source "arch/arm64/Kconfig.platforms"
229 This feature enables support for PCI bus system. If you say Y
230 here, the kernel will include drivers and infrastructure code
231 to support PCI bus devices.
236 config PCI_DOMAINS_GENERIC
242 source "drivers/pci/Kconfig"
243 source "drivers/pci/pcie/Kconfig"
244 source "drivers/pci/hotplug/Kconfig"
248 menu "Kernel Features"
250 menu "ARM errata workarounds via the alternatives framework"
252 config ARM64_ERRATUM_826319
253 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
256 This option adds an alternative code sequence to work around ARM
257 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
258 AXI master interface and an L2 cache.
260 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
261 and is unable to accept a certain write via this interface, it will
262 not progress on read data presented on the read data channel and the
265 The workaround promotes data cache clean instructions to
266 data cache clean-and-invalidate.
267 Please note that this does not necessarily enable the workaround,
268 as it depends on the alternative framework, which will only patch
269 the kernel if an affected CPU is detected.
273 config ARM64_ERRATUM_827319
274 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
277 This option adds an alternative code sequence to work around ARM
278 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
279 master interface and an L2 cache.
281 Under certain conditions this erratum can cause a clean line eviction
282 to occur at the same time as another transaction to the same address
283 on the AMBA 5 CHI interface, which can cause data corruption if the
284 interconnect reorders the two transactions.
286 The workaround promotes data cache clean instructions to
287 data cache clean-and-invalidate.
288 Please note that this does not necessarily enable the workaround,
289 as it depends on the alternative framework, which will only patch
290 the kernel if an affected CPU is detected.
294 config ARM64_ERRATUM_824069
295 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
298 This option adds an alternative code sequence to work around ARM
299 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
300 to a coherent interconnect.
302 If a Cortex-A53 processor is executing a store or prefetch for
303 write instruction at the same time as a processor in another
304 cluster is executing a cache maintenance operation to the same
305 address, then this erratum might cause a clean cache line to be
306 incorrectly marked as dirty.
308 The workaround promotes data cache clean instructions to
309 data cache clean-and-invalidate.
310 Please note that this option does not necessarily enable the
311 workaround, as it depends on the alternative framework, which will
312 only patch the kernel if an affected CPU is detected.
316 config ARM64_ERRATUM_819472
317 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
320 This option adds an alternative code sequence to work around ARM
321 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
322 present when it is connected to a coherent interconnect.
324 If the processor is executing a load and store exclusive sequence at
325 the same time as a processor in another cluster is executing a cache
326 maintenance operation to the same address, then this erratum might
327 cause data corruption.
329 The workaround promotes data cache clean instructions to
330 data cache clean-and-invalidate.
331 Please note that this does not necessarily enable the workaround,
332 as it depends on the alternative framework, which will only patch
333 the kernel if an affected CPU is detected.
337 config ARM64_ERRATUM_832075
338 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
341 This option adds an alternative code sequence to work around ARM
342 erratum 832075 on Cortex-A57 parts up to r1p2.
344 Affected Cortex-A57 parts might deadlock when exclusive load/store
345 instructions to Write-Back memory are mixed with Device loads.
347 The workaround is to promote device loads to use Load-Acquire
349 Please note that this does not necessarily enable the workaround,
350 as it depends on the alternative framework, which will only patch
351 the kernel if an affected CPU is detected.
355 config ARM64_ERRATUM_834220
356 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
360 This option adds an alternative code sequence to work around ARM
361 erratum 834220 on Cortex-A57 parts up to r1p2.
363 Affected Cortex-A57 parts might report a Stage 2 translation
364 fault as the result of a Stage 1 fault for load crossing a
365 page boundary when there is a permission or device memory
366 alignment fault at Stage 1 and a translation fault at Stage 2.
368 The workaround is to verify that the Stage 1 translation
369 doesn't generate a fault before handling the Stage 2 fault.
370 Please note that this does not necessarily enable the workaround,
371 as it depends on the alternative framework, which will only patch
372 the kernel if an affected CPU is detected.
376 config ARM64_ERRATUM_845719
377 bool "Cortex-A53: 845719: a load might read incorrect data"
381 This option adds an alternative code sequence to work around ARM
382 erratum 845719 on Cortex-A53 parts up to r0p4.
384 When running a compat (AArch32) userspace on an affected Cortex-A53
385 part, a load at EL0 from a virtual address that matches the bottom 32
386 bits of the virtual address used by a recent load at (AArch64) EL1
387 might return incorrect data.
389 The workaround is to write the contextidr_el1 register on exception
390 return to a 32-bit task.
391 Please note that this does not necessarily enable the workaround,
392 as it depends on the alternative framework, which will only patch
393 the kernel if an affected CPU is detected.
397 config ARM64_ERRATUM_843419
398 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
401 select ARM64_MODULE_CMODEL_LARGE
403 This option builds kernel modules using the large memory model in
404 order to avoid the use of the ADRP instruction, which can cause
405 a subsequent memory access to use an incorrect address on Cortex-A53
408 Note that the kernel itself must be linked with a version of ld
409 which fixes potentially affected ADRP instructions through the
414 config CAVIUM_ERRATUM_22375
415 bool "Cavium erratum 22375, 24313"
418 Enable workaround for erratum 22375, 24313.
420 This implements two gicv3-its errata workarounds for ThunderX. Both
421 with small impact affecting only ITS table allocation.
423 erratum 22375: only alloc 8MB table size
424 erratum 24313: ignore memory access type
426 The fixes are in ITS initialization and basically ignore memory access
427 type and table size provided by the TYPER and BASER registers.
431 config CAVIUM_ERRATUM_23154
432 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
435 The gicv3 of ThunderX requires a modified version for
436 reading the IAR status to ensure data synchronization
437 (access to icc_iar1_el1 is not sync'ed before and after).
446 default ARM64_4K_PAGES
448 Page size (translation granule) configuration.
450 config ARM64_4K_PAGES
453 This feature enables 4KB pages support.
455 config ARM64_16K_PAGES
458 The system will use 16KB pages support. AArch32 emulation
459 requires applications compiled with 16K (or a multiple of 16K)
462 config ARM64_64K_PAGES
465 This feature enables 64KB pages support (4KB by default)
466 allowing only two levels of page tables and faster TLB
467 look-up. AArch32 emulation requires applications compiled
468 with 64K aligned segments.
473 prompt "Virtual address space size"
474 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
475 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
476 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
478 Allows choosing one of multiple possible virtual address
479 space sizes. The level of translation table is determined by
480 a combination of page size and virtual address space size.
482 config ARM64_VA_BITS_36
483 bool "36-bit" if EXPERT
484 depends on ARM64_16K_PAGES
486 config ARM64_VA_BITS_39
488 depends on ARM64_4K_PAGES
490 config ARM64_VA_BITS_42
492 depends on ARM64_64K_PAGES
494 config ARM64_VA_BITS_47
496 depends on ARM64_16K_PAGES
498 config ARM64_VA_BITS_48
505 default 36 if ARM64_VA_BITS_36
506 default 39 if ARM64_VA_BITS_39
507 default 42 if ARM64_VA_BITS_42
508 default 47 if ARM64_VA_BITS_47
509 default 48 if ARM64_VA_BITS_48
511 config CPU_BIG_ENDIAN
512 bool "Build big-endian kernel"
514 Say Y if you plan on running a kernel in big-endian mode.
517 bool "Multi-core scheduler support"
519 Multi-core scheduler support improves the CPU scheduler's decision
520 making when dealing with multi-core CPU chips at a cost of slightly
521 increased overhead in some places. If unsure say N here.
524 bool "SMT scheduler support"
526 Improves the CPU scheduler's decision making when dealing with
527 MultiThreading at a cost of slightly increased overhead in some
528 places. If unsure say N here.
531 int "Maximum number of CPUs (2-4096)"
533 # These have to remain sorted largest to smallest
537 bool "Support for hot-pluggable CPUs"
538 select GENERIC_IRQ_MIGRATION
540 Say Y here to experiment with turning CPUs off and on. CPUs
541 can be controlled through /sys/devices/system/cpu.
543 source kernel/Kconfig.preempt
544 source kernel/Kconfig.hz
546 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
549 config ARCH_HAS_HOLES_MEMORYMODEL
550 def_bool y if SPARSEMEM
552 config ARCH_SPARSEMEM_ENABLE
554 select SPARSEMEM_VMEMMAP_ENABLE
556 config ARCH_SPARSEMEM_DEFAULT
557 def_bool ARCH_SPARSEMEM_ENABLE
559 config ARCH_SELECT_MEMORY_MODEL
560 def_bool ARCH_SPARSEMEM_ENABLE
562 config HAVE_ARCH_PFN_VALID
563 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
565 config HW_PERF_EVENTS
569 config SYS_SUPPORTS_HUGETLBFS
572 config ARCH_WANT_HUGE_PMD_SHARE
573 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
575 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
578 config ARCH_HAS_CACHE_LINE_SIZE
584 bool "Enable seccomp to safely compute untrusted bytecode"
586 This kernel feature is useful for number crunching applications
587 that may need to compute untrusted bytecode during their
588 execution. By using pipes or other transports made available to
589 the process as file descriptors supporting the read/write
590 syscalls, it's possible to isolate those applications in
591 their own address space using seccomp. Once seccomp is
592 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
593 and the task is only allowed to execute a few safe syscalls
594 defined by each seccomp mode.
601 bool "Xen guest support on ARM64"
602 depends on ARM64 && OF
605 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
607 config FORCE_MAX_ZONEORDER
609 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
610 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
613 The kernel memory allocator divides physically contiguous memory
614 blocks into "zones", where each zone is a power of two number of
615 pages. This option selects the largest power of two that the kernel
616 keeps in the memory allocator. If you need to allocate very large
617 blocks of physically contiguous memory, then you may need to
620 This config option is actually maximum order plus one. For example,
621 a value of 11 means that the largest free memory block is 2^10 pages.
623 We make sure that we can allocate upto a HugePage size for each configuration.
625 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
627 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
628 4M allocations matching the default size used by generic code.
630 menuconfig ARMV8_DEPRECATED
631 bool "Emulate deprecated/obsolete ARMv8 instructions"
634 Legacy software support may require certain instructions
635 that have been deprecated or obsoleted in the architecture.
637 Enable this config to enable selective emulation of these
645 bool "Emulate SWP/SWPB instructions"
647 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
648 they are always undefined. Say Y here to enable software
649 emulation of these instructions for userspace using LDXR/STXR.
651 In some older versions of glibc [<=2.8] SWP is used during futex
652 trylock() operations with the assumption that the code will not
653 be preempted. This invalid assumption may be more likely to fail
654 with SWP emulation enabled, leading to deadlock of the user
657 NOTE: when accessing uncached shared regions, LDXR/STXR rely
658 on an external transaction monitoring block called a global
659 monitor to maintain update atomicity. If your system does not
660 implement a global monitor, this option can cause programs that
661 perform SWP operations to uncached memory to deadlock.
665 config CP15_BARRIER_EMULATION
666 bool "Emulate CP15 Barrier instructions"
668 The CP15 barrier instructions - CP15ISB, CP15DSB, and
669 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
670 strongly recommended to use the ISB, DSB, and DMB
671 instructions instead.
673 Say Y here to enable software emulation of these
674 instructions for AArch32 userspace code. When this option is
675 enabled, CP15 barrier usage is traced which can help
676 identify software that needs updating.
680 config SETEND_EMULATION
681 bool "Emulate SETEND instruction"
683 The SETEND instruction alters the data-endianness of the
684 AArch32 EL0, and is deprecated in ARMv8.
686 Say Y here to enable software emulation of the instruction
687 for AArch32 userspace code.
689 Note: All the cpus on the system must have mixed endian support at EL0
690 for this feature to be enabled. If a new CPU - which doesn't support mixed
691 endian - is hotplugged in after this feature has been enabled, there could
692 be unexpected results in the applications.
697 menu "ARMv8.1 architectural features"
699 config ARM64_HW_AFDBM
700 bool "Support for hardware updates of the Access and Dirty page flags"
703 The ARMv8.1 architecture extensions introduce support for
704 hardware updates of the access and dirty information in page
705 table entries. When enabled in TCR_EL1 (HA and HD bits) on
706 capable processors, accesses to pages with PTE_AF cleared will
707 set this bit instead of raising an access flag fault.
708 Similarly, writes to read-only pages with the DBM bit set will
709 clear the read-only bit (AP[2]) instead of raising a
712 Kernels built with this configuration option enabled continue
713 to work on pre-ARMv8.1 hardware and the performance impact is
714 minimal. If unsure, say Y.
717 bool "Enable support for Privileged Access Never (PAN)"
720 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
721 prevents the kernel or hypervisor from accessing user-space (EL0)
724 Choosing this option will cause any unprotected (not using
725 copy_to_user et al) memory access to fail with a permission fault.
727 The feature is detected at runtime, and will remain as a 'nop'
728 instruction if the cpu does not implement the feature.
730 config ARM64_LSE_ATOMICS
731 bool "Atomic instructions"
733 As part of the Large System Extensions, ARMv8.1 introduces new
734 atomic instructions that are designed specifically to scale in
737 Say Y here to make use of these instructions for the in-kernel
738 atomic routines. This incurs a small overhead on CPUs that do
739 not support these instructions and requires the kernel to be
740 built with binutils >= 2.25.
745 bool "Enable support for User Access Override (UAO)"
748 User Access Override (UAO; part of the ARMv8.2 Extensions)
749 causes the 'unprivileged' variant of the load/store instructions to
750 be overriden to be privileged.
752 This option changes get_user() and friends to use the 'unprivileged'
753 variant of the load/store instructions. This ensures that user-space
754 really did have access to the supplied memory. When addr_limit is
755 set to kernel memory the UAO bit will be set, allowing privileged
756 access to kernel memory.
758 Choosing this option will cause copy_to_user() et al to use user-space
761 The feature is detected at runtime, the kernel will use the
762 regular load/store instructions if the cpu does not implement the
765 config ARM64_MODULE_CMODEL_LARGE
768 config ARM64_MODULE_PLTS
770 select ARM64_MODULE_CMODEL_LARGE
771 select HAVE_MOD_ARCH_SPECIFIC
776 This builds the kernel as a Position Independent Executable (PIE),
777 which retains all relocation metadata required to relocate the
778 kernel binary at runtime to a different virtual address than the
779 address it was linked at.
780 Since AArch64 uses the RELA relocation format, this requires a
781 relocation pass at runtime even if the kernel is loaded at the
782 same address it was linked at.
784 config RANDOMIZE_BASE
785 bool "Randomize the address of the kernel image"
786 select ARM64_MODULE_PLTS
789 Randomizes the virtual address at which the kernel image is
790 loaded, as a security feature that deters exploit attempts
791 relying on knowledge of the location of kernel internals.
793 It is the bootloader's job to provide entropy, by passing a
794 random u64 value in /chosen/kaslr-seed at kernel entry.
796 When booting via the UEFI stub, it will invoke the firmware's
797 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
798 to the kernel proper. In addition, it will randomise the physical
799 location of the kernel Image as well.
803 config RANDOMIZE_MODULE_REGION_FULL
804 bool "Randomize the module region independently from the core kernel"
805 depends on RANDOMIZE_BASE
808 Randomizes the location of the module region without considering the
809 location of the core kernel. This way, it is impossible for modules
810 to leak information about the location of core kernel data structures
811 but it does imply that function calls between modules and the core
812 kernel will need to be resolved via veneers in the module PLT.
814 When this option is not set, the module region will be randomized over
815 a limited range that contains the [_stext, _etext] interval of the
816 core kernel, so branch relocations are always in range.
822 config ARM64_ACPI_PARKING_PROTOCOL
823 bool "Enable support for the ARM64 ACPI parking protocol"
826 Enable support for the ARM64 ACPI parking protocol. If disabled
827 the kernel will not allow booting through the ARM64 ACPI parking
828 protocol even if the corresponding data is present in the ACPI
832 string "Default kernel command string"
835 Provide a set of default command-line options at build time by
836 entering them here. As a minimum, you should specify the the
837 root device (e.g. root=/dev/nfs).
840 prompt "Kernel command line type" if CMDLINE != ""
841 default CMDLINE_FROM_BOOTLOADER
843 config CMDLINE_FROM_BOOTLOADER
844 bool "Use bootloader kernel arguments if available"
846 Uses the command-line options passed by the boot loader. If
847 the boot loader doesn't provide any, the default kernel command
848 string provided in CMDLINE will be used.
850 config CMDLINE_EXTEND
851 bool "Extend bootloader kernel arguments"
853 The command-line arguments provided by the boot loader will be
854 appended to the default kernel command string.
857 bool "Always use the default kernel command string"
859 Always use the default kernel command string, even if the boot
860 loader passes other arguments to the kernel.
861 This is useful if you cannot or don't want to change the
862 command-line options your boot loader passes to the kernel.
869 bool "UEFI runtime support"
870 depends on OF && !CPU_BIG_ENDIAN
873 select EFI_PARAMS_FROM_FDT
874 select EFI_RUNTIME_WRAPPERS
879 This option provides support for runtime services provided
880 by UEFI firmware (such as non-volatile variables, realtime
881 clock, and platform reset). A UEFI stub is also provided to
882 allow the kernel to be booted as an EFI application. This
883 is only useful on systems that have UEFI firmware.
886 bool "Enable support for SMBIOS (DMI) tables"
890 This enables SMBIOS/DMI feature for systems.
892 This option is only useful on systems that have UEFI firmware.
893 However, even with this option, the resultant kernel should
894 continue to boot on existing non-UEFI platforms.
896 config BUILD_ARM64_APPENDED_DTB_IMAGE
897 bool "Build a concatenated Image.gz/dtb by default"
900 Enabling this option will cause a concatenated Image.gz and list of
901 DTBs to be built by default (instead of a standalone Image.gz.)
902 The image will built in arch/arm64/boot/Image.gz-dtb
904 config BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES
905 string "Default dtb names"
906 depends on BUILD_ARM64_APPENDED_DTB_IMAGE
908 Space separated list of names of dtbs to append when
909 building a concatenated Image.gz-dtb.
913 menu "Userspace binary formats"
915 source "fs/Kconfig.binfmt"
918 bool "Kernel support for 32-bit EL0"
919 depends on ARM64_4K_PAGES || EXPERT
920 select COMPAT_BINFMT_ELF
922 select OLD_SIGSUSPEND3
923 select COMPAT_OLD_SIGACTION
925 This option enables support for a 32-bit EL0 running under a 64-bit
926 kernel at EL1. AArch32-specific components such as system calls,
927 the user helper functions, VFP support and the ptrace interface are
928 handled appropriately by the kernel.
930 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
931 that you will only be able to execute AArch32 binaries that were compiled
932 with page size aligned segments.
934 If you want to execute 32-bit userspace applications, say Y.
936 config SYSVIPC_COMPAT
938 depends on COMPAT && SYSVIPC
942 menu "Power management options"
944 source "kernel/power/Kconfig"
946 config ARCH_SUSPEND_POSSIBLE
951 menu "CPU Power Management"
953 source "drivers/cpuidle/Kconfig"
955 source "drivers/cpufreq/Kconfig"
961 source "drivers/Kconfig"
963 source "drivers/firmware/Kconfig"
965 source "drivers/acpi/Kconfig"
969 source "arch/arm64/kvm/Kconfig"
971 source "arch/arm64/Kconfig.debug"
973 source "security/Kconfig"
975 source "crypto/Kconfig"
977 source "arch/arm64/crypto/Kconfig"