3 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_SG_CHAIN
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_USE_CMPXCHG_LOCKREF
8 select ARCH_SUPPORTS_ATOMIC_RMW
9 select ARCH_WANT_OPTIONAL_GPIOLIB
10 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
11 select ARCH_WANT_FRAME_POINTERS
15 select AUDIT_ARCH_COMPAT_GENERIC
17 select BUILDTIME_EXTABLE_SORT
18 select CLONE_BACKWARDS
20 select CPU_PM if (SUSPEND || CPU_IDLE)
21 select DCACHE_WORD_ACCESS
22 select GENERIC_ALLOCATOR
23 select GENERIC_CLOCKEVENTS
24 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
25 select GENERIC_CPU_AUTOPROBE
26 select GENERIC_EARLY_IOREMAP
27 select GENERIC_IRQ_PROBE
28 select GENERIC_IRQ_SHOW
29 select GENERIC_PCI_IOMAP
30 select GENERIC_SCHED_CLOCK
31 select GENERIC_SMP_IDLE_THREAD
32 select GENERIC_STRNCPY_FROM_USER
33 select GENERIC_STRNLEN_USER
34 select GENERIC_TIME_VSYSCALL
35 select HANDLE_DOMAIN_IRQ
36 select HARDIRQS_SW_RESEND
37 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
38 select HAVE_ARCH_AUDITSYSCALL
39 select HAVE_ARCH_JUMP_LABEL
41 select HAVE_ARCH_SECCOMP_FILTER
42 select HAVE_ARCH_TRACEHOOK
44 select HAVE_C_RECORDMCOUNT
45 select HAVE_CC_STACKPROTECTOR
46 select HAVE_CMPXCHG_DOUBLE
47 select HAVE_DEBUG_BUGVERBOSE
48 select HAVE_DEBUG_KMEMLEAK
49 select HAVE_DMA_API_DEBUG
51 select HAVE_DMA_CONTIGUOUS
52 select HAVE_DYNAMIC_FTRACE
53 select HAVE_EFFICIENT_UNALIGNED_ACCESS
54 select HAVE_FTRACE_MCOUNT_RECORD
55 select HAVE_FUNCTION_TRACER
56 select HAVE_FUNCTION_GRAPH_TRACER
57 select HAVE_GENERIC_DMA_COHERENT
58 select HAVE_HW_BREAKPOINT if PERF_EVENTS
60 select HAVE_PATA_PLATFORM
61 select HAVE_PERF_EVENTS
63 select HAVE_PERF_USER_STACK_DUMP
64 select HAVE_RCU_TABLE_FREE
65 select HAVE_SYSCALL_TRACEPOINTS
67 select MODULES_USE_ELF_RELA
70 select OF_EARLY_FLATTREE
71 select OF_RESERVED_MEM
72 select PERF_USE_VMALLOC
77 select SYSCTL_EXCEPTION_TRACE
78 select HAVE_CONTEXT_TRACKING
80 ARM 64-bit (AArch64) Linux support.
85 config ARCH_PHYS_ADDR_T_64BIT
94 config STACKTRACE_SUPPORT
97 config LOCKDEP_SUPPORT
100 config TRACE_IRQFLAGS_SUPPORT
103 config RWSEM_XCHGADD_ALGORITHM
106 config GENERIC_HWEIGHT
112 config GENERIC_CALIBRATE_DELAY
118 config HAVE_GENERIC_RCU_GUP
121 config ARCH_DMA_ADDR_T_64BIT
124 config NEED_DMA_MAP_STATE
127 config NEED_SG_DMA_LENGTH
136 config KERNEL_MODE_NEON
139 config FIX_EARLYCON_MEM
142 source "init/Kconfig"
144 source "kernel/Kconfig.freezer"
146 menu "Platform selection"
149 bool "AMD Seattle SoC Family"
151 This enables support for AMD Seattle SOC Family
154 bool "Cavium Inc. Thunder SoC Family"
156 This enables support for Cavium's Thunder Family of SoCs.
159 bool "ARMv8 software model (Versatile Express)"
160 select ARCH_REQUIRE_GPIOLIB
161 select COMMON_CLK_VERSATILE
162 select POWER_RESET_VEXPRESS
163 select VEXPRESS_CONFIG
165 This enables support for the ARMv8 software model (Versatile
169 bool "AppliedMicro X-Gene SOC Family"
171 This enables support for AppliedMicro X-Gene SOC Family
180 This feature enables support for PCI bus system. If you say Y
181 here, the kernel will include drivers and infrastructure code
182 to support PCI bus devices.
187 config PCI_DOMAINS_GENERIC
193 source "drivers/pci/Kconfig"
194 source "drivers/pci/pcie/Kconfig"
195 source "drivers/pci/hotplug/Kconfig"
199 menu "Kernel Features"
201 menu "ARM errata workarounds via the alternatives framework"
203 config ARM64_ERRATUM_826319
204 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
207 This option adds an alternative code sequence to work around ARM
208 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
209 AXI master interface and an L2 cache.
211 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
212 and is unable to accept a certain write via this interface, it will
213 not progress on read data presented on the read data channel and the
216 The workaround promotes data cache clean instructions to
217 data cache clean-and-invalidate.
218 Please note that this does not necessarily enable the workaround,
219 as it depends on the alternative framework, which will only patch
220 the kernel if an affected CPU is detected.
224 config ARM64_ERRATUM_827319
225 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
228 This option adds an alternative code sequence to work around ARM
229 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
230 master interface and an L2 cache.
232 Under certain conditions this erratum can cause a clean line eviction
233 to occur at the same time as another transaction to the same address
234 on the AMBA 5 CHI interface, which can cause data corruption if the
235 interconnect reorders the two transactions.
237 The workaround promotes data cache clean instructions to
238 data cache clean-and-invalidate.
239 Please note that this does not necessarily enable the workaround,
240 as it depends on the alternative framework, which will only patch
241 the kernel if an affected CPU is detected.
245 config ARM64_ERRATUM_824069
246 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
249 This option adds an alternative code sequence to work around ARM
250 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
251 to a coherent interconnect.
253 If a Cortex-A53 processor is executing a store or prefetch for
254 write instruction at the same time as a processor in another
255 cluster is executing a cache maintenance operation to the same
256 address, then this erratum might cause a clean cache line to be
257 incorrectly marked as dirty.
259 The workaround promotes data cache clean instructions to
260 data cache clean-and-invalidate.
261 Please note that this option does not necessarily enable the
262 workaround, as it depends on the alternative framework, which will
263 only patch the kernel if an affected CPU is detected.
267 config ARM64_ERRATUM_819472
268 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
271 This option adds an alternative code sequence to work around ARM
272 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
273 present when it is connected to a coherent interconnect.
275 If the processor is executing a load and store exclusive sequence at
276 the same time as a processor in another cluster is executing a cache
277 maintenance operation to the same address, then this erratum might
278 cause data corruption.
280 The workaround promotes data cache clean instructions to
281 data cache clean-and-invalidate.
282 Please note that this does not necessarily enable the workaround,
283 as it depends on the alternative framework, which will only patch
284 the kernel if an affected CPU is detected.
288 config ARM64_ERRATUM_832075
289 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
292 This option adds an alternative code sequence to work around ARM
293 erratum 832075 on Cortex-A57 parts up to r1p2.
295 Affected Cortex-A57 parts might deadlock when exclusive load/store
296 instructions to Write-Back memory are mixed with Device loads.
298 The workaround is to promote device loads to use Load-Acquire
300 Please note that this does not necessarily enable the workaround,
301 as it depends on the alternative framework, which will only patch
302 the kernel if an affected CPU is detected.
311 default ARM64_4K_PAGES
313 Page size (translation granule) configuration.
315 config ARM64_4K_PAGES
318 This feature enables 4KB pages support.
320 config ARM64_64K_PAGES
323 This feature enables 64KB pages support (4KB by default)
324 allowing only two levels of page tables and faster TLB
325 look-up. AArch32 emulation is not available when this feature
331 prompt "Virtual address space size"
332 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
333 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
335 Allows choosing one of multiple possible virtual address
336 space sizes. The level of translation table is determined by
337 a combination of page size and virtual address space size.
339 config ARM64_VA_BITS_39
341 depends on ARM64_4K_PAGES
343 config ARM64_VA_BITS_42
345 depends on ARM64_64K_PAGES
347 config ARM64_VA_BITS_48
355 default 39 if ARM64_VA_BITS_39
356 default 42 if ARM64_VA_BITS_42
357 default 48 if ARM64_VA_BITS_48
359 config ARM64_PGTABLE_LEVELS
361 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
362 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
363 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
364 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
366 config CPU_BIG_ENDIAN
367 bool "Build big-endian kernel"
369 Say Y if you plan on running a kernel in big-endian mode.
372 bool "Symmetric Multi-Processing"
374 This enables support for systems with more than one CPU. If
375 you say N here, the kernel will run on single and
376 multiprocessor machines, but will use only one CPU of a
377 multiprocessor machine. If you say Y here, the kernel will run
378 on many, but not all, single processor machines. On a single
379 processor machine, the kernel will run faster if you say N
382 If you don't know what to do here, say N.
385 bool "Multi-core scheduler support"
388 Multi-core scheduler support improves the CPU scheduler's decision
389 making when dealing with multi-core CPU chips at a cost of slightly
390 increased overhead in some places. If unsure say N here.
393 bool "SMT scheduler support"
396 Improves the CPU scheduler's decision making when dealing with
397 MultiThreading at a cost of slightly increased overhead in some
398 places. If unsure say N here.
401 int "Maximum number of CPUs (2-64)"
404 # These have to remain sorted largest to smallest
408 bool "Support for hot-pluggable CPUs"
411 Say Y here to experiment with turning CPUs off and on. CPUs
412 can be controlled through /sys/devices/system/cpu.
414 source kernel/Kconfig.preempt
420 config ARCH_HAS_HOLES_MEMORYMODEL
421 def_bool y if SPARSEMEM
423 config ARCH_SPARSEMEM_ENABLE
425 select SPARSEMEM_VMEMMAP_ENABLE
427 config ARCH_SPARSEMEM_DEFAULT
428 def_bool ARCH_SPARSEMEM_ENABLE
430 config ARCH_SELECT_MEMORY_MODEL
431 def_bool ARCH_SPARSEMEM_ENABLE
433 config HAVE_ARCH_PFN_VALID
434 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
436 config HW_PERF_EVENTS
437 bool "Enable hardware performance counter support for perf events"
438 depends on PERF_EVENTS
441 Enable hardware performance counter support for perf events. If
442 disabled, perf events will use software events only.
444 config SYS_SUPPORTS_HUGETLBFS
447 config ARCH_WANT_GENERAL_HUGETLB
450 config ARCH_WANT_HUGE_PMD_SHARE
451 def_bool y if !ARM64_64K_PAGES
453 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
456 config ARCH_HAS_CACHE_LINE_SIZE
462 bool "Enable seccomp to safely compute untrusted bytecode"
464 This kernel feature is useful for number crunching applications
465 that may need to compute untrusted bytecode during their
466 execution. By using pipes or other transports made available to
467 the process as file descriptors supporting the read/write
468 syscalls, it's possible to isolate those applications in
469 their own address space using seccomp. Once seccomp is
470 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
471 and the task is only allowed to execute a few safe syscalls
472 defined by each seccomp mode.
479 bool "Xen guest support on ARM64"
480 depends on ARM64 && OF
483 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
485 config FORCE_MAX_ZONEORDER
487 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
490 menuconfig ARMV8_DEPRECATED
491 bool "Emulate deprecated/obsolete ARMv8 instructions"
494 Legacy software support may require certain instructions
495 that have been deprecated or obsoleted in the architecture.
497 Enable this config to enable selective emulation of these
505 bool "Emulate SWP/SWPB instructions"
507 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
508 they are always undefined. Say Y here to enable software
509 emulation of these instructions for userspace using LDXR/STXR.
511 In some older versions of glibc [<=2.8] SWP is used during futex
512 trylock() operations with the assumption that the code will not
513 be preempted. This invalid assumption may be more likely to fail
514 with SWP emulation enabled, leading to deadlock of the user
517 NOTE: when accessing uncached shared regions, LDXR/STXR rely
518 on an external transaction monitoring block called a global
519 monitor to maintain update atomicity. If your system does not
520 implement a global monitor, this option can cause programs that
521 perform SWP operations to uncached memory to deadlock.
525 config CP15_BARRIER_EMULATION
526 bool "Emulate CP15 Barrier instructions"
528 The CP15 barrier instructions - CP15ISB, CP15DSB, and
529 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
530 strongly recommended to use the ISB, DSB, and DMB
531 instructions instead.
533 Say Y here to enable software emulation of these
534 instructions for AArch32 userspace code. When this option is
535 enabled, CP15 barrier usage is traced which can help
536 identify software that needs updating.
547 string "Default kernel command string"
550 Provide a set of default command-line options at build time by
551 entering them here. As a minimum, you should specify the the
552 root device (e.g. root=/dev/nfs).
555 bool "Always use the default kernel command string"
557 Always use the default kernel command string, even if the boot
558 loader passes other arguments to the kernel.
559 This is useful if you cannot or don't want to change the
560 command-line options your boot loader passes to the kernel.
566 bool "UEFI runtime support"
567 depends on OF && !CPU_BIG_ENDIAN
570 select EFI_PARAMS_FROM_FDT
571 select EFI_RUNTIME_WRAPPERS
576 This option provides support for runtime services provided
577 by UEFI firmware (such as non-volatile variables, realtime
578 clock, and platform reset). A UEFI stub is also provided to
579 allow the kernel to be booted as an EFI application. This
580 is only useful on systems that have UEFI firmware.
583 bool "Enable support for SMBIOS (DMI) tables"
587 This enables SMBIOS/DMI feature for systems.
589 This option is only useful on systems that have UEFI firmware.
590 However, even with this option, the resultant kernel should
591 continue to boot on existing non-UEFI platforms.
595 menu "Userspace binary formats"
597 source "fs/Kconfig.binfmt"
600 bool "Kernel support for 32-bit EL0"
601 depends on !ARM64_64K_PAGES
602 select COMPAT_BINFMT_ELF
604 select OLD_SIGSUSPEND3
605 select COMPAT_OLD_SIGACTION
607 This option enables support for a 32-bit EL0 running under a 64-bit
608 kernel at EL1. AArch32-specific components such as system calls,
609 the user helper functions, VFP support and the ptrace interface are
610 handled appropriately by the kernel.
612 If you want to execute 32-bit userspace applications, say Y.
614 config SYSVIPC_COMPAT
616 depends on COMPAT && SYSVIPC
620 menu "Power management options"
622 source "kernel/power/Kconfig"
624 config ARCH_SUSPEND_POSSIBLE
627 config ARM64_CPU_SUSPEND
632 menu "CPU Power Management"
634 source "drivers/cpuidle/Kconfig"
636 source "drivers/cpufreq/Kconfig"
642 source "drivers/Kconfig"
644 source "drivers/firmware/Kconfig"
648 source "arch/arm64/kvm/Kconfig"
650 source "arch/arm64/Kconfig.debug"
652 source "security/Kconfig"
654 source "crypto/Kconfig"
656 source "arch/arm64/crypto/Kconfig"