3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
19 select AUDIT_ARCH_COMPAT_GENERIC
20 select ARM_GIC_V2M if PCI_MSI
22 select ARM_GIC_V3_ITS if PCI_MSI
24 select BUILDTIME_EXTABLE_SORT
25 select CLONE_BACKWARDS
27 select CPU_PM if (SUSPEND || CPU_IDLE)
28 select DCACHE_WORD_ACCESS
30 select GENERIC_ALLOCATOR
31 select GENERIC_CLOCKEVENTS
32 select GENERIC_CLOCKEVENTS_BROADCAST
33 select GENERIC_CPU_AUTOPROBE
34 select GENERIC_EARLY_IOREMAP
35 select GENERIC_IDLE_POLL_SETUP
36 select GENERIC_IRQ_PROBE
37 select GENERIC_IRQ_SHOW
38 select GENERIC_IRQ_SHOW_LEVEL
39 select GENERIC_PCI_IOMAP
40 select GENERIC_SCHED_CLOCK
41 select GENERIC_SMP_IDLE_THREAD
42 select GENERIC_STRNCPY_FROM_USER
43 select GENERIC_STRNLEN_USER
44 select GENERIC_TIME_VSYSCALL
45 select HANDLE_DOMAIN_IRQ
46 select HARDIRQS_SW_RESEND
47 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
48 select HAVE_ARCH_AUDITSYSCALL
49 select HAVE_ARCH_BITREVERSE
50 select HAVE_ARCH_JUMP_LABEL
51 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP
53 select HAVE_ARCH_SECCOMP_FILTER
54 select HAVE_ARCH_TRACEHOOK
56 select HAVE_C_RECORDMCOUNT
57 select HAVE_CC_STACKPROTECTOR
58 select HAVE_CMPXCHG_DOUBLE
59 select HAVE_CMPXCHG_LOCAL
60 select HAVE_DEBUG_BUGVERBOSE
61 select HAVE_DEBUG_KMEMLEAK
62 select HAVE_DMA_API_DEBUG
64 select HAVE_DMA_CONTIGUOUS
65 select HAVE_DYNAMIC_FTRACE
66 select HAVE_EFFICIENT_UNALIGNED_ACCESS
67 select HAVE_FTRACE_MCOUNT_RECORD
68 select HAVE_FUNCTION_TRACER
69 select HAVE_FUNCTION_GRAPH_TRACER
70 select HAVE_GENERIC_DMA_COHERENT
71 select HAVE_HW_BREAKPOINT if PERF_EVENTS
73 select HAVE_PATA_PLATFORM
74 select HAVE_PERF_EVENTS
76 select HAVE_PERF_USER_STACK_DUMP
77 select HAVE_RCU_TABLE_FREE
78 select HAVE_SYSCALL_TRACEPOINTS
80 select IRQ_FORCED_THREADING
81 select MODULES_USE_ELF_RELA
84 select OF_EARLY_FLATTREE
85 select OF_RESERVED_MEM
86 select PERF_USE_VMALLOC
91 select SYSCTL_EXCEPTION_TRACE
92 select HAVE_CONTEXT_TRACKING
94 ARM 64-bit (AArch64) Linux support.
99 config ARCH_PHYS_ADDR_T_64BIT
108 config STACKTRACE_SUPPORT
111 config ILLEGAL_POINTER_VALUE
113 default 0xdead000000000000
115 config LOCKDEP_SUPPORT
118 config TRACE_IRQFLAGS_SUPPORT
121 config RWSEM_XCHGADD_ALGORITHM
128 config GENERIC_BUG_RELATIVE_POINTERS
130 depends on GENERIC_BUG
132 config GENERIC_HWEIGHT
138 config GENERIC_CALIBRATE_DELAY
144 config HAVE_GENERIC_RCU_GUP
147 config ARCH_DMA_ADDR_T_64BIT
150 config NEED_DMA_MAP_STATE
153 config NEED_SG_DMA_LENGTH
165 config KERNEL_MODE_NEON
168 config FIX_EARLYCON_MEM
171 config PGTABLE_LEVELS
173 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
174 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
175 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
176 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
177 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
178 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
180 source "init/Kconfig"
182 source "kernel/Kconfig.freezer"
184 source "arch/arm64/Kconfig.platforms"
191 This feature enables support for PCI bus system. If you say Y
192 here, the kernel will include drivers and infrastructure code
193 to support PCI bus devices.
198 config PCI_DOMAINS_GENERIC
204 source "drivers/pci/Kconfig"
205 source "drivers/pci/pcie/Kconfig"
206 source "drivers/pci/hotplug/Kconfig"
210 menu "Kernel Features"
212 menu "ARM errata workarounds via the alternatives framework"
214 config ARM64_ERRATUM_826319
215 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
218 This option adds an alternative code sequence to work around ARM
219 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
220 AXI master interface and an L2 cache.
222 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
223 and is unable to accept a certain write via this interface, it will
224 not progress on read data presented on the read data channel and the
227 The workaround promotes data cache clean instructions to
228 data cache clean-and-invalidate.
229 Please note that this does not necessarily enable the workaround,
230 as it depends on the alternative framework, which will only patch
231 the kernel if an affected CPU is detected.
235 config ARM64_ERRATUM_827319
236 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
239 This option adds an alternative code sequence to work around ARM
240 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
241 master interface and an L2 cache.
243 Under certain conditions this erratum can cause a clean line eviction
244 to occur at the same time as another transaction to the same address
245 on the AMBA 5 CHI interface, which can cause data corruption if the
246 interconnect reorders the two transactions.
248 The workaround promotes data cache clean instructions to
249 data cache clean-and-invalidate.
250 Please note that this does not necessarily enable the workaround,
251 as it depends on the alternative framework, which will only patch
252 the kernel if an affected CPU is detected.
256 config ARM64_ERRATUM_824069
257 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
260 This option adds an alternative code sequence to work around ARM
261 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
262 to a coherent interconnect.
264 If a Cortex-A53 processor is executing a store or prefetch for
265 write instruction at the same time as a processor in another
266 cluster is executing a cache maintenance operation to the same
267 address, then this erratum might cause a clean cache line to be
268 incorrectly marked as dirty.
270 The workaround promotes data cache clean instructions to
271 data cache clean-and-invalidate.
272 Please note that this option does not necessarily enable the
273 workaround, as it depends on the alternative framework, which will
274 only patch the kernel if an affected CPU is detected.
278 config ARM64_ERRATUM_819472
279 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
282 This option adds an alternative code sequence to work around ARM
283 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
284 present when it is connected to a coherent interconnect.
286 If the processor is executing a load and store exclusive sequence at
287 the same time as a processor in another cluster is executing a cache
288 maintenance operation to the same address, then this erratum might
289 cause data corruption.
291 The workaround promotes data cache clean instructions to
292 data cache clean-and-invalidate.
293 Please note that this does not necessarily enable the workaround,
294 as it depends on the alternative framework, which will only patch
295 the kernel if an affected CPU is detected.
299 config ARM64_ERRATUM_832075
300 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
303 This option adds an alternative code sequence to work around ARM
304 erratum 832075 on Cortex-A57 parts up to r1p2.
306 Affected Cortex-A57 parts might deadlock when exclusive load/store
307 instructions to Write-Back memory are mixed with Device loads.
309 The workaround is to promote device loads to use Load-Acquire
311 Please note that this does not necessarily enable the workaround,
312 as it depends on the alternative framework, which will only patch
313 the kernel if an affected CPU is detected.
317 config ARM64_ERRATUM_845719
318 bool "Cortex-A53: 845719: a load might read incorrect data"
322 This option adds an alternative code sequence to work around ARM
323 erratum 845719 on Cortex-A53 parts up to r0p4.
325 When running a compat (AArch32) userspace on an affected Cortex-A53
326 part, a load at EL0 from a virtual address that matches the bottom 32
327 bits of the virtual address used by a recent load at (AArch64) EL1
328 might return incorrect data.
330 The workaround is to write the contextidr_el1 register on exception
331 return to a 32-bit task.
332 Please note that this does not necessarily enable the workaround,
333 as it depends on the alternative framework, which will only patch
334 the kernel if an affected CPU is detected.
338 config ARM64_ERRATUM_843419
339 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
343 This option builds kernel modules using the large memory model in
344 order to avoid the use of the ADRP instruction, which can cause
345 a subsequent memory access to use an incorrect address on Cortex-A53
348 Note that the kernel itself must be linked with a version of ld
349 which fixes potentially affected ADRP instructions through the
359 default ARM64_4K_PAGES
361 Page size (translation granule) configuration.
363 config ARM64_4K_PAGES
366 This feature enables 4KB pages support.
368 config ARM64_16K_PAGES
371 The system will use 16KB pages support. AArch32 emulation
372 requires applications compiled with 16K (or a multiple of 16K)
375 config ARM64_64K_PAGES
378 This feature enables 64KB pages support (4KB by default)
379 allowing only two levels of page tables and faster TLB
380 look-up. AArch32 emulation requires applications compiled
381 with 64K aligned segments.
386 prompt "Virtual address space size"
387 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
388 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
389 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
391 Allows choosing one of multiple possible virtual address
392 space sizes. The level of translation table is determined by
393 a combination of page size and virtual address space size.
395 config ARM64_VA_BITS_36
396 bool "36-bit" if EXPERT
397 depends on ARM64_16K_PAGES
399 config ARM64_VA_BITS_39
401 depends on ARM64_4K_PAGES
403 config ARM64_VA_BITS_42
405 depends on ARM64_64K_PAGES
407 config ARM64_VA_BITS_47
409 depends on ARM64_16K_PAGES
411 config ARM64_VA_BITS_48
418 default 36 if ARM64_VA_BITS_36
419 default 39 if ARM64_VA_BITS_39
420 default 42 if ARM64_VA_BITS_42
421 default 47 if ARM64_VA_BITS_47
422 default 48 if ARM64_VA_BITS_48
424 config CPU_BIG_ENDIAN
425 bool "Build big-endian kernel"
427 Say Y if you plan on running a kernel in big-endian mode.
430 bool "Multi-core scheduler support"
432 Multi-core scheduler support improves the CPU scheduler's decision
433 making when dealing with multi-core CPU chips at a cost of slightly
434 increased overhead in some places. If unsure say N here.
437 bool "SMT scheduler support"
439 Improves the CPU scheduler's decision making when dealing with
440 MultiThreading at a cost of slightly increased overhead in some
441 places. If unsure say N here.
444 int "Maximum number of CPUs (2-4096)"
446 # These have to remain sorted largest to smallest
450 bool "Support for hot-pluggable CPUs"
451 select GENERIC_IRQ_MIGRATION
453 Say Y here to experiment with turning CPUs off and on. CPUs
454 can be controlled through /sys/devices/system/cpu.
456 source kernel/Kconfig.preempt
457 source kernel/Kconfig.hz
459 config ARCH_HAS_HOLES_MEMORYMODEL
460 def_bool y if SPARSEMEM
462 config ARCH_SPARSEMEM_ENABLE
464 select SPARSEMEM_VMEMMAP_ENABLE
466 config ARCH_SPARSEMEM_DEFAULT
467 def_bool ARCH_SPARSEMEM_ENABLE
469 config ARCH_SELECT_MEMORY_MODEL
470 def_bool ARCH_SPARSEMEM_ENABLE
472 config HAVE_ARCH_PFN_VALID
473 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
475 config HW_PERF_EVENTS
479 config SYS_SUPPORTS_HUGETLBFS
482 config ARCH_WANT_GENERAL_HUGETLB
485 config ARCH_WANT_HUGE_PMD_SHARE
486 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
488 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
491 config ARCH_HAS_CACHE_LINE_SIZE
497 bool "Enable seccomp to safely compute untrusted bytecode"
499 This kernel feature is useful for number crunching applications
500 that may need to compute untrusted bytecode during their
501 execution. By using pipes or other transports made available to
502 the process as file descriptors supporting the read/write
503 syscalls, it's possible to isolate those applications in
504 their own address space using seccomp. Once seccomp is
505 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
506 and the task is only allowed to execute a few safe syscalls
507 defined by each seccomp mode.
514 bool "Xen guest support on ARM64"
515 depends on ARM64 && OF
518 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
520 config FORCE_MAX_ZONEORDER
522 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
523 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
526 The kernel memory allocator divides physically contiguous memory
527 blocks into "zones", where each zone is a power of two number of
528 pages. This option selects the largest power of two that the kernel
529 keeps in the memory allocator. If you need to allocate very large
530 blocks of physically contiguous memory, then you may need to
533 This config option is actually maximum order plus one. For example,
534 a value of 11 means that the largest free memory block is 2^10 pages.
536 We make sure that we can allocate upto a HugePage size for each configuration.
538 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
540 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
541 4M allocations matching the default size used by generic code.
543 menuconfig ARMV8_DEPRECATED
544 bool "Emulate deprecated/obsolete ARMv8 instructions"
547 Legacy software support may require certain instructions
548 that have been deprecated or obsoleted in the architecture.
550 Enable this config to enable selective emulation of these
558 bool "Emulate SWP/SWPB instructions"
560 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
561 they are always undefined. Say Y here to enable software
562 emulation of these instructions for userspace using LDXR/STXR.
564 In some older versions of glibc [<=2.8] SWP is used during futex
565 trylock() operations with the assumption that the code will not
566 be preempted. This invalid assumption may be more likely to fail
567 with SWP emulation enabled, leading to deadlock of the user
570 NOTE: when accessing uncached shared regions, LDXR/STXR rely
571 on an external transaction monitoring block called a global
572 monitor to maintain update atomicity. If your system does not
573 implement a global monitor, this option can cause programs that
574 perform SWP operations to uncached memory to deadlock.
578 config CP15_BARRIER_EMULATION
579 bool "Emulate CP15 Barrier instructions"
581 The CP15 barrier instructions - CP15ISB, CP15DSB, and
582 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
583 strongly recommended to use the ISB, DSB, and DMB
584 instructions instead.
586 Say Y here to enable software emulation of these
587 instructions for AArch32 userspace code. When this option is
588 enabled, CP15 barrier usage is traced which can help
589 identify software that needs updating.
593 config SETEND_EMULATION
594 bool "Emulate SETEND instruction"
596 The SETEND instruction alters the data-endianness of the
597 AArch32 EL0, and is deprecated in ARMv8.
599 Say Y here to enable software emulation of the instruction
600 for AArch32 userspace code.
602 Note: All the cpus on the system must have mixed endian support at EL0
603 for this feature to be enabled. If a new CPU - which doesn't support mixed
604 endian - is hotplugged in after this feature has been enabled, there could
605 be unexpected results in the applications.
610 menu "ARMv8.1 architectural features"
612 config ARM64_HW_AFDBM
613 bool "Support for hardware updates of the Access and Dirty page flags"
616 The ARMv8.1 architecture extensions introduce support for
617 hardware updates of the access and dirty information in page
618 table entries. When enabled in TCR_EL1 (HA and HD bits) on
619 capable processors, accesses to pages with PTE_AF cleared will
620 set this bit instead of raising an access flag fault.
621 Similarly, writes to read-only pages with the DBM bit set will
622 clear the read-only bit (AP[2]) instead of raising a
625 Kernels built with this configuration option enabled continue
626 to work on pre-ARMv8.1 hardware and the performance impact is
627 minimal. If unsure, say Y.
630 bool "Enable support for Privileged Access Never (PAN)"
633 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
634 prevents the kernel or hypervisor from accessing user-space (EL0)
637 Choosing this option will cause any unprotected (not using
638 copy_to_user et al) memory access to fail with a permission fault.
640 The feature is detected at runtime, and will remain as a 'nop'
641 instruction if the cpu does not implement the feature.
643 config ARM64_LSE_ATOMICS
644 bool "Atomic instructions"
646 As part of the Large System Extensions, ARMv8.1 introduces new
647 atomic instructions that are designed specifically to scale in
650 Say Y here to make use of these instructions for the in-kernel
651 atomic routines. This incurs a small overhead on CPUs that do
652 not support these instructions and requires the kernel to be
653 built with binutils >= 2.25.
662 string "Default kernel command string"
665 Provide a set of default command-line options at build time by
666 entering them here. As a minimum, you should specify the the
667 root device (e.g. root=/dev/nfs).
670 bool "Always use the default kernel command string"
672 Always use the default kernel command string, even if the boot
673 loader passes other arguments to the kernel.
674 This is useful if you cannot or don't want to change the
675 command-line options your boot loader passes to the kernel.
681 bool "UEFI runtime support"
682 depends on OF && !CPU_BIG_ENDIAN
685 select EFI_PARAMS_FROM_FDT
686 select EFI_RUNTIME_WRAPPERS
691 This option provides support for runtime services provided
692 by UEFI firmware (such as non-volatile variables, realtime
693 clock, and platform reset). A UEFI stub is also provided to
694 allow the kernel to be booted as an EFI application. This
695 is only useful on systems that have UEFI firmware.
698 bool "Enable support for SMBIOS (DMI) tables"
702 This enables SMBIOS/DMI feature for systems.
704 This option is only useful on systems that have UEFI firmware.
705 However, even with this option, the resultant kernel should
706 continue to boot on existing non-UEFI platforms.
710 menu "Userspace binary formats"
712 source "fs/Kconfig.binfmt"
715 bool "Kernel support for 32-bit EL0"
716 depends on ARM64_4K_PAGES || EXPERT
717 select COMPAT_BINFMT_ELF
719 select OLD_SIGSUSPEND3
720 select COMPAT_OLD_SIGACTION
722 This option enables support for a 32-bit EL0 running under a 64-bit
723 kernel at EL1. AArch32-specific components such as system calls,
724 the user helper functions, VFP support and the ptrace interface are
725 handled appropriately by the kernel.
727 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
728 that you will only be able to execute AArch32 binaries that were compiled
729 with page size aligned segments.
731 If you want to execute 32-bit userspace applications, say Y.
733 config SYSVIPC_COMPAT
735 depends on COMPAT && SYSVIPC
739 menu "Power management options"
741 source "kernel/power/Kconfig"
743 config ARCH_SUSPEND_POSSIBLE
748 menu "CPU Power Management"
750 source "drivers/cpuidle/Kconfig"
752 source "drivers/cpufreq/Kconfig"
758 source "drivers/Kconfig"
760 source "drivers/firmware/Kconfig"
762 source "drivers/acpi/Kconfig"
766 source "arch/arm64/kvm/Kconfig"
768 source "arch/arm64/Kconfig.debug"
770 source "security/Kconfig"
772 source "crypto/Kconfig"
774 source "arch/arm64/crypto/Kconfig"