2 * Copyright 2009 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
5 * S5P - Common clock support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/list.h>
16 #include <linux/errno.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
19 #include <linux/device.h>
21 #include <asm/div64.h>
23 #include <mach/regs-clock.h>
25 #include <plat/clock.h>
26 #include <plat/clock-clksrc.h>
27 #include <plat/s5p-clock.h>
29 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
32 struct clk clk_ext_xtal_mux = {
37 struct clk clk_xusbxti = {
42 struct clk s5p_clk_27m = {
48 /* 48MHz USB Phy clock output */
49 struct clk clk_48m = {
56 * No need .ctrlbit, this is always on
58 struct clk clk_fout_apll = {
63 /* BPLL clock output */
65 struct clk clk_fout_bpll = {
70 struct clk clk_fout_bpll_div2 = {
71 .name = "fout_bpll_div2",
75 /* CPLL clock output */
77 struct clk clk_fout_cpll = {
83 * No need .ctrlbit, this is always on
85 struct clk clk_fout_mpll = {
90 struct clk clk_fout_mpll_div2 = {
91 .name = "fout_mpll_div2",
95 /* EPLL clock output */
96 struct clk clk_fout_epll = {
102 /* DPLL clock output */
103 struct clk clk_fout_dpll = {
106 .ctrlbit = (1 << 31),
109 /* VPLL clock output */
110 struct clk clk_fout_vpll = {
113 .ctrlbit = (1 << 31),
116 /* Possible clock sources for APLL Mux */
117 static struct clk *clk_src_apll_list[] = {
119 [1] = &clk_fout_apll,
122 struct clksrc_sources clk_src_apll = {
123 .sources = clk_src_apll_list,
124 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
127 /* Possible clock sources for BPLL Mux */
128 static struct clk *clk_src_bpll_list[] = {
130 [1] = &clk_fout_bpll,
133 struct clksrc_sources clk_src_bpll = {
134 .sources = clk_src_bpll_list,
135 .nr_sources = ARRAY_SIZE(clk_src_bpll_list),
138 static struct clk *clk_src_bpll_fout_list[] = {
139 [0] = &clk_fout_bpll_div2,
140 [1] = &clk_fout_bpll,
143 struct clksrc_sources clk_src_bpll_fout = {
144 .sources = clk_src_bpll_fout_list,
145 .nr_sources = ARRAY_SIZE(clk_src_bpll_fout_list),
148 /* Possible clock sources for CPLL Mux */
149 static struct clk *clk_src_cpll_list[] = {
151 [1] = &clk_fout_cpll,
154 struct clksrc_sources clk_src_cpll = {
155 .sources = clk_src_cpll_list,
156 .nr_sources = ARRAY_SIZE(clk_src_cpll_list),
159 /* Possible clock sources for MPLL Mux */
160 static struct clk *clk_src_mpll_list[] = {
162 [1] = &clk_fout_mpll,
165 struct clksrc_sources clk_src_mpll = {
166 .sources = clk_src_mpll_list,
167 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
170 static struct clk *clk_src_mpll_fout_list[] = {
171 [0] = &clk_fout_mpll_div2,
172 [1] = &clk_fout_mpll,
175 struct clksrc_sources clk_src_mpll_fout = {
176 .sources = clk_src_mpll_fout_list,
177 .nr_sources = ARRAY_SIZE(clk_src_mpll_fout_list),
180 /* Possible clock sources for EPLL Mux */
181 static struct clk *clk_src_epll_list[] = {
183 [1] = &clk_fout_epll,
186 struct clksrc_sources clk_src_epll = {
187 .sources = clk_src_epll_list,
188 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
191 /* Possible clock sources for DPLL Mux */
192 static struct clk *clk_src_dpll_list[] = {
194 [1] = &clk_fout_dpll,
197 struct clksrc_sources clk_src_dpll = {
198 .sources = clk_src_dpll_list,
199 .nr_sources = ARRAY_SIZE(clk_src_dpll_list),
202 struct clk clk_vpll = {
207 int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable)
209 unsigned int ctrlbit = clk->ctrlbit;
212 con = __raw_readl(reg);
213 con = enable ? (con | ctrlbit) : (con & ~ctrlbit);
214 __raw_writel(con, reg);
218 int s5p_epll_enable(struct clk *clk, int enable)
220 unsigned int ctrlbit = clk->ctrlbit;
221 unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
224 __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
226 __raw_writel(epll_con, S5P_EPLL_CON);
231 unsigned long s5p_epll_get_rate(struct clk *clk)
236 int s5p_spdif_set_rate(struct clk *clk, unsigned long rate)
241 pclk = clk_get_parent(clk);
245 ret = pclk->ops->set_rate(pclk, rate);
251 unsigned long s5p_spdif_get_rate(struct clk *clk)
256 pclk = clk_get_parent(clk);
260 rate = pclk->ops->get_rate(pclk);
266 struct clk_ops s5p_sclk_spdif_ops = {
267 .set_rate = s5p_spdif_set_rate,
268 .get_rate = s5p_spdif_get_rate,
271 static struct clk *s5p_clks[] __initdata = {
284 void __init s5p_register_clocks(unsigned long xtal_freq)
288 clk_ext_xtal_mux.rate = xtal_freq;
290 ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks));
292 printk(KERN_ERR "Failed to register s5p clocks\n");