1 /* linux/arch/arm/plat-s3c24xx/pwm-clock.c
3 * Copyright (c) 2007 Simtec Electronics
4 * Copyright (c) 2007, 2008 Ben Dooks
5 * Ben Dooks <ben-linux@fluff.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/list.h>
16 #include <linux/errno.h>
17 #include <linux/log2.h>
18 #include <linux/clk.h>
19 #include <linux/err.h>
22 #include <mach/hardware.h>
26 #include <plat/clock.h>
29 #include <plat/regs-timer.h>
30 #include <mach/pwm-clock.h>
32 /* Each of the timers 0 through 5 go through the following
33 * clock tree, with the inputs depending on the timers.
35 * pclk ---- [ prescaler 0 ] -+---> timer 0
38 * pclk ---- [ prescaler 1 ] -+---> timer 2
42 * Which are fed into the timers as so:
44 * prescaled 0 ---- [ div 2,4,8,16 ] ---\
46 * tclk 0 ------------------------------/
48 * prescaled 0 ---- [ div 2,4,8,16 ] ---\
50 * tclk 0 ------------------------------/
53 * prescaled 1 ---- [ div 2,4,8,16 ] ---\
55 * tclk 1 ------------------------------/
57 * prescaled 1 ---- [ div 2,4,8,16 ] ---\
59 * tclk 1 ------------------------------/
61 * prescaled 1 ---- [ div 2,4,8, 16 ] --\
63 * tclk 1 ------------------------------/
65 * Since the mux and the divider are tied together in the
66 * same register space, it is impossible to set the parent
67 * and the rate at the same time. To avoid this, we add an
68 * intermediate 'prescaled-and-divided' clock to select
69 * as the parent for the timer input clock called tdiv.
71 * prescaled clk --> pwm-tdiv ---\
73 * tclk -------------------------/
76 static struct clk clk_timer_scaler[];
78 static unsigned long clk_pwm_scaler_get_rate(struct clk *clk)
80 unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
82 if (clk == &clk_timer_scaler[1]) {
83 tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
84 tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
86 tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK;
89 return clk_get_rate(clk->parent) / (tcfg0 + 1);
92 static unsigned long clk_pwm_scaler_round_rate(struct clk *clk,
95 unsigned long parent_rate = clk_get_rate(clk->parent);
96 unsigned long divisor = parent_rate / rate;
100 else if (divisor < 2)
103 return parent_rate / divisor;
106 static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate)
108 unsigned long round = clk_pwm_scaler_round_rate(clk, rate);
110 unsigned long divisor;
113 divisor = clk_get_rate(clk->parent) / round;
116 local_irq_save(flags);
117 tcfg0 = __raw_readl(S3C2410_TCFG0);
119 if (clk == &clk_timer_scaler[1]) {
120 tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
121 tcfg0 |= divisor << S3C2410_TCFG_PRESCALER1_SHIFT;
123 tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
127 __raw_writel(tcfg0, S3C2410_TCFG0);
128 local_irq_restore(flags);
133 static struct clk_ops clk_pwm_scaler_ops = {
134 .get_rate = clk_pwm_scaler_get_rate,
135 .set_rate = clk_pwm_scaler_set_rate,
136 .round_rate = clk_pwm_scaler_round_rate,
139 static struct clk clk_timer_scaler[] = {
141 .name = "pwm-scaler0",
143 .ops = &clk_pwm_scaler_ops,
146 .name = "pwm-scaler1",
148 .ops = &clk_pwm_scaler_ops,
152 static struct clk clk_timer_tclk[] = {
163 struct pwm_tdiv_clk {
165 unsigned int divisor;
168 static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
170 return container_of(clk, struct pwm_tdiv_clk, clk);
173 static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
175 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
176 unsigned int divisor;
178 tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
179 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
181 if (pwm_cfg_src_is_tclk(tcfg1))
182 divisor = to_tdiv(clk)->divisor;
184 divisor = tcfg_to_divisor(tcfg1);
186 return clk_get_rate(clk->parent) / divisor;
189 static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
192 unsigned long parent_rate;
193 unsigned long divisor;
195 parent_rate = clk_get_rate(clk->parent);
196 divisor = parent_rate / rate;
198 if (divisor <= 1 && pwm_tdiv_has_div1())
200 else if (divisor <= 2)
202 else if (divisor <= 4)
204 else if (divisor <= 8)
209 return parent_rate / divisor;
212 static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
214 return pwm_tdiv_div_bits(divclk->divisor);
217 static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
219 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
220 unsigned long bits = clk_pwm_tdiv_bits(divclk);
222 unsigned long shift = S3C2410_TCFG1_SHIFT(divclk->clk.id);
224 local_irq_save(flags);
226 tcfg1 = __raw_readl(S3C2410_TCFG1);
227 tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
228 tcfg1 |= bits << shift;
229 __raw_writel(tcfg1, S3C2410_TCFG1);
231 local_irq_restore(flags);
234 static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
236 struct pwm_tdiv_clk *divclk = to_tdiv(clk);
237 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
238 unsigned long parent_rate = clk_get_rate(clk->parent);
239 unsigned long divisor;
241 tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
242 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
244 rate = clk_round_rate(clk, rate);
245 divisor = parent_rate / rate;
250 divclk->divisor = divisor;
252 /* Update the current MUX settings if we are currently
253 * selected as the clock source for this clock. */
255 if (!pwm_cfg_src_is_tclk(tcfg1))
256 clk_pwm_tdiv_update(divclk);
261 static struct clk_ops clk_tdiv_ops = {
262 .get_rate = clk_pwm_tdiv_get_rate,
263 .set_rate = clk_pwm_tdiv_set_rate,
264 .round_rate = clk_pwm_tdiv_round_rate,
267 static struct pwm_tdiv_clk clk_timer_tdiv[] = {
271 .devname = "s3c24xx-pwm.0",
272 .ops = &clk_tdiv_ops,
273 .parent = &clk_timer_scaler[0],
279 .devname = "s3c24xx-pwm.1",
280 .ops = &clk_tdiv_ops,
281 .parent = &clk_timer_scaler[0],
287 .devname = "s3c24xx-pwm.2",
288 .ops = &clk_tdiv_ops,
289 .parent = &clk_timer_scaler[1],
295 .devname = "s3c24xx-pwm.3",
296 .ops = &clk_tdiv_ops,
297 .parent = &clk_timer_scaler[1],
303 .devname = "s3c24xx-pwm.4",
304 .ops = &clk_tdiv_ops,
305 .parent = &clk_timer_scaler[1],
310 static int __init clk_pwm_tdiv_register(unsigned int id)
312 struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id];
313 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
315 tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
316 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
319 divclk->divisor = tcfg_to_divisor(tcfg1);
321 return s3c24xx_register_clock(&divclk->clk);
324 static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id)
326 return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0];
329 static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id)
331 return &clk_timer_tdiv[id].clk;
334 static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
336 unsigned int id = clk->id;
340 unsigned long shift = S3C2410_TCFG1_SHIFT(id);
342 if (parent == s3c24xx_pwmclk_tclk(id))
343 bits = S3C_TCFG1_MUX_TCLK << shift;
344 else if (parent == s3c24xx_pwmclk_tdiv(id))
345 bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
349 clk->parent = parent;
351 local_irq_save(flags);
353 tcfg1 = __raw_readl(S3C2410_TCFG1);
354 tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
355 __raw_writel(tcfg1 | bits, S3C2410_TCFG1);
357 local_irq_restore(flags);
362 static struct clk_ops clk_tin_ops = {
363 .set_parent = clk_pwm_tin_set_parent,
366 static struct clk clk_tin[] = {
369 .devname = "s3c24xx-pwm.0",
375 .devname = "s3c24xx-pwm.1",
381 .devname = "s3c24xx-pwm.2",
387 .devname = "s3c24xx-pwm.3",
393 .devname = "s3c24xx-pwm.4",
399 static __init int clk_pwm_tin_register(struct clk *pwm)
401 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
402 unsigned int id = pwm->id;
407 ret = s3c24xx_register_clock(pwm);
411 tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
412 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
414 if (pwm_cfg_src_is_tclk(tcfg1))
415 parent = s3c24xx_pwmclk_tclk(id);
417 parent = s3c24xx_pwmclk_tdiv(id);
419 return clk_set_parent(pwm, parent);
423 * s3c_pwmclk_init() - initialise pwm clocks
425 * Initialise and register the clocks which provide the inputs for the
428 * Note, this call is required by the time core, so must be called after
429 * the base clocks are added and before any of the initcalls are run.
431 __init void s3c_pwmclk_init(void)
433 struct clk *clk_timers;
437 clk_timers = clk_get(NULL, "timers");
438 if (IS_ERR(clk_timers)) {
439 printk(KERN_ERR "%s: no parent clock\n", __func__);
443 for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++)
444 clk_timer_scaler[clk].parent = clk_timers;
446 s3c_register_clocks(clk_timer_scaler, ARRAY_SIZE(clk_timer_scaler));
447 s3c_register_clocks(clk_timer_tclk, ARRAY_SIZE(clk_timer_tclk));
449 for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
450 ret = clk_pwm_tdiv_register(clk);
453 printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
458 for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) {
459 ret = clk_pwm_tin_register(&clk_tin[clk]);
461 printk(KERN_ERR "error adding pwm%d tin clock\n", clk);