1 /* linux/arch/arm/plat-s5pc1xx/clock.c
3 * Copyright 2009 Samsung Electronics Co.
5 * S5PC1XX Base clock support
7 * Based on plat-s3c64xx/clock.c
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/ioport.h>
18 #include <linux/clk.h>
21 #include <mach/hardware.h>
24 #include <plat/regs-clock.h>
25 #include <plat/devs.h>
26 #include <plat/clock.h>
28 struct clk clk_27m = {
34 static int clk_48m_ctrl(struct clk *clk, int enable)
39 /* can't rely on clock lock, this register has other usages */
40 local_irq_save(flags);
42 val = __raw_readl(S5PC100_CLKSRC1);
44 val |= S5PC100_CLKSRC1_CLK48M_MASK;
46 val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
48 __raw_writel(val, S5PC100_CLKSRC1);
49 local_irq_restore(flags);
54 struct clk clk_48m = {
58 .enable = clk_48m_ctrl,
61 struct clk clk_54m = {
67 struct clk clk_hd0 = {
73 .ops = &clk_ops_def_setrate,
76 struct clk clk_pd0 = {
82 .ops = &clk_ops_def_setrate,
85 static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
87 unsigned int ctrlbit = clk->ctrlbit;
90 con = __raw_readl(reg);
95 __raw_writel(con, reg);
100 static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable)
102 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
105 static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable)
107 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
110 static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable)
112 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
115 static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable)
117 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
120 static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable)
122 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
125 static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable)
127 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
130 static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable)
132 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
135 static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable)
137 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
140 static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable)
142 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
145 static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable)
147 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
150 int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
152 return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
155 int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
157 return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
160 static struct clk s5pc100_init_clocks_disable[] = {
165 .enable = s5pc100_clk_d11_ctrl,
166 .ctrlbit = S5PC100_CLKGATE_D11_DSI,
171 .enable = s5pc100_clk_d11_ctrl,
172 .ctrlbit = S5PC100_CLKGATE_D11_CSI,
177 .enable = s5pc100_clk_d14_ctrl,
178 .ctrlbit = S5PC100_CLKGATE_D14_CCAN0,
183 .enable = s5pc100_clk_d14_ctrl,
184 .ctrlbit = S5PC100_CLKGATE_D14_CCAN1,
189 .enable = s5pc100_clk_d15_ctrl,
190 .ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
195 .enable = s5pc100_clk_d20_ctrl,
196 .ctrlbit = S5PC100_CLKGATE_D20_HCLKD2,
201 .enable = s5pc100_clk_d20_ctrl,
202 .ctrlbit = S5PC100_CLKGATE_D20_I2SD2,
206 static struct clk s5pc100_init_clocks[] = {
207 /* System1 (D0_0) devices */
212 .enable = s5pc100_clk_d00_ctrl,
213 .ctrlbit = S5PC100_CLKGATE_D00_INTC,
218 .enable = s5pc100_clk_d00_ctrl,
219 .ctrlbit = S5PC100_CLKGATE_D00_TZIC,
224 .enable = s5pc100_clk_d00_ctrl,
225 .ctrlbit = S5PC100_CLKGATE_D00_CFCON,
230 .enable = s5pc100_clk_d00_ctrl,
231 .ctrlbit = S5PC100_CLKGATE_D00_MDMA,
236 .enable = s5pc100_clk_d00_ctrl,
237 .ctrlbit = S5PC100_CLKGATE_D00_G2D,
242 .enable = s5pc100_clk_d00_ctrl,
243 .ctrlbit = S5PC100_CLKGATE_D00_SECSS,
248 .enable = s5pc100_clk_d00_ctrl,
249 .ctrlbit = S5PC100_CLKGATE_D00_CSSYS,
252 /* Memory (D0_1) devices */
257 .enable = s5pc100_clk_d01_ctrl,
258 .ctrlbit = S5PC100_CLKGATE_D01_DMC,
263 .enable = s5pc100_clk_d01_ctrl,
264 .ctrlbit = S5PC100_CLKGATE_D01_SROMC,
269 .enable = s5pc100_clk_d01_ctrl,
270 .ctrlbit = S5PC100_CLKGATE_D01_ONENAND,
275 .enable = s5pc100_clk_d01_ctrl,
276 .ctrlbit = S5PC100_CLKGATE_D01_NFCON,
281 .enable = s5pc100_clk_d01_ctrl,
282 .ctrlbit = S5PC100_CLKGATE_D01_INTMEM,
287 .enable = s5pc100_clk_d01_ctrl,
288 .ctrlbit = S5PC100_CLKGATE_D01_EBI,
291 /* System2 (D0_2) devices */
296 .enable = s5pc100_clk_d02_ctrl,
297 .ctrlbit = S5PC100_CLKGATE_D02_SECKEY,
302 .enable = s5pc100_clk_d02_ctrl,
303 .ctrlbit = S5PC100_CLKGATE_D02_SDM,
306 /* File (D1_0) devices */
311 .enable = s5pc100_clk_d10_ctrl,
312 .ctrlbit = S5PC100_CLKGATE_D10_PDMA0,
317 .enable = s5pc100_clk_d10_ctrl,
318 .ctrlbit = S5PC100_CLKGATE_D10_PDMA1,
323 .enable = s5pc100_clk_d10_ctrl,
324 .ctrlbit = S5PC100_CLKGATE_D10_USBHOST,
329 .enable = s5pc100_clk_d10_ctrl,
330 .ctrlbit = S5PC100_CLKGATE_D10_USBOTG,
335 .enable = s5pc100_clk_d10_ctrl,
336 .ctrlbit = S5PC100_CLKGATE_D10_MODEMIF,
341 .enable = s5pc100_clk_d10_ctrl,
342 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC0,
347 .enable = s5pc100_clk_d10_ctrl,
348 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC1,
353 .enable = s5pc100_clk_d10_ctrl,
354 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC2,
357 /* Multimedia1 (D1_1) devices */
362 .enable = s5pc100_clk_d11_ctrl,
363 .ctrlbit = S5PC100_CLKGATE_D11_LCD,
368 .enable = s5pc100_clk_d11_ctrl,
369 .ctrlbit = S5PC100_CLKGATE_D11_ROTATOR,
374 .enable = s5pc100_clk_d11_ctrl,
375 .ctrlbit = S5PC100_CLKGATE_D11_FIMC0,
380 .enable = s5pc100_clk_d11_ctrl,
381 .ctrlbit = S5PC100_CLKGATE_D11_FIMC1,
386 .enable = s5pc100_clk_d11_ctrl,
387 .ctrlbit = S5PC100_CLKGATE_D11_FIMC2,
392 .enable = s5pc100_clk_d11_ctrl,
393 .ctrlbit = S5PC100_CLKGATE_D11_JPEG,
398 .enable = s5pc100_clk_d11_ctrl,
399 .ctrlbit = S5PC100_CLKGATE_D11_G3D,
402 /* Multimedia2 (D1_2) devices */
407 .enable = s5pc100_clk_d12_ctrl,
408 .ctrlbit = S5PC100_CLKGATE_D12_TV,
413 .enable = s5pc100_clk_d12_ctrl,
414 .ctrlbit = S5PC100_CLKGATE_D12_VP,
419 .enable = s5pc100_clk_d12_ctrl,
420 .ctrlbit = S5PC100_CLKGATE_D12_MIXER,
425 .enable = s5pc100_clk_d12_ctrl,
426 .ctrlbit = S5PC100_CLKGATE_D12_HDMI,
431 .enable = s5pc100_clk_d12_ctrl,
432 .ctrlbit = S5PC100_CLKGATE_D12_MFC,
435 /* System (D1_3) devices */
440 .enable = s5pc100_clk_d13_ctrl,
441 .ctrlbit = S5PC100_CLKGATE_D13_CHIPID,
446 .enable = s5pc100_clk_d13_ctrl,
447 .ctrlbit = S5PC100_CLKGATE_D13_GPIO,
452 .enable = s5pc100_clk_d13_ctrl,
453 .ctrlbit = S5PC100_CLKGATE_D13_APC,
458 .enable = s5pc100_clk_d13_ctrl,
459 .ctrlbit = S5PC100_CLKGATE_D13_IEC,
464 .enable = s5pc100_clk_d13_ctrl,
465 .ctrlbit = S5PC100_CLKGATE_D13_PWM,
470 .enable = s5pc100_clk_d13_ctrl,
471 .ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER,
476 .enable = s5pc100_clk_d13_ctrl,
477 .ctrlbit = S5PC100_CLKGATE_D13_WDT,
482 .enable = s5pc100_clk_d13_ctrl,
483 .ctrlbit = S5PC100_CLKGATE_D13_RTC,
486 /* Connectivity (D1_4) devices */
491 .enable = s5pc100_clk_d14_ctrl,
492 .ctrlbit = S5PC100_CLKGATE_D14_UART0,
497 .enable = s5pc100_clk_d14_ctrl,
498 .ctrlbit = S5PC100_CLKGATE_D14_UART1,
503 .enable = s5pc100_clk_d14_ctrl,
504 .ctrlbit = S5PC100_CLKGATE_D14_UART2,
509 .enable = s5pc100_clk_d14_ctrl,
510 .ctrlbit = S5PC100_CLKGATE_D14_UART3,
515 .enable = s5pc100_clk_d14_ctrl,
516 .ctrlbit = S5PC100_CLKGATE_D14_IIC,
521 .enable = s5pc100_clk_d14_ctrl,
522 .ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC,
527 .enable = s5pc100_clk_d14_ctrl,
528 .ctrlbit = S5PC100_CLKGATE_D14_SPI0,
533 .enable = s5pc100_clk_d14_ctrl,
534 .ctrlbit = S5PC100_CLKGATE_D14_SPI1,
539 .enable = s5pc100_clk_d14_ctrl,
540 .ctrlbit = S5PC100_CLKGATE_D14_SPI2,
545 .enable = s5pc100_clk_d14_ctrl,
546 .ctrlbit = S5PC100_CLKGATE_D14_IRDA,
551 .enable = s5pc100_clk_d14_ctrl,
552 .ctrlbit = S5PC100_CLKGATE_D14_HSITX,
557 .enable = s5pc100_clk_d14_ctrl,
558 .ctrlbit = S5PC100_CLKGATE_D14_HSIRX,
561 /* Audio (D1_5) devices */
566 .enable = s5pc100_clk_d15_ctrl,
567 .ctrlbit = S5PC100_CLKGATE_D15_IIS0,
572 .enable = s5pc100_clk_d15_ctrl,
573 .ctrlbit = S5PC100_CLKGATE_D15_IIS1,
578 .enable = s5pc100_clk_d15_ctrl,
579 .ctrlbit = S5PC100_CLKGATE_D15_IIS2,
584 .enable = s5pc100_clk_d15_ctrl,
585 .ctrlbit = S5PC100_CLKGATE_D15_AC97,
590 .enable = s5pc100_clk_d15_ctrl,
591 .ctrlbit = S5PC100_CLKGATE_D15_PCM0,
596 .enable = s5pc100_clk_d15_ctrl,
597 .ctrlbit = S5PC100_CLKGATE_D15_PCM1,
602 .enable = s5pc100_clk_d15_ctrl,
603 .ctrlbit = S5PC100_CLKGATE_D15_SPDIF,
608 .enable = s5pc100_clk_d15_ctrl,
609 .ctrlbit = S5PC100_CLKGATE_D15_TSADC,
614 .enable = s5pc100_clk_d15_ctrl,
615 .ctrlbit = S5PC100_CLKGATE_D15_CG,
618 /* Audio (D2_0) devices: all disabled */
620 /* Special Clocks 0 */
625 .enable = s5pc100_sclk0_ctrl,
626 .ctrlbit = S5PC100_CLKGATE_SCLK0_HPM,
628 .name = "sclk_onenand",
631 .enable = s5pc100_sclk0_ctrl,
632 .ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND,
637 .enable = s5pc100_sclk0_ctrl,
638 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48,
643 .enable = s5pc100_sclk0_ctrl,
644 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48,
649 .enable = s5pc100_sclk0_ctrl,
650 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48,
655 .enable = s5pc100_sclk0_ctrl,
656 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48,
661 .enable = s5pc100_sclk0_ctrl,
662 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48,
667 .enable = s5pc100_sclk0_ctrl,
668 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48,
670 /* Special Clocks 1 */
673 static struct clk *clks[] __initdata = {
683 void __init s5pc1xx_register_clocks(void)
690 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
692 s3c_register_clocks(s5pc100_init_clocks,
693 ARRAY_SIZE(s5pc100_init_clocks));
695 clkp = s5pc100_init_clocks_disable;
696 size = ARRAY_SIZE(s5pc100_init_clocks_disable);
698 for (ptr = 0; ptr < size; ptr++, clkp++) {
699 ret = s3c24xx_register_clock(clkp);
701 printk(KERN_ERR "Failed to register clock %s (%d)\n",
705 (clkp->enable)(clkp, 0);