1 /* linux/arch/arm/plat-s5p/clock.c
3 * Copyright 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5P - Common clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/device.h>
22 #include <asm/div64.h>
24 #include <mach/regs-clock.h>
26 #include <plat/clock.h>
27 #include <plat/clock-clksrc.h>
28 #include <plat/s5p-clock.h>
30 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
33 struct clk clk_ext_xtal_mux = {
38 struct clk clk_xusbxti = {
43 struct clk s5p_clk_27m = {
49 /* 48MHz USB Phy clock output */
50 struct clk clk_48m = {
57 * No need .ctrlbit, this is always on
59 struct clk clk_fout_apll = {
64 /* BPLL clock output */
66 struct clk clk_fout_bpll = {
71 /* CPLL clock output */
73 struct clk clk_fout_cpll = {
79 * No need .ctrlbit, this is always on
81 struct clk clk_fout_mpll = {
86 /* EPLL clock output */
87 struct clk clk_fout_epll = {
93 /* DPLL clock output */
94 struct clk clk_fout_dpll = {
100 /* VPLL clock output */
101 struct clk clk_fout_vpll = {
104 .ctrlbit = (1 << 31),
107 /* Possible clock sources for APLL Mux */
108 static struct clk *clk_src_apll_list[] = {
110 [1] = &clk_fout_apll,
113 struct clksrc_sources clk_src_apll = {
114 .sources = clk_src_apll_list,
115 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
118 /* Possible clock sources for BPLL Mux */
119 static struct clk *clk_src_bpll_list[] = {
121 [1] = &clk_fout_bpll,
124 struct clksrc_sources clk_src_bpll = {
125 .sources = clk_src_bpll_list,
126 .nr_sources = ARRAY_SIZE(clk_src_bpll_list),
129 /* Possible clock sources for CPLL Mux */
130 static struct clk *clk_src_cpll_list[] = {
132 [1] = &clk_fout_cpll,
135 struct clksrc_sources clk_src_cpll = {
136 .sources = clk_src_cpll_list,
137 .nr_sources = ARRAY_SIZE(clk_src_cpll_list),
140 /* Possible clock sources for MPLL Mux */
141 static struct clk *clk_src_mpll_list[] = {
143 [1] = &clk_fout_mpll,
146 struct clksrc_sources clk_src_mpll = {
147 .sources = clk_src_mpll_list,
148 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
151 /* Possible clock sources for EPLL Mux */
152 static struct clk *clk_src_epll_list[] = {
154 [1] = &clk_fout_epll,
157 struct clksrc_sources clk_src_epll = {
158 .sources = clk_src_epll_list,
159 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
162 /* Possible clock sources for DPLL Mux */
163 static struct clk *clk_src_dpll_list[] = {
165 [1] = &clk_fout_dpll,
168 struct clksrc_sources clk_src_dpll = {
169 .sources = clk_src_dpll_list,
170 .nr_sources = ARRAY_SIZE(clk_src_dpll_list),
173 struct clk clk_vpll = {
178 int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable)
180 unsigned int ctrlbit = clk->ctrlbit;
183 con = __raw_readl(reg);
184 con = enable ? (con | ctrlbit) : (con & ~ctrlbit);
185 __raw_writel(con, reg);
189 int s5p_epll_enable(struct clk *clk, int enable)
191 unsigned int ctrlbit = clk->ctrlbit;
192 unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
195 __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
197 __raw_writel(epll_con, S5P_EPLL_CON);
202 unsigned long s5p_epll_get_rate(struct clk *clk)
207 int s5p_spdif_set_rate(struct clk *clk, unsigned long rate)
212 pclk = clk_get_parent(clk);
216 ret = pclk->ops->set_rate(pclk, rate);
222 unsigned long s5p_spdif_get_rate(struct clk *clk)
227 pclk = clk_get_parent(clk);
231 rate = pclk->ops->get_rate(pclk);
237 struct clk_ops s5p_sclk_spdif_ops = {
238 .set_rate = s5p_spdif_set_rate,
239 .get_rate = s5p_spdif_get_rate,
242 static struct clk *s5p_clks[] __initdata = {
255 void __init s5p_register_clocks(unsigned long xtal_freq)
259 clk_ext_xtal_mux.rate = xtal_freq;
261 ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks));
263 printk(KERN_ERR "Failed to register s5p clocks\n");