arch/arm/plat-s3c64xx/irq.c

   1 /* arch/arm/plat-s3c64xx/irq.c
   2  *
   3  * Copyright 2008 Openmoko, Inc.
   4  * Copyright 2008 Simtec Electronics
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *      http://armlinux.simtec.co.uk/
   7  *
   8  * S3C64XX - Interrupt handling
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irq.h>
  18 #include <linux/io.h>
  19
  20 #include <asm/hardware/vic.h>
  21
  22 #include <mach/map.h>
  23 #include <plat/regs-timer.h>
  24 #include <plat/cpu.h>
  25
  26 /* Timer interrupt handling */
  27
  28 static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq)
  29 {
  30         generic_handle_irq(sub_irq);
  31 }
  32
  33 static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc)
  34 {
  35         s3c_irq_demux_timer(irq, IRQ_TIMER0);
  36 }
  37
  38 static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc)
  39 {
  40         s3c_irq_demux_timer(irq, IRQ_TIMER1);
  41 }
  42
  43 static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc)
  44 {
  45         s3c_irq_demux_timer(irq, IRQ_TIMER2);
  46 }
  47
  48 static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc)
  49 {
  50         s3c_irq_demux_timer(irq, IRQ_TIMER3);
  51 }
  52
  53 static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc)
  54 {
  55         s3c_irq_demux_timer(irq, IRQ_TIMER4);
  56 }
  57
  58 /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
  59
  60 static void s3c_irq_timer_mask(unsigned int irq)
  61 {
  62         u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
  63
  64         reg &= 0x1f;  /* mask out pending interrupts */
  65         reg &= ~(1 << (irq - IRQ_TIMER0));
  66         __raw_writel(reg, S3C64XX_TINT_CSTAT);
  67 }
  68
  69 static void s3c_irq_timer_unmask(unsigned int irq)
  70 {
  71         u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
  72
  73         reg &= 0x1f;  /* mask out pending interrupts */
  74         reg |= 1 << (irq - IRQ_TIMER0);
  75         __raw_writel(reg, S3C64XX_TINT_CSTAT);
  76 }
  77
  78 static void s3c_irq_timer_ack(unsigned int irq)
  79 {
  80         u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
  81
  82         reg &= 0x1f;
  83         reg |= (1 << 5) << (irq - IRQ_TIMER0);
  84         __raw_writel(reg, S3C64XX_TINT_CSTAT);
  85 }
  86
  87 static struct irq_chip s3c_irq_timer = {
  88         .name           = "s3c-timer",
  89         .mask           = s3c_irq_timer_mask,
  90         .unmask         = s3c_irq_timer_unmask,
  91         .ack            = s3c_irq_timer_ack,
  92 };
  93
  94 void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
  95 {
  96         int irq;
  97
  98         printk(KERN_INFO "%s: initialising interrupts\n", __func__);
  99
 100         /* initialise the pair of VICs */
 101         vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid);
 102         vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid);
 103
 104         /* add the timer sub-irqs */
 105
 106         set_irq_chained_handler(IRQ_TIMER0_VIC, s3c_irq_demux_timer0);
 107         set_irq_chained_handler(IRQ_TIMER1_VIC, s3c_irq_demux_timer1);
 108         set_irq_chained_handler(IRQ_TIMER2_VIC, s3c_irq_demux_timer2);
 109         set_irq_chained_handler(IRQ_TIMER3_VIC, s3c_irq_demux_timer3);
 110         set_irq_chained_handler(IRQ_TIMER4_VIC, s3c_irq_demux_timer4);
 111
 112         for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) {
 113                 set_irq_chip(irq, &s3c_irq_timer);
 114                 set_irq_handler(irq, handle_level_irq);
 115                 set_irq_flags(irq, IRQF_VALID);
 116         }
 117 }
 118
 119